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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/slab.h>
14#include <linux/spinlock.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/list.h>
20#include <linux/dma-mapping.h>
21
22#include <linux/usb/ch9.h>
23#include <linux/usb/gadget.h>
24
25#include "debug.h"
26#include "core.h"
27#include "gadget.h"
28#include "io.h"
29
30#define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
32
33/**
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
37 *
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
40 */
41int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
42{
43 u32 reg;
44
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
47
48 switch (mode) {
49 case USB_TEST_J:
50 case USB_TEST_K:
51 case USB_TEST_SE0_NAK:
52 case USB_TEST_PACKET:
53 case USB_TEST_FORCE_ENABLE:
54 reg |= mode << 1;
55 break;
56 default:
57 return -EINVAL;
58 }
59
60 dwc3_gadget_dctl_write_safe(dwc, reg);
61
62 return 0;
63}
64
65/**
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
68 *
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
71 */
72int dwc3_gadget_get_link_state(struct dwc3 *dwc)
73{
74 u32 reg;
75
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
77
78 return DWC3_DSTS_USBLNKST(reg);
79}
80
81/**
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
85 *
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
88 */
89int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
90{
91 int retries = 10000;
92 u32 reg;
93
94 /*
95 * Wait until device controller is ready. Only applies to 1.94a and
96 * later RTL.
97 */
98 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
99 while (--retries) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
102 udelay(5);
103 else
104 break;
105 }
106
107 if (retries <= 0)
108 return -ETIMEDOUT;
109 }
110
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
113
114 /* set no action before sending new link state change */
115 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
116
117 /* set requested state */
118 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
119 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
120
121 /*
122 * The following code is racy when called from dwc3_gadget_wakeup,
123 * and is not needed, at least on newer versions
124 */
125 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
126 return 0;
127
128 /* wait for a change in DSTS */
129 retries = 10000;
130 while (--retries) {
131 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
132
133 if (DWC3_DSTS_USBLNKST(reg) == state)
134 return 0;
135
136 udelay(5);
137 }
138
139 return -ETIMEDOUT;
140}
141
142static void dwc3_ep0_reset_state(struct dwc3 *dwc)
143{
144 unsigned int dir;
145
146 if (dwc->ep0state != EP0_SETUP_PHASE) {
147 dir = !!dwc->ep0_expect_in;
148 if (dwc->ep0state == EP0_DATA_PHASE)
149 dwc3_ep0_end_control_data(dwc, dwc->eps[dir]);
150 else
151 dwc3_ep0_end_control_data(dwc, dwc->eps[!dir]);
152
153 dwc->eps[0]->trb_enqueue = 0;
154 dwc->eps[1]->trb_enqueue = 0;
155
156 dwc3_ep0_stall_and_restart(dwc);
157 }
158}
159
160/**
161 * dwc3_ep_inc_trb - increment a trb index.
162 * @index: Pointer to the TRB index to increment.
163 *
164 * The index should never point to the link TRB. After incrementing,
165 * if it is point to the link TRB, wrap around to the beginning. The
166 * link TRB is always at the last TRB entry.
167 */
168static void dwc3_ep_inc_trb(u8 *index)
169{
170 (*index)++;
171 if (*index == (DWC3_TRB_NUM - 1))
172 *index = 0;
173}
174
175/**
176 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
177 * @dep: The endpoint whose enqueue pointer we're incrementing
178 */
179static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
180{
181 dwc3_ep_inc_trb(&dep->trb_enqueue);
182}
183
184/**
185 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
186 * @dep: The endpoint whose enqueue pointer we're incrementing
187 */
188static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
189{
190 dwc3_ep_inc_trb(&dep->trb_dequeue);
191}
192
193static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
194 struct dwc3_request *req, int status)
195{
196 struct dwc3 *dwc = dep->dwc;
197
198 list_del(&req->list);
199 req->remaining = 0;
200 req->needs_extra_trb = false;
201 req->num_trbs = 0;
202
203 if (req->request.status == -EINPROGRESS)
204 req->request.status = status;
205
206 if (req->trb)
207 usb_gadget_unmap_request_by_dev(dwc->sysdev,
208 &req->request, req->direction);
209
210 req->trb = NULL;
211 trace_dwc3_gadget_giveback(req);
212
213 if (dep->number > 1)
214 pm_runtime_put(dwc->dev);
215}
216
217/**
218 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
219 * @dep: The endpoint to whom the request belongs to
220 * @req: The request we're giving back
221 * @status: completion code for the request
222 *
223 * Must be called with controller's lock held and interrupts disabled. This
224 * function will unmap @req and call its ->complete() callback to notify upper
225 * layers that it has completed.
226 */
227void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
228 int status)
229{
230 struct dwc3 *dwc = dep->dwc;
231
232 dwc3_gadget_del_and_unmap_request(dep, req, status);
233 req->status = DWC3_REQUEST_STATUS_COMPLETED;
234
235 spin_unlock(&dwc->lock);
236 usb_gadget_giveback_request(&dep->endpoint, &req->request);
237 spin_lock(&dwc->lock);
238}
239
240/**
241 * dwc3_send_gadget_generic_command - issue a generic command for the controller
242 * @dwc: pointer to the controller context
243 * @cmd: the command to be issued
244 * @param: command parameter
245 *
246 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
247 * and wait for its completion.
248 */
249int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
250 u32 param)
251{
252 u32 timeout = 500;
253 int status = 0;
254 int ret = 0;
255 u32 reg;
256
257 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
258 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
259
260 do {
261 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
262 if (!(reg & DWC3_DGCMD_CMDACT)) {
263 status = DWC3_DGCMD_STATUS(reg);
264 if (status)
265 ret = -EINVAL;
266 break;
267 }
268 } while (--timeout);
269
270 if (!timeout) {
271 ret = -ETIMEDOUT;
272 status = -ETIMEDOUT;
273 }
274
275 trace_dwc3_gadget_generic_cmd(cmd, param, status);
276
277 return ret;
278}
279
280static int __dwc3_gadget_wakeup(struct dwc3 *dwc, bool async);
281
282/**
283 * dwc3_send_gadget_ep_cmd - issue an endpoint command
284 * @dep: the endpoint to which the command is going to be issued
285 * @cmd: the command to be issued
286 * @params: parameters to the command
287 *
288 * Caller should handle locking. This function will issue @cmd with given
289 * @params to @dep and wait for its completion.
290 */
291int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
292 struct dwc3_gadget_ep_cmd_params *params)
293{
294 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
295 struct dwc3 *dwc = dep->dwc;
296 u32 timeout = 5000;
297 u32 saved_config = 0;
298 u32 reg;
299
300 int cmd_status = 0;
301 int ret = -EINVAL;
302
303 /*
304 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
305 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
306 * endpoint command.
307 *
308 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
309 * settings. Restore them after the command is completed.
310 *
311 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
312 */
313 if (dwc->gadget->speed <= USB_SPEED_HIGH ||
314 DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER) {
315 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
316 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
317 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
318 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
319 }
320
321 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
322 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
323 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
324 }
325
326 if (saved_config)
327 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
328 }
329
330 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
331 int link_state;
332
333 /*
334 * Initiate remote wakeup if the link state is in U3 when
335 * operating in SS/SSP or L1/L2 when operating in HS/FS. If the
336 * link state is in U1/U2, no remote wakeup is needed. The Start
337 * Transfer command will initiate the link recovery.
338 */
339 link_state = dwc3_gadget_get_link_state(dwc);
340 switch (link_state) {
341 case DWC3_LINK_STATE_U2:
342 if (dwc->gadget->speed >= USB_SPEED_SUPER)
343 break;
344
345 fallthrough;
346 case DWC3_LINK_STATE_U3:
347 ret = __dwc3_gadget_wakeup(dwc, false);
348 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
349 ret);
350 break;
351 }
352 }
353
354 /*
355 * For some commands such as Update Transfer command, DEPCMDPARn
356 * registers are reserved. Since the driver often sends Update Transfer
357 * command, don't write to DEPCMDPARn to avoid register write delays and
358 * improve performance.
359 */
360 if (DWC3_DEPCMD_CMD(cmd) != DWC3_DEPCMD_UPDATETRANSFER) {
361 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
362 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
363 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
364 }
365
366 /*
367 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
368 * not relying on XferNotReady, we can make use of a special "No
369 * Response Update Transfer" command where we should clear both CmdAct
370 * and CmdIOC bits.
371 *
372 * With this, we don't need to wait for command completion and can
373 * straight away issue further commands to the endpoint.
374 *
375 * NOTICE: We're making an assumption that control endpoints will never
376 * make use of Update Transfer command. This is a safe assumption
377 * because we can never have more than one request at a time with
378 * Control Endpoints. If anybody changes that assumption, this chunk
379 * needs to be updated accordingly.
380 */
381 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
382 !usb_endpoint_xfer_isoc(desc))
383 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
384 else
385 cmd |= DWC3_DEPCMD_CMDACT;
386
387 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
388
389 if (!(cmd & DWC3_DEPCMD_CMDACT) ||
390 (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER &&
391 !(cmd & DWC3_DEPCMD_CMDIOC))) {
392 ret = 0;
393 goto skip_status;
394 }
395
396 do {
397 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
398 if (!(reg & DWC3_DEPCMD_CMDACT)) {
399 cmd_status = DWC3_DEPCMD_STATUS(reg);
400
401 switch (cmd_status) {
402 case 0:
403 ret = 0;
404 break;
405 case DEPEVT_TRANSFER_NO_RESOURCE:
406 dev_WARN(dwc->dev, "No resource for %s\n",
407 dep->name);
408 ret = -EINVAL;
409 break;
410 case DEPEVT_TRANSFER_BUS_EXPIRY:
411 /*
412 * SW issues START TRANSFER command to
413 * isochronous ep with future frame interval. If
414 * future interval time has already passed when
415 * core receives the command, it will respond
416 * with an error status of 'Bus Expiry'.
417 *
418 * Instead of always returning -EINVAL, let's
419 * give a hint to the gadget driver that this is
420 * the case by returning -EAGAIN.
421 */
422 ret = -EAGAIN;
423 break;
424 default:
425 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
426 }
427
428 break;
429 }
430 } while (--timeout);
431
432 if (timeout == 0) {
433 ret = -ETIMEDOUT;
434 cmd_status = -ETIMEDOUT;
435 }
436
437skip_status:
438 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
439
440 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
441 if (ret == 0)
442 dep->flags |= DWC3_EP_TRANSFER_STARTED;
443
444 if (ret != -ETIMEDOUT)
445 dwc3_gadget_ep_get_transfer_index(dep);
446 }
447
448 if (saved_config) {
449 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
450 reg |= saved_config;
451 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
452 }
453
454 return ret;
455}
456
457static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
458{
459 struct dwc3 *dwc = dep->dwc;
460 struct dwc3_gadget_ep_cmd_params params;
461 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
462
463 /*
464 * As of core revision 2.60a the recommended programming model
465 * is to set the ClearPendIN bit when issuing a Clear Stall EP
466 * command for IN endpoints. This is to prevent an issue where
467 * some (non-compliant) hosts may not send ACK TPs for pending
468 * IN transfers due to a mishandled error condition. Synopsys
469 * STAR 9000614252.
470 */
471 if (dep->direction &&
472 !DWC3_VER_IS_PRIOR(DWC3, 260A) &&
473 (dwc->gadget->speed >= USB_SPEED_SUPER))
474 cmd |= DWC3_DEPCMD_CLEARPENDIN;
475
476 memset(¶ms, 0, sizeof(params));
477
478 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
479}
480
481static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
482 struct dwc3_trb *trb)
483{
484 u32 offset = (char *) trb - (char *) dep->trb_pool;
485
486 return dep->trb_pool_dma + offset;
487}
488
489static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
490{
491 struct dwc3 *dwc = dep->dwc;
492
493 if (dep->trb_pool)
494 return 0;
495
496 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
497 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
498 &dep->trb_pool_dma, GFP_KERNEL);
499 if (!dep->trb_pool) {
500 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
501 dep->name);
502 return -ENOMEM;
503 }
504
505 return 0;
506}
507
508static void dwc3_free_trb_pool(struct dwc3_ep *dep)
509{
510 struct dwc3 *dwc = dep->dwc;
511
512 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
513 dep->trb_pool, dep->trb_pool_dma);
514
515 dep->trb_pool = NULL;
516 dep->trb_pool_dma = 0;
517}
518
519static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
520{
521 struct dwc3_gadget_ep_cmd_params params;
522
523 memset(¶ms, 0x00, sizeof(params));
524
525 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
526
527 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
528 ¶ms);
529}
530
531/**
532 * dwc3_gadget_start_config - configure ep resources
533 * @dep: endpoint that is being enabled
534 *
535 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
536 * completion, it will set Transfer Resource for all available endpoints.
537 *
538 * The assignment of transfer resources cannot perfectly follow the data book
539 * due to the fact that the controller driver does not have all knowledge of the
540 * configuration in advance. It is given this information piecemeal by the
541 * composite gadget framework after every SET_CONFIGURATION and
542 * SET_INTERFACE. Trying to follow the databook programming model in this
543 * scenario can cause errors. For two reasons:
544 *
545 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
546 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
547 * incorrect in the scenario of multiple interfaces.
548 *
549 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
550 * endpoint on alt setting (8.1.6).
551 *
552 * The following simplified method is used instead:
553 *
554 * All hardware endpoints can be assigned a transfer resource and this setting
555 * will stay persistent until either a core reset or hibernation. So whenever we
556 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
557 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
558 * guaranteed that there are as many transfer resources as endpoints.
559 *
560 * This function is called for each endpoint when it is being enabled but is
561 * triggered only when called for EP0-out, which always happens first, and which
562 * should only happen in one of the above conditions.
563 */
564static int dwc3_gadget_start_config(struct dwc3_ep *dep)
565{
566 struct dwc3_gadget_ep_cmd_params params;
567 struct dwc3 *dwc;
568 u32 cmd;
569 int i;
570 int ret;
571
572 if (dep->number)
573 return 0;
574
575 memset(¶ms, 0x00, sizeof(params));
576 cmd = DWC3_DEPCMD_DEPSTARTCFG;
577 dwc = dep->dwc;
578
579 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
580 if (ret)
581 return ret;
582
583 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
584 struct dwc3_ep *dep = dwc->eps[i];
585
586 if (!dep)
587 continue;
588
589 ret = dwc3_gadget_set_xfer_resource(dep);
590 if (ret)
591 return ret;
592 }
593
594 return 0;
595}
596
597static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
598{
599 const struct usb_ss_ep_comp_descriptor *comp_desc;
600 const struct usb_endpoint_descriptor *desc;
601 struct dwc3_gadget_ep_cmd_params params;
602 struct dwc3 *dwc = dep->dwc;
603
604 comp_desc = dep->endpoint.comp_desc;
605 desc = dep->endpoint.desc;
606
607 memset(¶ms, 0x00, sizeof(params));
608
609 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
610 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
611
612 /* Burst size is only needed in SuperSpeed mode */
613 if (dwc->gadget->speed >= USB_SPEED_SUPER) {
614 u32 burst = dep->endpoint.maxburst;
615
616 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
617 }
618
619 params.param0 |= action;
620 if (action == DWC3_DEPCFG_ACTION_RESTORE)
621 params.param2 |= dep->saved_state;
622
623 if (usb_endpoint_xfer_control(desc))
624 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
625
626 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
627 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
628
629 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
630 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
631 | DWC3_DEPCFG_XFER_COMPLETE_EN
632 | DWC3_DEPCFG_STREAM_EVENT_EN;
633 dep->stream_capable = true;
634 }
635
636 if (!usb_endpoint_xfer_control(desc))
637 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
638
639 /*
640 * We are doing 1:1 mapping for endpoints, meaning
641 * Physical Endpoints 2 maps to Logical Endpoint 2 and
642 * so on. We consider the direction bit as part of the physical
643 * endpoint number. So USB endpoint 0x81 is 0x03.
644 */
645 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
646
647 /*
648 * We must use the lower 16 TX FIFOs even though
649 * HW might have more
650 */
651 if (dep->direction)
652 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
653
654 if (desc->bInterval) {
655 u8 bInterval_m1;
656
657 /*
658 * Valid range for DEPCFG.bInterval_m1 is from 0 to 13.
659 *
660 * NOTE: The programming guide incorrectly stated bInterval_m1
661 * must be set to 0 when operating in fullspeed. Internally the
662 * controller does not have this limitation. See DWC_usb3x
663 * programming guide section 3.2.2.1.
664 */
665 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
666
667 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
668 dwc->gadget->speed == USB_SPEED_FULL)
669 dep->interval = desc->bInterval;
670 else
671 dep->interval = 1 << (desc->bInterval - 1);
672
673 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
674 }
675
676 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
677}
678
679/**
680 * dwc3_gadget_calc_tx_fifo_size - calculates the txfifo size value
681 * @dwc: pointer to the DWC3 context
682 * @mult: multiplier to be used when calculating the fifo_size
683 *
684 * Calculates the size value based on the equation below:
685 *
686 * DWC3 revision 280A and prior:
687 * fifo_size = mult * (max_packet / mdwidth) + 1;
688 *
689 * DWC3 revision 290A and onwards:
690 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
691 *
692 * The max packet size is set to 1024, as the txfifo requirements mainly apply
693 * to super speed USB use cases. However, it is safe to overestimate the fifo
694 * allocations for other scenarios, i.e. high speed USB.
695 */
696static int dwc3_gadget_calc_tx_fifo_size(struct dwc3 *dwc, int mult)
697{
698 int max_packet = 1024;
699 int fifo_size;
700 int mdwidth;
701
702 mdwidth = dwc3_mdwidth(dwc);
703
704 /* MDWIDTH is represented in bits, we need it in bytes */
705 mdwidth >>= 3;
706
707 if (DWC3_VER_IS_PRIOR(DWC3, 290A))
708 fifo_size = mult * (max_packet / mdwidth) + 1;
709 else
710 fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
711 return fifo_size;
712}
713
714/**
715 * dwc3_gadget_clear_tx_fifos - Clears txfifo allocation
716 * @dwc: pointer to the DWC3 context
717 *
718 * Iterates through all the endpoint registers and clears the previous txfifo
719 * allocations.
720 */
721void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
722{
723 struct dwc3_ep *dep;
724 int fifo_depth;
725 int size;
726 int num;
727
728 if (!dwc->do_fifo_resize)
729 return;
730
731 /* Read ep0IN related TXFIFO size */
732 dep = dwc->eps[1];
733 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
734 if (DWC3_IP_IS(DWC3))
735 fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
736 else
737 fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
738
739 dwc->last_fifo_depth = fifo_depth;
740 /* Clear existing TXFIFO for all IN eps except ep0 */
741 for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
742 num += 2) {
743 dep = dwc->eps[num];
744 /* Don't change TXFRAMNUM on usb31 version */
745 size = DWC3_IP_IS(DWC3) ? 0 :
746 dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
747 DWC31_GTXFIFOSIZ_TXFRAMNUM;
748
749 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
750 dep->flags &= ~DWC3_EP_TXFIFO_RESIZED;
751 }
752 dwc->num_ep_resized = 0;
753}
754
755/*
756 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
757 * @dwc: pointer to our context structure
758 *
759 * This function will a best effort FIFO allocation in order
760 * to improve FIFO usage and throughput, while still allowing
761 * us to enable as many endpoints as possible.
762 *
763 * Keep in mind that this operation will be highly dependent
764 * on the configured size for RAM1 - which contains TxFifo -,
765 * the amount of endpoints enabled on coreConsultant tool, and
766 * the width of the Master Bus.
767 *
768 * In general, FIFO depths are represented with the following equation:
769 *
770 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
771 *
772 * In conjunction with dwc3_gadget_check_config(), this resizing logic will
773 * ensure that all endpoints will have enough internal memory for one max
774 * packet per endpoint.
775 */
776static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
777{
778 struct dwc3 *dwc = dep->dwc;
779 int fifo_0_start;
780 int ram1_depth;
781 int fifo_size;
782 int min_depth;
783 int num_in_ep;
784 int remaining;
785 int num_fifos = 1;
786 int fifo;
787 int tmp;
788
789 if (!dwc->do_fifo_resize)
790 return 0;
791
792 /* resize IN endpoints except ep0 */
793 if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
794 return 0;
795
796 /* bail if already resized */
797 if (dep->flags & DWC3_EP_TXFIFO_RESIZED)
798 return 0;
799
800 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
801
802 if ((dep->endpoint.maxburst > 1 &&
803 usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
804 usb_endpoint_xfer_isoc(dep->endpoint.desc))
805 num_fifos = 3;
806
807 if (dep->endpoint.maxburst > 6 &&
808 (usb_endpoint_xfer_bulk(dep->endpoint.desc) ||
809 usb_endpoint_xfer_isoc(dep->endpoint.desc)) && DWC3_IP_IS(DWC31))
810 num_fifos = dwc->tx_fifo_resize_max_num;
811
812 /* FIFO size for a single buffer */
813 fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
814
815 /* Calculate the number of remaining EPs w/o any FIFO */
816 num_in_ep = dwc->max_cfg_eps;
817 num_in_ep -= dwc->num_ep_resized;
818
819 /* Reserve at least one FIFO for the number of IN EPs */
820 min_depth = num_in_ep * (fifo + 1);
821 remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
822 remaining = max_t(int, 0, remaining);
823 /*
824 * We've already reserved 1 FIFO per EP, so check what we can fit in
825 * addition to it. If there is not enough remaining space, allocate
826 * all the remaining space to the EP.
827 */
828 fifo_size = (num_fifos - 1) * fifo;
829 if (remaining < fifo_size)
830 fifo_size = remaining;
831
832 fifo_size += fifo;
833 /* Last increment according to the TX FIFO size equation */
834 fifo_size++;
835
836 /* Check if TXFIFOs start at non-zero addr */
837 tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
838 fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
839
840 fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
841 if (DWC3_IP_IS(DWC3))
842 dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
843 else
844 dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
845
846 /* Check fifo size allocation doesn't exceed available RAM size. */
847 if (dwc->last_fifo_depth >= ram1_depth) {
848 dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
849 dwc->last_fifo_depth, ram1_depth,
850 dep->endpoint.name, fifo_size);
851 if (DWC3_IP_IS(DWC3))
852 fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
853 else
854 fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
855
856 dwc->last_fifo_depth -= fifo_size;
857 return -ENOMEM;
858 }
859
860 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
861 dep->flags |= DWC3_EP_TXFIFO_RESIZED;
862 dwc->num_ep_resized++;
863
864 return 0;
865}
866
867/**
868 * __dwc3_gadget_ep_enable - initializes a hw endpoint
869 * @dep: endpoint to be initialized
870 * @action: one of INIT, MODIFY or RESTORE
871 *
872 * Caller should take care of locking. Execute all necessary commands to
873 * initialize a HW endpoint so it can be used by a gadget driver.
874 */
875static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
876{
877 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
878 struct dwc3 *dwc = dep->dwc;
879
880 u32 reg;
881 int ret;
882
883 if (!(dep->flags & DWC3_EP_ENABLED)) {
884 ret = dwc3_gadget_resize_tx_fifos(dep);
885 if (ret)
886 return ret;
887
888 ret = dwc3_gadget_start_config(dep);
889 if (ret)
890 return ret;
891 }
892
893 ret = dwc3_gadget_set_ep_config(dep, action);
894 if (ret)
895 return ret;
896
897 if (!(dep->flags & DWC3_EP_ENABLED)) {
898 struct dwc3_trb *trb_st_hw;
899 struct dwc3_trb *trb_link;
900
901 dep->type = usb_endpoint_type(desc);
902 dep->flags |= DWC3_EP_ENABLED;
903
904 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
905 reg |= DWC3_DALEPENA_EP(dep->number);
906 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
907
908 dep->trb_dequeue = 0;
909 dep->trb_enqueue = 0;
910
911 if (usb_endpoint_xfer_control(desc))
912 goto out;
913
914 /* Initialize the TRB ring */
915 memset(dep->trb_pool, 0,
916 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
917
918 /* Link TRB. The HWO bit is never reset */
919 trb_st_hw = &dep->trb_pool[0];
920
921 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
922 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
923 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
924 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
925 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
926 }
927
928 /*
929 * Issue StartTransfer here with no-op TRB so we can always rely on No
930 * Response Update Transfer command.
931 */
932 if (usb_endpoint_xfer_bulk(desc) ||
933 usb_endpoint_xfer_int(desc)) {
934 struct dwc3_gadget_ep_cmd_params params;
935 struct dwc3_trb *trb;
936 dma_addr_t trb_dma;
937 u32 cmd;
938
939 memset(¶ms, 0, sizeof(params));
940 trb = &dep->trb_pool[0];
941 trb_dma = dwc3_trb_dma_offset(dep, trb);
942
943 params.param0 = upper_32_bits(trb_dma);
944 params.param1 = lower_32_bits(trb_dma);
945
946 cmd = DWC3_DEPCMD_STARTTRANSFER;
947
948 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
949 if (ret < 0)
950 return ret;
951
952 if (dep->stream_capable) {
953 /*
954 * For streams, at start, there maybe a race where the
955 * host primes the endpoint before the function driver
956 * queues a request to initiate a stream. In that case,
957 * the controller will not see the prime to generate the
958 * ERDY and start stream. To workaround this, issue a
959 * no-op TRB as normal, but end it immediately. As a
960 * result, when the function driver queues the request,
961 * the next START_TRANSFER command will cause the
962 * controller to generate an ERDY to initiate the
963 * stream.
964 */
965 dwc3_stop_active_transfer(dep, true, true);
966
967 /*
968 * All stream eps will reinitiate stream on NoStream
969 * rejection until we can determine that the host can
970 * prime after the first transfer.
971 *
972 * However, if the controller is capable of
973 * TXF_FLUSH_BYPASS, then IN direction endpoints will
974 * automatically restart the stream without the driver
975 * initiation.
976 */
977 if (!dep->direction ||
978 !(dwc->hwparams.hwparams9 &
979 DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS))
980 dep->flags |= DWC3_EP_FORCE_RESTART_STREAM;
981 }
982 }
983
984out:
985 trace_dwc3_gadget_ep_enable(dep);
986
987 return 0;
988}
989
990void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status)
991{
992 struct dwc3_request *req;
993
994 dwc3_stop_active_transfer(dep, true, false);
995
996 /* If endxfer is delayed, avoid unmapping requests */
997 if (dep->flags & DWC3_EP_DELAY_STOP)
998 return;
999
1000 /* - giveback all requests to gadget driver */
1001 while (!list_empty(&dep->started_list)) {
1002 req = next_request(&dep->started_list);
1003
1004 dwc3_gadget_giveback(dep, req, status);
1005 }
1006
1007 while (!list_empty(&dep->pending_list)) {
1008 req = next_request(&dep->pending_list);
1009
1010 dwc3_gadget_giveback(dep, req, status);
1011 }
1012
1013 while (!list_empty(&dep->cancelled_list)) {
1014 req = next_request(&dep->cancelled_list);
1015
1016 dwc3_gadget_giveback(dep, req, status);
1017 }
1018}
1019
1020/**
1021 * __dwc3_gadget_ep_disable - disables a hw endpoint
1022 * @dep: the endpoint to disable
1023 *
1024 * This function undoes what __dwc3_gadget_ep_enable did and also removes
1025 * requests which are currently being processed by the hardware and those which
1026 * are not yet scheduled.
1027 *
1028 * Caller should take care of locking.
1029 */
1030static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
1031{
1032 struct dwc3 *dwc = dep->dwc;
1033 u32 reg;
1034 u32 mask;
1035
1036 trace_dwc3_gadget_ep_disable(dep);
1037
1038 /* make sure HW endpoint isn't stalled */
1039 if (dep->flags & DWC3_EP_STALL)
1040 __dwc3_gadget_ep_set_halt(dep, 0, false);
1041
1042 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
1043 reg &= ~DWC3_DALEPENA_EP(dep->number);
1044 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
1045
1046 dwc3_remove_requests(dwc, dep, -ESHUTDOWN);
1047
1048 dep->stream_capable = false;
1049 dep->type = 0;
1050 mask = DWC3_EP_TXFIFO_RESIZED;
1051 /*
1052 * dwc3_remove_requests() can exit early if DWC3 EP delayed stop is
1053 * set. Do not clear DEP flags, so that the end transfer command will
1054 * be reattempted during the next SETUP stage.
1055 */
1056 if (dep->flags & DWC3_EP_DELAY_STOP)
1057 mask |= (DWC3_EP_DELAY_STOP | DWC3_EP_TRANSFER_STARTED);
1058 dep->flags &= mask;
1059
1060 /* Clear out the ep descriptors for non-ep0 */
1061 if (dep->number > 1) {
1062 dep->endpoint.comp_desc = NULL;
1063 dep->endpoint.desc = NULL;
1064 }
1065
1066 return 0;
1067}
1068
1069/* -------------------------------------------------------------------------- */
1070
1071static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
1072 const struct usb_endpoint_descriptor *desc)
1073{
1074 return -EINVAL;
1075}
1076
1077static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
1078{
1079 return -EINVAL;
1080}
1081
1082/* -------------------------------------------------------------------------- */
1083
1084static int dwc3_gadget_ep_enable(struct usb_ep *ep,
1085 const struct usb_endpoint_descriptor *desc)
1086{
1087 struct dwc3_ep *dep;
1088 struct dwc3 *dwc;
1089 unsigned long flags;
1090 int ret;
1091
1092 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
1093 pr_debug("dwc3: invalid parameters\n");
1094 return -EINVAL;
1095 }
1096
1097 if (!desc->wMaxPacketSize) {
1098 pr_debug("dwc3: missing wMaxPacketSize\n");
1099 return -EINVAL;
1100 }
1101
1102 dep = to_dwc3_ep(ep);
1103 dwc = dep->dwc;
1104
1105 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
1106 "%s is already enabled\n",
1107 dep->name))
1108 return 0;
1109
1110 spin_lock_irqsave(&dwc->lock, flags);
1111 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1112 spin_unlock_irqrestore(&dwc->lock, flags);
1113
1114 return ret;
1115}
1116
1117static int dwc3_gadget_ep_disable(struct usb_ep *ep)
1118{
1119 struct dwc3_ep *dep;
1120 struct dwc3 *dwc;
1121 unsigned long flags;
1122 int ret;
1123
1124 if (!ep) {
1125 pr_debug("dwc3: invalid parameters\n");
1126 return -EINVAL;
1127 }
1128
1129 dep = to_dwc3_ep(ep);
1130 dwc = dep->dwc;
1131
1132 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
1133 "%s is already disabled\n",
1134 dep->name))
1135 return 0;
1136
1137 spin_lock_irqsave(&dwc->lock, flags);
1138 ret = __dwc3_gadget_ep_disable(dep);
1139 spin_unlock_irqrestore(&dwc->lock, flags);
1140
1141 return ret;
1142}
1143
1144static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
1145 gfp_t gfp_flags)
1146{
1147 struct dwc3_request *req;
1148 struct dwc3_ep *dep = to_dwc3_ep(ep);
1149
1150 req = kzalloc(sizeof(*req), gfp_flags);
1151 if (!req)
1152 return NULL;
1153
1154 req->direction = dep->direction;
1155 req->epnum = dep->number;
1156 req->dep = dep;
1157 req->status = DWC3_REQUEST_STATUS_UNKNOWN;
1158
1159 trace_dwc3_alloc_request(req);
1160
1161 return &req->request;
1162}
1163
1164static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
1165 struct usb_request *request)
1166{
1167 struct dwc3_request *req = to_dwc3_request(request);
1168
1169 trace_dwc3_free_request(req);
1170 kfree(req);
1171}
1172
1173/**
1174 * dwc3_ep_prev_trb - returns the previous TRB in the ring
1175 * @dep: The endpoint with the TRB ring
1176 * @index: The index of the current TRB in the ring
1177 *
1178 * Returns the TRB prior to the one pointed to by the index. If the
1179 * index is 0, we will wrap backwards, skip the link TRB, and return
1180 * the one just before that.
1181 */
1182static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
1183{
1184 u8 tmp = index;
1185
1186 if (!tmp)
1187 tmp = DWC3_TRB_NUM - 1;
1188
1189 return &dep->trb_pool[tmp - 1];
1190}
1191
1192static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
1193{
1194 u8 trbs_left;
1195
1196 /*
1197 * If the enqueue & dequeue are equal then the TRB ring is either full
1198 * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs
1199 * pending to be processed by the driver.
1200 */
1201 if (dep->trb_enqueue == dep->trb_dequeue) {
1202 /*
1203 * If there is any request remained in the started_list at
1204 * this point, that means there is no TRB available.
1205 */
1206 if (!list_empty(&dep->started_list))
1207 return 0;
1208
1209 return DWC3_TRB_NUM - 1;
1210 }
1211
1212 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
1213 trbs_left &= (DWC3_TRB_NUM - 1);
1214
1215 if (dep->trb_dequeue < dep->trb_enqueue)
1216 trbs_left--;
1217
1218 return trbs_left;
1219}
1220
1221/**
1222 * dwc3_prepare_one_trb - setup one TRB from one request
1223 * @dep: endpoint for which this request is prepared
1224 * @req: dwc3_request pointer
1225 * @trb_length: buffer size of the TRB
1226 * @chain: should this TRB be chained to the next?
1227 * @node: only for isochronous endpoints. First TRB needs different type.
1228 * @use_bounce_buffer: set to use bounce buffer
1229 * @must_interrupt: set to interrupt on TRB completion
1230 */
1231static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1232 struct dwc3_request *req, unsigned int trb_length,
1233 unsigned int chain, unsigned int node, bool use_bounce_buffer,
1234 bool must_interrupt)
1235{
1236 struct dwc3_trb *trb;
1237 dma_addr_t dma;
1238 unsigned int stream_id = req->request.stream_id;
1239 unsigned int short_not_ok = req->request.short_not_ok;
1240 unsigned int no_interrupt = req->request.no_interrupt;
1241 unsigned int is_last = req->request.is_last;
1242 struct dwc3 *dwc = dep->dwc;
1243 struct usb_gadget *gadget = dwc->gadget;
1244 enum usb_device_speed speed = gadget->speed;
1245
1246 if (use_bounce_buffer)
1247 dma = dep->dwc->bounce_addr;
1248 else if (req->request.num_sgs > 0)
1249 dma = sg_dma_address(req->start_sg);
1250 else
1251 dma = req->request.dma;
1252
1253 trb = &dep->trb_pool[dep->trb_enqueue];
1254
1255 if (!req->trb) {
1256 dwc3_gadget_move_started_request(req);
1257 req->trb = trb;
1258 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1259 }
1260
1261 req->num_trbs++;
1262
1263 trb->size = DWC3_TRB_SIZE_LENGTH(trb_length);
1264 trb->bpl = lower_32_bits(dma);
1265 trb->bph = upper_32_bits(dma);
1266
1267 switch (usb_endpoint_type(dep->endpoint.desc)) {
1268 case USB_ENDPOINT_XFER_CONTROL:
1269 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
1270 break;
1271
1272 case USB_ENDPOINT_XFER_ISOC:
1273 if (!node) {
1274 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
1275
1276 /*
1277 * USB Specification 2.0 Section 5.9.2 states that: "If
1278 * there is only a single transaction in the microframe,
1279 * only a DATA0 data packet PID is used. If there are
1280 * two transactions per microframe, DATA1 is used for
1281 * the first transaction data packet and DATA0 is used
1282 * for the second transaction data packet. If there are
1283 * three transactions per microframe, DATA2 is used for
1284 * the first transaction data packet, DATA1 is used for
1285 * the second, and DATA0 is used for the third."
1286 *
1287 * IOW, we should satisfy the following cases:
1288 *
1289 * 1) length <= maxpacket
1290 * - DATA0
1291 *
1292 * 2) maxpacket < length <= (2 * maxpacket)
1293 * - DATA1, DATA0
1294 *
1295 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
1296 * - DATA2, DATA1, DATA0
1297 */
1298 if (speed == USB_SPEED_HIGH) {
1299 struct usb_ep *ep = &dep->endpoint;
1300 unsigned int mult = 2;
1301 unsigned int maxp = usb_endpoint_maxp(ep->desc);
1302
1303 if (req->request.length <= (2 * maxp))
1304 mult--;
1305
1306 if (req->request.length <= maxp)
1307 mult--;
1308
1309 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
1310 }
1311 } else {
1312 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
1313 }
1314
1315 if (!no_interrupt && !chain)
1316 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1317 break;
1318
1319 case USB_ENDPOINT_XFER_BULK:
1320 case USB_ENDPOINT_XFER_INT:
1321 trb->ctrl = DWC3_TRBCTL_NORMAL;
1322 break;
1323 default:
1324 /*
1325 * This is only possible with faulty memory because we
1326 * checked it already :)
1327 */
1328 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
1329 usb_endpoint_type(dep->endpoint.desc));
1330 }
1331
1332 /*
1333 * Enable Continue on Short Packet
1334 * when endpoint is not a stream capable
1335 */
1336 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
1337 if (!dep->stream_capable)
1338 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1339
1340 if (short_not_ok)
1341 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1342 }
1343
1344 /* All TRBs setup for MST must set CSP=1 when LST=0 */
1345 if (dep->stream_capable && DWC3_MST_CAPABLE(&dwc->hwparams))
1346 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1347
1348 if ((!no_interrupt && !chain) || must_interrupt)
1349 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1350
1351 if (chain)
1352 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1353 else if (dep->stream_capable && is_last &&
1354 !DWC3_MST_CAPABLE(&dwc->hwparams))
1355 trb->ctrl |= DWC3_TRB_CTRL_LST;
1356
1357 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1358 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1359
1360 /*
1361 * As per data book 4.2.3.2TRB Control Bit Rules section
1362 *
1363 * The controller autonomously checks the HWO field of a TRB to determine if the
1364 * entire TRB is valid. Therefore, software must ensure that the rest of the TRB
1365 * is valid before setting the HWO field to '1'. In most systems, this means that
1366 * software must update the fourth DWORD of a TRB last.
1367 *
1368 * However there is a possibility of CPU re-ordering here which can cause
1369 * controller to observe the HWO bit set prematurely.
1370 * Add a write memory barrier to prevent CPU re-ordering.
1371 */
1372 wmb();
1373 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1374
1375 dwc3_ep_inc_enq(dep);
1376
1377 trace_dwc3_prepare_trb(dep, trb);
1378}
1379
1380static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req)
1381{
1382 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1383 unsigned int rem = req->request.length % maxp;
1384
1385 if ((req->request.length && req->request.zero && !rem &&
1386 !usb_endpoint_xfer_isoc(dep->endpoint.desc)) ||
1387 (!req->direction && rem))
1388 return true;
1389
1390 return false;
1391}
1392
1393/**
1394 * dwc3_prepare_last_sg - prepare TRBs for the last SG entry
1395 * @dep: The endpoint that the request belongs to
1396 * @req: The request to prepare
1397 * @entry_length: The last SG entry size
1398 * @node: Indicates whether this is not the first entry (for isoc only)
1399 *
1400 * Return the number of TRBs prepared.
1401 */
1402static int dwc3_prepare_last_sg(struct dwc3_ep *dep,
1403 struct dwc3_request *req, unsigned int entry_length,
1404 unsigned int node)
1405{
1406 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1407 unsigned int rem = req->request.length % maxp;
1408 unsigned int num_trbs = 1;
1409
1410 if (dwc3_needs_extra_trb(dep, req))
1411 num_trbs++;
1412
1413 if (dwc3_calc_trbs_left(dep) < num_trbs)
1414 return 0;
1415
1416 req->needs_extra_trb = num_trbs > 1;
1417
1418 /* Prepare a normal TRB */
1419 if (req->direction || req->request.length)
1420 dwc3_prepare_one_trb(dep, req, entry_length,
1421 req->needs_extra_trb, node, false, false);
1422
1423 /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */
1424 if ((!req->direction && !req->request.length) || req->needs_extra_trb)
1425 dwc3_prepare_one_trb(dep, req,
1426 req->direction ? 0 : maxp - rem,
1427 false, 1, true, false);
1428
1429 return num_trbs;
1430}
1431
1432static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep,
1433 struct dwc3_request *req)
1434{
1435 struct scatterlist *sg = req->start_sg;
1436 struct scatterlist *s;
1437 int i;
1438 unsigned int length = req->request.length;
1439 unsigned int remaining = req->request.num_mapped_sgs
1440 - req->num_queued_sgs;
1441 unsigned int num_trbs = req->num_trbs;
1442 bool needs_extra_trb = dwc3_needs_extra_trb(dep, req);
1443
1444 /*
1445 * If we resume preparing the request, then get the remaining length of
1446 * the request and resume where we left off.
1447 */
1448 for_each_sg(req->request.sg, s, req->num_queued_sgs, i)
1449 length -= sg_dma_len(s);
1450
1451 for_each_sg(sg, s, remaining, i) {
1452 unsigned int num_trbs_left = dwc3_calc_trbs_left(dep);
1453 unsigned int trb_length;
1454 bool must_interrupt = false;
1455 bool last_sg = false;
1456
1457 trb_length = min_t(unsigned int, length, sg_dma_len(s));
1458
1459 length -= trb_length;
1460
1461 /*
1462 * IOMMU driver is coalescing the list of sgs which shares a
1463 * page boundary into one and giving it to USB driver. With
1464 * this the number of sgs mapped is not equal to the number of
1465 * sgs passed. So mark the chain bit to false if it isthe last
1466 * mapped sg.
1467 */
1468 if ((i == remaining - 1) || !length)
1469 last_sg = true;
1470
1471 if (!num_trbs_left)
1472 break;
1473
1474 if (last_sg) {
1475 if (!dwc3_prepare_last_sg(dep, req, trb_length, i))
1476 break;
1477 } else {
1478 /*
1479 * Look ahead to check if we have enough TRBs for the
1480 * next SG entry. If not, set interrupt on this TRB to
1481 * resume preparing the next SG entry when more TRBs are
1482 * free.
1483 */
1484 if (num_trbs_left == 1 || (needs_extra_trb &&
1485 num_trbs_left <= 2 &&
1486 sg_dma_len(sg_next(s)) >= length)) {
1487 struct dwc3_request *r;
1488
1489 /* Check if previous requests already set IOC */
1490 list_for_each_entry(r, &dep->started_list, list) {
1491 if (r != req && !r->request.no_interrupt)
1492 break;
1493
1494 if (r == req)
1495 must_interrupt = true;
1496 }
1497 }
1498
1499 dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false,
1500 must_interrupt);
1501 }
1502
1503 /*
1504 * There can be a situation where all sgs in sglist are not
1505 * queued because of insufficient trb number. To handle this
1506 * case, update start_sg to next sg to be queued, so that
1507 * we have free trbs we can continue queuing from where we
1508 * previously stopped
1509 */
1510 if (!last_sg)
1511 req->start_sg = sg_next(s);
1512
1513 req->num_queued_sgs++;
1514 req->num_pending_sgs--;
1515
1516 /*
1517 * The number of pending SG entries may not correspond to the
1518 * number of mapped SG entries. If all the data are queued, then
1519 * don't include unused SG entries.
1520 */
1521 if (length == 0) {
1522 req->num_pending_sgs = 0;
1523 break;
1524 }
1525
1526 if (must_interrupt)
1527 break;
1528 }
1529
1530 return req->num_trbs - num_trbs;
1531}
1532
1533static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep,
1534 struct dwc3_request *req)
1535{
1536 return dwc3_prepare_last_sg(dep, req, req->request.length, 0);
1537}
1538
1539/*
1540 * dwc3_prepare_trbs - setup TRBs from requests
1541 * @dep: endpoint for which requests are being prepared
1542 *
1543 * The function goes through the requests list and sets up TRBs for the
1544 * transfers. The function returns once there are no more TRBs available or
1545 * it runs out of requests.
1546 *
1547 * Returns the number of TRBs prepared or negative errno.
1548 */
1549static int dwc3_prepare_trbs(struct dwc3_ep *dep)
1550{
1551 struct dwc3_request *req, *n;
1552 int ret = 0;
1553
1554 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1555
1556 /*
1557 * We can get in a situation where there's a request in the started list
1558 * but there weren't enough TRBs to fully kick it in the first time
1559 * around, so it has been waiting for more TRBs to be freed up.
1560 *
1561 * In that case, we should check if we have a request with pending_sgs
1562 * in the started list and prepare TRBs for that request first,
1563 * otherwise we will prepare TRBs completely out of order and that will
1564 * break things.
1565 */
1566 list_for_each_entry(req, &dep->started_list, list) {
1567 if (req->num_pending_sgs > 0) {
1568 ret = dwc3_prepare_trbs_sg(dep, req);
1569 if (!ret || req->num_pending_sgs)
1570 return ret;
1571 }
1572
1573 if (!dwc3_calc_trbs_left(dep))
1574 return ret;
1575
1576 /*
1577 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1578 * burst capability may try to read and use TRBs beyond the
1579 * active transfer instead of stopping.
1580 */
1581 if (dep->stream_capable && req->request.is_last &&
1582 !DWC3_MST_CAPABLE(&dep->dwc->hwparams))
1583 return ret;
1584 }
1585
1586 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1587 struct dwc3 *dwc = dep->dwc;
1588
1589 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1590 dep->direction);
1591 if (ret)
1592 return ret;
1593
1594 req->sg = req->request.sg;
1595 req->start_sg = req->sg;
1596 req->num_queued_sgs = 0;
1597 req->num_pending_sgs = req->request.num_mapped_sgs;
1598
1599 if (req->num_pending_sgs > 0) {
1600 ret = dwc3_prepare_trbs_sg(dep, req);
1601 if (req->num_pending_sgs)
1602 return ret;
1603 } else {
1604 ret = dwc3_prepare_trbs_linear(dep, req);
1605 }
1606
1607 if (!ret || !dwc3_calc_trbs_left(dep))
1608 return ret;
1609
1610 /*
1611 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1612 * burst capability may try to read and use TRBs beyond the
1613 * active transfer instead of stopping.
1614 */
1615 if (dep->stream_capable && req->request.is_last &&
1616 !DWC3_MST_CAPABLE(&dwc->hwparams))
1617 return ret;
1618 }
1619
1620 return ret;
1621}
1622
1623static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
1624
1625static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1626{
1627 struct dwc3_gadget_ep_cmd_params params;
1628 struct dwc3_request *req;
1629 int starting;
1630 int ret;
1631 u32 cmd;
1632
1633 /*
1634 * Note that it's normal to have no new TRBs prepared (i.e. ret == 0).
1635 * This happens when we need to stop and restart a transfer such as in
1636 * the case of reinitiating a stream or retrying an isoc transfer.
1637 */
1638 ret = dwc3_prepare_trbs(dep);
1639 if (ret < 0)
1640 return ret;
1641
1642 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1643
1644 /*
1645 * If there's no new TRB prepared and we don't need to restart a
1646 * transfer, there's no need to update the transfer.
1647 */
1648 if (!ret && !starting)
1649 return ret;
1650
1651 req = next_request(&dep->started_list);
1652 if (!req) {
1653 dep->flags |= DWC3_EP_PENDING_REQUEST;
1654 return 0;
1655 }
1656
1657 memset(¶ms, 0, sizeof(params));
1658
1659 if (starting) {
1660 params.param0 = upper_32_bits(req->trb_dma);
1661 params.param1 = lower_32_bits(req->trb_dma);
1662 cmd = DWC3_DEPCMD_STARTTRANSFER;
1663
1664 if (dep->stream_capable)
1665 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1666
1667 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1668 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1669 } else {
1670 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1671 DWC3_DEPCMD_PARAM(dep->resource_index);
1672 }
1673
1674 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1675 if (ret < 0) {
1676 struct dwc3_request *tmp;
1677
1678 if (ret == -EAGAIN)
1679 return ret;
1680
1681 dwc3_stop_active_transfer(dep, true, true);
1682
1683 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1684 dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED);
1685
1686 /* If ep isn't started, then there's no end transfer pending */
1687 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1688 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1689
1690 return ret;
1691 }
1692
1693 if (dep->stream_capable && req->request.is_last &&
1694 !DWC3_MST_CAPABLE(&dep->dwc->hwparams))
1695 dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE;
1696
1697 return 0;
1698}
1699
1700static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1701{
1702 u32 reg;
1703
1704 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1705 return DWC3_DSTS_SOFFN(reg);
1706}
1707
1708/**
1709 * __dwc3_stop_active_transfer - stop the current active transfer
1710 * @dep: isoc endpoint
1711 * @force: set forcerm bit in the command
1712 * @interrupt: command complete interrupt after End Transfer command
1713 *
1714 * When setting force, the ForceRM bit will be set. In that case
1715 * the controller won't update the TRB progress on command
1716 * completion. It also won't clear the HWO bit in the TRB.
1717 * The command will also not complete immediately in that case.
1718 */
1719static int __dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt)
1720{
1721 struct dwc3 *dwc = dep->dwc;
1722 struct dwc3_gadget_ep_cmd_params params;
1723 u32 cmd;
1724 int ret;
1725
1726 cmd = DWC3_DEPCMD_ENDTRANSFER;
1727 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
1728 cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
1729 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1730 memset(¶ms, 0, sizeof(params));
1731 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1732 /*
1733 * If the End Transfer command was timed out while the device is
1734 * not in SETUP phase, it's possible that an incoming Setup packet
1735 * may prevent the command's completion. Let's retry when the
1736 * ep0state returns to EP0_SETUP_PHASE.
1737 */
1738 if (ret == -ETIMEDOUT && dep->dwc->ep0state != EP0_SETUP_PHASE) {
1739 dep->flags |= DWC3_EP_DELAY_STOP;
1740 return 0;
1741 }
1742 WARN_ON_ONCE(ret);
1743 dep->resource_index = 0;
1744
1745 if (!interrupt) {
1746 if (!DWC3_IP_IS(DWC3) || DWC3_VER_IS_PRIOR(DWC3, 310A))
1747 mdelay(1);
1748 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1749 } else if (!ret) {
1750 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
1751 }
1752
1753 dep->flags &= ~DWC3_EP_DELAY_STOP;
1754 return ret;
1755}
1756
1757/**
1758 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1759 * @dep: isoc endpoint
1760 *
1761 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1762 * microframe number reported by the XferNotReady event for the future frame
1763 * number to start the isoc transfer.
1764 *
1765 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1766 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1767 * XferNotReady event are invalid. The driver uses this number to schedule the
1768 * isochronous transfer and passes it to the START TRANSFER command. Because
1769 * this number is invalid, the command may fail. If BIT[15:14] matches the
1770 * internal 16-bit microframe, the START TRANSFER command will pass and the
1771 * transfer will start at the scheduled time, if it is off by 1, the command
1772 * will still pass, but the transfer will start 2 seconds in the future. For all
1773 * other conditions, the START TRANSFER command will fail with bus-expiry.
1774 *
1775 * In order to workaround this issue, we can test for the correct combination of
1776 * BIT[15:14] by sending START TRANSFER commands with different values of
1777 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1778 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1779 * As the result, within the 4 possible combinations for BIT[15:14], there will
1780 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1781 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1782 * value is the correct combination.
1783 *
1784 * Since there are only 4 outcomes and the results are ordered, we can simply
1785 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1786 * deduce the smaller successful combination.
1787 *
1788 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1789 * of BIT[15:14]. The correct combination is as follow:
1790 *
1791 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1792 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1793 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1794 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1795 *
1796 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1797 * endpoints.
1798 */
1799static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1800{
1801 int cmd_status = 0;
1802 bool test0;
1803 bool test1;
1804
1805 while (dep->combo_num < 2) {
1806 struct dwc3_gadget_ep_cmd_params params;
1807 u32 test_frame_number;
1808 u32 cmd;
1809
1810 /*
1811 * Check if we can start isoc transfer on the next interval or
1812 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1813 */
1814 test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK;
1815 test_frame_number |= dep->combo_num << 14;
1816 test_frame_number += max_t(u32, 4, dep->interval);
1817
1818 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1819 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1820
1821 cmd = DWC3_DEPCMD_STARTTRANSFER;
1822 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1823 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1824
1825 /* Redo if some other failure beside bus-expiry is received */
1826 if (cmd_status && cmd_status != -EAGAIN) {
1827 dep->start_cmd_status = 0;
1828 dep->combo_num = 0;
1829 return 0;
1830 }
1831
1832 /* Store the first test status */
1833 if (dep->combo_num == 0)
1834 dep->start_cmd_status = cmd_status;
1835
1836 dep->combo_num++;
1837
1838 /*
1839 * End the transfer if the START_TRANSFER command is successful
1840 * to wait for the next XferNotReady to test the command again
1841 */
1842 if (cmd_status == 0) {
1843 dwc3_stop_active_transfer(dep, true, true);
1844 return 0;
1845 }
1846 }
1847
1848 /* test0 and test1 are both completed at this point */
1849 test0 = (dep->start_cmd_status == 0);
1850 test1 = (cmd_status == 0);
1851
1852 if (!test0 && test1)
1853 dep->combo_num = 1;
1854 else if (!test0 && !test1)
1855 dep->combo_num = 2;
1856 else if (test0 && !test1)
1857 dep->combo_num = 3;
1858 else if (test0 && test1)
1859 dep->combo_num = 0;
1860
1861 dep->frame_number &= DWC3_FRNUMBER_MASK;
1862 dep->frame_number |= dep->combo_num << 14;
1863 dep->frame_number += max_t(u32, 4, dep->interval);
1864
1865 /* Reinitialize test variables */
1866 dep->start_cmd_status = 0;
1867 dep->combo_num = 0;
1868
1869 return __dwc3_gadget_kick_transfer(dep);
1870}
1871
1872static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1873{
1874 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
1875 struct dwc3 *dwc = dep->dwc;
1876 int ret;
1877 int i;
1878
1879 if (list_empty(&dep->pending_list) &&
1880 list_empty(&dep->started_list)) {
1881 dep->flags |= DWC3_EP_PENDING_REQUEST;
1882 return -EAGAIN;
1883 }
1884
1885 if (!dwc->dis_start_transfer_quirk &&
1886 (DWC3_VER_IS_PRIOR(DWC31, 170A) ||
1887 DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) {
1888 if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction)
1889 return dwc3_gadget_start_isoc_quirk(dep);
1890 }
1891
1892 if (desc->bInterval <= 14 &&
1893 dwc->gadget->speed >= USB_SPEED_HIGH) {
1894 u32 frame = __dwc3_gadget_get_frame(dwc);
1895 bool rollover = frame <
1896 (dep->frame_number & DWC3_FRNUMBER_MASK);
1897
1898 /*
1899 * frame_number is set from XferNotReady and may be already
1900 * out of date. DSTS only provides the lower 14 bit of the
1901 * current frame number. So add the upper two bits of
1902 * frame_number and handle a possible rollover.
1903 * This will provide the correct frame_number unless more than
1904 * rollover has happened since XferNotReady.
1905 */
1906
1907 dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) |
1908 frame;
1909 if (rollover)
1910 dep->frame_number += BIT(14);
1911 }
1912
1913 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1914 int future_interval = i + 1;
1915
1916 /* Give the controller at least 500us to schedule transfers */
1917 if (desc->bInterval < 3)
1918 future_interval += 3 - desc->bInterval;
1919
1920 dep->frame_number = DWC3_ALIGN_FRAME(dep, future_interval);
1921
1922 ret = __dwc3_gadget_kick_transfer(dep);
1923 if (ret != -EAGAIN)
1924 break;
1925 }
1926
1927 /*
1928 * After a number of unsuccessful start attempts due to bus-expiry
1929 * status, issue END_TRANSFER command and retry on the next XferNotReady
1930 * event.
1931 */
1932 if (ret == -EAGAIN)
1933 ret = __dwc3_stop_active_transfer(dep, false, true);
1934
1935 return ret;
1936}
1937
1938static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1939{
1940 struct dwc3 *dwc = dep->dwc;
1941
1942 if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
1943 dev_dbg(dwc->dev, "%s: can't queue to disabled endpoint\n",
1944 dep->name);
1945 return -ESHUTDOWN;
1946 }
1947
1948 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1949 &req->request, req->dep->name))
1950 return -EINVAL;
1951
1952 if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1953 "%s: request %pK already in flight\n",
1954 dep->name, &req->request))
1955 return -EINVAL;
1956
1957 pm_runtime_get(dwc->dev);
1958
1959 req->request.actual = 0;
1960 req->request.status = -EINPROGRESS;
1961
1962 trace_dwc3_ep_queue(req);
1963
1964 list_add_tail(&req->list, &dep->pending_list);
1965 req->status = DWC3_REQUEST_STATUS_QUEUED;
1966
1967 if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)
1968 return 0;
1969
1970 /*
1971 * Start the transfer only after the END_TRANSFER is completed
1972 * and endpoint STALL is cleared.
1973 */
1974 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
1975 (dep->flags & DWC3_EP_WEDGE) ||
1976 (dep->flags & DWC3_EP_DELAY_STOP) ||
1977 (dep->flags & DWC3_EP_STALL)) {
1978 dep->flags |= DWC3_EP_DELAY_START;
1979 return 0;
1980 }
1981
1982 /*
1983 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1984 * wait for a XferNotReady event so we will know what's the current
1985 * (micro-)frame number.
1986 *
1987 * Without this trick, we are very, very likely gonna get Bus Expiry
1988 * errors which will force us issue EndTransfer command.
1989 */
1990 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1991 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1992 if ((dep->flags & DWC3_EP_PENDING_REQUEST))
1993 return __dwc3_gadget_start_isoc(dep);
1994
1995 return 0;
1996 }
1997 }
1998
1999 __dwc3_gadget_kick_transfer(dep);
2000
2001 return 0;
2002}
2003
2004static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
2005 gfp_t gfp_flags)
2006{
2007 struct dwc3_request *req = to_dwc3_request(request);
2008 struct dwc3_ep *dep = to_dwc3_ep(ep);
2009 struct dwc3 *dwc = dep->dwc;
2010
2011 unsigned long flags;
2012
2013 int ret;
2014
2015 spin_lock_irqsave(&dwc->lock, flags);
2016 ret = __dwc3_gadget_ep_queue(dep, req);
2017 spin_unlock_irqrestore(&dwc->lock, flags);
2018
2019 return ret;
2020}
2021
2022static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
2023{
2024 int i;
2025
2026 /* If req->trb is not set, then the request has not started */
2027 if (!req->trb)
2028 return;
2029
2030 /*
2031 * If request was already started, this means we had to
2032 * stop the transfer. With that we also need to ignore
2033 * all TRBs used by the request, however TRBs can only
2034 * be modified after completion of END_TRANSFER
2035 * command. So what we do here is that we wait for
2036 * END_TRANSFER completion and only after that, we jump
2037 * over TRBs by clearing HWO and incrementing dequeue
2038 * pointer.
2039 */
2040 for (i = 0; i < req->num_trbs; i++) {
2041 struct dwc3_trb *trb;
2042
2043 trb = &dep->trb_pool[dep->trb_dequeue];
2044 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2045 dwc3_ep_inc_deq(dep);
2046 }
2047
2048 req->num_trbs = 0;
2049}
2050
2051static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
2052{
2053 struct dwc3_request *req;
2054 struct dwc3 *dwc = dep->dwc;
2055
2056 while (!list_empty(&dep->cancelled_list)) {
2057 req = next_request(&dep->cancelled_list);
2058 dwc3_gadget_ep_skip_trbs(dep, req);
2059 switch (req->status) {
2060 case DWC3_REQUEST_STATUS_DISCONNECTED:
2061 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
2062 break;
2063 case DWC3_REQUEST_STATUS_DEQUEUED:
2064 dwc3_gadget_giveback(dep, req, -ECONNRESET);
2065 break;
2066 case DWC3_REQUEST_STATUS_STALLED:
2067 dwc3_gadget_giveback(dep, req, -EPIPE);
2068 break;
2069 default:
2070 dev_err(dwc->dev, "request cancelled with wrong reason:%d\n", req->status);
2071 dwc3_gadget_giveback(dep, req, -ECONNRESET);
2072 break;
2073 }
2074 /*
2075 * The endpoint is disabled, let the dwc3_remove_requests()
2076 * handle the cleanup.
2077 */
2078 if (!dep->endpoint.desc)
2079 break;
2080 }
2081}
2082
2083static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
2084 struct usb_request *request)
2085{
2086 struct dwc3_request *req = to_dwc3_request(request);
2087 struct dwc3_request *r = NULL;
2088
2089 struct dwc3_ep *dep = to_dwc3_ep(ep);
2090 struct dwc3 *dwc = dep->dwc;
2091
2092 unsigned long flags;
2093 int ret = 0;
2094
2095 trace_dwc3_ep_dequeue(req);
2096
2097 spin_lock_irqsave(&dwc->lock, flags);
2098
2099 list_for_each_entry(r, &dep->cancelled_list, list) {
2100 if (r == req)
2101 goto out;
2102 }
2103
2104 list_for_each_entry(r, &dep->pending_list, list) {
2105 if (r == req) {
2106 /*
2107 * Explicitly check for EP0/1 as dequeue for those
2108 * EPs need to be handled differently. Control EP
2109 * only deals with one USB req, and giveback will
2110 * occur during dwc3_ep0_stall_and_restart(). EP0
2111 * requests are never added to started_list.
2112 */
2113 if (dep->number > 1)
2114 dwc3_gadget_giveback(dep, req, -ECONNRESET);
2115 else
2116 dwc3_ep0_reset_state(dwc);
2117 goto out;
2118 }
2119 }
2120
2121 list_for_each_entry(r, &dep->started_list, list) {
2122 if (r == req) {
2123 struct dwc3_request *t;
2124
2125 /* wait until it is processed */
2126 dwc3_stop_active_transfer(dep, true, true);
2127
2128 /*
2129 * Remove any started request if the transfer is
2130 * cancelled.
2131 */
2132 list_for_each_entry_safe(r, t, &dep->started_list, list)
2133 dwc3_gadget_move_cancelled_request(r,
2134 DWC3_REQUEST_STATUS_DEQUEUED);
2135
2136 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
2137
2138 goto out;
2139 }
2140 }
2141
2142 dev_err(dwc->dev, "request %pK was not queued to %s\n",
2143 request, ep->name);
2144 ret = -EINVAL;
2145out:
2146 spin_unlock_irqrestore(&dwc->lock, flags);
2147
2148 return ret;
2149}
2150
2151int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
2152{
2153 struct dwc3_gadget_ep_cmd_params params;
2154 struct dwc3 *dwc = dep->dwc;
2155 struct dwc3_request *req;
2156 struct dwc3_request *tmp;
2157 int ret;
2158
2159 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2160 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
2161 return -EINVAL;
2162 }
2163
2164 memset(¶ms, 0x00, sizeof(params));
2165
2166 if (value) {
2167 struct dwc3_trb *trb;
2168
2169 unsigned int transfer_in_flight;
2170 unsigned int started;
2171
2172 if (dep->number > 1)
2173 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
2174 else
2175 trb = &dwc->ep0_trb[dep->trb_enqueue];
2176
2177 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
2178 started = !list_empty(&dep->started_list);
2179
2180 if (!protocol && ((dep->direction && transfer_in_flight) ||
2181 (!dep->direction && started))) {
2182 return -EAGAIN;
2183 }
2184
2185 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
2186 ¶ms);
2187 if (ret)
2188 dev_err(dwc->dev, "failed to set STALL on %s\n",
2189 dep->name);
2190 else
2191 dep->flags |= DWC3_EP_STALL;
2192 } else {
2193 /*
2194 * Don't issue CLEAR_STALL command to control endpoints. The
2195 * controller automatically clears the STALL when it receives
2196 * the SETUP token.
2197 */
2198 if (dep->number <= 1) {
2199 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2200 return 0;
2201 }
2202
2203 dwc3_stop_active_transfer(dep, true, true);
2204
2205 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
2206 dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_STALLED);
2207
2208 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING ||
2209 (dep->flags & DWC3_EP_DELAY_STOP)) {
2210 dep->flags |= DWC3_EP_PENDING_CLEAR_STALL;
2211 if (protocol)
2212 dwc->clear_stall_protocol = dep->number;
2213
2214 return 0;
2215 }
2216
2217 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2218
2219 ret = dwc3_send_clear_stall_ep_cmd(dep);
2220 if (ret) {
2221 dev_err(dwc->dev, "failed to clear STALL on %s\n",
2222 dep->name);
2223 return ret;
2224 }
2225
2226 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2227
2228 if ((dep->flags & DWC3_EP_DELAY_START) &&
2229 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
2230 __dwc3_gadget_kick_transfer(dep);
2231
2232 dep->flags &= ~DWC3_EP_DELAY_START;
2233 }
2234
2235 return ret;
2236}
2237
2238static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
2239{
2240 struct dwc3_ep *dep = to_dwc3_ep(ep);
2241 struct dwc3 *dwc = dep->dwc;
2242
2243 unsigned long flags;
2244
2245 int ret;
2246
2247 spin_lock_irqsave(&dwc->lock, flags);
2248 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
2249 spin_unlock_irqrestore(&dwc->lock, flags);
2250
2251 return ret;
2252}
2253
2254static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
2255{
2256 struct dwc3_ep *dep = to_dwc3_ep(ep);
2257 struct dwc3 *dwc = dep->dwc;
2258 unsigned long flags;
2259 int ret;
2260
2261 spin_lock_irqsave(&dwc->lock, flags);
2262 dep->flags |= DWC3_EP_WEDGE;
2263
2264 if (dep->number == 0 || dep->number == 1)
2265 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
2266 else
2267 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
2268 spin_unlock_irqrestore(&dwc->lock, flags);
2269
2270 return ret;
2271}
2272
2273/* -------------------------------------------------------------------------- */
2274
2275static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
2276 .bLength = USB_DT_ENDPOINT_SIZE,
2277 .bDescriptorType = USB_DT_ENDPOINT,
2278 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
2279};
2280
2281static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
2282 .enable = dwc3_gadget_ep0_enable,
2283 .disable = dwc3_gadget_ep0_disable,
2284 .alloc_request = dwc3_gadget_ep_alloc_request,
2285 .free_request = dwc3_gadget_ep_free_request,
2286 .queue = dwc3_gadget_ep0_queue,
2287 .dequeue = dwc3_gadget_ep_dequeue,
2288 .set_halt = dwc3_gadget_ep0_set_halt,
2289 .set_wedge = dwc3_gadget_ep_set_wedge,
2290};
2291
2292static const struct usb_ep_ops dwc3_gadget_ep_ops = {
2293 .enable = dwc3_gadget_ep_enable,
2294 .disable = dwc3_gadget_ep_disable,
2295 .alloc_request = dwc3_gadget_ep_alloc_request,
2296 .free_request = dwc3_gadget_ep_free_request,
2297 .queue = dwc3_gadget_ep_queue,
2298 .dequeue = dwc3_gadget_ep_dequeue,
2299 .set_halt = dwc3_gadget_ep_set_halt,
2300 .set_wedge = dwc3_gadget_ep_set_wedge,
2301};
2302
2303/* -------------------------------------------------------------------------- */
2304
2305static void dwc3_gadget_enable_linksts_evts(struct dwc3 *dwc, bool set)
2306{
2307 u32 reg;
2308
2309 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2310 return;
2311
2312 reg = dwc3_readl(dwc->regs, DWC3_DEVTEN);
2313 if (set)
2314 reg |= DWC3_DEVTEN_ULSTCNGEN;
2315 else
2316 reg &= ~DWC3_DEVTEN_ULSTCNGEN;
2317
2318 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2319}
2320
2321static int dwc3_gadget_get_frame(struct usb_gadget *g)
2322{
2323 struct dwc3 *dwc = gadget_to_dwc(g);
2324
2325 return __dwc3_gadget_get_frame(dwc);
2326}
2327
2328static int __dwc3_gadget_wakeup(struct dwc3 *dwc, bool async)
2329{
2330 int retries;
2331
2332 int ret;
2333 u32 reg;
2334
2335 u8 link_state;
2336
2337 /*
2338 * According to the Databook Remote wakeup request should
2339 * be issued only when the device is in early suspend state.
2340 *
2341 * We can check that via USB Link State bits in DSTS register.
2342 */
2343 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2344
2345 link_state = DWC3_DSTS_USBLNKST(reg);
2346
2347 switch (link_state) {
2348 case DWC3_LINK_STATE_RESET:
2349 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
2350 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
2351 case DWC3_LINK_STATE_U2: /* in HS, means Sleep (L1) */
2352 case DWC3_LINK_STATE_U1:
2353 case DWC3_LINK_STATE_RESUME:
2354 break;
2355 default:
2356 return -EINVAL;
2357 }
2358
2359 if (async)
2360 dwc3_gadget_enable_linksts_evts(dwc, true);
2361
2362 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
2363 if (ret < 0) {
2364 dev_err(dwc->dev, "failed to put link in Recovery\n");
2365 dwc3_gadget_enable_linksts_evts(dwc, false);
2366 return ret;
2367 }
2368
2369 /* Recent versions do this automatically */
2370 if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
2371 /* write zeroes to Link Change Request */
2372 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2373 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
2374 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2375 }
2376
2377 /*
2378 * Since link status change events are enabled we will receive
2379 * an U0 event when wakeup is successful. So bail out.
2380 */
2381 if (async)
2382 return 0;
2383
2384 /* poll until Link State changes to ON */
2385 retries = 20000;
2386
2387 while (retries--) {
2388 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2389
2390 /* in HS, means ON */
2391 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
2392 break;
2393 }
2394
2395 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
2396 dev_err(dwc->dev, "failed to send remote wakeup\n");
2397 return -EINVAL;
2398 }
2399
2400 return 0;
2401}
2402
2403static int dwc3_gadget_wakeup(struct usb_gadget *g)
2404{
2405 struct dwc3 *dwc = gadget_to_dwc(g);
2406 unsigned long flags;
2407 int ret;
2408
2409 if (!dwc->wakeup_configured) {
2410 dev_err(dwc->dev, "remote wakeup not configured\n");
2411 return -EINVAL;
2412 }
2413
2414 spin_lock_irqsave(&dwc->lock, flags);
2415 if (!dwc->gadget->wakeup_armed) {
2416 dev_err(dwc->dev, "not armed for remote wakeup\n");
2417 spin_unlock_irqrestore(&dwc->lock, flags);
2418 return -EINVAL;
2419 }
2420 ret = __dwc3_gadget_wakeup(dwc, true);
2421
2422 spin_unlock_irqrestore(&dwc->lock, flags);
2423
2424 return ret;
2425}
2426
2427static void dwc3_resume_gadget(struct dwc3 *dwc);
2428
2429static int dwc3_gadget_func_wakeup(struct usb_gadget *g, int intf_id)
2430{
2431 struct dwc3 *dwc = gadget_to_dwc(g);
2432 unsigned long flags;
2433 int ret;
2434 int link_state;
2435
2436 if (!dwc->wakeup_configured) {
2437 dev_err(dwc->dev, "remote wakeup not configured\n");
2438 return -EINVAL;
2439 }
2440
2441 spin_lock_irqsave(&dwc->lock, flags);
2442 /*
2443 * If the link is in U3, signal for remote wakeup and wait for the
2444 * link to transition to U0 before sending device notification.
2445 */
2446 link_state = dwc3_gadget_get_link_state(dwc);
2447 if (link_state == DWC3_LINK_STATE_U3) {
2448 ret = __dwc3_gadget_wakeup(dwc, false);
2449 if (ret) {
2450 spin_unlock_irqrestore(&dwc->lock, flags);
2451 return -EINVAL;
2452 }
2453 dwc3_resume_gadget(dwc);
2454 dwc->suspended = false;
2455 dwc->link_state = DWC3_LINK_STATE_U0;
2456 }
2457
2458 ret = dwc3_send_gadget_generic_command(dwc, DWC3_DGCMD_DEV_NOTIFICATION,
2459 DWC3_DGCMDPAR_DN_FUNC_WAKE |
2460 DWC3_DGCMDPAR_INTF_SEL(intf_id));
2461 if (ret)
2462 dev_err(dwc->dev, "function remote wakeup failed, ret:%d\n", ret);
2463
2464 spin_unlock_irqrestore(&dwc->lock, flags);
2465
2466 return ret;
2467}
2468
2469static int dwc3_gadget_set_remote_wakeup(struct usb_gadget *g, int set)
2470{
2471 struct dwc3 *dwc = gadget_to_dwc(g);
2472 unsigned long flags;
2473
2474 spin_lock_irqsave(&dwc->lock, flags);
2475 dwc->wakeup_configured = !!set;
2476 spin_unlock_irqrestore(&dwc->lock, flags);
2477
2478 return 0;
2479}
2480
2481static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
2482 int is_selfpowered)
2483{
2484 struct dwc3 *dwc = gadget_to_dwc(g);
2485 unsigned long flags;
2486
2487 spin_lock_irqsave(&dwc->lock, flags);
2488 g->is_selfpowered = !!is_selfpowered;
2489 spin_unlock_irqrestore(&dwc->lock, flags);
2490
2491 return 0;
2492}
2493
2494static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2495{
2496 u32 epnum;
2497
2498 for (epnum = 2; epnum < dwc->num_eps; epnum++) {
2499 struct dwc3_ep *dep;
2500
2501 dep = dwc->eps[epnum];
2502 if (!dep)
2503 continue;
2504
2505 dwc3_remove_requests(dwc, dep, -ESHUTDOWN);
2506 }
2507}
2508
2509static void __dwc3_gadget_set_ssp_rate(struct dwc3 *dwc)
2510{
2511 enum usb_ssp_rate ssp_rate = dwc->gadget_ssp_rate;
2512 u32 reg;
2513
2514 if (ssp_rate == USB_SSP_GEN_UNKNOWN)
2515 ssp_rate = dwc->max_ssp_rate;
2516
2517 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2518 reg &= ~DWC3_DCFG_SPEED_MASK;
2519 reg &= ~DWC3_DCFG_NUMLANES(~0);
2520
2521 if (ssp_rate == USB_SSP_GEN_1x2)
2522 reg |= DWC3_DCFG_SUPERSPEED;
2523 else if (dwc->max_ssp_rate != USB_SSP_GEN_1x2)
2524 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2525
2526 if (ssp_rate != USB_SSP_GEN_2x1 &&
2527 dwc->max_ssp_rate != USB_SSP_GEN_2x1)
2528 reg |= DWC3_DCFG_NUMLANES(1);
2529
2530 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2531}
2532
2533static void __dwc3_gadget_set_speed(struct dwc3 *dwc)
2534{
2535 enum usb_device_speed speed;
2536 u32 reg;
2537
2538 speed = dwc->gadget_max_speed;
2539 if (speed == USB_SPEED_UNKNOWN || speed > dwc->maximum_speed)
2540 speed = dwc->maximum_speed;
2541
2542 if (speed == USB_SPEED_SUPER_PLUS &&
2543 DWC3_IP_IS(DWC32)) {
2544 __dwc3_gadget_set_ssp_rate(dwc);
2545 return;
2546 }
2547
2548 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2549 reg &= ~(DWC3_DCFG_SPEED_MASK);
2550
2551 /*
2552 * WORKAROUND: DWC3 revision < 2.20a have an issue
2553 * which would cause metastability state on Run/Stop
2554 * bit if we try to force the IP to USB2-only mode.
2555 *
2556 * Because of that, we cannot configure the IP to any
2557 * speed other than the SuperSpeed
2558 *
2559 * Refers to:
2560 *
2561 * STAR#9000525659: Clock Domain Crossing on DCTL in
2562 * USB 2.0 Mode
2563 */
2564 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
2565 !dwc->dis_metastability_quirk) {
2566 reg |= DWC3_DCFG_SUPERSPEED;
2567 } else {
2568 switch (speed) {
2569 case USB_SPEED_FULL:
2570 reg |= DWC3_DCFG_FULLSPEED;
2571 break;
2572 case USB_SPEED_HIGH:
2573 reg |= DWC3_DCFG_HIGHSPEED;
2574 break;
2575 case USB_SPEED_SUPER:
2576 reg |= DWC3_DCFG_SUPERSPEED;
2577 break;
2578 case USB_SPEED_SUPER_PLUS:
2579 if (DWC3_IP_IS(DWC3))
2580 reg |= DWC3_DCFG_SUPERSPEED;
2581 else
2582 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2583 break;
2584 default:
2585 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2586
2587 if (DWC3_IP_IS(DWC3))
2588 reg |= DWC3_DCFG_SUPERSPEED;
2589 else
2590 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2591 }
2592 }
2593
2594 if (DWC3_IP_IS(DWC32) &&
2595 speed > USB_SPEED_UNKNOWN &&
2596 speed < USB_SPEED_SUPER_PLUS)
2597 reg &= ~DWC3_DCFG_NUMLANES(~0);
2598
2599 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2600}
2601
2602static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
2603{
2604 u32 reg;
2605 u32 timeout = 2000;
2606
2607 if (pm_runtime_suspended(dwc->dev))
2608 return 0;
2609
2610 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2611 if (is_on) {
2612 if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
2613 reg &= ~DWC3_DCTL_TRGTULST_MASK;
2614 reg |= DWC3_DCTL_TRGTULST_RX_DET;
2615 }
2616
2617 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
2618 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2619 reg |= DWC3_DCTL_RUN_STOP;
2620
2621 __dwc3_gadget_set_speed(dwc);
2622 dwc->pullups_connected = true;
2623 } else {
2624 reg &= ~DWC3_DCTL_RUN_STOP;
2625
2626 dwc->pullups_connected = false;
2627 }
2628
2629 dwc3_gadget_dctl_write_safe(dwc, reg);
2630
2631 do {
2632 usleep_range(1000, 2000);
2633 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2634 reg &= DWC3_DSTS_DEVCTRLHLT;
2635 } while (--timeout && !(!is_on ^ !reg));
2636
2637 if (!timeout)
2638 return -ETIMEDOUT;
2639
2640 return 0;
2641}
2642
2643static void dwc3_gadget_disable_irq(struct dwc3 *dwc);
2644static void __dwc3_gadget_stop(struct dwc3 *dwc);
2645static int __dwc3_gadget_start(struct dwc3 *dwc);
2646
2647static int dwc3_gadget_soft_disconnect(struct dwc3 *dwc)
2648{
2649 unsigned long flags;
2650 int ret;
2651
2652 spin_lock_irqsave(&dwc->lock, flags);
2653 if (!dwc->pullups_connected) {
2654 spin_unlock_irqrestore(&dwc->lock, flags);
2655 return 0;
2656 }
2657
2658 dwc->connected = false;
2659
2660 /*
2661 * Attempt to end pending SETUP status phase, and not wait for the
2662 * function to do so.
2663 */
2664 if (dwc->delayed_status)
2665 dwc3_ep0_send_delayed_status(dwc);
2666
2667 /*
2668 * In the Synopsys DesignWare Cores USB3 Databook Rev. 3.30a
2669 * Section 4.1.8 Table 4-7, it states that for a device-initiated
2670 * disconnect, the SW needs to ensure that it sends "a DEPENDXFER
2671 * command for any active transfers" before clearing the RunStop
2672 * bit.
2673 */
2674 dwc3_stop_active_transfers(dwc);
2675 spin_unlock_irqrestore(&dwc->lock, flags);
2676
2677 /*
2678 * Per databook, when we want to stop the gadget, if a control transfer
2679 * is still in process, complete it and get the core into setup phase.
2680 * In case the host is unresponsive to a SETUP transaction, forcefully
2681 * stall the transfer, and move back to the SETUP phase, so that any
2682 * pending endxfers can be executed.
2683 */
2684 if (dwc->ep0state != EP0_SETUP_PHASE) {
2685 reinit_completion(&dwc->ep0_in_setup);
2686
2687 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
2688 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
2689 if (ret == 0) {
2690 dev_warn(dwc->dev, "wait for SETUP phase timed out\n");
2691 spin_lock_irqsave(&dwc->lock, flags);
2692 dwc3_ep0_reset_state(dwc);
2693 spin_unlock_irqrestore(&dwc->lock, flags);
2694 }
2695 }
2696
2697 /*
2698 * Note: if the GEVNTCOUNT indicates events in the event buffer, the
2699 * driver needs to acknowledge them before the controller can halt.
2700 * Simply let the interrupt handler acknowledges and handle the
2701 * remaining event generated by the controller while polling for
2702 * DSTS.DEVCTLHLT.
2703 */
2704 ret = dwc3_gadget_run_stop(dwc, false);
2705
2706 /*
2707 * Stop the gadget after controller is halted, so that if needed, the
2708 * events to update EP0 state can still occur while the run/stop
2709 * routine polls for the halted state. DEVTEN is cleared as part of
2710 * gadget stop.
2711 */
2712 spin_lock_irqsave(&dwc->lock, flags);
2713 __dwc3_gadget_stop(dwc);
2714 spin_unlock_irqrestore(&dwc->lock, flags);
2715
2716 return ret;
2717}
2718
2719static int dwc3_gadget_soft_connect(struct dwc3 *dwc)
2720{
2721 int ret;
2722
2723 /*
2724 * In the Synopsys DWC_usb31 1.90a programming guide section
2725 * 4.1.9, it specifies that for a reconnect after a
2726 * device-initiated disconnect requires a core soft reset
2727 * (DCTL.CSftRst) before enabling the run/stop bit.
2728 */
2729 ret = dwc3_core_soft_reset(dwc);
2730 if (ret)
2731 return ret;
2732
2733 dwc3_event_buffers_setup(dwc);
2734 __dwc3_gadget_start(dwc);
2735 return dwc3_gadget_run_stop(dwc, true);
2736}
2737
2738static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
2739{
2740 struct dwc3 *dwc = gadget_to_dwc(g);
2741 int ret;
2742
2743 is_on = !!is_on;
2744
2745 dwc->softconnect = is_on;
2746
2747 /*
2748 * Avoid issuing a runtime resume if the device is already in the
2749 * suspended state during gadget disconnect. DWC3 gadget was already
2750 * halted/stopped during runtime suspend.
2751 */
2752 if (!is_on) {
2753 pm_runtime_barrier(dwc->dev);
2754 if (pm_runtime_suspended(dwc->dev))
2755 return 0;
2756 }
2757
2758 /*
2759 * Check the return value for successful resume, or error. For a
2760 * successful resume, the DWC3 runtime PM resume routine will handle
2761 * the run stop sequence, so avoid duplicate operations here.
2762 */
2763 ret = pm_runtime_get_sync(dwc->dev);
2764 if (!ret || ret < 0) {
2765 pm_runtime_put(dwc->dev);
2766 if (ret < 0)
2767 pm_runtime_set_suspended(dwc->dev);
2768 return ret;
2769 }
2770
2771 if (dwc->pullups_connected == is_on) {
2772 pm_runtime_put(dwc->dev);
2773 return 0;
2774 }
2775
2776 synchronize_irq(dwc->irq_gadget);
2777
2778 if (!is_on)
2779 ret = dwc3_gadget_soft_disconnect(dwc);
2780 else
2781 ret = dwc3_gadget_soft_connect(dwc);
2782
2783 pm_runtime_put(dwc->dev);
2784
2785 return ret;
2786}
2787
2788static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
2789{
2790 u32 reg;
2791
2792 /* Enable all but Start and End of Frame IRQs */
2793 reg = (DWC3_DEVTEN_EVNTOVERFLOWEN |
2794 DWC3_DEVTEN_CMDCMPLTEN |
2795 DWC3_DEVTEN_ERRTICERREN |
2796 DWC3_DEVTEN_WKUPEVTEN |
2797 DWC3_DEVTEN_CONNECTDONEEN |
2798 DWC3_DEVTEN_USBRSTEN |
2799 DWC3_DEVTEN_DISCONNEVTEN);
2800
2801 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2802 reg |= DWC3_DEVTEN_ULSTCNGEN;
2803
2804 /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
2805 if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
2806 reg |= DWC3_DEVTEN_U3L2L1SUSPEN;
2807
2808 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2809}
2810
2811static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
2812{
2813 /* mask all interrupts */
2814 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2815}
2816
2817static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
2818static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
2819
2820/**
2821 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
2822 * @dwc: pointer to our context structure
2823 *
2824 * The following looks like complex but it's actually very simple. In order to
2825 * calculate the number of packets we can burst at once on OUT transfers, we're
2826 * gonna use RxFIFO size.
2827 *
2828 * To calculate RxFIFO size we need two numbers:
2829 * MDWIDTH = size, in bits, of the internal memory bus
2830 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
2831 *
2832 * Given these two numbers, the formula is simple:
2833 *
2834 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
2835 *
2836 * 24 bytes is for 3x SETUP packets
2837 * 16 bytes is a clock domain crossing tolerance
2838 *
2839 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
2840 */
2841static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
2842{
2843 u32 ram2_depth;
2844 u32 mdwidth;
2845 u32 nump;
2846 u32 reg;
2847
2848 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
2849 mdwidth = dwc3_mdwidth(dwc);
2850
2851 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
2852 nump = min_t(u32, nump, 16);
2853
2854 /* update NumP */
2855 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2856 reg &= ~DWC3_DCFG_NUMP_MASK;
2857 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2858 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2859}
2860
2861static int __dwc3_gadget_start(struct dwc3 *dwc)
2862{
2863 struct dwc3_ep *dep;
2864 int ret = 0;
2865 u32 reg;
2866
2867 /*
2868 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
2869 * the core supports IMOD, disable it.
2870 */
2871 if (dwc->imod_interval) {
2872 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2873 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2874 } else if (dwc3_has_imod(dwc)) {
2875 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
2876 }
2877
2878 /*
2879 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
2880 * field instead of letting dwc3 itself calculate that automatically.
2881 *
2882 * This way, we maximize the chances that we'll be able to get several
2883 * bursts of data without going through any sort of endpoint throttling.
2884 */
2885 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2886 if (DWC3_IP_IS(DWC3))
2887 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2888 else
2889 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2890
2891 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2892
2893 dwc3_gadget_setup_nump(dwc);
2894
2895 /*
2896 * Currently the controller handles single stream only. So, Ignore
2897 * Packet Pending bit for stream selection and don't search for another
2898 * stream if the host sends Data Packet with PP=0 (for OUT direction) or
2899 * ACK with NumP=0 and PP=0 (for IN direction). This slightly improves
2900 * the stream performance.
2901 */
2902 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2903 reg |= DWC3_DCFG_IGNSTRMPP;
2904 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2905
2906 /* Enable MST by default if the device is capable of MST */
2907 if (DWC3_MST_CAPABLE(&dwc->hwparams)) {
2908 reg = dwc3_readl(dwc->regs, DWC3_DCFG1);
2909 reg &= ~DWC3_DCFG1_DIS_MST_ENH;
2910 dwc3_writel(dwc->regs, DWC3_DCFG1, reg);
2911 }
2912
2913 /* Start with SuperSpeed Default */
2914 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2915
2916 dep = dwc->eps[0];
2917 dep->flags = 0;
2918 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2919 if (ret) {
2920 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2921 goto err0;
2922 }
2923
2924 dep = dwc->eps[1];
2925 dep->flags = 0;
2926 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2927 if (ret) {
2928 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2929 goto err1;
2930 }
2931
2932 /* begin to receive SETUP packets */
2933 dwc->ep0state = EP0_SETUP_PHASE;
2934 dwc->ep0_bounced = false;
2935 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
2936 dwc->delayed_status = false;
2937 dwc3_ep0_out_start(dwc);
2938
2939 dwc3_gadget_enable_irq(dwc);
2940
2941 return 0;
2942
2943err1:
2944 __dwc3_gadget_ep_disable(dwc->eps[0]);
2945
2946err0:
2947 return ret;
2948}
2949
2950static int dwc3_gadget_start(struct usb_gadget *g,
2951 struct usb_gadget_driver *driver)
2952{
2953 struct dwc3 *dwc = gadget_to_dwc(g);
2954 unsigned long flags;
2955 int ret;
2956 int irq;
2957
2958 irq = dwc->irq_gadget;
2959 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2960 IRQF_SHARED, "dwc3", dwc->ev_buf);
2961 if (ret) {
2962 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2963 irq, ret);
2964 return ret;
2965 }
2966
2967 spin_lock_irqsave(&dwc->lock, flags);
2968 dwc->gadget_driver = driver;
2969 spin_unlock_irqrestore(&dwc->lock, flags);
2970
2971 return 0;
2972}
2973
2974static void __dwc3_gadget_stop(struct dwc3 *dwc)
2975{
2976 dwc3_gadget_disable_irq(dwc);
2977 __dwc3_gadget_ep_disable(dwc->eps[0]);
2978 __dwc3_gadget_ep_disable(dwc->eps[1]);
2979}
2980
2981static int dwc3_gadget_stop(struct usb_gadget *g)
2982{
2983 struct dwc3 *dwc = gadget_to_dwc(g);
2984 unsigned long flags;
2985
2986 spin_lock_irqsave(&dwc->lock, flags);
2987 dwc->gadget_driver = NULL;
2988 dwc->max_cfg_eps = 0;
2989 spin_unlock_irqrestore(&dwc->lock, flags);
2990
2991 free_irq(dwc->irq_gadget, dwc->ev_buf);
2992
2993 return 0;
2994}
2995
2996static void dwc3_gadget_config_params(struct usb_gadget *g,
2997 struct usb_dcd_config_params *params)
2998{
2999 struct dwc3 *dwc = gadget_to_dwc(g);
3000
3001 params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
3002 params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
3003
3004 /* Recommended BESL */
3005 if (!dwc->dis_enblslpm_quirk) {
3006 /*
3007 * If the recommended BESL baseline is 0 or if the BESL deep is
3008 * less than 2, Microsoft's Windows 10 host usb stack will issue
3009 * a usb reset immediately after it receives the extended BOS
3010 * descriptor and the enumeration will fail. To maintain
3011 * compatibility with the Windows' usb stack, let's set the
3012 * recommended BESL baseline to 1 and clamp the BESL deep to be
3013 * within 2 to 15.
3014 */
3015 params->besl_baseline = 1;
3016 if (dwc->is_utmi_l1_suspend)
3017 params->besl_deep =
3018 clamp_t(u8, dwc->hird_threshold, 2, 15);
3019 }
3020
3021 /* U1 Device exit Latency */
3022 if (dwc->dis_u1_entry_quirk)
3023 params->bU1devExitLat = 0;
3024 else
3025 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
3026
3027 /* U2 Device exit Latency */
3028 if (dwc->dis_u2_entry_quirk)
3029 params->bU2DevExitLat = 0;
3030 else
3031 params->bU2DevExitLat =
3032 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
3033}
3034
3035static void dwc3_gadget_set_speed(struct usb_gadget *g,
3036 enum usb_device_speed speed)
3037{
3038 struct dwc3 *dwc = gadget_to_dwc(g);
3039 unsigned long flags;
3040
3041 spin_lock_irqsave(&dwc->lock, flags);
3042 dwc->gadget_max_speed = speed;
3043 spin_unlock_irqrestore(&dwc->lock, flags);
3044}
3045
3046static void dwc3_gadget_set_ssp_rate(struct usb_gadget *g,
3047 enum usb_ssp_rate rate)
3048{
3049 struct dwc3 *dwc = gadget_to_dwc(g);
3050 unsigned long flags;
3051
3052 spin_lock_irqsave(&dwc->lock, flags);
3053 dwc->gadget_max_speed = USB_SPEED_SUPER_PLUS;
3054 dwc->gadget_ssp_rate = rate;
3055 spin_unlock_irqrestore(&dwc->lock, flags);
3056}
3057
3058static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
3059{
3060 struct dwc3 *dwc = gadget_to_dwc(g);
3061 union power_supply_propval val = {0};
3062 int ret;
3063
3064 if (dwc->usb2_phy)
3065 return usb_phy_set_power(dwc->usb2_phy, mA);
3066
3067 if (!dwc->usb_psy)
3068 return -EOPNOTSUPP;
3069
3070 val.intval = 1000 * mA;
3071 ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val);
3072
3073 return ret;
3074}
3075
3076/**
3077 * dwc3_gadget_check_config - ensure dwc3 can support the USB configuration
3078 * @g: pointer to the USB gadget
3079 *
3080 * Used to record the maximum number of endpoints being used in a USB composite
3081 * device. (across all configurations) This is to be used in the calculation
3082 * of the TXFIFO sizes when resizing internal memory for individual endpoints.
3083 * It will help ensured that the resizing logic reserves enough space for at
3084 * least one max packet.
3085 */
3086static int dwc3_gadget_check_config(struct usb_gadget *g)
3087{
3088 struct dwc3 *dwc = gadget_to_dwc(g);
3089 struct usb_ep *ep;
3090 int fifo_size = 0;
3091 int ram1_depth;
3092 int ep_num = 0;
3093
3094 if (!dwc->do_fifo_resize)
3095 return 0;
3096
3097 list_for_each_entry(ep, &g->ep_list, ep_list) {
3098 /* Only interested in the IN endpoints */
3099 if (ep->claimed && (ep->address & USB_DIR_IN))
3100 ep_num++;
3101 }
3102
3103 if (ep_num <= dwc->max_cfg_eps)
3104 return 0;
3105
3106 /* Update the max number of eps in the composition */
3107 dwc->max_cfg_eps = ep_num;
3108
3109 fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
3110 /* Based on the equation, increment by one for every ep */
3111 fifo_size += dwc->max_cfg_eps;
3112
3113 /* Check if we can fit a single fifo per endpoint */
3114 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
3115 if (fifo_size > ram1_depth)
3116 return -ENOMEM;
3117
3118 return 0;
3119}
3120
3121static void dwc3_gadget_async_callbacks(struct usb_gadget *g, bool enable)
3122{
3123 struct dwc3 *dwc = gadget_to_dwc(g);
3124 unsigned long flags;
3125
3126 spin_lock_irqsave(&dwc->lock, flags);
3127 dwc->async_callbacks = enable;
3128 spin_unlock_irqrestore(&dwc->lock, flags);
3129}
3130
3131static const struct usb_gadget_ops dwc3_gadget_ops = {
3132 .get_frame = dwc3_gadget_get_frame,
3133 .wakeup = dwc3_gadget_wakeup,
3134 .func_wakeup = dwc3_gadget_func_wakeup,
3135 .set_remote_wakeup = dwc3_gadget_set_remote_wakeup,
3136 .set_selfpowered = dwc3_gadget_set_selfpowered,
3137 .pullup = dwc3_gadget_pullup,
3138 .udc_start = dwc3_gadget_start,
3139 .udc_stop = dwc3_gadget_stop,
3140 .udc_set_speed = dwc3_gadget_set_speed,
3141 .udc_set_ssp_rate = dwc3_gadget_set_ssp_rate,
3142 .get_config_params = dwc3_gadget_config_params,
3143 .vbus_draw = dwc3_gadget_vbus_draw,
3144 .check_config = dwc3_gadget_check_config,
3145 .udc_async_callbacks = dwc3_gadget_async_callbacks,
3146};
3147
3148/* -------------------------------------------------------------------------- */
3149
3150static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
3151{
3152 struct dwc3 *dwc = dep->dwc;
3153
3154 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
3155 dep->endpoint.maxburst = 1;
3156 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
3157 if (!dep->direction)
3158 dwc->gadget->ep0 = &dep->endpoint;
3159
3160 dep->endpoint.caps.type_control = true;
3161
3162 return 0;
3163}
3164
3165static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
3166{
3167 struct dwc3 *dwc = dep->dwc;
3168 u32 mdwidth;
3169 int size;
3170 int maxpacket;
3171
3172 mdwidth = dwc3_mdwidth(dwc);
3173
3174 /* MDWIDTH is represented in bits, we need it in bytes */
3175 mdwidth /= 8;
3176
3177 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
3178 if (DWC3_IP_IS(DWC3))
3179 size = DWC3_GTXFIFOSIZ_TXFDEP(size);
3180 else
3181 size = DWC31_GTXFIFOSIZ_TXFDEP(size);
3182
3183 /*
3184 * maxpacket size is determined as part of the following, after assuming
3185 * a mult value of one maxpacket:
3186 * DWC3 revision 280A and prior:
3187 * fifo_size = mult * (max_packet / mdwidth) + 1;
3188 * maxpacket = mdwidth * (fifo_size - 1);
3189 *
3190 * DWC3 revision 290A and onwards:
3191 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
3192 * maxpacket = mdwidth * ((fifo_size - 1) - 1) - mdwidth;
3193 */
3194 if (DWC3_VER_IS_PRIOR(DWC3, 290A))
3195 maxpacket = mdwidth * (size - 1);
3196 else
3197 maxpacket = mdwidth * ((size - 1) - 1) - mdwidth;
3198
3199 /* Functionally, space for one max packet is sufficient */
3200 size = min_t(int, maxpacket, 1024);
3201 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
3202
3203 dep->endpoint.max_streams = 16;
3204 dep->endpoint.ops = &dwc3_gadget_ep_ops;
3205 list_add_tail(&dep->endpoint.ep_list,
3206 &dwc->gadget->ep_list);
3207 dep->endpoint.caps.type_iso = true;
3208 dep->endpoint.caps.type_bulk = true;
3209 dep->endpoint.caps.type_int = true;
3210
3211 return dwc3_alloc_trb_pool(dep);
3212}
3213
3214static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
3215{
3216 struct dwc3 *dwc = dep->dwc;
3217 u32 mdwidth;
3218 int size;
3219
3220 mdwidth = dwc3_mdwidth(dwc);
3221
3222 /* MDWIDTH is represented in bits, convert to bytes */
3223 mdwidth /= 8;
3224
3225 /* All OUT endpoints share a single RxFIFO space */
3226 size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
3227 if (DWC3_IP_IS(DWC3))
3228 size = DWC3_GRXFIFOSIZ_RXFDEP(size);
3229 else
3230 size = DWC31_GRXFIFOSIZ_RXFDEP(size);
3231
3232 /* FIFO depth is in MDWDITH bytes */
3233 size *= mdwidth;
3234
3235 /*
3236 * To meet performance requirement, a minimum recommended RxFIFO size
3237 * is defined as follow:
3238 * RxFIFO size >= (3 x MaxPacketSize) +
3239 * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
3240 *
3241 * Then calculate the max packet limit as below.
3242 */
3243 size -= (3 * 8) + 16;
3244 if (size < 0)
3245 size = 0;
3246 else
3247 size /= 3;
3248
3249 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
3250 dep->endpoint.max_streams = 16;
3251 dep->endpoint.ops = &dwc3_gadget_ep_ops;
3252 list_add_tail(&dep->endpoint.ep_list,
3253 &dwc->gadget->ep_list);
3254 dep->endpoint.caps.type_iso = true;
3255 dep->endpoint.caps.type_bulk = true;
3256 dep->endpoint.caps.type_int = true;
3257
3258 return dwc3_alloc_trb_pool(dep);
3259}
3260
3261static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
3262{
3263 struct dwc3_ep *dep;
3264 bool direction = epnum & 1;
3265 int ret;
3266 u8 num = epnum >> 1;
3267
3268 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
3269 if (!dep)
3270 return -ENOMEM;
3271
3272 dep->dwc = dwc;
3273 dep->number = epnum;
3274 dep->direction = direction;
3275 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
3276 dwc->eps[epnum] = dep;
3277 dep->combo_num = 0;
3278 dep->start_cmd_status = 0;
3279
3280 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
3281 direction ? "in" : "out");
3282
3283 dep->endpoint.name = dep->name;
3284
3285 if (!(dep->number > 1)) {
3286 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
3287 dep->endpoint.comp_desc = NULL;
3288 }
3289
3290 if (num == 0)
3291 ret = dwc3_gadget_init_control_endpoint(dep);
3292 else if (direction)
3293 ret = dwc3_gadget_init_in_endpoint(dep);
3294 else
3295 ret = dwc3_gadget_init_out_endpoint(dep);
3296
3297 if (ret)
3298 return ret;
3299
3300 dep->endpoint.caps.dir_in = direction;
3301 dep->endpoint.caps.dir_out = !direction;
3302
3303 INIT_LIST_HEAD(&dep->pending_list);
3304 INIT_LIST_HEAD(&dep->started_list);
3305 INIT_LIST_HEAD(&dep->cancelled_list);
3306
3307 dwc3_debugfs_create_endpoint_dir(dep);
3308
3309 return 0;
3310}
3311
3312static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
3313{
3314 u8 epnum;
3315
3316 INIT_LIST_HEAD(&dwc->gadget->ep_list);
3317
3318 for (epnum = 0; epnum < total; epnum++) {
3319 int ret;
3320
3321 ret = dwc3_gadget_init_endpoint(dwc, epnum);
3322 if (ret)
3323 return ret;
3324 }
3325
3326 return 0;
3327}
3328
3329static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
3330{
3331 struct dwc3_ep *dep;
3332 u8 epnum;
3333
3334 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3335 dep = dwc->eps[epnum];
3336 if (!dep)
3337 continue;
3338 /*
3339 * Physical endpoints 0 and 1 are special; they form the
3340 * bi-directional USB endpoint 0.
3341 *
3342 * For those two physical endpoints, we don't allocate a TRB
3343 * pool nor do we add them the endpoints list. Due to that, we
3344 * shouldn't do these two operations otherwise we would end up
3345 * with all sorts of bugs when removing dwc3.ko.
3346 */
3347 if (epnum != 0 && epnum != 1) {
3348 dwc3_free_trb_pool(dep);
3349 list_del(&dep->endpoint.ep_list);
3350 }
3351
3352 dwc3_debugfs_remove_endpoint_dir(dep);
3353 kfree(dep);
3354 }
3355}
3356
3357/* -------------------------------------------------------------------------- */
3358
3359static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
3360 struct dwc3_request *req, struct dwc3_trb *trb,
3361 const struct dwc3_event_depevt *event, int status, int chain)
3362{
3363 unsigned int count;
3364
3365 dwc3_ep_inc_deq(dep);
3366
3367 trace_dwc3_complete_trb(dep, trb);
3368 req->num_trbs--;
3369
3370 /*
3371 * If we're in the middle of series of chained TRBs and we
3372 * receive a short transfer along the way, DWC3 will skip
3373 * through all TRBs including the last TRB in the chain (the
3374 * where CHN bit is zero. DWC3 will also avoid clearing HWO
3375 * bit and SW has to do it manually.
3376 *
3377 * We're going to do that here to avoid problems of HW trying
3378 * to use bogus TRBs for transfers.
3379 */
3380 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
3381 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3382
3383 /*
3384 * For isochronous transfers, the first TRB in a service interval must
3385 * have the Isoc-First type. Track and report its interval frame number.
3386 */
3387 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3388 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
3389 unsigned int frame_number;
3390
3391 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
3392 frame_number &= ~(dep->interval - 1);
3393 req->request.frame_number = frame_number;
3394 }
3395
3396 /*
3397 * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If
3398 * this TRB points to the bounce buffer address, it's a MPS alignment
3399 * TRB. Don't add it to req->remaining calculation.
3400 */
3401 if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) &&
3402 trb->bph == upper_32_bits(dep->dwc->bounce_addr)) {
3403 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3404 return 1;
3405 }
3406
3407 count = trb->size & DWC3_TRB_SIZE_MASK;
3408 req->remaining += count;
3409
3410 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
3411 return 1;
3412
3413 if (event->status & DEPEVT_STATUS_SHORT && !chain)
3414 return 1;
3415
3416 if ((trb->ctrl & DWC3_TRB_CTRL_ISP_IMI) &&
3417 DWC3_TRB_SIZE_TRBSTS(trb->size) == DWC3_TRBSTS_MISSED_ISOC)
3418 return 1;
3419
3420 if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
3421 (trb->ctrl & DWC3_TRB_CTRL_LST))
3422 return 1;
3423
3424 return 0;
3425}
3426
3427static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
3428 struct dwc3_request *req, const struct dwc3_event_depevt *event,
3429 int status)
3430{
3431 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
3432 struct scatterlist *sg = req->sg;
3433 struct scatterlist *s;
3434 unsigned int num_queued = req->num_queued_sgs;
3435 unsigned int i;
3436 int ret = 0;
3437
3438 for_each_sg(sg, s, num_queued, i) {
3439 trb = &dep->trb_pool[dep->trb_dequeue];
3440
3441 req->sg = sg_next(s);
3442 req->num_queued_sgs--;
3443
3444 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
3445 trb, event, status, true);
3446 if (ret)
3447 break;
3448 }
3449
3450 return ret;
3451}
3452
3453static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
3454 struct dwc3_request *req, const struct dwc3_event_depevt *event,
3455 int status)
3456{
3457 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
3458
3459 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
3460 event, status, false);
3461}
3462
3463static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
3464{
3465 return req->num_pending_sgs == 0 && req->num_queued_sgs == 0;
3466}
3467
3468static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
3469 const struct dwc3_event_depevt *event,
3470 struct dwc3_request *req, int status)
3471{
3472 int request_status;
3473 int ret;
3474
3475 if (req->request.num_mapped_sgs)
3476 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
3477 status);
3478 else
3479 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
3480 status);
3481
3482 req->request.actual = req->request.length - req->remaining;
3483
3484 if (!dwc3_gadget_ep_request_completed(req))
3485 goto out;
3486
3487 if (req->needs_extra_trb) {
3488 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
3489 status);
3490 req->needs_extra_trb = false;
3491 }
3492
3493 /*
3494 * The event status only reflects the status of the TRB with IOC set.
3495 * For the requests that don't set interrupt on completion, the driver
3496 * needs to check and return the status of the completed TRBs associated
3497 * with the request. Use the status of the last TRB of the request.
3498 */
3499 if (req->request.no_interrupt) {
3500 struct dwc3_trb *trb;
3501
3502 trb = dwc3_ep_prev_trb(dep, dep->trb_dequeue);
3503 switch (DWC3_TRB_SIZE_TRBSTS(trb->size)) {
3504 case DWC3_TRBSTS_MISSED_ISOC:
3505 /* Isoc endpoint only */
3506 request_status = -EXDEV;
3507 break;
3508 case DWC3_TRB_STS_XFER_IN_PROG:
3509 /* Applicable when End Transfer with ForceRM=0 */
3510 case DWC3_TRBSTS_SETUP_PENDING:
3511 /* Control endpoint only */
3512 case DWC3_TRBSTS_OK:
3513 default:
3514 request_status = 0;
3515 break;
3516 }
3517 } else {
3518 request_status = status;
3519 }
3520
3521 dwc3_gadget_giveback(dep, req, request_status);
3522
3523out:
3524 return ret;
3525}
3526
3527static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
3528 const struct dwc3_event_depevt *event, int status)
3529{
3530 struct dwc3_request *req;
3531
3532 while (!list_empty(&dep->started_list)) {
3533 int ret;
3534
3535 req = next_request(&dep->started_list);
3536 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
3537 req, status);
3538 if (ret)
3539 break;
3540 /*
3541 * The endpoint is disabled, let the dwc3_remove_requests()
3542 * handle the cleanup.
3543 */
3544 if (!dep->endpoint.desc)
3545 break;
3546 }
3547}
3548
3549static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
3550{
3551 struct dwc3_request *req;
3552 struct dwc3 *dwc = dep->dwc;
3553
3554 if (!dep->endpoint.desc || !dwc->pullups_connected ||
3555 !dwc->connected)
3556 return false;
3557
3558 if (!list_empty(&dep->pending_list))
3559 return true;
3560
3561 /*
3562 * We only need to check the first entry of the started list. We can
3563 * assume the completed requests are removed from the started list.
3564 */
3565 req = next_request(&dep->started_list);
3566 if (!req)
3567 return false;
3568
3569 return !dwc3_gadget_ep_request_completed(req);
3570}
3571
3572static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
3573 const struct dwc3_event_depevt *event)
3574{
3575 dep->frame_number = event->parameters;
3576}
3577
3578static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep,
3579 const struct dwc3_event_depevt *event, int status)
3580{
3581 struct dwc3 *dwc = dep->dwc;
3582 bool no_started_trb = true;
3583
3584 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
3585
3586 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3587 goto out;
3588
3589 if (!dep->endpoint.desc)
3590 return no_started_trb;
3591
3592 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3593 list_empty(&dep->started_list) &&
3594 (list_empty(&dep->pending_list) || status == -EXDEV))
3595 dwc3_stop_active_transfer(dep, true, true);
3596 else if (dwc3_gadget_ep_should_continue(dep))
3597 if (__dwc3_gadget_kick_transfer(dep) == 0)
3598 no_started_trb = false;
3599
3600out:
3601 /*
3602 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
3603 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
3604 */
3605 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3606 u32 reg;
3607 int i;
3608
3609 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
3610 dep = dwc->eps[i];
3611
3612 if (!(dep->flags & DWC3_EP_ENABLED))
3613 continue;
3614
3615 if (!list_empty(&dep->started_list))
3616 return no_started_trb;
3617 }
3618
3619 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3620 reg |= dwc->u1u2;
3621 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3622
3623 dwc->u1u2 = 0;
3624 }
3625
3626 return no_started_trb;
3627}
3628
3629static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
3630 const struct dwc3_event_depevt *event)
3631{
3632 int status = 0;
3633
3634 if (!dep->endpoint.desc)
3635 return;
3636
3637 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
3638 dwc3_gadget_endpoint_frame_from_event(dep, event);
3639
3640 if (event->status & DEPEVT_STATUS_BUSERR)
3641 status = -ECONNRESET;
3642
3643 if (event->status & DEPEVT_STATUS_MISSED_ISOC)
3644 status = -EXDEV;
3645
3646 dwc3_gadget_endpoint_trbs_complete(dep, event, status);
3647}
3648
3649static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep,
3650 const struct dwc3_event_depevt *event)
3651{
3652 int status = 0;
3653
3654 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3655
3656 if (event->status & DEPEVT_STATUS_BUSERR)
3657 status = -ECONNRESET;
3658
3659 if (dwc3_gadget_endpoint_trbs_complete(dep, event, status))
3660 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
3661}
3662
3663static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
3664 const struct dwc3_event_depevt *event)
3665{
3666 dwc3_gadget_endpoint_frame_from_event(dep, event);
3667
3668 /*
3669 * The XferNotReady event is generated only once before the endpoint
3670 * starts. It will be generated again when END_TRANSFER command is
3671 * issued. For some controller versions, the XferNotReady event may be
3672 * generated while the END_TRANSFER command is still in process. Ignore
3673 * it and wait for the next XferNotReady event after the command is
3674 * completed.
3675 */
3676 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3677 return;
3678
3679 (void) __dwc3_gadget_start_isoc(dep);
3680}
3681
3682static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep,
3683 const struct dwc3_event_depevt *event)
3684{
3685 u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
3686
3687 if (cmd != DWC3_DEPCMD_ENDTRANSFER)
3688 return;
3689
3690 /*
3691 * The END_TRANSFER command will cause the controller to generate a
3692 * NoStream Event, and it's not due to the host DP NoStream rejection.
3693 * Ignore the next NoStream event.
3694 */
3695 if (dep->stream_capable)
3696 dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM;
3697
3698 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
3699 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3700 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
3701
3702 if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) {
3703 struct dwc3 *dwc = dep->dwc;
3704
3705 dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL;
3706 if (dwc3_send_clear_stall_ep_cmd(dep)) {
3707 struct usb_ep *ep0 = &dwc->eps[0]->endpoint;
3708
3709 dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name);
3710 if (dwc->delayed_status)
3711 __dwc3_gadget_ep0_set_halt(ep0, 1);
3712 return;
3713 }
3714
3715 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
3716 if (dwc->clear_stall_protocol == dep->number)
3717 dwc3_ep0_send_delayed_status(dwc);
3718 }
3719
3720 if ((dep->flags & DWC3_EP_DELAY_START) &&
3721 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
3722 __dwc3_gadget_kick_transfer(dep);
3723
3724 dep->flags &= ~DWC3_EP_DELAY_START;
3725}
3726
3727static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
3728 const struct dwc3_event_depevt *event)
3729{
3730 struct dwc3 *dwc = dep->dwc;
3731
3732 if (event->status == DEPEVT_STREAMEVT_FOUND) {
3733 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3734 goto out;
3735 }
3736
3737 /* Note: NoStream rejection event param value is 0 and not 0xFFFF */
3738 switch (event->parameters) {
3739 case DEPEVT_STREAM_PRIME:
3740 /*
3741 * If the host can properly transition the endpoint state from
3742 * idle to prime after a NoStream rejection, there's no need to
3743 * force restarting the endpoint to reinitiate the stream. To
3744 * simplify the check, assume the host follows the USB spec if
3745 * it primed the endpoint more than once.
3746 */
3747 if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) {
3748 if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED)
3749 dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM;
3750 else
3751 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3752 }
3753
3754 break;
3755 case DEPEVT_STREAM_NOSTREAM:
3756 if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) ||
3757 !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) ||
3758 (!DWC3_MST_CAPABLE(&dwc->hwparams) &&
3759 !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)))
3760 break;
3761
3762 /*
3763 * If the host rejects a stream due to no active stream, by the
3764 * USB and xHCI spec, the endpoint will be put back to idle
3765 * state. When the host is ready (buffer added/updated), it will
3766 * prime the endpoint to inform the usb device controller. This
3767 * triggers the device controller to issue ERDY to restart the
3768 * stream. However, some hosts don't follow this and keep the
3769 * endpoint in the idle state. No prime will come despite host
3770 * streams are updated, and the device controller will not be
3771 * triggered to generate ERDY to move the next stream data. To
3772 * workaround this and maintain compatibility with various
3773 * hosts, force to reinitiate the stream until the host is ready
3774 * instead of waiting for the host to prime the endpoint.
3775 */
3776 if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
3777 unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME;
3778
3779 dwc3_send_gadget_generic_command(dwc, cmd, dep->number);
3780 } else {
3781 dep->flags |= DWC3_EP_DELAY_START;
3782 dwc3_stop_active_transfer(dep, true, true);
3783 return;
3784 }
3785 break;
3786 }
3787
3788out:
3789 dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM;
3790}
3791
3792static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
3793 const struct dwc3_event_depevt *event)
3794{
3795 struct dwc3_ep *dep;
3796 u8 epnum = event->endpoint_number;
3797
3798 dep = dwc->eps[epnum];
3799
3800 if (!(dep->flags & DWC3_EP_ENABLED)) {
3801 if ((epnum > 1) && !(dep->flags & DWC3_EP_TRANSFER_STARTED))
3802 return;
3803
3804 /* Handle only EPCMDCMPLT when EP disabled */
3805 if ((event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT) &&
3806 !(epnum <= 1 && event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE))
3807 return;
3808 }
3809
3810 if (epnum == 0 || epnum == 1) {
3811 dwc3_ep0_interrupt(dwc, event);
3812 return;
3813 }
3814
3815 switch (event->endpoint_event) {
3816 case DWC3_DEPEVT_XFERINPROGRESS:
3817 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
3818 break;
3819 case DWC3_DEPEVT_XFERNOTREADY:
3820 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
3821 break;
3822 case DWC3_DEPEVT_EPCMDCMPLT:
3823 dwc3_gadget_endpoint_command_complete(dep, event);
3824 break;
3825 case DWC3_DEPEVT_XFERCOMPLETE:
3826 dwc3_gadget_endpoint_transfer_complete(dep, event);
3827 break;
3828 case DWC3_DEPEVT_STREAMEVT:
3829 dwc3_gadget_endpoint_stream_event(dep, event);
3830 break;
3831 case DWC3_DEPEVT_RXTXFIFOEVT:
3832 break;
3833 default:
3834 dev_err(dwc->dev, "unknown endpoint event %d\n", event->endpoint_event);
3835 break;
3836 }
3837}
3838
3839static void dwc3_disconnect_gadget(struct dwc3 *dwc)
3840{
3841 if (dwc->async_callbacks && dwc->gadget_driver->disconnect) {
3842 spin_unlock(&dwc->lock);
3843 dwc->gadget_driver->disconnect(dwc->gadget);
3844 spin_lock(&dwc->lock);
3845 }
3846}
3847
3848static void dwc3_suspend_gadget(struct dwc3 *dwc)
3849{
3850 if (dwc->async_callbacks && dwc->gadget_driver->suspend) {
3851 spin_unlock(&dwc->lock);
3852 dwc->gadget_driver->suspend(dwc->gadget);
3853 spin_lock(&dwc->lock);
3854 }
3855}
3856
3857static void dwc3_resume_gadget(struct dwc3 *dwc)
3858{
3859 if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3860 spin_unlock(&dwc->lock);
3861 dwc->gadget_driver->resume(dwc->gadget);
3862 spin_lock(&dwc->lock);
3863 }
3864}
3865
3866static void dwc3_reset_gadget(struct dwc3 *dwc)
3867{
3868 if (!dwc->gadget_driver)
3869 return;
3870
3871 if (dwc->async_callbacks && dwc->gadget->speed != USB_SPEED_UNKNOWN) {
3872 spin_unlock(&dwc->lock);
3873 usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver);
3874 spin_lock(&dwc->lock);
3875 }
3876}
3877
3878void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
3879 bool interrupt)
3880{
3881 struct dwc3 *dwc = dep->dwc;
3882
3883 /*
3884 * Only issue End Transfer command to the control endpoint of a started
3885 * Data Phase. Typically we should only do so in error cases such as
3886 * invalid/unexpected direction as described in the control transfer
3887 * flow of the programming guide.
3888 */
3889 if (dep->number <= 1 && dwc->ep0state != EP0_DATA_PHASE)
3890 return;
3891
3892 if (interrupt && (dep->flags & DWC3_EP_DELAY_STOP))
3893 return;
3894
3895 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) ||
3896 (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
3897 return;
3898
3899 /*
3900 * If a Setup packet is received but yet to DMA out, the controller will
3901 * not process the End Transfer command of any endpoint. Polling of its
3902 * DEPCMD.CmdAct may block setting up TRB for Setup packet, causing a
3903 * timeout. Delay issuing the End Transfer command until the Setup TRB is
3904 * prepared.
3905 */
3906 if (dwc->ep0state != EP0_SETUP_PHASE && !dwc->delayed_status) {
3907 dep->flags |= DWC3_EP_DELAY_STOP;
3908 return;
3909 }
3910
3911 /*
3912 * NOTICE: We are violating what the Databook says about the
3913 * EndTransfer command. Ideally we would _always_ wait for the
3914 * EndTransfer Command Completion IRQ, but that's causing too
3915 * much trouble synchronizing between us and gadget driver.
3916 *
3917 * We have discussed this with the IP Provider and it was
3918 * suggested to giveback all requests here.
3919 *
3920 * Note also that a similar handling was tested by Synopsys
3921 * (thanks a lot Paul) and nothing bad has come out of it.
3922 * In short, what we're doing is issuing EndTransfer with
3923 * CMDIOC bit set and delay kicking transfer until the
3924 * EndTransfer command had completed.
3925 *
3926 * As of IP version 3.10a of the DWC_usb3 IP, the controller
3927 * supports a mode to work around the above limitation. The
3928 * software can poll the CMDACT bit in the DEPCMD register
3929 * after issuing a EndTransfer command. This mode is enabled
3930 * by writing GUCTL2[14]. This polling is already done in the
3931 * dwc3_send_gadget_ep_cmd() function so if the mode is
3932 * enabled, the EndTransfer command will have completed upon
3933 * returning from this function.
3934 *
3935 * This mode is NOT available on the DWC_usb31 IP. In this
3936 * case, if the IOC bit is not set, then delay by 1ms
3937 * after issuing the EndTransfer command. This allows for the
3938 * controller to handle the command completely before DWC3
3939 * remove requests attempts to unmap USB request buffers.
3940 */
3941
3942 __dwc3_stop_active_transfer(dep, force, interrupt);
3943}
3944
3945static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
3946{
3947 u32 epnum;
3948
3949 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3950 struct dwc3_ep *dep;
3951 int ret;
3952
3953 dep = dwc->eps[epnum];
3954 if (!dep)
3955 continue;
3956
3957 if (!(dep->flags & DWC3_EP_STALL))
3958 continue;
3959
3960 dep->flags &= ~DWC3_EP_STALL;
3961
3962 ret = dwc3_send_clear_stall_ep_cmd(dep);
3963 WARN_ON_ONCE(ret);
3964 }
3965}
3966
3967static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
3968{
3969 int reg;
3970
3971 dwc->suspended = false;
3972
3973 dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
3974
3975 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3976 reg &= ~DWC3_DCTL_INITU1ENA;
3977 reg &= ~DWC3_DCTL_INITU2ENA;
3978 dwc3_gadget_dctl_write_safe(dwc, reg);
3979
3980 dwc->connected = false;
3981
3982 dwc3_disconnect_gadget(dwc);
3983
3984 dwc->gadget->speed = USB_SPEED_UNKNOWN;
3985 dwc->setup_packet_pending = false;
3986 dwc->gadget->wakeup_armed = false;
3987 dwc3_gadget_enable_linksts_evts(dwc, false);
3988 usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED);
3989
3990 dwc3_ep0_reset_state(dwc);
3991
3992 /*
3993 * Request PM idle to address condition where usage count is
3994 * already decremented to zero, but waiting for the disconnect
3995 * interrupt to set dwc->connected to FALSE.
3996 */
3997 pm_request_idle(dwc->dev);
3998}
3999
4000static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
4001{
4002 u32 reg;
4003
4004 dwc->suspended = false;
4005
4006 /*
4007 * Ideally, dwc3_reset_gadget() would trigger the function
4008 * drivers to stop any active transfers through ep disable.
4009 * However, for functions which defer ep disable, such as mass
4010 * storage, we will need to rely on the call to stop active
4011 * transfers here, and avoid allowing of request queuing.
4012 */
4013 dwc->connected = false;
4014
4015 /*
4016 * WORKAROUND: DWC3 revisions <1.88a have an issue which
4017 * would cause a missing Disconnect Event if there's a
4018 * pending Setup Packet in the FIFO.
4019 *
4020 * There's no suggested workaround on the official Bug
4021 * report, which states that "unless the driver/application
4022 * is doing any special handling of a disconnect event,
4023 * there is no functional issue".
4024 *
4025 * Unfortunately, it turns out that we _do_ some special
4026 * handling of a disconnect event, namely complete all
4027 * pending transfers, notify gadget driver of the
4028 * disconnection, and so on.
4029 *
4030 * Our suggested workaround is to follow the Disconnect
4031 * Event steps here, instead, based on a setup_packet_pending
4032 * flag. Such flag gets set whenever we have a SETUP_PENDING
4033 * status for EP0 TRBs and gets cleared on XferComplete for the
4034 * same endpoint.
4035 *
4036 * Refers to:
4037 *
4038 * STAR#9000466709: RTL: Device : Disconnect event not
4039 * generated if setup packet pending in FIFO
4040 */
4041 if (DWC3_VER_IS_PRIOR(DWC3, 188A)) {
4042 if (dwc->setup_packet_pending)
4043 dwc3_gadget_disconnect_interrupt(dwc);
4044 }
4045
4046 dwc3_reset_gadget(dwc);
4047
4048 /*
4049 * From SNPS databook section 8.1.2, the EP0 should be in setup
4050 * phase. So ensure that EP0 is in setup phase by issuing a stall
4051 * and restart if EP0 is not in setup phase.
4052 */
4053 dwc3_ep0_reset_state(dwc);
4054
4055 /*
4056 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
4057 * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
4058 * needs to ensure that it sends "a DEPENDXFER command for any active
4059 * transfers."
4060 */
4061 dwc3_stop_active_transfers(dwc);
4062 dwc->connected = true;
4063
4064 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4065 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
4066 dwc3_gadget_dctl_write_safe(dwc, reg);
4067 dwc->test_mode = false;
4068 dwc->gadget->wakeup_armed = false;
4069 dwc3_gadget_enable_linksts_evts(dwc, false);
4070 dwc3_clear_stall_all_ep(dwc);
4071
4072 /* Reset device address to zero */
4073 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4074 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
4075 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4076}
4077
4078static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
4079{
4080 struct dwc3_ep *dep;
4081 int ret;
4082 u32 reg;
4083 u8 lanes = 1;
4084 u8 speed;
4085
4086 if (!dwc->softconnect)
4087 return;
4088
4089 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
4090 speed = reg & DWC3_DSTS_CONNECTSPD;
4091 dwc->speed = speed;
4092
4093 if (DWC3_IP_IS(DWC32))
4094 lanes = DWC3_DSTS_CONNLANES(reg) + 1;
4095
4096 dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
4097
4098 /*
4099 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
4100 * each time on Connect Done.
4101 *
4102 * Currently we always use the reset value. If any platform
4103 * wants to set this to a different value, we need to add a
4104 * setting and update GCTL.RAMCLKSEL here.
4105 */
4106
4107 switch (speed) {
4108 case DWC3_DSTS_SUPERSPEED_PLUS:
4109 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
4110 dwc->gadget->ep0->maxpacket = 512;
4111 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
4112
4113 if (lanes > 1)
4114 dwc->gadget->ssp_rate = USB_SSP_GEN_2x2;
4115 else
4116 dwc->gadget->ssp_rate = USB_SSP_GEN_2x1;
4117 break;
4118 case DWC3_DSTS_SUPERSPEED:
4119 /*
4120 * WORKAROUND: DWC3 revisions <1.90a have an issue which
4121 * would cause a missing USB3 Reset event.
4122 *
4123 * In such situations, we should force a USB3 Reset
4124 * event by calling our dwc3_gadget_reset_interrupt()
4125 * routine.
4126 *
4127 * Refers to:
4128 *
4129 * STAR#9000483510: RTL: SS : USB3 reset event may
4130 * not be generated always when the link enters poll
4131 */
4132 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
4133 dwc3_gadget_reset_interrupt(dwc);
4134
4135 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
4136 dwc->gadget->ep0->maxpacket = 512;
4137 dwc->gadget->speed = USB_SPEED_SUPER;
4138
4139 if (lanes > 1) {
4140 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
4141 dwc->gadget->ssp_rate = USB_SSP_GEN_1x2;
4142 }
4143 break;
4144 case DWC3_DSTS_HIGHSPEED:
4145 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
4146 dwc->gadget->ep0->maxpacket = 64;
4147 dwc->gadget->speed = USB_SPEED_HIGH;
4148 break;
4149 case DWC3_DSTS_FULLSPEED:
4150 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
4151 dwc->gadget->ep0->maxpacket = 64;
4152 dwc->gadget->speed = USB_SPEED_FULL;
4153 break;
4154 }
4155
4156 dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket;
4157
4158 /* Enable USB2 LPM Capability */
4159
4160 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) &&
4161 !dwc->usb2_gadget_lpm_disable &&
4162 (speed != DWC3_DSTS_SUPERSPEED) &&
4163 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
4164 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4165 reg |= DWC3_DCFG_LPM_CAP;
4166 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4167
4168 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4169 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
4170
4171 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
4172 (dwc->is_utmi_l1_suspend << 4));
4173
4174 /*
4175 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
4176 * DCFG.LPMCap is set, core responses with an ACK and the
4177 * BESL value in the LPM token is less than or equal to LPM
4178 * NYET threshold.
4179 */
4180 WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum,
4181 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
4182
4183 if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A))
4184 reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
4185
4186 dwc3_gadget_dctl_write_safe(dwc, reg);
4187 } else {
4188 if (dwc->usb2_gadget_lpm_disable) {
4189 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4190 reg &= ~DWC3_DCFG_LPM_CAP;
4191 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4192 }
4193
4194 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4195 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
4196 dwc3_gadget_dctl_write_safe(dwc, reg);
4197 }
4198
4199 dep = dwc->eps[0];
4200 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
4201 if (ret) {
4202 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
4203 return;
4204 }
4205
4206 dep = dwc->eps[1];
4207 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
4208 if (ret) {
4209 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
4210 return;
4211 }
4212
4213 /*
4214 * Configure PHY via GUSB3PIPECTLn if required.
4215 *
4216 * Update GTXFIFOSIZn
4217 *
4218 * In both cases reset values should be sufficient.
4219 */
4220}
4221
4222static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc, unsigned int evtinfo)
4223{
4224 dwc->suspended = false;
4225
4226 /*
4227 * TODO take core out of low power mode when that's
4228 * implemented.
4229 */
4230
4231 if (dwc->async_callbacks && dwc->gadget_driver->resume) {
4232 spin_unlock(&dwc->lock);
4233 dwc->gadget_driver->resume(dwc->gadget);
4234 spin_lock(&dwc->lock);
4235 }
4236
4237 dwc->link_state = evtinfo & DWC3_LINK_STATE_MASK;
4238}
4239
4240static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
4241 unsigned int evtinfo)
4242{
4243 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
4244 unsigned int pwropt;
4245
4246 /*
4247 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
4248 * Hibernation mode enabled which would show up when device detects
4249 * host-initiated U3 exit.
4250 *
4251 * In that case, device will generate a Link State Change Interrupt
4252 * from U3 to RESUME which is only necessary if Hibernation is
4253 * configured in.
4254 *
4255 * There are no functional changes due to such spurious event and we
4256 * just need to ignore it.
4257 *
4258 * Refers to:
4259 *
4260 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
4261 * operational mode
4262 */
4263 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
4264 if (DWC3_VER_IS_PRIOR(DWC3, 250A) &&
4265 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
4266 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
4267 (next == DWC3_LINK_STATE_RESUME)) {
4268 return;
4269 }
4270 }
4271
4272 /*
4273 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
4274 * on the link partner, the USB session might do multiple entry/exit
4275 * of low power states before a transfer takes place.
4276 *
4277 * Due to this problem, we might experience lower throughput. The
4278 * suggested workaround is to disable DCTL[12:9] bits if we're
4279 * transitioning from U1/U2 to U0 and enable those bits again
4280 * after a transfer completes and there are no pending transfers
4281 * on any of the enabled endpoints.
4282 *
4283 * This is the first half of that workaround.
4284 *
4285 * Refers to:
4286 *
4287 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
4288 * core send LGO_Ux entering U0
4289 */
4290 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
4291 if (next == DWC3_LINK_STATE_U0) {
4292 u32 u1u2;
4293 u32 reg;
4294
4295 switch (dwc->link_state) {
4296 case DWC3_LINK_STATE_U1:
4297 case DWC3_LINK_STATE_U2:
4298 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4299 u1u2 = reg & (DWC3_DCTL_INITU2ENA
4300 | DWC3_DCTL_ACCEPTU2ENA
4301 | DWC3_DCTL_INITU1ENA
4302 | DWC3_DCTL_ACCEPTU1ENA);
4303
4304 if (!dwc->u1u2)
4305 dwc->u1u2 = reg & u1u2;
4306
4307 reg &= ~u1u2;
4308
4309 dwc3_gadget_dctl_write_safe(dwc, reg);
4310 break;
4311 default:
4312 /* do nothing */
4313 break;
4314 }
4315 }
4316 }
4317
4318 switch (next) {
4319 case DWC3_LINK_STATE_U0:
4320 if (dwc->gadget->wakeup_armed) {
4321 dwc3_gadget_enable_linksts_evts(dwc, false);
4322 dwc3_resume_gadget(dwc);
4323 dwc->suspended = false;
4324 }
4325 break;
4326 case DWC3_LINK_STATE_U1:
4327 if (dwc->speed == USB_SPEED_SUPER)
4328 dwc3_suspend_gadget(dwc);
4329 break;
4330 case DWC3_LINK_STATE_U2:
4331 case DWC3_LINK_STATE_U3:
4332 dwc3_suspend_gadget(dwc);
4333 break;
4334 case DWC3_LINK_STATE_RESUME:
4335 dwc3_resume_gadget(dwc);
4336 break;
4337 default:
4338 /* do nothing */
4339 break;
4340 }
4341
4342 dwc->link_state = next;
4343}
4344
4345static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
4346 unsigned int evtinfo)
4347{
4348 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
4349
4350 if (!dwc->suspended && next == DWC3_LINK_STATE_U3) {
4351 dwc->suspended = true;
4352 dwc3_suspend_gadget(dwc);
4353 }
4354
4355 dwc->link_state = next;
4356}
4357
4358static void dwc3_gadget_interrupt(struct dwc3 *dwc,
4359 const struct dwc3_event_devt *event)
4360{
4361 switch (event->type) {
4362 case DWC3_DEVICE_EVENT_DISCONNECT:
4363 dwc3_gadget_disconnect_interrupt(dwc);
4364 break;
4365 case DWC3_DEVICE_EVENT_RESET:
4366 dwc3_gadget_reset_interrupt(dwc);
4367 break;
4368 case DWC3_DEVICE_EVENT_CONNECT_DONE:
4369 dwc3_gadget_conndone_interrupt(dwc);
4370 break;
4371 case DWC3_DEVICE_EVENT_WAKEUP:
4372 dwc3_gadget_wakeup_interrupt(dwc, event->event_info);
4373 break;
4374 case DWC3_DEVICE_EVENT_HIBER_REQ:
4375 dev_WARN_ONCE(dwc->dev, true, "unexpected hibernation event\n");
4376 break;
4377 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
4378 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
4379 break;
4380 case DWC3_DEVICE_EVENT_SUSPEND:
4381 /* It changed to be suspend event for version 2.30a and above */
4382 if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
4383 dwc3_gadget_suspend_interrupt(dwc, event->event_info);
4384 break;
4385 case DWC3_DEVICE_EVENT_SOF:
4386 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
4387 case DWC3_DEVICE_EVENT_CMD_CMPL:
4388 case DWC3_DEVICE_EVENT_OVERFLOW:
4389 break;
4390 default:
4391 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
4392 }
4393}
4394
4395static void dwc3_process_event_entry(struct dwc3 *dwc,
4396 const union dwc3_event *event)
4397{
4398 trace_dwc3_event(event->raw, dwc);
4399
4400 if (!event->type.is_devspec)
4401 dwc3_endpoint_interrupt(dwc, &event->depevt);
4402 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
4403 dwc3_gadget_interrupt(dwc, &event->devt);
4404 else
4405 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
4406}
4407
4408static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
4409{
4410 struct dwc3 *dwc = evt->dwc;
4411 irqreturn_t ret = IRQ_NONE;
4412 int left;
4413
4414 left = evt->count;
4415
4416 if (!(evt->flags & DWC3_EVENT_PENDING))
4417 return IRQ_NONE;
4418
4419 while (left > 0) {
4420 union dwc3_event event;
4421
4422 event.raw = *(u32 *) (evt->cache + evt->lpos);
4423
4424 dwc3_process_event_entry(dwc, &event);
4425
4426 /*
4427 * FIXME we wrap around correctly to the next entry as
4428 * almost all entries are 4 bytes in size. There is one
4429 * entry which has 12 bytes which is a regular entry
4430 * followed by 8 bytes data. ATM I don't know how
4431 * things are organized if we get next to the a
4432 * boundary so I worry about that once we try to handle
4433 * that.
4434 */
4435 evt->lpos = (evt->lpos + 4) % evt->length;
4436 left -= 4;
4437 }
4438
4439 evt->count = 0;
4440 ret = IRQ_HANDLED;
4441
4442 /* Unmask interrupt */
4443 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
4444 DWC3_GEVNTSIZ_SIZE(evt->length));
4445
4446 if (dwc->imod_interval) {
4447 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
4448 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
4449 }
4450
4451 /* Keep the clearing of DWC3_EVENT_PENDING at the end */
4452 evt->flags &= ~DWC3_EVENT_PENDING;
4453
4454 return ret;
4455}
4456
4457static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
4458{
4459 struct dwc3_event_buffer *evt = _evt;
4460 struct dwc3 *dwc = evt->dwc;
4461 unsigned long flags;
4462 irqreturn_t ret = IRQ_NONE;
4463
4464 local_bh_disable();
4465 spin_lock_irqsave(&dwc->lock, flags);
4466 ret = dwc3_process_event_buf(evt);
4467 spin_unlock_irqrestore(&dwc->lock, flags);
4468 local_bh_enable();
4469
4470 return ret;
4471}
4472
4473static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
4474{
4475 struct dwc3 *dwc = evt->dwc;
4476 u32 amount;
4477 u32 count;
4478
4479 if (pm_runtime_suspended(dwc->dev)) {
4480 dwc->pending_events = true;
4481 /*
4482 * Trigger runtime resume. The get() function will be balanced
4483 * after processing the pending events in dwc3_process_pending
4484 * events().
4485 */
4486 pm_runtime_get(dwc->dev);
4487 disable_irq_nosync(dwc->irq_gadget);
4488 return IRQ_HANDLED;
4489 }
4490
4491 /*
4492 * With PCIe legacy interrupt, test shows that top-half irq handler can
4493 * be called again after HW interrupt deassertion. Check if bottom-half
4494 * irq event handler completes before caching new event to prevent
4495 * losing events.
4496 */
4497 if (evt->flags & DWC3_EVENT_PENDING)
4498 return IRQ_HANDLED;
4499
4500 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
4501 count &= DWC3_GEVNTCOUNT_MASK;
4502 if (!count)
4503 return IRQ_NONE;
4504
4505 evt->count = count;
4506 evt->flags |= DWC3_EVENT_PENDING;
4507
4508 /* Mask interrupt */
4509 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
4510 DWC3_GEVNTSIZ_INTMASK | DWC3_GEVNTSIZ_SIZE(evt->length));
4511
4512 amount = min(count, evt->length - evt->lpos);
4513 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
4514
4515 if (amount < count)
4516 memcpy(evt->cache, evt->buf, count - amount);
4517
4518 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
4519
4520 return IRQ_WAKE_THREAD;
4521}
4522
4523static irqreturn_t dwc3_interrupt(int irq, void *_evt)
4524{
4525 struct dwc3_event_buffer *evt = _evt;
4526
4527 return dwc3_check_event_buf(evt);
4528}
4529
4530static int dwc3_gadget_get_irq(struct dwc3 *dwc)
4531{
4532 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
4533 int irq;
4534
4535 irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
4536 if (irq > 0)
4537 goto out;
4538
4539 if (irq == -EPROBE_DEFER)
4540 goto out;
4541
4542 irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
4543 if (irq > 0)
4544 goto out;
4545
4546 if (irq == -EPROBE_DEFER)
4547 goto out;
4548
4549 irq = platform_get_irq(dwc3_pdev, 0);
4550
4551out:
4552 return irq;
4553}
4554
4555static void dwc_gadget_release(struct device *dev)
4556{
4557 struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev);
4558
4559 kfree(gadget);
4560}
4561
4562/**
4563 * dwc3_gadget_init - initializes gadget related registers
4564 * @dwc: pointer to our controller context structure
4565 *
4566 * Returns 0 on success otherwise negative errno.
4567 */
4568int dwc3_gadget_init(struct dwc3 *dwc)
4569{
4570 int ret;
4571 int irq;
4572 struct device *dev;
4573
4574 irq = dwc3_gadget_get_irq(dwc);
4575 if (irq < 0) {
4576 ret = irq;
4577 goto err0;
4578 }
4579
4580 dwc->irq_gadget = irq;
4581
4582 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
4583 sizeof(*dwc->ep0_trb) * 2,
4584 &dwc->ep0_trb_addr, GFP_KERNEL);
4585 if (!dwc->ep0_trb) {
4586 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
4587 ret = -ENOMEM;
4588 goto err0;
4589 }
4590
4591 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
4592 if (!dwc->setup_buf) {
4593 ret = -ENOMEM;
4594 goto err1;
4595 }
4596
4597 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
4598 &dwc->bounce_addr, GFP_KERNEL);
4599 if (!dwc->bounce) {
4600 ret = -ENOMEM;
4601 goto err2;
4602 }
4603
4604 init_completion(&dwc->ep0_in_setup);
4605 dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL);
4606 if (!dwc->gadget) {
4607 ret = -ENOMEM;
4608 goto err3;
4609 }
4610
4611
4612 usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release);
4613 dev = &dwc->gadget->dev;
4614 dev->platform_data = dwc;
4615 dwc->gadget->ops = &dwc3_gadget_ops;
4616 dwc->gadget->speed = USB_SPEED_UNKNOWN;
4617 dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
4618 dwc->gadget->sg_supported = true;
4619 dwc->gadget->name = "dwc3-gadget";
4620 dwc->gadget->lpm_capable = !dwc->usb2_gadget_lpm_disable;
4621 dwc->gadget->wakeup_capable = true;
4622
4623 /*
4624 * FIXME We might be setting max_speed to <SUPER, however versions
4625 * <2.20a of dwc3 have an issue with metastability (documented
4626 * elsewhere in this driver) which tells us we can't set max speed to
4627 * anything lower than SUPER.
4628 *
4629 * Because gadget.max_speed is only used by composite.c and function
4630 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
4631 * to happen so we avoid sending SuperSpeed Capability descriptor
4632 * together with our BOS descriptor as that could confuse host into
4633 * thinking we can handle super speed.
4634 *
4635 * Note that, in fact, we won't even support GetBOS requests when speed
4636 * is less than super speed because we don't have means, yet, to tell
4637 * composite.c that we are USB 2.0 + LPM ECN.
4638 */
4639 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
4640 !dwc->dis_metastability_quirk)
4641 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
4642 dwc->revision);
4643
4644 dwc->gadget->max_speed = dwc->maximum_speed;
4645 dwc->gadget->max_ssp_rate = dwc->max_ssp_rate;
4646
4647 /*
4648 * REVISIT: Here we should clear all pending IRQs to be
4649 * sure we're starting from a well known location.
4650 */
4651
4652 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
4653 if (ret)
4654 goto err4;
4655
4656 ret = usb_add_gadget(dwc->gadget);
4657 if (ret) {
4658 dev_err(dwc->dev, "failed to add gadget\n");
4659 goto err5;
4660 }
4661
4662 if (DWC3_IP_IS(DWC32) && dwc->maximum_speed == USB_SPEED_SUPER_PLUS)
4663 dwc3_gadget_set_ssp_rate(dwc->gadget, dwc->max_ssp_rate);
4664 else
4665 dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed);
4666
4667 return 0;
4668
4669err5:
4670 dwc3_gadget_free_endpoints(dwc);
4671err4:
4672 usb_put_gadget(dwc->gadget);
4673 dwc->gadget = NULL;
4674err3:
4675 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4676 dwc->bounce_addr);
4677
4678err2:
4679 kfree(dwc->setup_buf);
4680
4681err1:
4682 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4683 dwc->ep0_trb, dwc->ep0_trb_addr);
4684
4685err0:
4686 return ret;
4687}
4688
4689/* -------------------------------------------------------------------------- */
4690
4691void dwc3_gadget_exit(struct dwc3 *dwc)
4692{
4693 if (!dwc->gadget)
4694 return;
4695
4696 usb_del_gadget(dwc->gadget);
4697 dwc3_gadget_free_endpoints(dwc);
4698 usb_put_gadget(dwc->gadget);
4699 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4700 dwc->bounce_addr);
4701 kfree(dwc->setup_buf);
4702 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4703 dwc->ep0_trb, dwc->ep0_trb_addr);
4704}
4705
4706int dwc3_gadget_suspend(struct dwc3 *dwc)
4707{
4708 unsigned long flags;
4709 int ret;
4710
4711 ret = dwc3_gadget_soft_disconnect(dwc);
4712 if (ret)
4713 goto err;
4714
4715 spin_lock_irqsave(&dwc->lock, flags);
4716 if (dwc->gadget_driver)
4717 dwc3_disconnect_gadget(dwc);
4718 spin_unlock_irqrestore(&dwc->lock, flags);
4719
4720 return 0;
4721
4722err:
4723 /*
4724 * Attempt to reset the controller's state. Likely no
4725 * communication can be established until the host
4726 * performs a port reset.
4727 */
4728 if (dwc->softconnect)
4729 dwc3_gadget_soft_connect(dwc);
4730
4731 return ret;
4732}
4733
4734int dwc3_gadget_resume(struct dwc3 *dwc)
4735{
4736 if (!dwc->gadget_driver || !dwc->softconnect)
4737 return 0;
4738
4739 return dwc3_gadget_soft_connect(dwc);
4740}
4741
4742void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
4743{
4744 if (dwc->pending_events) {
4745 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
4746 dwc3_thread_interrupt(dwc->irq_gadget, dwc->ev_buf);
4747 pm_runtime_put(dwc->dev);
4748 dwc->pending_events = false;
4749 enable_irq(dwc->irq_gadget);
4750 }
4751}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/slab.h>
14#include <linux/spinlock.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/list.h>
20#include <linux/dma-mapping.h>
21
22#include <linux/usb/ch9.h>
23#include <linux/usb/gadget.h>
24
25#include "debug.h"
26#include "core.h"
27#include "gadget.h"
28#include "io.h"
29
30#define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
32
33/**
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
37 *
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
40 */
41int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
42{
43 u32 reg;
44
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
47
48 switch (mode) {
49 case TEST_J:
50 case TEST_K:
51 case TEST_SE0_NAK:
52 case TEST_PACKET:
53 case TEST_FORCE_EN:
54 reg |= mode << 1;
55 break;
56 default:
57 return -EINVAL;
58 }
59
60 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
61
62 return 0;
63}
64
65/**
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
68 *
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
71 */
72int dwc3_gadget_get_link_state(struct dwc3 *dwc)
73{
74 u32 reg;
75
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
77
78 return DWC3_DSTS_USBLNKST(reg);
79}
80
81/**
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
85 *
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
88 */
89int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
90{
91 int retries = 10000;
92 u32 reg;
93
94 /*
95 * Wait until device controller is ready. Only applies to 1.94a and
96 * later RTL.
97 */
98 if (dwc->revision >= DWC3_REVISION_194A) {
99 while (--retries) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
102 udelay(5);
103 else
104 break;
105 }
106
107 if (retries <= 0)
108 return -ETIMEDOUT;
109 }
110
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
113
114 /* set requested state */
115 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
116 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
117
118 /*
119 * The following code is racy when called from dwc3_gadget_wakeup,
120 * and is not needed, at least on newer versions
121 */
122 if (dwc->revision >= DWC3_REVISION_194A)
123 return 0;
124
125 /* wait for a change in DSTS */
126 retries = 10000;
127 while (--retries) {
128 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
129
130 if (DWC3_DSTS_USBLNKST(reg) == state)
131 return 0;
132
133 udelay(5);
134 }
135
136 return -ETIMEDOUT;
137}
138
139/**
140 * dwc3_ep_inc_trb - increment a trb index.
141 * @index: Pointer to the TRB index to increment.
142 *
143 * The index should never point to the link TRB. After incrementing,
144 * if it is point to the link TRB, wrap around to the beginning. The
145 * link TRB is always at the last TRB entry.
146 */
147static void dwc3_ep_inc_trb(u8 *index)
148{
149 (*index)++;
150 if (*index == (DWC3_TRB_NUM - 1))
151 *index = 0;
152}
153
154/**
155 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
156 * @dep: The endpoint whose enqueue pointer we're incrementing
157 */
158static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
159{
160 dwc3_ep_inc_trb(&dep->trb_enqueue);
161}
162
163/**
164 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
165 * @dep: The endpoint whose enqueue pointer we're incrementing
166 */
167static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
168{
169 dwc3_ep_inc_trb(&dep->trb_dequeue);
170}
171
172static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
173 struct dwc3_request *req, int status)
174{
175 struct dwc3 *dwc = dep->dwc;
176
177 list_del(&req->list);
178 req->remaining = 0;
179 req->needs_extra_trb = false;
180
181 if (req->request.status == -EINPROGRESS)
182 req->request.status = status;
183
184 if (req->trb)
185 usb_gadget_unmap_request_by_dev(dwc->sysdev,
186 &req->request, req->direction);
187
188 req->trb = NULL;
189 trace_dwc3_gadget_giveback(req);
190
191 if (dep->number > 1)
192 pm_runtime_put(dwc->dev);
193}
194
195/**
196 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
197 * @dep: The endpoint to whom the request belongs to
198 * @req: The request we're giving back
199 * @status: completion code for the request
200 *
201 * Must be called with controller's lock held and interrupts disabled. This
202 * function will unmap @req and call its ->complete() callback to notify upper
203 * layers that it has completed.
204 */
205void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
206 int status)
207{
208 struct dwc3 *dwc = dep->dwc;
209
210 dwc3_gadget_del_and_unmap_request(dep, req, status);
211 req->status = DWC3_REQUEST_STATUS_COMPLETED;
212
213 spin_unlock(&dwc->lock);
214 usb_gadget_giveback_request(&dep->endpoint, &req->request);
215 spin_lock(&dwc->lock);
216}
217
218/**
219 * dwc3_send_gadget_generic_command - issue a generic command for the controller
220 * @dwc: pointer to the controller context
221 * @cmd: the command to be issued
222 * @param: command parameter
223 *
224 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
225 * and wait for its completion.
226 */
227int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
228{
229 u32 timeout = 500;
230 int status = 0;
231 int ret = 0;
232 u32 reg;
233
234 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
235 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
236
237 do {
238 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
239 if (!(reg & DWC3_DGCMD_CMDACT)) {
240 status = DWC3_DGCMD_STATUS(reg);
241 if (status)
242 ret = -EINVAL;
243 break;
244 }
245 } while (--timeout);
246
247 if (!timeout) {
248 ret = -ETIMEDOUT;
249 status = -ETIMEDOUT;
250 }
251
252 trace_dwc3_gadget_generic_cmd(cmd, param, status);
253
254 return ret;
255}
256
257static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
258
259/**
260 * dwc3_send_gadget_ep_cmd - issue an endpoint command
261 * @dep: the endpoint to which the command is going to be issued
262 * @cmd: the command to be issued
263 * @params: parameters to the command
264 *
265 * Caller should handle locking. This function will issue @cmd with given
266 * @params to @dep and wait for its completion.
267 */
268int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
269 struct dwc3_gadget_ep_cmd_params *params)
270{
271 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
272 struct dwc3 *dwc = dep->dwc;
273 u32 timeout = 1000;
274 u32 saved_config = 0;
275 u32 reg;
276
277 int cmd_status = 0;
278 int ret = -EINVAL;
279
280 /*
281 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
282 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
283 * endpoint command.
284 *
285 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
286 * settings. Restore them after the command is completed.
287 *
288 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
289 */
290 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
291 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
292 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
293 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
294 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
295 }
296
297 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
298 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
299 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
300 }
301
302 if (saved_config)
303 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
304 }
305
306 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
307 int needs_wakeup;
308
309 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
310 dwc->link_state == DWC3_LINK_STATE_U2 ||
311 dwc->link_state == DWC3_LINK_STATE_U3);
312
313 if (unlikely(needs_wakeup)) {
314 ret = __dwc3_gadget_wakeup(dwc);
315 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
316 ret);
317 }
318 }
319
320 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
321 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
322 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
323
324 /*
325 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
326 * not relying on XferNotReady, we can make use of a special "No
327 * Response Update Transfer" command where we should clear both CmdAct
328 * and CmdIOC bits.
329 *
330 * With this, we don't need to wait for command completion and can
331 * straight away issue further commands to the endpoint.
332 *
333 * NOTICE: We're making an assumption that control endpoints will never
334 * make use of Update Transfer command. This is a safe assumption
335 * because we can never have more than one request at a time with
336 * Control Endpoints. If anybody changes that assumption, this chunk
337 * needs to be updated accordingly.
338 */
339 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
340 !usb_endpoint_xfer_isoc(desc))
341 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
342 else
343 cmd |= DWC3_DEPCMD_CMDACT;
344
345 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
346 do {
347 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
348 if (!(reg & DWC3_DEPCMD_CMDACT)) {
349 cmd_status = DWC3_DEPCMD_STATUS(reg);
350
351 switch (cmd_status) {
352 case 0:
353 ret = 0;
354 break;
355 case DEPEVT_TRANSFER_NO_RESOURCE:
356 ret = -EINVAL;
357 break;
358 case DEPEVT_TRANSFER_BUS_EXPIRY:
359 /*
360 * SW issues START TRANSFER command to
361 * isochronous ep with future frame interval. If
362 * future interval time has already passed when
363 * core receives the command, it will respond
364 * with an error status of 'Bus Expiry'.
365 *
366 * Instead of always returning -EINVAL, let's
367 * give a hint to the gadget driver that this is
368 * the case by returning -EAGAIN.
369 */
370 ret = -EAGAIN;
371 break;
372 default:
373 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
374 }
375
376 break;
377 }
378 } while (--timeout);
379
380 if (timeout == 0) {
381 ret = -ETIMEDOUT;
382 cmd_status = -ETIMEDOUT;
383 }
384
385 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
386
387 if (ret == 0 && DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
388 dep->flags |= DWC3_EP_TRANSFER_STARTED;
389 dwc3_gadget_ep_get_transfer_index(dep);
390 }
391
392 if (saved_config) {
393 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
394 reg |= saved_config;
395 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
396 }
397
398 return ret;
399}
400
401static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
402{
403 struct dwc3 *dwc = dep->dwc;
404 struct dwc3_gadget_ep_cmd_params params;
405 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
406
407 /*
408 * As of core revision 2.60a the recommended programming model
409 * is to set the ClearPendIN bit when issuing a Clear Stall EP
410 * command for IN endpoints. This is to prevent an issue where
411 * some (non-compliant) hosts may not send ACK TPs for pending
412 * IN transfers due to a mishandled error condition. Synopsys
413 * STAR 9000614252.
414 */
415 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
416 (dwc->gadget.speed >= USB_SPEED_SUPER))
417 cmd |= DWC3_DEPCMD_CLEARPENDIN;
418
419 memset(¶ms, 0, sizeof(params));
420
421 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
422}
423
424static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
425 struct dwc3_trb *trb)
426{
427 u32 offset = (char *) trb - (char *) dep->trb_pool;
428
429 return dep->trb_pool_dma + offset;
430}
431
432static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
433{
434 struct dwc3 *dwc = dep->dwc;
435
436 if (dep->trb_pool)
437 return 0;
438
439 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
440 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
441 &dep->trb_pool_dma, GFP_KERNEL);
442 if (!dep->trb_pool) {
443 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
444 dep->name);
445 return -ENOMEM;
446 }
447
448 return 0;
449}
450
451static void dwc3_free_trb_pool(struct dwc3_ep *dep)
452{
453 struct dwc3 *dwc = dep->dwc;
454
455 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
456 dep->trb_pool, dep->trb_pool_dma);
457
458 dep->trb_pool = NULL;
459 dep->trb_pool_dma = 0;
460}
461
462static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
463{
464 struct dwc3_gadget_ep_cmd_params params;
465
466 memset(¶ms, 0x00, sizeof(params));
467
468 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
469
470 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
471 ¶ms);
472}
473
474/**
475 * dwc3_gadget_start_config - configure ep resources
476 * @dep: endpoint that is being enabled
477 *
478 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
479 * completion, it will set Transfer Resource for all available endpoints.
480 *
481 * The assignment of transfer resources cannot perfectly follow the data book
482 * due to the fact that the controller driver does not have all knowledge of the
483 * configuration in advance. It is given this information piecemeal by the
484 * composite gadget framework after every SET_CONFIGURATION and
485 * SET_INTERFACE. Trying to follow the databook programming model in this
486 * scenario can cause errors. For two reasons:
487 *
488 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
489 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
490 * incorrect in the scenario of multiple interfaces.
491 *
492 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
493 * endpoint on alt setting (8.1.6).
494 *
495 * The following simplified method is used instead:
496 *
497 * All hardware endpoints can be assigned a transfer resource and this setting
498 * will stay persistent until either a core reset or hibernation. So whenever we
499 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
500 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
501 * guaranteed that there are as many transfer resources as endpoints.
502 *
503 * This function is called for each endpoint when it is being enabled but is
504 * triggered only when called for EP0-out, which always happens first, and which
505 * should only happen in one of the above conditions.
506 */
507static int dwc3_gadget_start_config(struct dwc3_ep *dep)
508{
509 struct dwc3_gadget_ep_cmd_params params;
510 struct dwc3 *dwc;
511 u32 cmd;
512 int i;
513 int ret;
514
515 if (dep->number)
516 return 0;
517
518 memset(¶ms, 0x00, sizeof(params));
519 cmd = DWC3_DEPCMD_DEPSTARTCFG;
520 dwc = dep->dwc;
521
522 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
523 if (ret)
524 return ret;
525
526 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
527 struct dwc3_ep *dep = dwc->eps[i];
528
529 if (!dep)
530 continue;
531
532 ret = dwc3_gadget_set_xfer_resource(dep);
533 if (ret)
534 return ret;
535 }
536
537 return 0;
538}
539
540static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
541{
542 const struct usb_ss_ep_comp_descriptor *comp_desc;
543 const struct usb_endpoint_descriptor *desc;
544 struct dwc3_gadget_ep_cmd_params params;
545 struct dwc3 *dwc = dep->dwc;
546
547 comp_desc = dep->endpoint.comp_desc;
548 desc = dep->endpoint.desc;
549
550 memset(¶ms, 0x00, sizeof(params));
551
552 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
553 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
554
555 /* Burst size is only needed in SuperSpeed mode */
556 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
557 u32 burst = dep->endpoint.maxburst;
558 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
559 }
560
561 params.param0 |= action;
562 if (action == DWC3_DEPCFG_ACTION_RESTORE)
563 params.param2 |= dep->saved_state;
564
565 if (usb_endpoint_xfer_control(desc))
566 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
567
568 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
569 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
570
571 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
572 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
573 | DWC3_DEPCFG_STREAM_EVENT_EN;
574 dep->stream_capable = true;
575 }
576
577 if (!usb_endpoint_xfer_control(desc))
578 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
579
580 /*
581 * We are doing 1:1 mapping for endpoints, meaning
582 * Physical Endpoints 2 maps to Logical Endpoint 2 and
583 * so on. We consider the direction bit as part of the physical
584 * endpoint number. So USB endpoint 0x81 is 0x03.
585 */
586 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
587
588 /*
589 * We must use the lower 16 TX FIFOs even though
590 * HW might have more
591 */
592 if (dep->direction)
593 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
594
595 if (desc->bInterval) {
596 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
597 dep->interval = 1 << (desc->bInterval - 1);
598 }
599
600 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
601}
602
603/**
604 * __dwc3_gadget_ep_enable - initializes a hw endpoint
605 * @dep: endpoint to be initialized
606 * @action: one of INIT, MODIFY or RESTORE
607 *
608 * Caller should take care of locking. Execute all necessary commands to
609 * initialize a HW endpoint so it can be used by a gadget driver.
610 */
611static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
612{
613 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
614 struct dwc3 *dwc = dep->dwc;
615
616 u32 reg;
617 int ret;
618
619 if (!(dep->flags & DWC3_EP_ENABLED)) {
620 ret = dwc3_gadget_start_config(dep);
621 if (ret)
622 return ret;
623 }
624
625 ret = dwc3_gadget_set_ep_config(dep, action);
626 if (ret)
627 return ret;
628
629 if (!(dep->flags & DWC3_EP_ENABLED)) {
630 struct dwc3_trb *trb_st_hw;
631 struct dwc3_trb *trb_link;
632
633 dep->type = usb_endpoint_type(desc);
634 dep->flags |= DWC3_EP_ENABLED;
635
636 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
637 reg |= DWC3_DALEPENA_EP(dep->number);
638 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
639
640 if (usb_endpoint_xfer_control(desc))
641 goto out;
642
643 /* Initialize the TRB ring */
644 dep->trb_dequeue = 0;
645 dep->trb_enqueue = 0;
646 memset(dep->trb_pool, 0,
647 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
648
649 /* Link TRB. The HWO bit is never reset */
650 trb_st_hw = &dep->trb_pool[0];
651
652 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
653 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
654 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
655 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
656 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
657 }
658
659 /*
660 * Issue StartTransfer here with no-op TRB so we can always rely on No
661 * Response Update Transfer command.
662 */
663 if ((usb_endpoint_xfer_bulk(desc) && !dep->stream_capable) ||
664 usb_endpoint_xfer_int(desc)) {
665 struct dwc3_gadget_ep_cmd_params params;
666 struct dwc3_trb *trb;
667 dma_addr_t trb_dma;
668 u32 cmd;
669
670 memset(¶ms, 0, sizeof(params));
671 trb = &dep->trb_pool[0];
672 trb_dma = dwc3_trb_dma_offset(dep, trb);
673
674 params.param0 = upper_32_bits(trb_dma);
675 params.param1 = lower_32_bits(trb_dma);
676
677 cmd = DWC3_DEPCMD_STARTTRANSFER;
678
679 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
680 if (ret < 0)
681 return ret;
682 }
683
684out:
685 trace_dwc3_gadget_ep_enable(dep);
686
687 return 0;
688}
689
690static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
691 bool interrupt);
692static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
693{
694 struct dwc3_request *req;
695
696 dwc3_stop_active_transfer(dep, true, false);
697
698 /* - giveback all requests to gadget driver */
699 while (!list_empty(&dep->started_list)) {
700 req = next_request(&dep->started_list);
701
702 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
703 }
704
705 while (!list_empty(&dep->pending_list)) {
706 req = next_request(&dep->pending_list);
707
708 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
709 }
710
711 while (!list_empty(&dep->cancelled_list)) {
712 req = next_request(&dep->cancelled_list);
713
714 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
715 }
716}
717
718/**
719 * __dwc3_gadget_ep_disable - disables a hw endpoint
720 * @dep: the endpoint to disable
721 *
722 * This function undoes what __dwc3_gadget_ep_enable did and also removes
723 * requests which are currently being processed by the hardware and those which
724 * are not yet scheduled.
725 *
726 * Caller should take care of locking.
727 */
728static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
729{
730 struct dwc3 *dwc = dep->dwc;
731 u32 reg;
732
733 trace_dwc3_gadget_ep_disable(dep);
734
735 dwc3_remove_requests(dwc, dep);
736
737 /* make sure HW endpoint isn't stalled */
738 if (dep->flags & DWC3_EP_STALL)
739 __dwc3_gadget_ep_set_halt(dep, 0, false);
740
741 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
742 reg &= ~DWC3_DALEPENA_EP(dep->number);
743 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
744
745 dep->stream_capable = false;
746 dep->type = 0;
747 dep->flags = 0;
748
749 /* Clear out the ep descriptors for non-ep0 */
750 if (dep->number > 1) {
751 dep->endpoint.comp_desc = NULL;
752 dep->endpoint.desc = NULL;
753 }
754
755 return 0;
756}
757
758/* -------------------------------------------------------------------------- */
759
760static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
761 const struct usb_endpoint_descriptor *desc)
762{
763 return -EINVAL;
764}
765
766static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
767{
768 return -EINVAL;
769}
770
771/* -------------------------------------------------------------------------- */
772
773static int dwc3_gadget_ep_enable(struct usb_ep *ep,
774 const struct usb_endpoint_descriptor *desc)
775{
776 struct dwc3_ep *dep;
777 struct dwc3 *dwc;
778 unsigned long flags;
779 int ret;
780
781 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
782 pr_debug("dwc3: invalid parameters\n");
783 return -EINVAL;
784 }
785
786 if (!desc->wMaxPacketSize) {
787 pr_debug("dwc3: missing wMaxPacketSize\n");
788 return -EINVAL;
789 }
790
791 dep = to_dwc3_ep(ep);
792 dwc = dep->dwc;
793
794 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
795 "%s is already enabled\n",
796 dep->name))
797 return 0;
798
799 spin_lock_irqsave(&dwc->lock, flags);
800 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
801 spin_unlock_irqrestore(&dwc->lock, flags);
802
803 return ret;
804}
805
806static int dwc3_gadget_ep_disable(struct usb_ep *ep)
807{
808 struct dwc3_ep *dep;
809 struct dwc3 *dwc;
810 unsigned long flags;
811 int ret;
812
813 if (!ep) {
814 pr_debug("dwc3: invalid parameters\n");
815 return -EINVAL;
816 }
817
818 dep = to_dwc3_ep(ep);
819 dwc = dep->dwc;
820
821 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
822 "%s is already disabled\n",
823 dep->name))
824 return 0;
825
826 spin_lock_irqsave(&dwc->lock, flags);
827 ret = __dwc3_gadget_ep_disable(dep);
828 spin_unlock_irqrestore(&dwc->lock, flags);
829
830 return ret;
831}
832
833static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
834 gfp_t gfp_flags)
835{
836 struct dwc3_request *req;
837 struct dwc3_ep *dep = to_dwc3_ep(ep);
838
839 req = kzalloc(sizeof(*req), gfp_flags);
840 if (!req)
841 return NULL;
842
843 req->direction = dep->direction;
844 req->epnum = dep->number;
845 req->dep = dep;
846 req->status = DWC3_REQUEST_STATUS_UNKNOWN;
847
848 trace_dwc3_alloc_request(req);
849
850 return &req->request;
851}
852
853static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
854 struct usb_request *request)
855{
856 struct dwc3_request *req = to_dwc3_request(request);
857
858 trace_dwc3_free_request(req);
859 kfree(req);
860}
861
862/**
863 * dwc3_ep_prev_trb - returns the previous TRB in the ring
864 * @dep: The endpoint with the TRB ring
865 * @index: The index of the current TRB in the ring
866 *
867 * Returns the TRB prior to the one pointed to by the index. If the
868 * index is 0, we will wrap backwards, skip the link TRB, and return
869 * the one just before that.
870 */
871static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
872{
873 u8 tmp = index;
874
875 if (!tmp)
876 tmp = DWC3_TRB_NUM - 1;
877
878 return &dep->trb_pool[tmp - 1];
879}
880
881static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
882{
883 struct dwc3_trb *tmp;
884 u8 trbs_left;
885
886 /*
887 * If enqueue & dequeue are equal than it is either full or empty.
888 *
889 * One way to know for sure is if the TRB right before us has HWO bit
890 * set or not. If it has, then we're definitely full and can't fit any
891 * more transfers in our ring.
892 */
893 if (dep->trb_enqueue == dep->trb_dequeue) {
894 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
895 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
896 return 0;
897
898 return DWC3_TRB_NUM - 1;
899 }
900
901 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
902 trbs_left &= (DWC3_TRB_NUM - 1);
903
904 if (dep->trb_dequeue < dep->trb_enqueue)
905 trbs_left--;
906
907 return trbs_left;
908}
909
910static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
911 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
912 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
913{
914 struct dwc3 *dwc = dep->dwc;
915 struct usb_gadget *gadget = &dwc->gadget;
916 enum usb_device_speed speed = gadget->speed;
917
918 trb->size = DWC3_TRB_SIZE_LENGTH(length);
919 trb->bpl = lower_32_bits(dma);
920 trb->bph = upper_32_bits(dma);
921
922 switch (usb_endpoint_type(dep->endpoint.desc)) {
923 case USB_ENDPOINT_XFER_CONTROL:
924 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
925 break;
926
927 case USB_ENDPOINT_XFER_ISOC:
928 if (!node) {
929 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
930
931 /*
932 * USB Specification 2.0 Section 5.9.2 states that: "If
933 * there is only a single transaction in the microframe,
934 * only a DATA0 data packet PID is used. If there are
935 * two transactions per microframe, DATA1 is used for
936 * the first transaction data packet and DATA0 is used
937 * for the second transaction data packet. If there are
938 * three transactions per microframe, DATA2 is used for
939 * the first transaction data packet, DATA1 is used for
940 * the second, and DATA0 is used for the third."
941 *
942 * IOW, we should satisfy the following cases:
943 *
944 * 1) length <= maxpacket
945 * - DATA0
946 *
947 * 2) maxpacket < length <= (2 * maxpacket)
948 * - DATA1, DATA0
949 *
950 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
951 * - DATA2, DATA1, DATA0
952 */
953 if (speed == USB_SPEED_HIGH) {
954 struct usb_ep *ep = &dep->endpoint;
955 unsigned int mult = 2;
956 unsigned int maxp = usb_endpoint_maxp(ep->desc);
957
958 if (length <= (2 * maxp))
959 mult--;
960
961 if (length <= maxp)
962 mult--;
963
964 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
965 }
966 } else {
967 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
968 }
969
970 /* always enable Interrupt on Missed ISOC */
971 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
972 break;
973
974 case USB_ENDPOINT_XFER_BULK:
975 case USB_ENDPOINT_XFER_INT:
976 trb->ctrl = DWC3_TRBCTL_NORMAL;
977 break;
978 default:
979 /*
980 * This is only possible with faulty memory because we
981 * checked it already :)
982 */
983 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
984 usb_endpoint_type(dep->endpoint.desc));
985 }
986
987 /*
988 * Enable Continue on Short Packet
989 * when endpoint is not a stream capable
990 */
991 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
992 if (!dep->stream_capable)
993 trb->ctrl |= DWC3_TRB_CTRL_CSP;
994
995 if (short_not_ok)
996 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
997 }
998
999 if ((!no_interrupt && !chain) ||
1000 (dwc3_calc_trbs_left(dep) == 1))
1001 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1002
1003 if (chain)
1004 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1005
1006 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1007 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1008
1009 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1010
1011 dwc3_ep_inc_enq(dep);
1012
1013 trace_dwc3_prepare_trb(dep, trb);
1014}
1015
1016/**
1017 * dwc3_prepare_one_trb - setup one TRB from one request
1018 * @dep: endpoint for which this request is prepared
1019 * @req: dwc3_request pointer
1020 * @chain: should this TRB be chained to the next?
1021 * @node: only for isochronous endpoints. First TRB needs different type.
1022 */
1023static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1024 struct dwc3_request *req, unsigned chain, unsigned node)
1025{
1026 struct dwc3_trb *trb;
1027 unsigned int length;
1028 dma_addr_t dma;
1029 unsigned stream_id = req->request.stream_id;
1030 unsigned short_not_ok = req->request.short_not_ok;
1031 unsigned no_interrupt = req->request.no_interrupt;
1032
1033 if (req->request.num_sgs > 0) {
1034 length = sg_dma_len(req->start_sg);
1035 dma = sg_dma_address(req->start_sg);
1036 } else {
1037 length = req->request.length;
1038 dma = req->request.dma;
1039 }
1040
1041 trb = &dep->trb_pool[dep->trb_enqueue];
1042
1043 if (!req->trb) {
1044 dwc3_gadget_move_started_request(req);
1045 req->trb = trb;
1046 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1047 }
1048
1049 req->num_trbs++;
1050
1051 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
1052 stream_id, short_not_ok, no_interrupt);
1053}
1054
1055static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1056 struct dwc3_request *req)
1057{
1058 struct scatterlist *sg = req->start_sg;
1059 struct scatterlist *s;
1060 int i;
1061
1062 unsigned int remaining = req->request.num_mapped_sgs
1063 - req->num_queued_sgs;
1064
1065 for_each_sg(sg, s, remaining, i) {
1066 unsigned int length = req->request.length;
1067 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1068 unsigned int rem = length % maxp;
1069 unsigned chain = true;
1070
1071 if (sg_is_last(s))
1072 chain = false;
1073
1074 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1075 struct dwc3 *dwc = dep->dwc;
1076 struct dwc3_trb *trb;
1077
1078 req->needs_extra_trb = true;
1079
1080 /* prepare normal TRB */
1081 dwc3_prepare_one_trb(dep, req, true, i);
1082
1083 /* Now prepare one extra TRB to align transfer size */
1084 trb = &dep->trb_pool[dep->trb_enqueue];
1085 req->num_trbs++;
1086 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1087 maxp - rem, false, 1,
1088 req->request.stream_id,
1089 req->request.short_not_ok,
1090 req->request.no_interrupt);
1091 } else {
1092 dwc3_prepare_one_trb(dep, req, chain, i);
1093 }
1094
1095 /*
1096 * There can be a situation where all sgs in sglist are not
1097 * queued because of insufficient trb number. To handle this
1098 * case, update start_sg to next sg to be queued, so that
1099 * we have free trbs we can continue queuing from where we
1100 * previously stopped
1101 */
1102 if (chain)
1103 req->start_sg = sg_next(s);
1104
1105 req->num_queued_sgs++;
1106
1107 if (!dwc3_calc_trbs_left(dep))
1108 break;
1109 }
1110}
1111
1112static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1113 struct dwc3_request *req)
1114{
1115 unsigned int length = req->request.length;
1116 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1117 unsigned int rem = length % maxp;
1118
1119 if ((!length || rem) && usb_endpoint_dir_out(dep->endpoint.desc)) {
1120 struct dwc3 *dwc = dep->dwc;
1121 struct dwc3_trb *trb;
1122
1123 req->needs_extra_trb = true;
1124
1125 /* prepare normal TRB */
1126 dwc3_prepare_one_trb(dep, req, true, 0);
1127
1128 /* Now prepare one extra TRB to align transfer size */
1129 trb = &dep->trb_pool[dep->trb_enqueue];
1130 req->num_trbs++;
1131 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1132 false, 1, req->request.stream_id,
1133 req->request.short_not_ok,
1134 req->request.no_interrupt);
1135 } else if (req->request.zero && req->request.length &&
1136 (IS_ALIGNED(req->request.length, maxp))) {
1137 struct dwc3 *dwc = dep->dwc;
1138 struct dwc3_trb *trb;
1139
1140 req->needs_extra_trb = true;
1141
1142 /* prepare normal TRB */
1143 dwc3_prepare_one_trb(dep, req, true, 0);
1144
1145 /* Now prepare one extra TRB to handle ZLP */
1146 trb = &dep->trb_pool[dep->trb_enqueue];
1147 req->num_trbs++;
1148 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1149 false, 1, req->request.stream_id,
1150 req->request.short_not_ok,
1151 req->request.no_interrupt);
1152 } else {
1153 dwc3_prepare_one_trb(dep, req, false, 0);
1154 }
1155}
1156
1157/*
1158 * dwc3_prepare_trbs - setup TRBs from requests
1159 * @dep: endpoint for which requests are being prepared
1160 *
1161 * The function goes through the requests list and sets up TRBs for the
1162 * transfers. The function returns once there are no more TRBs available or
1163 * it runs out of requests.
1164 */
1165static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1166{
1167 struct dwc3_request *req, *n;
1168
1169 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1170
1171 /*
1172 * We can get in a situation where there's a request in the started list
1173 * but there weren't enough TRBs to fully kick it in the first time
1174 * around, so it has been waiting for more TRBs to be freed up.
1175 *
1176 * In that case, we should check if we have a request with pending_sgs
1177 * in the started list and prepare TRBs for that request first,
1178 * otherwise we will prepare TRBs completely out of order and that will
1179 * break things.
1180 */
1181 list_for_each_entry(req, &dep->started_list, list) {
1182 if (req->num_pending_sgs > 0)
1183 dwc3_prepare_one_trb_sg(dep, req);
1184
1185 if (!dwc3_calc_trbs_left(dep))
1186 return;
1187 }
1188
1189 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1190 struct dwc3 *dwc = dep->dwc;
1191 int ret;
1192
1193 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1194 dep->direction);
1195 if (ret)
1196 return;
1197
1198 req->sg = req->request.sg;
1199 req->start_sg = req->sg;
1200 req->num_queued_sgs = 0;
1201 req->num_pending_sgs = req->request.num_mapped_sgs;
1202
1203 if (req->num_pending_sgs > 0)
1204 dwc3_prepare_one_trb_sg(dep, req);
1205 else
1206 dwc3_prepare_one_trb_linear(dep, req);
1207
1208 if (!dwc3_calc_trbs_left(dep))
1209 return;
1210 }
1211}
1212
1213static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1214{
1215 struct dwc3_gadget_ep_cmd_params params;
1216 struct dwc3_request *req;
1217 int starting;
1218 int ret;
1219 u32 cmd;
1220
1221 if (!dwc3_calc_trbs_left(dep))
1222 return 0;
1223
1224 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1225
1226 dwc3_prepare_trbs(dep);
1227 req = next_request(&dep->started_list);
1228 if (!req) {
1229 dep->flags |= DWC3_EP_PENDING_REQUEST;
1230 return 0;
1231 }
1232
1233 memset(¶ms, 0, sizeof(params));
1234
1235 if (starting) {
1236 params.param0 = upper_32_bits(req->trb_dma);
1237 params.param1 = lower_32_bits(req->trb_dma);
1238 cmd = DWC3_DEPCMD_STARTTRANSFER;
1239
1240 if (dep->stream_capable)
1241 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1242
1243 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1244 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1245 } else {
1246 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1247 DWC3_DEPCMD_PARAM(dep->resource_index);
1248 }
1249
1250 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1251 if (ret < 0) {
1252 /*
1253 * FIXME we need to iterate over the list of requests
1254 * here and stop, unmap, free and del each of the linked
1255 * requests instead of what we do now.
1256 */
1257 if (req->trb)
1258 memset(req->trb, 0, sizeof(struct dwc3_trb));
1259 dwc3_gadget_del_and_unmap_request(dep, req, ret);
1260 return ret;
1261 }
1262
1263 return 0;
1264}
1265
1266static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1267{
1268 u32 reg;
1269
1270 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1271 return DWC3_DSTS_SOFFN(reg);
1272}
1273
1274/**
1275 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1276 * @dep: isoc endpoint
1277 *
1278 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1279 * microframe number reported by the XferNotReady event for the future frame
1280 * number to start the isoc transfer.
1281 *
1282 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1283 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1284 * XferNotReady event are invalid. The driver uses this number to schedule the
1285 * isochronous transfer and passes it to the START TRANSFER command. Because
1286 * this number is invalid, the command may fail. If BIT[15:14] matches the
1287 * internal 16-bit microframe, the START TRANSFER command will pass and the
1288 * transfer will start at the scheduled time, if it is off by 1, the command
1289 * will still pass, but the transfer will start 2 seconds in the future. For all
1290 * other conditions, the START TRANSFER command will fail with bus-expiry.
1291 *
1292 * In order to workaround this issue, we can test for the correct combination of
1293 * BIT[15:14] by sending START TRANSFER commands with different values of
1294 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1295 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1296 * As the result, within the 4 possible combinations for BIT[15:14], there will
1297 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1298 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1299 * value is the correct combination.
1300 *
1301 * Since there are only 4 outcomes and the results are ordered, we can simply
1302 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1303 * deduce the smaller successful combination.
1304 *
1305 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1306 * of BIT[15:14]. The correct combination is as follow:
1307 *
1308 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1309 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1310 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1311 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1312 *
1313 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1314 * endpoints.
1315 */
1316static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1317{
1318 int cmd_status = 0;
1319 bool test0;
1320 bool test1;
1321
1322 while (dep->combo_num < 2) {
1323 struct dwc3_gadget_ep_cmd_params params;
1324 u32 test_frame_number;
1325 u32 cmd;
1326
1327 /*
1328 * Check if we can start isoc transfer on the next interval or
1329 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1330 */
1331 test_frame_number = dep->frame_number & 0x3fff;
1332 test_frame_number |= dep->combo_num << 14;
1333 test_frame_number += max_t(u32, 4, dep->interval);
1334
1335 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1336 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1337
1338 cmd = DWC3_DEPCMD_STARTTRANSFER;
1339 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1340 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1341
1342 /* Redo if some other failure beside bus-expiry is received */
1343 if (cmd_status && cmd_status != -EAGAIN) {
1344 dep->start_cmd_status = 0;
1345 dep->combo_num = 0;
1346 return 0;
1347 }
1348
1349 /* Store the first test status */
1350 if (dep->combo_num == 0)
1351 dep->start_cmd_status = cmd_status;
1352
1353 dep->combo_num++;
1354
1355 /*
1356 * End the transfer if the START_TRANSFER command is successful
1357 * to wait for the next XferNotReady to test the command again
1358 */
1359 if (cmd_status == 0) {
1360 dwc3_stop_active_transfer(dep, true, true);
1361 return 0;
1362 }
1363 }
1364
1365 /* test0 and test1 are both completed at this point */
1366 test0 = (dep->start_cmd_status == 0);
1367 test1 = (cmd_status == 0);
1368
1369 if (!test0 && test1)
1370 dep->combo_num = 1;
1371 else if (!test0 && !test1)
1372 dep->combo_num = 2;
1373 else if (test0 && !test1)
1374 dep->combo_num = 3;
1375 else if (test0 && test1)
1376 dep->combo_num = 0;
1377
1378 dep->frame_number &= 0x3fff;
1379 dep->frame_number |= dep->combo_num << 14;
1380 dep->frame_number += max_t(u32, 4, dep->interval);
1381
1382 /* Reinitialize test variables */
1383 dep->start_cmd_status = 0;
1384 dep->combo_num = 0;
1385
1386 return __dwc3_gadget_kick_transfer(dep);
1387}
1388
1389static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1390{
1391 struct dwc3 *dwc = dep->dwc;
1392 int ret;
1393 int i;
1394
1395 if (list_empty(&dep->pending_list)) {
1396 dep->flags |= DWC3_EP_PENDING_REQUEST;
1397 return -EAGAIN;
1398 }
1399
1400 if (!dwc->dis_start_transfer_quirk && dwc3_is_usb31(dwc) &&
1401 (dwc->revision <= DWC3_USB31_REVISION_160A ||
1402 (dwc->revision == DWC3_USB31_REVISION_170A &&
1403 dwc->version_type >= DWC31_VERSIONTYPE_EA01 &&
1404 dwc->version_type <= DWC31_VERSIONTYPE_EA06))) {
1405
1406 if (dwc->gadget.speed <= USB_SPEED_HIGH && dep->direction)
1407 return dwc3_gadget_start_isoc_quirk(dep);
1408 }
1409
1410 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1411 dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);
1412
1413 ret = __dwc3_gadget_kick_transfer(dep);
1414 if (ret != -EAGAIN)
1415 break;
1416 }
1417
1418 return ret;
1419}
1420
1421static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1422{
1423 struct dwc3 *dwc = dep->dwc;
1424
1425 if (!dep->endpoint.desc) {
1426 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1427 dep->name);
1428 return -ESHUTDOWN;
1429 }
1430
1431 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1432 &req->request, req->dep->name))
1433 return -EINVAL;
1434
1435 if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1436 "%s: request %pK already in flight\n",
1437 dep->name, &req->request))
1438 return -EINVAL;
1439
1440 pm_runtime_get(dwc->dev);
1441
1442 req->request.actual = 0;
1443 req->request.status = -EINPROGRESS;
1444
1445 trace_dwc3_ep_queue(req);
1446
1447 list_add_tail(&req->list, &dep->pending_list);
1448 req->status = DWC3_REQUEST_STATUS_QUEUED;
1449
1450 /*
1451 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1452 * wait for a XferNotReady event so we will know what's the current
1453 * (micro-)frame number.
1454 *
1455 * Without this trick, we are very, very likely gonna get Bus Expiry
1456 * errors which will force us issue EndTransfer command.
1457 */
1458 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1459 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1460 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1461 return 0;
1462
1463 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1464 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1465 return __dwc3_gadget_start_isoc(dep);
1466 }
1467 }
1468 }
1469
1470 return __dwc3_gadget_kick_transfer(dep);
1471}
1472
1473static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1474 gfp_t gfp_flags)
1475{
1476 struct dwc3_request *req = to_dwc3_request(request);
1477 struct dwc3_ep *dep = to_dwc3_ep(ep);
1478 struct dwc3 *dwc = dep->dwc;
1479
1480 unsigned long flags;
1481
1482 int ret;
1483
1484 spin_lock_irqsave(&dwc->lock, flags);
1485 ret = __dwc3_gadget_ep_queue(dep, req);
1486 spin_unlock_irqrestore(&dwc->lock, flags);
1487
1488 return ret;
1489}
1490
1491static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1492{
1493 int i;
1494
1495 /*
1496 * If request was already started, this means we had to
1497 * stop the transfer. With that we also need to ignore
1498 * all TRBs used by the request, however TRBs can only
1499 * be modified after completion of END_TRANSFER
1500 * command. So what we do here is that we wait for
1501 * END_TRANSFER completion and only after that, we jump
1502 * over TRBs by clearing HWO and incrementing dequeue
1503 * pointer.
1504 */
1505 for (i = 0; i < req->num_trbs; i++) {
1506 struct dwc3_trb *trb;
1507
1508 trb = req->trb + i;
1509 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1510 dwc3_ep_inc_deq(dep);
1511 }
1512
1513 req->num_trbs = 0;
1514}
1515
1516static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1517{
1518 struct dwc3_request *req;
1519 struct dwc3_request *tmp;
1520
1521 list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) {
1522 dwc3_gadget_ep_skip_trbs(dep, req);
1523 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1524 }
1525}
1526
1527static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1528 struct usb_request *request)
1529{
1530 struct dwc3_request *req = to_dwc3_request(request);
1531 struct dwc3_request *r = NULL;
1532
1533 struct dwc3_ep *dep = to_dwc3_ep(ep);
1534 struct dwc3 *dwc = dep->dwc;
1535
1536 unsigned long flags;
1537 int ret = 0;
1538
1539 trace_dwc3_ep_dequeue(req);
1540
1541 spin_lock_irqsave(&dwc->lock, flags);
1542
1543 list_for_each_entry(r, &dep->pending_list, list) {
1544 if (r == req)
1545 break;
1546 }
1547
1548 if (r != req) {
1549 list_for_each_entry(r, &dep->started_list, list) {
1550 if (r == req)
1551 break;
1552 }
1553 if (r == req) {
1554 /* wait until it is processed */
1555 dwc3_stop_active_transfer(dep, true, true);
1556
1557 if (!r->trb)
1558 goto out0;
1559
1560 dwc3_gadget_move_cancelled_request(req);
1561 if (dep->flags & DWC3_EP_TRANSFER_STARTED)
1562 goto out0;
1563 else
1564 goto out1;
1565 }
1566 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1567 request, ep->name);
1568 ret = -EINVAL;
1569 goto out0;
1570 }
1571
1572out1:
1573 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1574
1575out0:
1576 spin_unlock_irqrestore(&dwc->lock, flags);
1577
1578 return ret;
1579}
1580
1581int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1582{
1583 struct dwc3_gadget_ep_cmd_params params;
1584 struct dwc3 *dwc = dep->dwc;
1585 int ret;
1586
1587 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1588 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1589 return -EINVAL;
1590 }
1591
1592 memset(¶ms, 0x00, sizeof(params));
1593
1594 if (value) {
1595 struct dwc3_trb *trb;
1596
1597 unsigned transfer_in_flight;
1598 unsigned started;
1599
1600 if (dep->number > 1)
1601 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1602 else
1603 trb = &dwc->ep0_trb[dep->trb_enqueue];
1604
1605 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1606 started = !list_empty(&dep->started_list);
1607
1608 if (!protocol && ((dep->direction && transfer_in_flight) ||
1609 (!dep->direction && started))) {
1610 return -EAGAIN;
1611 }
1612
1613 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1614 ¶ms);
1615 if (ret)
1616 dev_err(dwc->dev, "failed to set STALL on %s\n",
1617 dep->name);
1618 else
1619 dep->flags |= DWC3_EP_STALL;
1620 } else {
1621
1622 ret = dwc3_send_clear_stall_ep_cmd(dep);
1623 if (ret)
1624 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1625 dep->name);
1626 else
1627 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1628 }
1629
1630 return ret;
1631}
1632
1633static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1634{
1635 struct dwc3_ep *dep = to_dwc3_ep(ep);
1636 struct dwc3 *dwc = dep->dwc;
1637
1638 unsigned long flags;
1639
1640 int ret;
1641
1642 spin_lock_irqsave(&dwc->lock, flags);
1643 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1644 spin_unlock_irqrestore(&dwc->lock, flags);
1645
1646 return ret;
1647}
1648
1649static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1650{
1651 struct dwc3_ep *dep = to_dwc3_ep(ep);
1652 struct dwc3 *dwc = dep->dwc;
1653 unsigned long flags;
1654 int ret;
1655
1656 spin_lock_irqsave(&dwc->lock, flags);
1657 dep->flags |= DWC3_EP_WEDGE;
1658
1659 if (dep->number == 0 || dep->number == 1)
1660 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1661 else
1662 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1663 spin_unlock_irqrestore(&dwc->lock, flags);
1664
1665 return ret;
1666}
1667
1668/* -------------------------------------------------------------------------- */
1669
1670static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1671 .bLength = USB_DT_ENDPOINT_SIZE,
1672 .bDescriptorType = USB_DT_ENDPOINT,
1673 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1674};
1675
1676static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1677 .enable = dwc3_gadget_ep0_enable,
1678 .disable = dwc3_gadget_ep0_disable,
1679 .alloc_request = dwc3_gadget_ep_alloc_request,
1680 .free_request = dwc3_gadget_ep_free_request,
1681 .queue = dwc3_gadget_ep0_queue,
1682 .dequeue = dwc3_gadget_ep_dequeue,
1683 .set_halt = dwc3_gadget_ep0_set_halt,
1684 .set_wedge = dwc3_gadget_ep_set_wedge,
1685};
1686
1687static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1688 .enable = dwc3_gadget_ep_enable,
1689 .disable = dwc3_gadget_ep_disable,
1690 .alloc_request = dwc3_gadget_ep_alloc_request,
1691 .free_request = dwc3_gadget_ep_free_request,
1692 .queue = dwc3_gadget_ep_queue,
1693 .dequeue = dwc3_gadget_ep_dequeue,
1694 .set_halt = dwc3_gadget_ep_set_halt,
1695 .set_wedge = dwc3_gadget_ep_set_wedge,
1696};
1697
1698/* -------------------------------------------------------------------------- */
1699
1700static int dwc3_gadget_get_frame(struct usb_gadget *g)
1701{
1702 struct dwc3 *dwc = gadget_to_dwc(g);
1703
1704 return __dwc3_gadget_get_frame(dwc);
1705}
1706
1707static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1708{
1709 int retries;
1710
1711 int ret;
1712 u32 reg;
1713
1714 u8 link_state;
1715 u8 speed;
1716
1717 /*
1718 * According to the Databook Remote wakeup request should
1719 * be issued only when the device is in early suspend state.
1720 *
1721 * We can check that via USB Link State bits in DSTS register.
1722 */
1723 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1724
1725 speed = reg & DWC3_DSTS_CONNECTSPD;
1726 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1727 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1728 return 0;
1729
1730 link_state = DWC3_DSTS_USBLNKST(reg);
1731
1732 switch (link_state) {
1733 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1734 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1735 break;
1736 default:
1737 return -EINVAL;
1738 }
1739
1740 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1741 if (ret < 0) {
1742 dev_err(dwc->dev, "failed to put link in Recovery\n");
1743 return ret;
1744 }
1745
1746 /* Recent versions do this automatically */
1747 if (dwc->revision < DWC3_REVISION_194A) {
1748 /* write zeroes to Link Change Request */
1749 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1750 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1751 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1752 }
1753
1754 /* poll until Link State changes to ON */
1755 retries = 20000;
1756
1757 while (retries--) {
1758 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1759
1760 /* in HS, means ON */
1761 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1762 break;
1763 }
1764
1765 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1766 dev_err(dwc->dev, "failed to send remote wakeup\n");
1767 return -EINVAL;
1768 }
1769
1770 return 0;
1771}
1772
1773static int dwc3_gadget_wakeup(struct usb_gadget *g)
1774{
1775 struct dwc3 *dwc = gadget_to_dwc(g);
1776 unsigned long flags;
1777 int ret;
1778
1779 spin_lock_irqsave(&dwc->lock, flags);
1780 ret = __dwc3_gadget_wakeup(dwc);
1781 spin_unlock_irqrestore(&dwc->lock, flags);
1782
1783 return ret;
1784}
1785
1786static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1787 int is_selfpowered)
1788{
1789 struct dwc3 *dwc = gadget_to_dwc(g);
1790 unsigned long flags;
1791
1792 spin_lock_irqsave(&dwc->lock, flags);
1793 g->is_selfpowered = !!is_selfpowered;
1794 spin_unlock_irqrestore(&dwc->lock, flags);
1795
1796 return 0;
1797}
1798
1799static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1800{
1801 u32 reg;
1802 u32 timeout = 500;
1803
1804 if (pm_runtime_suspended(dwc->dev))
1805 return 0;
1806
1807 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1808 if (is_on) {
1809 if (dwc->revision <= DWC3_REVISION_187A) {
1810 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1811 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1812 }
1813
1814 if (dwc->revision >= DWC3_REVISION_194A)
1815 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1816 reg |= DWC3_DCTL_RUN_STOP;
1817
1818 if (dwc->has_hibernation)
1819 reg |= DWC3_DCTL_KEEP_CONNECT;
1820
1821 dwc->pullups_connected = true;
1822 } else {
1823 reg &= ~DWC3_DCTL_RUN_STOP;
1824
1825 if (dwc->has_hibernation && !suspend)
1826 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1827
1828 dwc->pullups_connected = false;
1829 }
1830
1831 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1832
1833 do {
1834 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1835 reg &= DWC3_DSTS_DEVCTRLHLT;
1836 } while (--timeout && !(!is_on ^ !reg));
1837
1838 if (!timeout)
1839 return -ETIMEDOUT;
1840
1841 return 0;
1842}
1843
1844static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1845{
1846 struct dwc3 *dwc = gadget_to_dwc(g);
1847 unsigned long flags;
1848 int ret;
1849
1850 is_on = !!is_on;
1851
1852 /*
1853 * Per databook, when we want to stop the gadget, if a control transfer
1854 * is still in process, complete it and get the core into setup phase.
1855 */
1856 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1857 reinit_completion(&dwc->ep0_in_setup);
1858
1859 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1860 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1861 if (ret == 0) {
1862 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1863 return -ETIMEDOUT;
1864 }
1865 }
1866
1867 spin_lock_irqsave(&dwc->lock, flags);
1868 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1869 spin_unlock_irqrestore(&dwc->lock, flags);
1870
1871 return ret;
1872}
1873
1874static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1875{
1876 u32 reg;
1877
1878 /* Enable all but Start and End of Frame IRQs */
1879 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1880 DWC3_DEVTEN_EVNTOVERFLOWEN |
1881 DWC3_DEVTEN_CMDCMPLTEN |
1882 DWC3_DEVTEN_ERRTICERREN |
1883 DWC3_DEVTEN_WKUPEVTEN |
1884 DWC3_DEVTEN_CONNECTDONEEN |
1885 DWC3_DEVTEN_USBRSTEN |
1886 DWC3_DEVTEN_DISCONNEVTEN);
1887
1888 if (dwc->revision < DWC3_REVISION_250A)
1889 reg |= DWC3_DEVTEN_ULSTCNGEN;
1890
1891 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1892}
1893
1894static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1895{
1896 /* mask all interrupts */
1897 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1898}
1899
1900static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1901static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1902
1903/**
1904 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1905 * @dwc: pointer to our context structure
1906 *
1907 * The following looks like complex but it's actually very simple. In order to
1908 * calculate the number of packets we can burst at once on OUT transfers, we're
1909 * gonna use RxFIFO size.
1910 *
1911 * To calculate RxFIFO size we need two numbers:
1912 * MDWIDTH = size, in bits, of the internal memory bus
1913 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1914 *
1915 * Given these two numbers, the formula is simple:
1916 *
1917 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1918 *
1919 * 24 bytes is for 3x SETUP packets
1920 * 16 bytes is a clock domain crossing tolerance
1921 *
1922 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1923 */
1924static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1925{
1926 u32 ram2_depth;
1927 u32 mdwidth;
1928 u32 nump;
1929 u32 reg;
1930
1931 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1932 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1933
1934 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1935 nump = min_t(u32, nump, 16);
1936
1937 /* update NumP */
1938 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1939 reg &= ~DWC3_DCFG_NUMP_MASK;
1940 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1941 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1942}
1943
1944static int __dwc3_gadget_start(struct dwc3 *dwc)
1945{
1946 struct dwc3_ep *dep;
1947 int ret = 0;
1948 u32 reg;
1949
1950 /*
1951 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1952 * the core supports IMOD, disable it.
1953 */
1954 if (dwc->imod_interval) {
1955 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1956 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1957 } else if (dwc3_has_imod(dwc)) {
1958 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1959 }
1960
1961 /*
1962 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1963 * field instead of letting dwc3 itself calculate that automatically.
1964 *
1965 * This way, we maximize the chances that we'll be able to get several
1966 * bursts of data without going through any sort of endpoint throttling.
1967 */
1968 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1969 if (dwc3_is_usb31(dwc))
1970 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
1971 else
1972 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1973
1974 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1975
1976 dwc3_gadget_setup_nump(dwc);
1977
1978 /* Start with SuperSpeed Default */
1979 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1980
1981 dep = dwc->eps[0];
1982 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1983 if (ret) {
1984 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1985 goto err0;
1986 }
1987
1988 dep = dwc->eps[1];
1989 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1990 if (ret) {
1991 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1992 goto err1;
1993 }
1994
1995 /* begin to receive SETUP packets */
1996 dwc->ep0state = EP0_SETUP_PHASE;
1997 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
1998 dwc3_ep0_out_start(dwc);
1999
2000 dwc3_gadget_enable_irq(dwc);
2001
2002 return 0;
2003
2004err1:
2005 __dwc3_gadget_ep_disable(dwc->eps[0]);
2006
2007err0:
2008 return ret;
2009}
2010
2011static int dwc3_gadget_start(struct usb_gadget *g,
2012 struct usb_gadget_driver *driver)
2013{
2014 struct dwc3 *dwc = gadget_to_dwc(g);
2015 unsigned long flags;
2016 int ret = 0;
2017 int irq;
2018
2019 irq = dwc->irq_gadget;
2020 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2021 IRQF_SHARED, "dwc3", dwc->ev_buf);
2022 if (ret) {
2023 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2024 irq, ret);
2025 goto err0;
2026 }
2027
2028 spin_lock_irqsave(&dwc->lock, flags);
2029 if (dwc->gadget_driver) {
2030 dev_err(dwc->dev, "%s is already bound to %s\n",
2031 dwc->gadget.name,
2032 dwc->gadget_driver->driver.name);
2033 ret = -EBUSY;
2034 goto err1;
2035 }
2036
2037 dwc->gadget_driver = driver;
2038
2039 if (pm_runtime_active(dwc->dev))
2040 __dwc3_gadget_start(dwc);
2041
2042 spin_unlock_irqrestore(&dwc->lock, flags);
2043
2044 return 0;
2045
2046err1:
2047 spin_unlock_irqrestore(&dwc->lock, flags);
2048 free_irq(irq, dwc);
2049
2050err0:
2051 return ret;
2052}
2053
2054static void __dwc3_gadget_stop(struct dwc3 *dwc)
2055{
2056 dwc3_gadget_disable_irq(dwc);
2057 __dwc3_gadget_ep_disable(dwc->eps[0]);
2058 __dwc3_gadget_ep_disable(dwc->eps[1]);
2059}
2060
2061static int dwc3_gadget_stop(struct usb_gadget *g)
2062{
2063 struct dwc3 *dwc = gadget_to_dwc(g);
2064 unsigned long flags;
2065
2066 spin_lock_irqsave(&dwc->lock, flags);
2067
2068 if (pm_runtime_suspended(dwc->dev))
2069 goto out;
2070
2071 __dwc3_gadget_stop(dwc);
2072
2073out:
2074 dwc->gadget_driver = NULL;
2075 spin_unlock_irqrestore(&dwc->lock, flags);
2076
2077 free_irq(dwc->irq_gadget, dwc->ev_buf);
2078
2079 return 0;
2080}
2081
2082static void dwc3_gadget_config_params(struct usb_gadget *g,
2083 struct usb_dcd_config_params *params)
2084{
2085 struct dwc3 *dwc = gadget_to_dwc(g);
2086
2087 params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2088 params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2089
2090 /* Recommended BESL */
2091 if (!dwc->dis_enblslpm_quirk) {
2092 /*
2093 * If the recommended BESL baseline is 0 or if the BESL deep is
2094 * less than 2, Microsoft's Windows 10 host usb stack will issue
2095 * a usb reset immediately after it receives the extended BOS
2096 * descriptor and the enumeration will fail. To maintain
2097 * compatibility with the Windows' usb stack, let's set the
2098 * recommended BESL baseline to 1 and clamp the BESL deep to be
2099 * within 2 to 15.
2100 */
2101 params->besl_baseline = 1;
2102 if (dwc->is_utmi_l1_suspend)
2103 params->besl_deep =
2104 clamp_t(u8, dwc->hird_threshold, 2, 15);
2105 }
2106
2107 /* U1 Device exit Latency */
2108 if (dwc->dis_u1_entry_quirk)
2109 params->bU1devExitLat = 0;
2110 else
2111 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
2112
2113 /* U2 Device exit Latency */
2114 if (dwc->dis_u2_entry_quirk)
2115 params->bU2DevExitLat = 0;
2116 else
2117 params->bU2DevExitLat =
2118 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
2119}
2120
2121static void dwc3_gadget_set_speed(struct usb_gadget *g,
2122 enum usb_device_speed speed)
2123{
2124 struct dwc3 *dwc = gadget_to_dwc(g);
2125 unsigned long flags;
2126 u32 reg;
2127
2128 spin_lock_irqsave(&dwc->lock, flags);
2129 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2130 reg &= ~(DWC3_DCFG_SPEED_MASK);
2131
2132 /*
2133 * WORKAROUND: DWC3 revision < 2.20a have an issue
2134 * which would cause metastability state on Run/Stop
2135 * bit if we try to force the IP to USB2-only mode.
2136 *
2137 * Because of that, we cannot configure the IP to any
2138 * speed other than the SuperSpeed
2139 *
2140 * Refers to:
2141 *
2142 * STAR#9000525659: Clock Domain Crossing on DCTL in
2143 * USB 2.0 Mode
2144 */
2145 if (dwc->revision < DWC3_REVISION_220A &&
2146 !dwc->dis_metastability_quirk) {
2147 reg |= DWC3_DCFG_SUPERSPEED;
2148 } else {
2149 switch (speed) {
2150 case USB_SPEED_LOW:
2151 reg |= DWC3_DCFG_LOWSPEED;
2152 break;
2153 case USB_SPEED_FULL:
2154 reg |= DWC3_DCFG_FULLSPEED;
2155 break;
2156 case USB_SPEED_HIGH:
2157 reg |= DWC3_DCFG_HIGHSPEED;
2158 break;
2159 case USB_SPEED_SUPER:
2160 reg |= DWC3_DCFG_SUPERSPEED;
2161 break;
2162 case USB_SPEED_SUPER_PLUS:
2163 if (dwc3_is_usb31(dwc))
2164 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2165 else
2166 reg |= DWC3_DCFG_SUPERSPEED;
2167 break;
2168 default:
2169 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2170
2171 if (dwc->revision & DWC3_REVISION_IS_DWC31)
2172 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2173 else
2174 reg |= DWC3_DCFG_SUPERSPEED;
2175 }
2176 }
2177 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2178
2179 spin_unlock_irqrestore(&dwc->lock, flags);
2180}
2181
2182static const struct usb_gadget_ops dwc3_gadget_ops = {
2183 .get_frame = dwc3_gadget_get_frame,
2184 .wakeup = dwc3_gadget_wakeup,
2185 .set_selfpowered = dwc3_gadget_set_selfpowered,
2186 .pullup = dwc3_gadget_pullup,
2187 .udc_start = dwc3_gadget_start,
2188 .udc_stop = dwc3_gadget_stop,
2189 .udc_set_speed = dwc3_gadget_set_speed,
2190 .get_config_params = dwc3_gadget_config_params,
2191};
2192
2193/* -------------------------------------------------------------------------- */
2194
2195static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2196{
2197 struct dwc3 *dwc = dep->dwc;
2198
2199 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2200 dep->endpoint.maxburst = 1;
2201 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2202 if (!dep->direction)
2203 dwc->gadget.ep0 = &dep->endpoint;
2204
2205 dep->endpoint.caps.type_control = true;
2206
2207 return 0;
2208}
2209
2210static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2211{
2212 struct dwc3 *dwc = dep->dwc;
2213 int mdwidth;
2214 int kbytes;
2215 int size;
2216
2217 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2218 /* MDWIDTH is represented in bits, we need it in bytes */
2219 mdwidth /= 8;
2220
2221 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2222 if (dwc3_is_usb31(dwc))
2223 size = DWC31_GTXFIFOSIZ_TXFDEF(size);
2224 else
2225 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2226
2227 /* FIFO Depth is in MDWDITH bytes. Multiply */
2228 size *= mdwidth;
2229
2230 kbytes = size / 1024;
2231 if (kbytes == 0)
2232 kbytes = 1;
2233
2234 /*
2235 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2236 * internal overhead. We don't really know how these are used,
2237 * but documentation say it exists.
2238 */
2239 size -= mdwidth * (kbytes + 1);
2240 size /= kbytes;
2241
2242 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2243
2244 dep->endpoint.max_streams = 15;
2245 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2246 list_add_tail(&dep->endpoint.ep_list,
2247 &dwc->gadget.ep_list);
2248 dep->endpoint.caps.type_iso = true;
2249 dep->endpoint.caps.type_bulk = true;
2250 dep->endpoint.caps.type_int = true;
2251
2252 return dwc3_alloc_trb_pool(dep);
2253}
2254
2255static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2256{
2257 struct dwc3 *dwc = dep->dwc;
2258
2259 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2260 dep->endpoint.max_streams = 15;
2261 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2262 list_add_tail(&dep->endpoint.ep_list,
2263 &dwc->gadget.ep_list);
2264 dep->endpoint.caps.type_iso = true;
2265 dep->endpoint.caps.type_bulk = true;
2266 dep->endpoint.caps.type_int = true;
2267
2268 return dwc3_alloc_trb_pool(dep);
2269}
2270
2271static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2272{
2273 struct dwc3_ep *dep;
2274 bool direction = epnum & 1;
2275 int ret;
2276 u8 num = epnum >> 1;
2277
2278 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2279 if (!dep)
2280 return -ENOMEM;
2281
2282 dep->dwc = dwc;
2283 dep->number = epnum;
2284 dep->direction = direction;
2285 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2286 dwc->eps[epnum] = dep;
2287 dep->combo_num = 0;
2288 dep->start_cmd_status = 0;
2289
2290 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2291 direction ? "in" : "out");
2292
2293 dep->endpoint.name = dep->name;
2294
2295 if (!(dep->number > 1)) {
2296 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2297 dep->endpoint.comp_desc = NULL;
2298 }
2299
2300 if (num == 0)
2301 ret = dwc3_gadget_init_control_endpoint(dep);
2302 else if (direction)
2303 ret = dwc3_gadget_init_in_endpoint(dep);
2304 else
2305 ret = dwc3_gadget_init_out_endpoint(dep);
2306
2307 if (ret)
2308 return ret;
2309
2310 dep->endpoint.caps.dir_in = direction;
2311 dep->endpoint.caps.dir_out = !direction;
2312
2313 INIT_LIST_HEAD(&dep->pending_list);
2314 INIT_LIST_HEAD(&dep->started_list);
2315 INIT_LIST_HEAD(&dep->cancelled_list);
2316
2317 return 0;
2318}
2319
2320static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2321{
2322 u8 epnum;
2323
2324 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2325
2326 for (epnum = 0; epnum < total; epnum++) {
2327 int ret;
2328
2329 ret = dwc3_gadget_init_endpoint(dwc, epnum);
2330 if (ret)
2331 return ret;
2332 }
2333
2334 return 0;
2335}
2336
2337static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2338{
2339 struct dwc3_ep *dep;
2340 u8 epnum;
2341
2342 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2343 dep = dwc->eps[epnum];
2344 if (!dep)
2345 continue;
2346 /*
2347 * Physical endpoints 0 and 1 are special; they form the
2348 * bi-directional USB endpoint 0.
2349 *
2350 * For those two physical endpoints, we don't allocate a TRB
2351 * pool nor do we add them the endpoints list. Due to that, we
2352 * shouldn't do these two operations otherwise we would end up
2353 * with all sorts of bugs when removing dwc3.ko.
2354 */
2355 if (epnum != 0 && epnum != 1) {
2356 dwc3_free_trb_pool(dep);
2357 list_del(&dep->endpoint.ep_list);
2358 }
2359
2360 kfree(dep);
2361 }
2362}
2363
2364/* -------------------------------------------------------------------------- */
2365
2366static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2367 struct dwc3_request *req, struct dwc3_trb *trb,
2368 const struct dwc3_event_depevt *event, int status, int chain)
2369{
2370 unsigned int count;
2371
2372 dwc3_ep_inc_deq(dep);
2373
2374 trace_dwc3_complete_trb(dep, trb);
2375 req->num_trbs--;
2376
2377 /*
2378 * If we're in the middle of series of chained TRBs and we
2379 * receive a short transfer along the way, DWC3 will skip
2380 * through all TRBs including the last TRB in the chain (the
2381 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2382 * bit and SW has to do it manually.
2383 *
2384 * We're going to do that here to avoid problems of HW trying
2385 * to use bogus TRBs for transfers.
2386 */
2387 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2388 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2389
2390 /*
2391 * For isochronous transfers, the first TRB in a service interval must
2392 * have the Isoc-First type. Track and report its interval frame number.
2393 */
2394 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2395 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
2396 unsigned int frame_number;
2397
2398 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
2399 frame_number &= ~(dep->interval - 1);
2400 req->request.frame_number = frame_number;
2401 }
2402
2403 /*
2404 * If we're dealing with unaligned size OUT transfer, we will be left
2405 * with one TRB pending in the ring. We need to manually clear HWO bit
2406 * from that TRB.
2407 */
2408
2409 if (req->needs_extra_trb && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) {
2410 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2411 return 1;
2412 }
2413
2414 count = trb->size & DWC3_TRB_SIZE_MASK;
2415 req->remaining += count;
2416
2417 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2418 return 1;
2419
2420 if (event->status & DEPEVT_STATUS_SHORT && !chain)
2421 return 1;
2422
2423 if (event->status & DEPEVT_STATUS_IOC)
2424 return 1;
2425
2426 return 0;
2427}
2428
2429static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2430 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2431 int status)
2432{
2433 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2434 struct scatterlist *sg = req->sg;
2435 struct scatterlist *s;
2436 unsigned int pending = req->num_pending_sgs;
2437 unsigned int i;
2438 int ret = 0;
2439
2440 for_each_sg(sg, s, pending, i) {
2441 trb = &dep->trb_pool[dep->trb_dequeue];
2442
2443 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2444 break;
2445
2446 req->sg = sg_next(s);
2447 req->num_pending_sgs--;
2448
2449 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2450 trb, event, status, true);
2451 if (ret)
2452 break;
2453 }
2454
2455 return ret;
2456}
2457
2458static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2459 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2460 int status)
2461{
2462 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2463
2464 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2465 event, status, false);
2466}
2467
2468static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2469{
2470 return req->request.actual == req->request.length;
2471}
2472
2473static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2474 const struct dwc3_event_depevt *event,
2475 struct dwc3_request *req, int status)
2476{
2477 int ret;
2478
2479 if (req->num_pending_sgs)
2480 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2481 status);
2482 else
2483 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2484 status);
2485
2486 if (req->needs_extra_trb) {
2487 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2488 status);
2489 req->needs_extra_trb = false;
2490 }
2491
2492 req->request.actual = req->request.length - req->remaining;
2493
2494 if (!dwc3_gadget_ep_request_completed(req) &&
2495 req->num_pending_sgs) {
2496 __dwc3_gadget_kick_transfer(dep);
2497 goto out;
2498 }
2499
2500 dwc3_gadget_giveback(dep, req, status);
2501
2502out:
2503 return ret;
2504}
2505
2506static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2507 const struct dwc3_event_depevt *event, int status)
2508{
2509 struct dwc3_request *req;
2510 struct dwc3_request *tmp;
2511
2512 list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2513 int ret;
2514
2515 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2516 req, status);
2517 if (ret)
2518 break;
2519 }
2520}
2521
2522static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
2523 const struct dwc3_event_depevt *event)
2524{
2525 dep->frame_number = event->parameters;
2526}
2527
2528static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
2529 const struct dwc3_event_depevt *event)
2530{
2531 struct dwc3 *dwc = dep->dwc;
2532 unsigned status = 0;
2533 bool stop = false;
2534
2535 dwc3_gadget_endpoint_frame_from_event(dep, event);
2536
2537 if (event->status & DEPEVT_STATUS_BUSERR)
2538 status = -ECONNRESET;
2539
2540 if (event->status & DEPEVT_STATUS_MISSED_ISOC) {
2541 status = -EXDEV;
2542
2543 if (list_empty(&dep->started_list))
2544 stop = true;
2545 }
2546
2547 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
2548
2549 if (stop) {
2550 dwc3_stop_active_transfer(dep, true, true);
2551 dep->flags = DWC3_EP_ENABLED;
2552 }
2553
2554 /*
2555 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2556 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2557 */
2558 if (dwc->revision < DWC3_REVISION_183A) {
2559 u32 reg;
2560 int i;
2561
2562 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2563 dep = dwc->eps[i];
2564
2565 if (!(dep->flags & DWC3_EP_ENABLED))
2566 continue;
2567
2568 if (!list_empty(&dep->started_list))
2569 return;
2570 }
2571
2572 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2573 reg |= dwc->u1u2;
2574 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2575
2576 dwc->u1u2 = 0;
2577 }
2578}
2579
2580static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
2581 const struct dwc3_event_depevt *event)
2582{
2583 dwc3_gadget_endpoint_frame_from_event(dep, event);
2584 (void) __dwc3_gadget_start_isoc(dep);
2585}
2586
2587static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2588 const struct dwc3_event_depevt *event)
2589{
2590 struct dwc3_ep *dep;
2591 u8 epnum = event->endpoint_number;
2592 u8 cmd;
2593
2594 dep = dwc->eps[epnum];
2595
2596 if (!(dep->flags & DWC3_EP_ENABLED)) {
2597 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
2598 return;
2599
2600 /* Handle only EPCMDCMPLT when EP disabled */
2601 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2602 return;
2603 }
2604
2605 if (epnum == 0 || epnum == 1) {
2606 dwc3_ep0_interrupt(dwc, event);
2607 return;
2608 }
2609
2610 switch (event->endpoint_event) {
2611 case DWC3_DEPEVT_XFERINPROGRESS:
2612 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
2613 break;
2614 case DWC3_DEPEVT_XFERNOTREADY:
2615 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
2616 break;
2617 case DWC3_DEPEVT_EPCMDCMPLT:
2618 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2619
2620 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2621 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
2622 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2623 }
2624 break;
2625 case DWC3_DEPEVT_STREAMEVT:
2626 case DWC3_DEPEVT_XFERCOMPLETE:
2627 case DWC3_DEPEVT_RXTXFIFOEVT:
2628 break;
2629 }
2630}
2631
2632static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2633{
2634 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2635 spin_unlock(&dwc->lock);
2636 dwc->gadget_driver->disconnect(&dwc->gadget);
2637 spin_lock(&dwc->lock);
2638 }
2639}
2640
2641static void dwc3_suspend_gadget(struct dwc3 *dwc)
2642{
2643 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2644 spin_unlock(&dwc->lock);
2645 dwc->gadget_driver->suspend(&dwc->gadget);
2646 spin_lock(&dwc->lock);
2647 }
2648}
2649
2650static void dwc3_resume_gadget(struct dwc3 *dwc)
2651{
2652 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2653 spin_unlock(&dwc->lock);
2654 dwc->gadget_driver->resume(&dwc->gadget);
2655 spin_lock(&dwc->lock);
2656 }
2657}
2658
2659static void dwc3_reset_gadget(struct dwc3 *dwc)
2660{
2661 if (!dwc->gadget_driver)
2662 return;
2663
2664 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2665 spin_unlock(&dwc->lock);
2666 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2667 spin_lock(&dwc->lock);
2668 }
2669}
2670
2671static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
2672 bool interrupt)
2673{
2674 struct dwc3 *dwc = dep->dwc;
2675 struct dwc3_gadget_ep_cmd_params params;
2676 u32 cmd;
2677 int ret;
2678
2679 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
2680 return;
2681
2682 /*
2683 * NOTICE: We are violating what the Databook says about the
2684 * EndTransfer command. Ideally we would _always_ wait for the
2685 * EndTransfer Command Completion IRQ, but that's causing too
2686 * much trouble synchronizing between us and gadget driver.
2687 *
2688 * We have discussed this with the IP Provider and it was
2689 * suggested to giveback all requests here, but give HW some
2690 * extra time to synchronize with the interconnect. We're using
2691 * an arbitrary 100us delay for that.
2692 *
2693 * Note also that a similar handling was tested by Synopsys
2694 * (thanks a lot Paul) and nothing bad has come out of it.
2695 * In short, what we're doing is:
2696 *
2697 * - Issue EndTransfer WITH CMDIOC bit set
2698 * - Wait 100us
2699 *
2700 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2701 * supports a mode to work around the above limitation. The
2702 * software can poll the CMDACT bit in the DEPCMD register
2703 * after issuing a EndTransfer command. This mode is enabled
2704 * by writing GUCTL2[14]. This polling is already done in the
2705 * dwc3_send_gadget_ep_cmd() function so if the mode is
2706 * enabled, the EndTransfer command will have completed upon
2707 * returning from this function and we don't need to delay for
2708 * 100us.
2709 *
2710 * This mode is NOT available on the DWC_usb31 IP.
2711 */
2712
2713 cmd = DWC3_DEPCMD_ENDTRANSFER;
2714 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2715 cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
2716 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2717 memset(¶ms, 0, sizeof(params));
2718 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2719 WARN_ON_ONCE(ret);
2720 dep->resource_index = 0;
2721
2722 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A)
2723 udelay(100);
2724}
2725
2726static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2727{
2728 u32 epnum;
2729
2730 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2731 struct dwc3_ep *dep;
2732 int ret;
2733
2734 dep = dwc->eps[epnum];
2735 if (!dep)
2736 continue;
2737
2738 if (!(dep->flags & DWC3_EP_STALL))
2739 continue;
2740
2741 dep->flags &= ~DWC3_EP_STALL;
2742
2743 ret = dwc3_send_clear_stall_ep_cmd(dep);
2744 WARN_ON_ONCE(ret);
2745 }
2746}
2747
2748static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2749{
2750 int reg;
2751
2752 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2753 reg &= ~DWC3_DCTL_INITU1ENA;
2754 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2755
2756 reg &= ~DWC3_DCTL_INITU2ENA;
2757 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2758
2759 dwc3_disconnect_gadget(dwc);
2760
2761 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2762 dwc->setup_packet_pending = false;
2763 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2764
2765 dwc->connected = false;
2766}
2767
2768static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2769{
2770 u32 reg;
2771
2772 dwc->connected = true;
2773
2774 /*
2775 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2776 * would cause a missing Disconnect Event if there's a
2777 * pending Setup Packet in the FIFO.
2778 *
2779 * There's no suggested workaround on the official Bug
2780 * report, which states that "unless the driver/application
2781 * is doing any special handling of a disconnect event,
2782 * there is no functional issue".
2783 *
2784 * Unfortunately, it turns out that we _do_ some special
2785 * handling of a disconnect event, namely complete all
2786 * pending transfers, notify gadget driver of the
2787 * disconnection, and so on.
2788 *
2789 * Our suggested workaround is to follow the Disconnect
2790 * Event steps here, instead, based on a setup_packet_pending
2791 * flag. Such flag gets set whenever we have a SETUP_PENDING
2792 * status for EP0 TRBs and gets cleared on XferComplete for the
2793 * same endpoint.
2794 *
2795 * Refers to:
2796 *
2797 * STAR#9000466709: RTL: Device : Disconnect event not
2798 * generated if setup packet pending in FIFO
2799 */
2800 if (dwc->revision < DWC3_REVISION_188A) {
2801 if (dwc->setup_packet_pending)
2802 dwc3_gadget_disconnect_interrupt(dwc);
2803 }
2804
2805 dwc3_reset_gadget(dwc);
2806
2807 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2808 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2809 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2810 dwc->test_mode = false;
2811 dwc3_clear_stall_all_ep(dwc);
2812
2813 /* Reset device address to zero */
2814 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2815 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2816 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2817}
2818
2819static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2820{
2821 struct dwc3_ep *dep;
2822 int ret;
2823 u32 reg;
2824 u8 speed;
2825
2826 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2827 speed = reg & DWC3_DSTS_CONNECTSPD;
2828 dwc->speed = speed;
2829
2830 /*
2831 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2832 * each time on Connect Done.
2833 *
2834 * Currently we always use the reset value. If any platform
2835 * wants to set this to a different value, we need to add a
2836 * setting and update GCTL.RAMCLKSEL here.
2837 */
2838
2839 switch (speed) {
2840 case DWC3_DSTS_SUPERSPEED_PLUS:
2841 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2842 dwc->gadget.ep0->maxpacket = 512;
2843 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2844 break;
2845 case DWC3_DSTS_SUPERSPEED:
2846 /*
2847 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2848 * would cause a missing USB3 Reset event.
2849 *
2850 * In such situations, we should force a USB3 Reset
2851 * event by calling our dwc3_gadget_reset_interrupt()
2852 * routine.
2853 *
2854 * Refers to:
2855 *
2856 * STAR#9000483510: RTL: SS : USB3 reset event may
2857 * not be generated always when the link enters poll
2858 */
2859 if (dwc->revision < DWC3_REVISION_190A)
2860 dwc3_gadget_reset_interrupt(dwc);
2861
2862 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2863 dwc->gadget.ep0->maxpacket = 512;
2864 dwc->gadget.speed = USB_SPEED_SUPER;
2865 break;
2866 case DWC3_DSTS_HIGHSPEED:
2867 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2868 dwc->gadget.ep0->maxpacket = 64;
2869 dwc->gadget.speed = USB_SPEED_HIGH;
2870 break;
2871 case DWC3_DSTS_FULLSPEED:
2872 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2873 dwc->gadget.ep0->maxpacket = 64;
2874 dwc->gadget.speed = USB_SPEED_FULL;
2875 break;
2876 case DWC3_DSTS_LOWSPEED:
2877 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2878 dwc->gadget.ep0->maxpacket = 8;
2879 dwc->gadget.speed = USB_SPEED_LOW;
2880 break;
2881 }
2882
2883 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2884
2885 /* Enable USB2 LPM Capability */
2886
2887 if ((dwc->revision > DWC3_REVISION_194A) &&
2888 (speed != DWC3_DSTS_SUPERSPEED) &&
2889 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2890 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2891 reg |= DWC3_DCFG_LPM_CAP;
2892 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2893
2894 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2895 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2896
2897 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
2898 (dwc->is_utmi_l1_suspend << 4));
2899
2900 /*
2901 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2902 * DCFG.LPMCap is set, core responses with an ACK and the
2903 * BESL value in the LPM token is less than or equal to LPM
2904 * NYET threshold.
2905 */
2906 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2907 && dwc->has_lpm_erratum,
2908 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2909
2910 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2911 reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
2912
2913 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2914 } else {
2915 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2916 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2917 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2918 }
2919
2920 dep = dwc->eps[0];
2921 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2922 if (ret) {
2923 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2924 return;
2925 }
2926
2927 dep = dwc->eps[1];
2928 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2929 if (ret) {
2930 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2931 return;
2932 }
2933
2934 /*
2935 * Configure PHY via GUSB3PIPECTLn if required.
2936 *
2937 * Update GTXFIFOSIZn
2938 *
2939 * In both cases reset values should be sufficient.
2940 */
2941}
2942
2943static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2944{
2945 /*
2946 * TODO take core out of low power mode when that's
2947 * implemented.
2948 */
2949
2950 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2951 spin_unlock(&dwc->lock);
2952 dwc->gadget_driver->resume(&dwc->gadget);
2953 spin_lock(&dwc->lock);
2954 }
2955}
2956
2957static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2958 unsigned int evtinfo)
2959{
2960 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2961 unsigned int pwropt;
2962
2963 /*
2964 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2965 * Hibernation mode enabled which would show up when device detects
2966 * host-initiated U3 exit.
2967 *
2968 * In that case, device will generate a Link State Change Interrupt
2969 * from U3 to RESUME which is only necessary if Hibernation is
2970 * configured in.
2971 *
2972 * There are no functional changes due to such spurious event and we
2973 * just need to ignore it.
2974 *
2975 * Refers to:
2976 *
2977 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2978 * operational mode
2979 */
2980 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2981 if ((dwc->revision < DWC3_REVISION_250A) &&
2982 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2983 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2984 (next == DWC3_LINK_STATE_RESUME)) {
2985 return;
2986 }
2987 }
2988
2989 /*
2990 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2991 * on the link partner, the USB session might do multiple entry/exit
2992 * of low power states before a transfer takes place.
2993 *
2994 * Due to this problem, we might experience lower throughput. The
2995 * suggested workaround is to disable DCTL[12:9] bits if we're
2996 * transitioning from U1/U2 to U0 and enable those bits again
2997 * after a transfer completes and there are no pending transfers
2998 * on any of the enabled endpoints.
2999 *
3000 * This is the first half of that workaround.
3001 *
3002 * Refers to:
3003 *
3004 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
3005 * core send LGO_Ux entering U0
3006 */
3007 if (dwc->revision < DWC3_REVISION_183A) {
3008 if (next == DWC3_LINK_STATE_U0) {
3009 u32 u1u2;
3010 u32 reg;
3011
3012 switch (dwc->link_state) {
3013 case DWC3_LINK_STATE_U1:
3014 case DWC3_LINK_STATE_U2:
3015 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3016 u1u2 = reg & (DWC3_DCTL_INITU2ENA
3017 | DWC3_DCTL_ACCEPTU2ENA
3018 | DWC3_DCTL_INITU1ENA
3019 | DWC3_DCTL_ACCEPTU1ENA);
3020
3021 if (!dwc->u1u2)
3022 dwc->u1u2 = reg & u1u2;
3023
3024 reg &= ~u1u2;
3025
3026 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3027 break;
3028 default:
3029 /* do nothing */
3030 break;
3031 }
3032 }
3033 }
3034
3035 switch (next) {
3036 case DWC3_LINK_STATE_U1:
3037 if (dwc->speed == USB_SPEED_SUPER)
3038 dwc3_suspend_gadget(dwc);
3039 break;
3040 case DWC3_LINK_STATE_U2:
3041 case DWC3_LINK_STATE_U3:
3042 dwc3_suspend_gadget(dwc);
3043 break;
3044 case DWC3_LINK_STATE_RESUME:
3045 dwc3_resume_gadget(dwc);
3046 break;
3047 default:
3048 /* do nothing */
3049 break;
3050 }
3051
3052 dwc->link_state = next;
3053}
3054
3055static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3056 unsigned int evtinfo)
3057{
3058 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3059
3060 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3061 dwc3_suspend_gadget(dwc);
3062
3063 dwc->link_state = next;
3064}
3065
3066static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3067 unsigned int evtinfo)
3068{
3069 unsigned int is_ss = evtinfo & BIT(4);
3070
3071 /*
3072 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3073 * have a known issue which can cause USB CV TD.9.23 to fail
3074 * randomly.
3075 *
3076 * Because of this issue, core could generate bogus hibernation
3077 * events which SW needs to ignore.
3078 *
3079 * Refers to:
3080 *
3081 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3082 * Device Fallback from SuperSpeed
3083 */
3084 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3085 return;
3086
3087 /* enter hibernation here */
3088}
3089
3090static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3091 const struct dwc3_event_devt *event)
3092{
3093 switch (event->type) {
3094 case DWC3_DEVICE_EVENT_DISCONNECT:
3095 dwc3_gadget_disconnect_interrupt(dwc);
3096 break;
3097 case DWC3_DEVICE_EVENT_RESET:
3098 dwc3_gadget_reset_interrupt(dwc);
3099 break;
3100 case DWC3_DEVICE_EVENT_CONNECT_DONE:
3101 dwc3_gadget_conndone_interrupt(dwc);
3102 break;
3103 case DWC3_DEVICE_EVENT_WAKEUP:
3104 dwc3_gadget_wakeup_interrupt(dwc);
3105 break;
3106 case DWC3_DEVICE_EVENT_HIBER_REQ:
3107 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3108 "unexpected hibernation event\n"))
3109 break;
3110
3111 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3112 break;
3113 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3114 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3115 break;
3116 case DWC3_DEVICE_EVENT_EOPF:
3117 /* It changed to be suspend event for version 2.30a and above */
3118 if (dwc->revision >= DWC3_REVISION_230A) {
3119 /*
3120 * Ignore suspend event until the gadget enters into
3121 * USB_STATE_CONFIGURED state.
3122 */
3123 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
3124 dwc3_gadget_suspend_interrupt(dwc,
3125 event->event_info);
3126 }
3127 break;
3128 case DWC3_DEVICE_EVENT_SOF:
3129 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3130 case DWC3_DEVICE_EVENT_CMD_CMPL:
3131 case DWC3_DEVICE_EVENT_OVERFLOW:
3132 break;
3133 default:
3134 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3135 }
3136}
3137
3138static void dwc3_process_event_entry(struct dwc3 *dwc,
3139 const union dwc3_event *event)
3140{
3141 trace_dwc3_event(event->raw, dwc);
3142
3143 if (!event->type.is_devspec)
3144 dwc3_endpoint_interrupt(dwc, &event->depevt);
3145 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3146 dwc3_gadget_interrupt(dwc, &event->devt);
3147 else
3148 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3149}
3150
3151static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3152{
3153 struct dwc3 *dwc = evt->dwc;
3154 irqreturn_t ret = IRQ_NONE;
3155 int left;
3156 u32 reg;
3157
3158 left = evt->count;
3159
3160 if (!(evt->flags & DWC3_EVENT_PENDING))
3161 return IRQ_NONE;
3162
3163 while (left > 0) {
3164 union dwc3_event event;
3165
3166 event.raw = *(u32 *) (evt->cache + evt->lpos);
3167
3168 dwc3_process_event_entry(dwc, &event);
3169
3170 /*
3171 * FIXME we wrap around correctly to the next entry as
3172 * almost all entries are 4 bytes in size. There is one
3173 * entry which has 12 bytes which is a regular entry
3174 * followed by 8 bytes data. ATM I don't know how
3175 * things are organized if we get next to the a
3176 * boundary so I worry about that once we try to handle
3177 * that.
3178 */
3179 evt->lpos = (evt->lpos + 4) % evt->length;
3180 left -= 4;
3181 }
3182
3183 evt->count = 0;
3184 evt->flags &= ~DWC3_EVENT_PENDING;
3185 ret = IRQ_HANDLED;
3186
3187 /* Unmask interrupt */
3188 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3189 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3190 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3191
3192 if (dwc->imod_interval) {
3193 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3194 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3195 }
3196
3197 return ret;
3198}
3199
3200static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3201{
3202 struct dwc3_event_buffer *evt = _evt;
3203 struct dwc3 *dwc = evt->dwc;
3204 unsigned long flags;
3205 irqreturn_t ret = IRQ_NONE;
3206
3207 spin_lock_irqsave(&dwc->lock, flags);
3208 ret = dwc3_process_event_buf(evt);
3209 spin_unlock_irqrestore(&dwc->lock, flags);
3210
3211 return ret;
3212}
3213
3214static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3215{
3216 struct dwc3 *dwc = evt->dwc;
3217 u32 amount;
3218 u32 count;
3219 u32 reg;
3220
3221 if (pm_runtime_suspended(dwc->dev)) {
3222 pm_runtime_get(dwc->dev);
3223 disable_irq_nosync(dwc->irq_gadget);
3224 dwc->pending_events = true;
3225 return IRQ_HANDLED;
3226 }
3227
3228 /*
3229 * With PCIe legacy interrupt, test shows that top-half irq handler can
3230 * be called again after HW interrupt deassertion. Check if bottom-half
3231 * irq event handler completes before caching new event to prevent
3232 * losing events.
3233 */
3234 if (evt->flags & DWC3_EVENT_PENDING)
3235 return IRQ_HANDLED;
3236
3237 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3238 count &= DWC3_GEVNTCOUNT_MASK;
3239 if (!count)
3240 return IRQ_NONE;
3241
3242 evt->count = count;
3243 evt->flags |= DWC3_EVENT_PENDING;
3244
3245 /* Mask interrupt */
3246 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3247 reg |= DWC3_GEVNTSIZ_INTMASK;
3248 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3249
3250 amount = min(count, evt->length - evt->lpos);
3251 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3252
3253 if (amount < count)
3254 memcpy(evt->cache, evt->buf, count - amount);
3255
3256 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3257
3258 return IRQ_WAKE_THREAD;
3259}
3260
3261static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3262{
3263 struct dwc3_event_buffer *evt = _evt;
3264
3265 return dwc3_check_event_buf(evt);
3266}
3267
3268static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3269{
3270 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3271 int irq;
3272
3273 irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
3274 if (irq > 0)
3275 goto out;
3276
3277 if (irq == -EPROBE_DEFER)
3278 goto out;
3279
3280 irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
3281 if (irq > 0)
3282 goto out;
3283
3284 if (irq == -EPROBE_DEFER)
3285 goto out;
3286
3287 irq = platform_get_irq(dwc3_pdev, 0);
3288 if (irq > 0)
3289 goto out;
3290
3291 if (!irq)
3292 irq = -EINVAL;
3293
3294out:
3295 return irq;
3296}
3297
3298/**
3299 * dwc3_gadget_init - initializes gadget related registers
3300 * @dwc: pointer to our controller context structure
3301 *
3302 * Returns 0 on success otherwise negative errno.
3303 */
3304int dwc3_gadget_init(struct dwc3 *dwc)
3305{
3306 int ret;
3307 int irq;
3308
3309 irq = dwc3_gadget_get_irq(dwc);
3310 if (irq < 0) {
3311 ret = irq;
3312 goto err0;
3313 }
3314
3315 dwc->irq_gadget = irq;
3316
3317 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3318 sizeof(*dwc->ep0_trb) * 2,
3319 &dwc->ep0_trb_addr, GFP_KERNEL);
3320 if (!dwc->ep0_trb) {
3321 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3322 ret = -ENOMEM;
3323 goto err0;
3324 }
3325
3326 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3327 if (!dwc->setup_buf) {
3328 ret = -ENOMEM;
3329 goto err1;
3330 }
3331
3332 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3333 &dwc->bounce_addr, GFP_KERNEL);
3334 if (!dwc->bounce) {
3335 ret = -ENOMEM;
3336 goto err2;
3337 }
3338
3339 init_completion(&dwc->ep0_in_setup);
3340
3341 dwc->gadget.ops = &dwc3_gadget_ops;
3342 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3343 dwc->gadget.sg_supported = true;
3344 dwc->gadget.name = "dwc3-gadget";
3345 dwc->gadget.lpm_capable = true;
3346
3347 /*
3348 * FIXME We might be setting max_speed to <SUPER, however versions
3349 * <2.20a of dwc3 have an issue with metastability (documented
3350 * elsewhere in this driver) which tells us we can't set max speed to
3351 * anything lower than SUPER.
3352 *
3353 * Because gadget.max_speed is only used by composite.c and function
3354 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3355 * to happen so we avoid sending SuperSpeed Capability descriptor
3356 * together with our BOS descriptor as that could confuse host into
3357 * thinking we can handle super speed.
3358 *
3359 * Note that, in fact, we won't even support GetBOS requests when speed
3360 * is less than super speed because we don't have means, yet, to tell
3361 * composite.c that we are USB 2.0 + LPM ECN.
3362 */
3363 if (dwc->revision < DWC3_REVISION_220A &&
3364 !dwc->dis_metastability_quirk)
3365 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3366 dwc->revision);
3367
3368 dwc->gadget.max_speed = dwc->maximum_speed;
3369
3370 /*
3371 * REVISIT: Here we should clear all pending IRQs to be
3372 * sure we're starting from a well known location.
3373 */
3374
3375 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3376 if (ret)
3377 goto err3;
3378
3379 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3380 if (ret) {
3381 dev_err(dwc->dev, "failed to register udc\n");
3382 goto err4;
3383 }
3384
3385 dwc3_gadget_set_speed(&dwc->gadget, dwc->maximum_speed);
3386
3387 return 0;
3388
3389err4:
3390 dwc3_gadget_free_endpoints(dwc);
3391
3392err3:
3393 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3394 dwc->bounce_addr);
3395
3396err2:
3397 kfree(dwc->setup_buf);
3398
3399err1:
3400 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3401 dwc->ep0_trb, dwc->ep0_trb_addr);
3402
3403err0:
3404 return ret;
3405}
3406
3407/* -------------------------------------------------------------------------- */
3408
3409void dwc3_gadget_exit(struct dwc3 *dwc)
3410{
3411 usb_del_gadget_udc(&dwc->gadget);
3412 dwc3_gadget_free_endpoints(dwc);
3413 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3414 dwc->bounce_addr);
3415 kfree(dwc->setup_buf);
3416 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3417 dwc->ep0_trb, dwc->ep0_trb_addr);
3418}
3419
3420int dwc3_gadget_suspend(struct dwc3 *dwc)
3421{
3422 if (!dwc->gadget_driver)
3423 return 0;
3424
3425 dwc3_gadget_run_stop(dwc, false, false);
3426 dwc3_disconnect_gadget(dwc);
3427 __dwc3_gadget_stop(dwc);
3428
3429 return 0;
3430}
3431
3432int dwc3_gadget_resume(struct dwc3 *dwc)
3433{
3434 int ret;
3435
3436 if (!dwc->gadget_driver)
3437 return 0;
3438
3439 ret = __dwc3_gadget_start(dwc);
3440 if (ret < 0)
3441 goto err0;
3442
3443 ret = dwc3_gadget_run_stop(dwc, true, false);
3444 if (ret < 0)
3445 goto err1;
3446
3447 return 0;
3448
3449err1:
3450 __dwc3_gadget_stop(dwc);
3451
3452err0:
3453 return ret;
3454}
3455
3456void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3457{
3458 if (dwc->pending_events) {
3459 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3460 dwc->pending_events = false;
3461 enable_irq(dwc->irq_gadget);
3462 }
3463}