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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015, Sony Mobile Communications AB.
4 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
5 */
6
7#include <linux/module.h>
8#include <linux/of.h>
9#include <linux/platform_device.h>
10#include <linux/regulator/driver.h>
11#include <linux/regulator/of_regulator.h>
12#include <linux/soc/qcom/smd-rpm.h>
13
14struct qcom_rpm_reg {
15 struct device *dev;
16
17 struct qcom_smd_rpm *rpm;
18
19 u32 type;
20 u32 id;
21
22 struct regulator_desc desc;
23
24 int is_enabled;
25 int uV;
26 u32 load;
27
28 unsigned int enabled_updated:1;
29 unsigned int uv_updated:1;
30 unsigned int load_updated:1;
31};
32
33struct rpm_regulator_req {
34 __le32 key;
35 __le32 nbytes;
36 __le32 value;
37};
38
39#define RPM_KEY_SWEN 0x6e657773 /* "swen" */
40#define RPM_KEY_UV 0x00007675 /* "uv" */
41#define RPM_KEY_MA 0x0000616d /* "ma" */
42
43static int rpm_reg_write_active(struct qcom_rpm_reg *vreg)
44{
45 struct rpm_regulator_req req[3];
46 int reqlen = 0;
47 int ret;
48
49 if (vreg->enabled_updated) {
50 req[reqlen].key = cpu_to_le32(RPM_KEY_SWEN);
51 req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
52 req[reqlen].value = cpu_to_le32(vreg->is_enabled);
53 reqlen++;
54 }
55
56 if (vreg->uv_updated && vreg->is_enabled) {
57 req[reqlen].key = cpu_to_le32(RPM_KEY_UV);
58 req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
59 req[reqlen].value = cpu_to_le32(vreg->uV);
60 reqlen++;
61 }
62
63 if (vreg->load_updated && vreg->is_enabled) {
64 req[reqlen].key = cpu_to_le32(RPM_KEY_MA);
65 req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
66 req[reqlen].value = cpu_to_le32(vreg->load / 1000);
67 reqlen++;
68 }
69
70 if (!reqlen)
71 return 0;
72
73 ret = qcom_rpm_smd_write(vreg->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
74 vreg->type, vreg->id,
75 req, sizeof(req[0]) * reqlen);
76 if (!ret) {
77 vreg->enabled_updated = 0;
78 vreg->uv_updated = 0;
79 vreg->load_updated = 0;
80 }
81
82 return ret;
83}
84
85static int rpm_reg_enable(struct regulator_dev *rdev)
86{
87 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
88 int ret;
89
90 vreg->is_enabled = 1;
91 vreg->enabled_updated = 1;
92
93 ret = rpm_reg_write_active(vreg);
94 if (ret)
95 vreg->is_enabled = 0;
96
97 return ret;
98}
99
100static int rpm_reg_is_enabled(struct regulator_dev *rdev)
101{
102 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
103
104 return vreg->is_enabled;
105}
106
107static int rpm_reg_disable(struct regulator_dev *rdev)
108{
109 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
110 int ret;
111
112 vreg->is_enabled = 0;
113 vreg->enabled_updated = 1;
114
115 ret = rpm_reg_write_active(vreg);
116 if (ret)
117 vreg->is_enabled = 1;
118
119 return ret;
120}
121
122static int rpm_reg_get_voltage(struct regulator_dev *rdev)
123{
124 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
125
126 return vreg->uV;
127}
128
129static int rpm_reg_set_voltage(struct regulator_dev *rdev,
130 int min_uV,
131 int max_uV,
132 unsigned *selector)
133{
134 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
135 int ret;
136 int old_uV = vreg->uV;
137
138 vreg->uV = min_uV;
139 vreg->uv_updated = 1;
140
141 ret = rpm_reg_write_active(vreg);
142 if (ret)
143 vreg->uV = old_uV;
144
145 return ret;
146}
147
148static int rpm_reg_set_load(struct regulator_dev *rdev, int load_uA)
149{
150 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
151 u32 old_load = vreg->load;
152 int ret;
153
154 vreg->load = load_uA;
155 vreg->load_updated = 1;
156 ret = rpm_reg_write_active(vreg);
157 if (ret)
158 vreg->load = old_load;
159
160 return ret;
161}
162
163static const struct regulator_ops rpm_smps_ldo_ops = {
164 .enable = rpm_reg_enable,
165 .disable = rpm_reg_disable,
166 .is_enabled = rpm_reg_is_enabled,
167 .list_voltage = regulator_list_voltage_linear_range,
168
169 .get_voltage = rpm_reg_get_voltage,
170 .set_voltage = rpm_reg_set_voltage,
171
172 .set_load = rpm_reg_set_load,
173};
174
175static const struct regulator_ops rpm_smps_ldo_ops_fixed = {
176 .enable = rpm_reg_enable,
177 .disable = rpm_reg_disable,
178 .is_enabled = rpm_reg_is_enabled,
179
180 .get_voltage = rpm_reg_get_voltage,
181 .set_voltage = rpm_reg_set_voltage,
182
183 .set_load = rpm_reg_set_load,
184};
185
186static const struct regulator_ops rpm_switch_ops = {
187 .enable = rpm_reg_enable,
188 .disable = rpm_reg_disable,
189 .is_enabled = rpm_reg_is_enabled,
190};
191
192static const struct regulator_ops rpm_bob_ops = {
193 .enable = rpm_reg_enable,
194 .disable = rpm_reg_disable,
195 .is_enabled = rpm_reg_is_enabled,
196
197 .get_voltage = rpm_reg_get_voltage,
198 .set_voltage = rpm_reg_set_voltage,
199};
200
201static const struct regulator_ops rpm_mp5496_ops = {
202 .enable = rpm_reg_enable,
203 .disable = rpm_reg_disable,
204 .is_enabled = rpm_reg_is_enabled,
205 .list_voltage = regulator_list_voltage_linear_range,
206
207 .get_voltage = rpm_reg_get_voltage,
208 .set_voltage = rpm_reg_set_voltage,
209};
210
211static const struct regulator_desc pma8084_hfsmps = {
212 .linear_ranges = (struct linear_range[]) {
213 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
214 REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000),
215 },
216 .n_linear_ranges = 2,
217 .n_voltages = 159,
218 .ops = &rpm_smps_ldo_ops,
219};
220
221static const struct regulator_desc pma8084_ftsmps = {
222 .linear_ranges = (struct linear_range[]) {
223 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
224 REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
225 },
226 .n_linear_ranges = 2,
227 .n_voltages = 262,
228 .ops = &rpm_smps_ldo_ops,
229};
230
231static const struct regulator_desc pma8084_pldo = {
232 .linear_ranges = (struct linear_range[]) {
233 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
234 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
235 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
236 },
237 .n_linear_ranges = 3,
238 .n_voltages = 164,
239 .ops = &rpm_smps_ldo_ops,
240};
241
242static const struct regulator_desc pma8084_nldo = {
243 .linear_ranges = (struct linear_range[]) {
244 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
245 },
246 .n_linear_ranges = 1,
247 .n_voltages = 64,
248 .ops = &rpm_smps_ldo_ops,
249};
250
251static const struct regulator_desc pma8084_switch = {
252 .ops = &rpm_switch_ops,
253};
254
255static const struct regulator_desc pm8226_hfsmps = {
256 .linear_ranges = (struct linear_range[]) {
257 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
258 REGULATOR_LINEAR_RANGE(1575000, 96, 158, 25000),
259 },
260 .n_linear_ranges = 2,
261 .n_voltages = 159,
262 .ops = &rpm_smps_ldo_ops,
263};
264
265static const struct regulator_desc pm8226_ftsmps = {
266 .linear_ranges = (struct linear_range[]) {
267 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
268 REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
269 },
270 .n_linear_ranges = 2,
271 .n_voltages = 262,
272 .ops = &rpm_smps_ldo_ops,
273};
274
275static const struct regulator_desc pm8226_pldo = {
276 .linear_ranges = (struct linear_range[]) {
277 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
278 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
279 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
280 },
281 .n_linear_ranges = 3,
282 .n_voltages = 164,
283 .ops = &rpm_smps_ldo_ops,
284};
285
286static const struct regulator_desc pm8226_nldo = {
287 .linear_ranges = (struct linear_range[]) {
288 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
289 },
290 .n_linear_ranges = 1,
291 .n_voltages = 64,
292 .ops = &rpm_smps_ldo_ops,
293};
294
295static const struct regulator_desc pm8226_switch = {
296 .ops = &rpm_switch_ops,
297};
298
299static const struct regulator_desc pm8x41_hfsmps = {
300 .linear_ranges = (struct linear_range[]) {
301 REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500),
302 REGULATOR_LINEAR_RANGE(1575000, 96, 158, 25000),
303 },
304 .n_linear_ranges = 2,
305 .n_voltages = 159,
306 .ops = &rpm_smps_ldo_ops,
307};
308
309static const struct regulator_desc pm8841_ftsmps = {
310 .linear_ranges = (struct linear_range[]) {
311 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
312 REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
313 },
314 .n_linear_ranges = 2,
315 .n_voltages = 262,
316 .ops = &rpm_smps_ldo_ops,
317};
318
319static const struct regulator_desc pm8941_boost = {
320 .linear_ranges = (struct linear_range[]) {
321 REGULATOR_LINEAR_RANGE(4000000, 0, 30, 50000),
322 },
323 .n_linear_ranges = 1,
324 .n_voltages = 31,
325 .ops = &rpm_smps_ldo_ops,
326};
327
328static const struct regulator_desc pm8941_pldo = {
329 .linear_ranges = (struct linear_range[]) {
330 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
331 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
332 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
333 },
334 .n_linear_ranges = 3,
335 .n_voltages = 164,
336 .ops = &rpm_smps_ldo_ops,
337};
338
339static const struct regulator_desc pm8941_nldo = {
340 .linear_ranges = (struct linear_range[]) {
341 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
342 },
343 .n_linear_ranges = 1,
344 .n_voltages = 64,
345 .ops = &rpm_smps_ldo_ops,
346};
347
348static const struct regulator_desc pm8941_lnldo = {
349 .fixed_uV = 1740000,
350 .n_voltages = 1,
351 .ops = &rpm_smps_ldo_ops_fixed,
352};
353
354static const struct regulator_desc pm8941_switch = {
355 .ops = &rpm_switch_ops,
356};
357
358static const struct regulator_desc pm8916_pldo = {
359 .linear_ranges = (struct linear_range[]) {
360 REGULATOR_LINEAR_RANGE(1750000, 0, 127, 12500),
361 },
362 .n_linear_ranges = 1,
363 .n_voltages = 128,
364 .ops = &rpm_smps_ldo_ops,
365};
366
367static const struct regulator_desc pm8916_nldo = {
368 .linear_ranges = (struct linear_range[]) {
369 REGULATOR_LINEAR_RANGE(375000, 0, 93, 12500),
370 },
371 .n_linear_ranges = 1,
372 .n_voltages = 94,
373 .ops = &rpm_smps_ldo_ops,
374};
375
376static const struct regulator_desc pm8916_buck_lvo_smps = {
377 .linear_ranges = (struct linear_range[]) {
378 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
379 REGULATOR_LINEAR_RANGE(750000, 96, 127, 25000),
380 },
381 .n_linear_ranges = 2,
382 .n_voltages = 128,
383 .ops = &rpm_smps_ldo_ops,
384};
385
386static const struct regulator_desc pm8916_buck_hvo_smps = {
387 .linear_ranges = (struct linear_range[]) {
388 REGULATOR_LINEAR_RANGE(1550000, 0, 31, 25000),
389 },
390 .n_linear_ranges = 1,
391 .n_voltages = 32,
392 .ops = &rpm_smps_ldo_ops,
393};
394
395static const struct regulator_desc pm8950_hfsmps = {
396 .linear_ranges = (struct linear_range[]) {
397 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
398 REGULATOR_LINEAR_RANGE(1550000, 96, 127, 25000),
399 },
400 .n_linear_ranges = 2,
401 .n_voltages = 128,
402 .ops = &rpm_smps_ldo_ops,
403};
404
405static const struct regulator_desc pm8950_ftsmps2p5 = {
406 .linear_ranges = (struct linear_range[]) {
407 REGULATOR_LINEAR_RANGE(80000, 0, 255, 5000),
408 REGULATOR_LINEAR_RANGE(160000, 256, 460, 10000),
409 },
410 .n_linear_ranges = 2,
411 .n_voltages = 461,
412 .ops = &rpm_smps_ldo_ops,
413};
414
415static const struct regulator_desc pm8950_ult_nldo = {
416 .linear_ranges = (struct linear_range[]) {
417 REGULATOR_LINEAR_RANGE(375000, 0, 202, 12500),
418 },
419 .n_linear_ranges = 1,
420 .n_voltages = 203,
421 .ops = &rpm_smps_ldo_ops,
422};
423
424static const struct regulator_desc pm8950_ult_pldo = {
425 .linear_ranges = (struct linear_range[]) {
426 REGULATOR_LINEAR_RANGE(1750000, 0, 127, 12500),
427 },
428 .n_linear_ranges = 1,
429 .n_voltages = 128,
430 .ops = &rpm_smps_ldo_ops,
431};
432
433static const struct regulator_desc pm8950_pldo_lv = {
434 .linear_ranges = (struct linear_range[]) {
435 REGULATOR_LINEAR_RANGE(1500000, 0, 16, 25000),
436 },
437 .n_linear_ranges = 1,
438 .n_voltages = 17,
439 .ops = &rpm_smps_ldo_ops,
440};
441
442static const struct regulator_desc pm8950_pldo = {
443 .linear_ranges = (struct linear_range[]) {
444 REGULATOR_LINEAR_RANGE(975000, 0, 164, 12500),
445 },
446 .n_linear_ranges = 1,
447 .n_voltages = 165,
448 .ops = &rpm_smps_ldo_ops,
449};
450
451static const struct regulator_desc pm8953_lnldo = {
452 .linear_ranges = (struct linear_range[]) {
453 REGULATOR_LINEAR_RANGE(690000, 0, 7, 60000),
454 REGULATOR_LINEAR_RANGE(1380000, 8, 15, 120000),
455 },
456 .n_linear_ranges = 2,
457 .n_voltages = 16,
458 .ops = &rpm_smps_ldo_ops,
459};
460
461static const struct regulator_desc pm8953_ult_nldo = {
462 .linear_ranges = (struct linear_range[]) {
463 REGULATOR_LINEAR_RANGE(375000, 0, 93, 12500),
464 },
465 .n_linear_ranges = 1,
466 .n_voltages = 94,
467 .ops = &rpm_smps_ldo_ops,
468};
469
470static const struct regulator_desc pm8994_hfsmps = {
471 .linear_ranges = (struct linear_range[]) {
472 REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500),
473 REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000),
474 },
475 .n_linear_ranges = 2,
476 .n_voltages = 159,
477 .ops = &rpm_smps_ldo_ops,
478};
479
480static const struct regulator_desc pm8994_ftsmps = {
481 .linear_ranges = (struct linear_range[]) {
482 REGULATOR_LINEAR_RANGE(350000, 0, 199, 5000),
483 REGULATOR_LINEAR_RANGE(700000, 200, 349, 10000),
484 },
485 .n_linear_ranges = 2,
486 .n_voltages = 350,
487 .ops = &rpm_smps_ldo_ops,
488};
489
490static const struct regulator_desc pm8994_nldo = {
491 .linear_ranges = (struct linear_range[]) {
492 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
493 },
494 .n_linear_ranges = 1,
495 .n_voltages = 64,
496 .ops = &rpm_smps_ldo_ops,
497};
498
499static const struct regulator_desc pm8994_pldo = {
500 .linear_ranges = (struct linear_range[]) {
501 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
502 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
503 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
504 },
505 .n_linear_ranges = 3,
506 .n_voltages = 164,
507 .ops = &rpm_smps_ldo_ops,
508};
509
510static const struct regulator_desc pm8994_switch = {
511 .ops = &rpm_switch_ops,
512};
513
514static const struct regulator_desc pm8994_lnldo = {
515 .fixed_uV = 1740000,
516 .n_voltages = 1,
517 .ops = &rpm_smps_ldo_ops_fixed,
518};
519
520static const struct regulator_desc pmi8994_ftsmps = {
521 .linear_ranges = (struct linear_range[]) {
522 REGULATOR_LINEAR_RANGE(350000, 0, 199, 5000),
523 REGULATOR_LINEAR_RANGE(700000, 200, 349, 10000),
524 },
525 .n_linear_ranges = 2,
526 .n_voltages = 350,
527 .ops = &rpm_smps_ldo_ops,
528};
529
530static const struct regulator_desc pmi8994_hfsmps = {
531 .linear_ranges = (struct linear_range[]) {
532 REGULATOR_LINEAR_RANGE(350000, 0, 80, 12500),
533 REGULATOR_LINEAR_RANGE(700000, 81, 141, 25000),
534 },
535 .n_linear_ranges = 2,
536 .n_voltages = 142,
537 .ops = &rpm_smps_ldo_ops,
538};
539
540static const struct regulator_desc pmi8994_bby = {
541 .linear_ranges = (struct linear_range[]) {
542 REGULATOR_LINEAR_RANGE(3000000, 0, 44, 50000),
543 },
544 .n_linear_ranges = 1,
545 .n_voltages = 45,
546 .ops = &rpm_bob_ops,
547};
548
549static const struct regulator_desc pm8998_ftsmps = {
550 .linear_ranges = (struct linear_range[]) {
551 REGULATOR_LINEAR_RANGE(320000, 0, 258, 4000),
552 },
553 .n_linear_ranges = 1,
554 .n_voltages = 259,
555 .ops = &rpm_smps_ldo_ops,
556};
557
558static const struct regulator_desc pm8998_hfsmps = {
559 .linear_ranges = (struct linear_range[]) {
560 REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000),
561 },
562 .n_linear_ranges = 1,
563 .n_voltages = 216,
564 .ops = &rpm_smps_ldo_ops,
565};
566
567static const struct regulator_desc pm8998_nldo = {
568 .linear_ranges = (struct linear_range[]) {
569 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
570 },
571 .n_linear_ranges = 1,
572 .n_voltages = 128,
573 .ops = &rpm_smps_ldo_ops,
574};
575
576static const struct regulator_desc pm8998_pldo = {
577 .linear_ranges = (struct linear_range[]) {
578 REGULATOR_LINEAR_RANGE(1664000, 0, 255, 8000),
579 },
580 .n_linear_ranges = 1,
581 .n_voltages = 256,
582 .ops = &rpm_smps_ldo_ops,
583};
584
585static const struct regulator_desc pm8998_pldo_lv = {
586 .linear_ranges = (struct linear_range[]) {
587 REGULATOR_LINEAR_RANGE(1256000, 0, 127, 8000),
588 },
589 .n_linear_ranges = 1,
590 .n_voltages = 128,
591 .ops = &rpm_smps_ldo_ops,
592};
593
594static const struct regulator_desc pm8998_switch = {
595 .ops = &rpm_switch_ops,
596};
597
598static const struct regulator_desc pmi8998_bob = {
599 .linear_ranges = (struct linear_range[]) {
600 REGULATOR_LINEAR_RANGE(1824000, 0, 83, 32000),
601 },
602 .n_linear_ranges = 1,
603 .n_voltages = 84,
604 .ops = &rpm_bob_ops,
605};
606
607static const struct regulator_desc pm660_ftsmps = {
608 .linear_ranges = (struct linear_range[]) {
609 REGULATOR_LINEAR_RANGE(355000, 0, 199, 5000),
610 },
611 .n_linear_ranges = 1,
612 .n_voltages = 200,
613 .ops = &rpm_smps_ldo_ops,
614};
615
616static const struct regulator_desc pm660_hfsmps = {
617 .linear_ranges = (struct linear_range[]) {
618 REGULATOR_LINEAR_RANGE(320000, 0, 216, 8000),
619 },
620 .n_linear_ranges = 1,
621 .n_voltages = 217,
622 .ops = &rpm_smps_ldo_ops,
623};
624
625static const struct regulator_desc pm660_ht_nldo = {
626 .linear_ranges = (struct linear_range[]) {
627 REGULATOR_LINEAR_RANGE(312000, 0, 124, 8000),
628 },
629 .n_linear_ranges = 1,
630 .n_voltages = 125,
631 .ops = &rpm_smps_ldo_ops,
632};
633
634static const struct regulator_desc pm660_ht_lvpldo = {
635 .linear_ranges = (struct linear_range[]) {
636 REGULATOR_LINEAR_RANGE(1504000, 0, 62, 8000),
637 },
638 .n_linear_ranges = 1,
639 .n_voltages = 63,
640 .ops = &rpm_smps_ldo_ops,
641};
642
643static const struct regulator_desc pm660_nldo660 = {
644 .linear_ranges = (struct linear_range[]) {
645 REGULATOR_LINEAR_RANGE(320000, 0, 123, 8000),
646 },
647 .n_linear_ranges = 1,
648 .n_voltages = 124,
649 .ops = &rpm_smps_ldo_ops,
650};
651
652static const struct regulator_desc pm660_pldo660 = {
653 .linear_ranges = (struct linear_range[]) {
654 REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000),
655 },
656 .n_linear_ranges = 1,
657 .n_voltages = 256,
658 .ops = &rpm_smps_ldo_ops,
659};
660
661static const struct regulator_desc pm660l_bob = {
662 .linear_ranges = (struct linear_range[]) {
663 REGULATOR_LINEAR_RANGE(1800000, 0, 84, 32000),
664 },
665 .n_linear_ranges = 1,
666 .n_voltages = 85,
667 .ops = &rpm_bob_ops,
668};
669
670static const struct regulator_desc pm6125_ftsmps = {
671 .linear_ranges = (struct linear_range[]) {
672 REGULATOR_LINEAR_RANGE(300000, 0, 268, 4000),
673 },
674 .n_linear_ranges = 1,
675 .n_voltages = 269,
676 .ops = &rpm_smps_ldo_ops,
677};
678
679static const struct regulator_desc pmic5_ftsmps520 = {
680 .linear_ranges = (struct linear_range[]) {
681 REGULATOR_LINEAR_RANGE(300000, 0, 263, 4000),
682 },
683 .n_linear_ranges = 1,
684 .n_voltages = 264,
685 .ops = &rpm_smps_ldo_ops,
686};
687
688static const struct regulator_desc pmic5_hfsmps515 = {
689 .linear_ranges = (struct linear_range[]) {
690 REGULATOR_LINEAR_RANGE(320000, 0, 235, 16000),
691 },
692 .n_linear_ranges = 1,
693 .n_voltages = 236,
694 .ops = &rpm_smps_ldo_ops,
695};
696
697static const struct regulator_desc pms405_hfsmps3 = {
698 .linear_ranges = (struct linear_range[]) {
699 REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000),
700 },
701 .n_linear_ranges = 1,
702 .n_voltages = 216,
703 .ops = &rpm_smps_ldo_ops,
704};
705
706static const struct regulator_desc pms405_nldo300 = {
707 .linear_ranges = (struct linear_range[]) {
708 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
709 },
710 .n_linear_ranges = 1,
711 .n_voltages = 128,
712 .ops = &rpm_smps_ldo_ops,
713};
714
715static const struct regulator_desc pms405_nldo1200 = {
716 .linear_ranges = (struct linear_range[]) {
717 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
718 },
719 .n_linear_ranges = 1,
720 .n_voltages = 128,
721 .ops = &rpm_smps_ldo_ops,
722};
723
724static const struct regulator_desc pms405_pldo50 = {
725 .linear_ranges = (struct linear_range[]) {
726 REGULATOR_LINEAR_RANGE(1664000, 0, 128, 16000),
727 },
728 .n_linear_ranges = 1,
729 .n_voltages = 129,
730 .ops = &rpm_smps_ldo_ops,
731};
732
733static const struct regulator_desc pms405_pldo150 = {
734 .linear_ranges = (struct linear_range[]) {
735 REGULATOR_LINEAR_RANGE(1664000, 0, 128, 16000),
736 },
737 .n_linear_ranges = 1,
738 .n_voltages = 129,
739 .ops = &rpm_smps_ldo_ops,
740};
741
742static const struct regulator_desc pms405_pldo600 = {
743 .linear_ranges = (struct linear_range[]) {
744 REGULATOR_LINEAR_RANGE(1256000, 0, 98, 8000),
745 },
746 .n_linear_ranges = 1,
747 .n_voltages = 99,
748 .ops = &rpm_smps_ldo_ops,
749};
750
751static const struct regulator_desc mp5496_smps = {
752 .linear_ranges = (struct linear_range[]) {
753 REGULATOR_LINEAR_RANGE(600000, 0, 127, 12500),
754 },
755 .n_linear_ranges = 1,
756 .n_voltages = 128,
757 .ops = &rpm_mp5496_ops,
758};
759
760static const struct regulator_desc mp5496_ldoa2 = {
761 .linear_ranges = (struct linear_range[]) {
762 REGULATOR_LINEAR_RANGE(800000, 0, 127, 25000),
763 },
764 .n_linear_ranges = 1,
765 .n_voltages = 128,
766 .ops = &rpm_mp5496_ops,
767};
768
769static const struct regulator_desc pm2250_lvftsmps = {
770 .linear_ranges = (struct linear_range[]) {
771 REGULATOR_LINEAR_RANGE(320000, 0, 269, 4000),
772 },
773 .n_linear_ranges = 1,
774 .n_voltages = 270,
775 .ops = &rpm_smps_ldo_ops,
776};
777
778static const struct regulator_desc pm2250_ftsmps = {
779 .linear_ranges = (struct linear_range[]) {
780 REGULATOR_LINEAR_RANGE(640000, 0, 269, 8000),
781 },
782 .n_linear_ranges = 1,
783 .n_voltages = 270,
784 .ops = &rpm_smps_ldo_ops,
785};
786
787struct rpm_regulator_data {
788 const char *name;
789 u32 type;
790 u32 id;
791 const struct regulator_desc *desc;
792 const char *supply;
793};
794
795static const struct rpm_regulator_data rpm_mp5496_regulators[] = {
796 { "s1", QCOM_SMD_RPM_SMPA, 1, &mp5496_smps, "s1" },
797 { "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smps, "s2" },
798 { "l2", QCOM_SMD_RPM_LDOA, 2, &mp5496_ldoa2, "l2" },
799 { "l5", QCOM_SMD_RPM_LDOA, 5, &mp5496_ldoa2, "l5" },
800 {}
801};
802
803static const struct rpm_regulator_data rpm_pm2250_regulators[] = {
804 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm2250_lvftsmps, "vdd_s1" },
805 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm2250_lvftsmps, "vdd_s2" },
806 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm2250_lvftsmps, "vdd_s3" },
807 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm2250_ftsmps, "vdd_s4" },
808 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
809 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
810 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
811 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
812 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
813 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
814 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
815 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
816 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
817 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
818 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
819 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
820 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" },
821 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" },
822 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" },
823 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" },
824 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
825 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
826 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
827 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
828 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
829 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
830 {}
831};
832
833static const struct rpm_regulator_data rpm_pm6125_regulators[] = {
834 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm6125_ftsmps, "vdd_s1" },
835 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm6125_ftsmps, "vdd_s2" },
836 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm6125_ftsmps, "vdd_s3" },
837 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm6125_ftsmps, "vdd_s4" },
838 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8998_hfsmps, "vdd_s5" },
839 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8998_hfsmps, "vdd_s6" },
840 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_hfsmps, "vdd_s7" },
841 { "s8", QCOM_SMD_RPM_SMPA, 8, &pm6125_ftsmps, "vdd_s8" },
842 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l7_l17_l18" },
843 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_nldo660, "vdd_l2_l3_l4" },
844 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l2_l3_l4" },
845 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm660_nldo660, "vdd_l2_l3_l4" },
846 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
847 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_nldo660, "vdd_l6_l8" },
848 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_nldo660, "vdd_l1_l7_l17_l18" },
849 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_nldo660, "vdd_l6_l8" },
850 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_ht_lvpldo, "vdd_l9_l11" },
851 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_ht_lvpldo, "vdd_l10_l13_l14" },
852 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_ht_lvpldo, "vdd_l9_l11" },
853 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_ht_lvpldo, "vdd_l12_l16" },
854 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_ht_lvpldo, "vdd_l10_l13_l14" },
855 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l10_l13_l14" },
856 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
857 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_ht_lvpldo, "vdd_l12_l16" },
858 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_nldo660, "vdd_l1_l7_l17_l18" },
859 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_nldo660, "vdd_l1_l7_l17_l18" },
860 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
861 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
862 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
863 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
864 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm660_pldo660, "vdd_l23_l24" },
865 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm660_pldo660, "vdd_l23_l24" },
866 { }
867};
868
869static const struct rpm_regulator_data rpm_pm660_regulators[] = {
870 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm660_ftsmps, "vdd_s1" },
871 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm660_ftsmps, "vdd_s2" },
872 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm660_ftsmps, "vdd_s3" },
873 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm660_hfsmps, "vdd_s4" },
874 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm660_hfsmps, "vdd_s5" },
875 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm660_hfsmps, "vdd_s6" },
876 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l6_l7" },
877 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_ht_nldo, "vdd_l2_l3" },
878 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l2_l3" },
879 /* l4 is unaccessible on PM660 */
880 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_ht_nldo, "vdd_l5" },
881 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_ht_nldo, "vdd_l1_l6_l7" },
882 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_ht_nldo, "vdd_l1_l6_l7" },
883 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
884 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
885 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
886 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
887 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
888 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
889 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
890 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
891 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
892 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
893 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
894 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
895 { }
896};
897
898static const struct rpm_regulator_data rpm_pm660l_regulators[] = {
899 { "s1", QCOM_SMD_RPM_SMPB, 1, &pm660_ftsmps, "vdd_s1" },
900 { "s2", QCOM_SMD_RPM_SMPB, 2, &pm660_ftsmps, "vdd_s2" },
901 { "s3", QCOM_SMD_RPM_RWCX, 0, &pm660_ftsmps, "vdd_s3_s4" },
902 { "s5", QCOM_SMD_RPM_RWMX, 0, &pm660_ftsmps, "vdd_s5" },
903 { "l1", QCOM_SMD_RPM_LDOB, 1, &pm660_nldo660, "vdd_l1_l9_l10" },
904 { "l2", QCOM_SMD_RPM_LDOB, 2, &pm660_pldo660, "vdd_l2" },
905 { "l3", QCOM_SMD_RPM_LDOB, 3, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
906 { "l4", QCOM_SMD_RPM_LDOB, 4, &pm660_pldo660, "vdd_l4_l6" },
907 { "l5", QCOM_SMD_RPM_LDOB, 5, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
908 { "l6", QCOM_SMD_RPM_LDOB, 6, &pm660_pldo660, "vdd_l4_l6" },
909 { "l7", QCOM_SMD_RPM_LDOB, 7, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
910 { "l8", QCOM_SMD_RPM_LDOB, 8, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
911 { "l9", QCOM_SMD_RPM_RWLC, 0, &pm660_ht_nldo, "vdd_l1_l9_l10" },
912 { "l10", QCOM_SMD_RPM_RWLM, 0, &pm660_ht_nldo, "vdd_l1_l9_l10" },
913 { "bob", QCOM_SMD_RPM_BOBB, 1, &pm660l_bob, "vdd_bob", },
914 { }
915};
916
917static const struct rpm_regulator_data rpm_pm8226_regulators[] = {
918 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8226_hfsmps, "vdd_s1" },
919 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8226_ftsmps, "vdd_s2" },
920 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8226_hfsmps, "vdd_s3" },
921 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8226_hfsmps, "vdd_s4" },
922 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8226_hfsmps, "vdd_s5" },
923 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
924 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
925 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8226_nldo, "vdd_l3_l24_l26" },
926 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
927 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
928 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
929 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
930 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
931 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
932 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8226_pldo, "vdd_l10_l11_l13" },
933 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8226_pldo, "vdd_l10_l11_l13" },
934 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8226_pldo, "vdd_l12_l14" },
935 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8226_pldo, "vdd_l10_l11_l13" },
936 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8226_pldo, "vdd_l12_l14" },
937 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8226_pldo, "vdd_l15_l16_l17_l18" },
938 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8226_pldo, "vdd_l15_l16_l17_l18" },
939 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8226_pldo, "vdd_l15_l16_l17_l18" },
940 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8226_pldo, "vdd_l15_l16_l17_l18" },
941 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
942 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
943 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
944 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
945 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
946 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8226_nldo, "vdd_l3_l24_l26" },
947 { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8226_pldo, "vdd_l25" },
948 { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8226_nldo, "vdd_l3_l24_l26" },
949 { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
950 { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
951 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8226_switch, "vdd_lvs1" },
952 {}
953};
954
955static const struct rpm_regulator_data rpm_pm8841_regulators[] = {
956 { "s1", QCOM_SMD_RPM_SMPB, 1, &pm8x41_hfsmps, "vdd_s1" },
957 { "s2", QCOM_SMD_RPM_SMPB, 2, &pm8841_ftsmps, "vdd_s2" },
958 { "s3", QCOM_SMD_RPM_SMPB, 3, &pm8x41_hfsmps, "vdd_s3" },
959 { "s4", QCOM_SMD_RPM_SMPB, 4, &pm8841_ftsmps, "vdd_s4" },
960 { "s5", QCOM_SMD_RPM_SMPB, 5, &pm8841_ftsmps, "vdd_s5" },
961 { "s6", QCOM_SMD_RPM_SMPB, 6, &pm8841_ftsmps, "vdd_s6" },
962 { "s7", QCOM_SMD_RPM_SMPB, 7, &pm8841_ftsmps, "vdd_s7" },
963 { "s8", QCOM_SMD_RPM_SMPB, 8, &pm8841_ftsmps, "vdd_s8" },
964 {}
965};
966
967static const struct rpm_regulator_data rpm_pm8909_regulators[] = {
968 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8916_buck_lvo_smps, "vdd_s1" },
969 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8916_buck_hvo_smps, "vdd_s2" },
970 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8916_nldo, "vdd_l1" },
971 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8916_nldo, "vdd_l2_l5" },
972 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8916_nldo, "vdd_l3_l6_l10" },
973 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8916_pldo, "vdd_l4_l7" },
974 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8226_pldo, "vdd_l2_l5" },
975 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8226_pldo, "vdd_l3_l6_l10" },
976 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8226_pldo, "vdd_l4_l7" },
977 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8916_pldo, "vdd_l8_l11_l15_l18" },
978 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8916_pldo, "vdd_l9_l12_l14_l17" },
979 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8916_nldo, "vdd_l3_l6_l10" },
980 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8226_pldo, "vdd_l8_l11_l15_l18" },
981 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8916_pldo, "vdd_l9_l12_l14_l17" },
982 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8916_pldo, "vdd_l13" },
983 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8916_pldo, "vdd_l9_l12_l14_l17" },
984 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8916_pldo, "vdd_l8_l11_l15_l18" },
985 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8916_pldo, "vdd_l9_l12_l14_l17" },
986 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8916_pldo, "vdd_l8_l11_l15_l18" },
987 {}
988};
989
990static const struct rpm_regulator_data rpm_pm8916_regulators[] = {
991 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8916_buck_lvo_smps, "vdd_s1" },
992 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8916_buck_lvo_smps, "vdd_s2" },
993 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8916_buck_lvo_smps, "vdd_s3" },
994 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8916_buck_hvo_smps, "vdd_s4" },
995 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8916_nldo, "vdd_l1_l2_l3" },
996 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8916_nldo, "vdd_l1_l2_l3" },
997 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8916_nldo, "vdd_l1_l2_l3" },
998 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8916_pldo, "vdd_l4_l5_l6" },
999 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8916_pldo, "vdd_l4_l5_l6" },
1000 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8916_pldo, "vdd_l4_l5_l6" },
1001 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8916_pldo, "vdd_l7" },
1002 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" },
1003 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" },
1004 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
1005 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
1006 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
1007 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
1008 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
1009 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
1010 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
1011 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
1012 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
1013 {}
1014};
1015
1016static const struct rpm_regulator_data rpm_pm8937_regulators[] = {
1017 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8994_hfsmps, "vdd_s1" },
1018 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8994_hfsmps, "vdd_s2" },
1019 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8994_hfsmps, "vdd_s3" },
1020 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8994_hfsmps, "vdd_s4" },
1021 /* S5 - S6 are managed by SPMI */
1022
1023 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8953_ult_nldo, "vdd_l1_l19" },
1024 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8953_ult_nldo, "vdd_l2_l23" },
1025 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8953_ult_nldo, "vdd_l3" },
1026 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16" },
1027 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16" },
1028 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16" },
1029 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16" },
1030 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
1031 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
1032 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18"},
1033 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
1034 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
1035 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
1036 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
1037 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
1038 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16" },
1039 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
1040 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
1041 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8953_ult_nldo, "vdd_l1_l19" },
1042 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8953_lnldo, "vdd_l20_l21" },
1043 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8953_lnldo, "vdd_l20_l21" },
1044 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
1045 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8994_nldo, "vdd_l2_l23" },
1046 {}
1047};
1048
1049static const struct rpm_regulator_data rpm_pm8941_regulators[] = {
1050 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8x41_hfsmps, "vdd_s1" },
1051 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8x41_hfsmps, "vdd_s2" },
1052 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8x41_hfsmps, "vdd_s3" },
1053 { "s4", QCOM_SMD_RPM_BOOST, 1, &pm8941_boost },
1054
1055 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8941_nldo, "vdd_l1_l3" },
1056 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8941_nldo, "vdd_l2_lvs1_2_3" },
1057 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8941_nldo, "vdd_l1_l3" },
1058 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8941_nldo, "vdd_l4_l11" },
1059 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8941_lnldo, "vdd_l5_l7" },
1060 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
1061 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8941_lnldo, "vdd_l5_l7" },
1062 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
1063 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
1064 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
1065 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8941_nldo, "vdd_l4_l11" },
1066 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
1067 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
1068 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
1069 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
1070 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
1071 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
1072 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
1073 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
1074 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
1075 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8941_pldo, "vdd_l21" },
1076 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
1077 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
1078 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
1079
1080 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8941_switch, "vdd_l2_lvs1_2_3" },
1081 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8941_switch, "vdd_l2_lvs1_2_3" },
1082 { "lvs3", QCOM_SMD_RPM_VSA, 3, &pm8941_switch, "vdd_l2_lvs1_2_3" },
1083
1084 { "5vs1", QCOM_SMD_RPM_VSA, 4, &pm8941_switch, "vin_5vs" },
1085 { "5vs2", QCOM_SMD_RPM_VSA, 5, &pm8941_switch, "vin_5vs" },
1086
1087 {}
1088};
1089
1090static const struct rpm_regulator_data rpm_pm8950_regulators[] = {
1091 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8950_hfsmps, "vdd_s1" },
1092 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8950_hfsmps, "vdd_s2" },
1093 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8950_hfsmps, "vdd_s3" },
1094 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8950_hfsmps, "vdd_s4" },
1095 /* S5 is managed via SPMI. */
1096 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8950_hfsmps, "vdd_s6" },
1097
1098 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8950_ult_nldo, "vdd_l1_l19" },
1099 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8950_ult_nldo, "vdd_l2_l23" },
1100 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8950_ult_nldo, "vdd_l3" },
1101 /* L4 seems not to exist. */
1102 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" },
1103 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" },
1104 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" },
1105 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
1106 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
1107 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8950_ult_nldo, "vdd_l9_l10_l13_l14_l15_l18"},
1108 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
1109 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
1110 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
1111 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
1112 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
1113 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8950_ult_pldo, "vdd_l5_l6_l7_l16" },
1114 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
1115 /* L18 seems not to exist. */
1116 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8950_pldo, "vdd_l1_l19" },
1117 /* L20 & L21 seem not to exist. */
1118 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8950_pldo, "vdd_l8_l11_l12_l17_l22" },
1119 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8950_pldo, "vdd_l2_l23" },
1120 {}
1121};
1122
1123static const struct rpm_regulator_data rpm_pm8953_regulators[] = {
1124 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8998_hfsmps, "vdd_s1" },
1125 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8998_hfsmps, "vdd_s2" },
1126 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8998_hfsmps, "vdd_s3" },
1127 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8998_hfsmps, "vdd_s4" },
1128 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8950_ftsmps2p5, "vdd_s5" },
1129 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8950_ftsmps2p5, "vdd_s6" },
1130 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_hfsmps, "vdd_s7" },
1131
1132 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8953_ult_nldo, "vdd_l1" },
1133 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8953_ult_nldo, "vdd_l2_l3" },
1134 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8953_ult_nldo, "vdd_l2_l3" },
1135 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
1136 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
1137 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
1138 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
1139 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
1140 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
1141 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
1142 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
1143 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
1144 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
1145 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
1146 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
1147 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
1148 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
1149 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
1150 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8953_ult_nldo, "vdd_l4_l5_l6_l7_l16_l19" },
1151 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8953_lnldo, "vdd_l20" },
1152 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8953_lnldo, "vdd_l21" },
1153 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
1154 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8953_ult_nldo, "vdd_l23" },
1155 {}
1156};
1157
1158static const struct rpm_regulator_data rpm_pm8994_regulators[] = {
1159 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8994_ftsmps, "vdd_s1" },
1160 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8994_ftsmps, "vdd_s2" },
1161 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8994_hfsmps, "vdd_s3" },
1162 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8994_hfsmps, "vdd_s4" },
1163 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8994_hfsmps, "vdd_s5" },
1164 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8994_ftsmps, "vdd_s6" },
1165 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8994_hfsmps, "vdd_s7" },
1166 { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8994_ftsmps, "vdd_s8" },
1167 { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8994_ftsmps, "vdd_s9" },
1168 { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8994_ftsmps, "vdd_s10" },
1169 { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8994_ftsmps, "vdd_s11" },
1170 { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8994_ftsmps, "vdd_s12" },
1171 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8994_nldo, "vdd_l1" },
1172 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8994_nldo, "vdd_l2_l26_l28" },
1173 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8994_nldo, "vdd_l3_l11" },
1174 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8994_nldo, "vdd_l4_l27_l31" },
1175 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8994_lnldo, "vdd_l5_l7" },
1176 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8994_pldo, "vdd_l6_l12_l32" },
1177 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8994_lnldo, "vdd_l5_l7" },
1178 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8994_pldo, "vdd_l8_l16_l30" },
1179 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
1180 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
1181 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8994_nldo, "vdd_l3_l11" },
1182 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8994_pldo, "vdd_l6_l12_l32" },
1183 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
1184 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8994_pldo, "vdd_l14_l15" },
1185 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8994_pldo, "vdd_l14_l15" },
1186 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8994_pldo, "vdd_l8_l16_l30" },
1187 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8994_pldo, "vdd_l17_l29" },
1188 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
1189 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
1190 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8994_pldo, "vdd_l20_l21" },
1191 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8994_pldo, "vdd_l20_l21" },
1192 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
1193 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
1194 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
1195 { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8994_pldo, "vdd_l25" },
1196 { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8994_nldo, "vdd_l2_l26_l28" },
1197 { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8994_nldo, "vdd_l4_l27_l31" },
1198 { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8994_nldo, "vdd_l2_l26_l28" },
1199 { "l29", QCOM_SMD_RPM_LDOA, 29, &pm8994_pldo, "vdd_l17_l29" },
1200 { "l30", QCOM_SMD_RPM_LDOA, 30, &pm8994_pldo, "vdd_l8_l16_l30" },
1201 { "l31", QCOM_SMD_RPM_LDOA, 31, &pm8994_nldo, "vdd_l4_l27_l31" },
1202 { "l32", QCOM_SMD_RPM_LDOA, 32, &pm8994_pldo, "vdd_l6_l12_l32" },
1203 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8994_switch, "vdd_lvs1_2" },
1204 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8994_switch, "vdd_lvs1_2" },
1205
1206 {}
1207};
1208
1209static const struct rpm_regulator_data rpm_pm8998_regulators[] = {
1210 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8998_ftsmps, "vdd_s1" },
1211 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8998_ftsmps, "vdd_s2" },
1212 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8998_hfsmps, "vdd_s3" },
1213 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8998_hfsmps, "vdd_s4" },
1214 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8998_hfsmps, "vdd_s5" },
1215 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8998_ftsmps, "vdd_s6" },
1216 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_ftsmps, "vdd_s7" },
1217 { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8998_ftsmps, "vdd_s8" },
1218 { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8998_ftsmps, "vdd_s9" },
1219 { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8998_ftsmps, "vdd_s10" },
1220 { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8998_ftsmps, "vdd_s11" },
1221 { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8998_ftsmps, "vdd_s12" },
1222 { "s13", QCOM_SMD_RPM_SMPA, 13, &pm8998_ftsmps, "vdd_s13" },
1223 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8998_nldo, "vdd_l1_l27" },
1224 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8998_nldo, "vdd_l2_l8_l17" },
1225 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8998_nldo, "vdd_l3_l11" },
1226 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8998_nldo, "vdd_l4_l5" },
1227 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8998_nldo, "vdd_l4_l5" },
1228 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8998_pldo, "vdd_l6" },
1229 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
1230 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8998_nldo, "vdd_l2_l8_l17" },
1231 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8998_pldo, "vdd_l9" },
1232 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8998_pldo, "vdd_l10_l23_l25" },
1233 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8998_nldo, "vdd_l3_l11" },
1234 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
1235 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8998_pldo, "vdd_l13_l19_l21" },
1236 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
1237 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
1238 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8998_pldo, "vdd_l16_l28" },
1239 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8998_nldo, "vdd_l2_l8_l17" },
1240 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8998_pldo, "vdd_l18_l22" },
1241 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8998_pldo, "vdd_l13_l19_l21" },
1242 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8998_pldo, "vdd_l20_l24" },
1243 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8998_pldo, "vdd_l13_l19_l21" },
1244 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8998_pldo, "vdd_l18_l22" },
1245 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8998_pldo, "vdd_l10_l23_l25" },
1246 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8998_pldo, "vdd_l20_l24" },
1247 { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8998_pldo, "vdd_l10_l23_l25" },
1248 { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8998_nldo, "vdd_l26" },
1249 { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8998_nldo, "vdd_l1_l27" },
1250 { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8998_pldo, "vdd_l16_l28" },
1251 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8998_switch, "vdd_lvs1_lvs2" },
1252 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8998_switch, "vdd_lvs1_lvs2" },
1253 {}
1254};
1255
1256static const struct rpm_regulator_data rpm_pma8084_regulators[] = {
1257 { "s1", QCOM_SMD_RPM_SMPA, 1, &pma8084_ftsmps, "vdd_s1" },
1258 { "s2", QCOM_SMD_RPM_SMPA, 2, &pma8084_ftsmps, "vdd_s2" },
1259 { "s3", QCOM_SMD_RPM_SMPA, 3, &pma8084_hfsmps, "vdd_s3" },
1260 { "s4", QCOM_SMD_RPM_SMPA, 4, &pma8084_hfsmps, "vdd_s4" },
1261 { "s5", QCOM_SMD_RPM_SMPA, 5, &pma8084_hfsmps, "vdd_s5" },
1262 { "s6", QCOM_SMD_RPM_SMPA, 6, &pma8084_ftsmps, "vdd_s6" },
1263 { "s7", QCOM_SMD_RPM_SMPA, 7, &pma8084_ftsmps, "vdd_s7" },
1264 { "s8", QCOM_SMD_RPM_SMPA, 8, &pma8084_ftsmps, "vdd_s8" },
1265 { "s9", QCOM_SMD_RPM_SMPA, 9, &pma8084_ftsmps, "vdd_s9" },
1266 { "s10", QCOM_SMD_RPM_SMPA, 10, &pma8084_ftsmps, "vdd_s10" },
1267 { "s11", QCOM_SMD_RPM_SMPA, 11, &pma8084_ftsmps, "vdd_s11" },
1268 { "s12", QCOM_SMD_RPM_SMPA, 12, &pma8084_ftsmps, "vdd_s12" },
1269
1270 { "l1", QCOM_SMD_RPM_LDOA, 1, &pma8084_nldo, "vdd_l1_l11" },
1271 { "l2", QCOM_SMD_RPM_LDOA, 2, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
1272 { "l3", QCOM_SMD_RPM_LDOA, 3, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
1273 { "l4", QCOM_SMD_RPM_LDOA, 4, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
1274 { "l5", QCOM_SMD_RPM_LDOA, 5, &pma8084_pldo, "vdd_l5_l7" },
1275 { "l6", QCOM_SMD_RPM_LDOA, 6, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
1276 { "l7", QCOM_SMD_RPM_LDOA, 7, &pma8084_pldo, "vdd_l5_l7" },
1277 { "l8", QCOM_SMD_RPM_LDOA, 8, &pma8084_pldo, "vdd_l8" },
1278 { "l9", QCOM_SMD_RPM_LDOA, 9, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
1279 { "l10", QCOM_SMD_RPM_LDOA, 10, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
1280 { "l11", QCOM_SMD_RPM_LDOA, 11, &pma8084_nldo, "vdd_l1_l11" },
1281 { "l12", QCOM_SMD_RPM_LDOA, 12, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
1282 { "l13", QCOM_SMD_RPM_LDOA, 13, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
1283 { "l14", QCOM_SMD_RPM_LDOA, 14, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
1284 { "l15", QCOM_SMD_RPM_LDOA, 15, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
1285 { "l16", QCOM_SMD_RPM_LDOA, 16, &pma8084_pldo, "vdd_l16_l25" },
1286 { "l17", QCOM_SMD_RPM_LDOA, 17, &pma8084_pldo, "vdd_l17" },
1287 { "l18", QCOM_SMD_RPM_LDOA, 18, &pma8084_pldo, "vdd_l18" },
1288 { "l19", QCOM_SMD_RPM_LDOA, 19, &pma8084_pldo, "vdd_l19" },
1289 { "l20", QCOM_SMD_RPM_LDOA, 20, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
1290 { "l21", QCOM_SMD_RPM_LDOA, 21, &pma8084_pldo, "vdd_l21" },
1291 { "l22", QCOM_SMD_RPM_LDOA, 22, &pma8084_pldo, "vdd_l22" },
1292 { "l23", QCOM_SMD_RPM_LDOA, 23, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
1293 { "l24", QCOM_SMD_RPM_LDOA, 24, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
1294 { "l25", QCOM_SMD_RPM_LDOA, 25, &pma8084_pldo, "vdd_l16_l25" },
1295 { "l26", QCOM_SMD_RPM_LDOA, 26, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
1296 { "l27", QCOM_SMD_RPM_LDOA, 27, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
1297
1298 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pma8084_switch },
1299 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pma8084_switch },
1300 { "lvs3", QCOM_SMD_RPM_VSA, 3, &pma8084_switch },
1301 { "lvs4", QCOM_SMD_RPM_VSA, 4, &pma8084_switch },
1302 { "5vs1", QCOM_SMD_RPM_VSA, 5, &pma8084_switch },
1303
1304 {}
1305};
1306
1307static const struct rpm_regulator_data rpm_pmi8994_regulators[] = {
1308 { "s1", QCOM_SMD_RPM_SMPB, 1, &pmi8994_ftsmps, "vdd_s1" },
1309 { "s2", QCOM_SMD_RPM_SMPB, 2, &pmi8994_hfsmps, "vdd_s2" },
1310 { "s3", QCOM_SMD_RPM_SMPB, 3, &pmi8994_hfsmps, "vdd_s3" },
1311 { "boost-bypass", QCOM_SMD_RPM_BBYB, 1, &pmi8994_bby, "vdd_bst_byp" },
1312 {}
1313};
1314
1315static const struct rpm_regulator_data rpm_pmi8998_regulators[] = {
1316 { "bob", QCOM_SMD_RPM_BOBB, 1, &pmi8998_bob, "vdd_bob" },
1317 {}
1318};
1319
1320static const struct rpm_regulator_data rpm_pmr735a_regulators[] = {
1321 { "s1", QCOM_SMD_RPM_SMPE, 1, &pmic5_ftsmps520, "vdd_s1"},
1322 { "s2", QCOM_SMD_RPM_SMPE, 2, &pmic5_ftsmps520, "vdd_s2"},
1323 { "s3", QCOM_SMD_RPM_SMPE, 3, &pmic5_hfsmps515, "vdd_s3"},
1324 { "l1", QCOM_SMD_RPM_LDOE, 1, &pm660_nldo660, "vdd_l1_l2"},
1325 { "l2", QCOM_SMD_RPM_LDOE, 2, &pm660_nldo660, "vdd_l1_l2"},
1326 { "l3", QCOM_SMD_RPM_LDOE, 3, &pm660_nldo660, "vdd_l3"},
1327 { "l4", QCOM_SMD_RPM_LDOE, 4, &pm660_ht_lvpldo, "vdd_l4"},
1328 { "l5", QCOM_SMD_RPM_LDOE, 5, &pm660_nldo660, "vdd_l5_l6"},
1329 { "l6", QCOM_SMD_RPM_LDOE, 6, &pm660_nldo660, "vdd_l5_l6"},
1330 { "l7", QCOM_SMD_RPM_LDOE, 7, &pm660_pldo660, "vdd_l7_bob"},
1331 {}
1332};
1333
1334static const struct rpm_regulator_data rpm_pms405_regulators[] = {
1335 { "s1", QCOM_SMD_RPM_SMPA, 1, &pms405_hfsmps3, "vdd_s1" },
1336 { "s2", QCOM_SMD_RPM_SMPA, 2, &pms405_hfsmps3, "vdd_s2" },
1337 { "s3", QCOM_SMD_RPM_SMPA, 3, &pms405_hfsmps3, "vdd_s3" },
1338 { "s4", QCOM_SMD_RPM_SMPA, 4, &pms405_hfsmps3, "vdd_s4" },
1339 { "s5", QCOM_SMD_RPM_SMPA, 5, &pms405_hfsmps3, "vdd_s5" },
1340 { "l1", QCOM_SMD_RPM_LDOA, 1, &pms405_nldo1200, "vdd_l1_l2" },
1341 { "l2", QCOM_SMD_RPM_LDOA, 2, &pms405_nldo1200, "vdd_l1_l2" },
1342 { "l3", QCOM_SMD_RPM_LDOA, 3, &pms405_nldo1200, "vdd_l3_l8" },
1343 { "l4", QCOM_SMD_RPM_LDOA, 4, &pms405_nldo300, "vdd_l4" },
1344 { "l5", QCOM_SMD_RPM_LDOA, 5, &pms405_pldo600, "vdd_l5_l6" },
1345 { "l6", QCOM_SMD_RPM_LDOA, 6, &pms405_pldo600, "vdd_l5_l6" },
1346 { "l7", QCOM_SMD_RPM_LDOA, 7, &pms405_pldo150, "vdd_l7" },
1347 { "l8", QCOM_SMD_RPM_LDOA, 8, &pms405_nldo1200, "vdd_l3_l8" },
1348 { "l9", QCOM_SMD_RPM_LDOA, 9, &pms405_nldo1200, "vdd_l9" },
1349 { "l10", QCOM_SMD_RPM_LDOA, 10, &pms405_pldo50, "vdd_l10_l11_l12_l13" },
1350 { "l11", QCOM_SMD_RPM_LDOA, 11, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
1351 { "l12", QCOM_SMD_RPM_LDOA, 12, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
1352 { "l13", QCOM_SMD_RPM_LDOA, 13, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
1353 {}
1354};
1355
1356static const struct of_device_id rpm_of_match[] = {
1357 { .compatible = "qcom,rpm-mp5496-regulators", .data = &rpm_mp5496_regulators },
1358 { .compatible = "qcom,rpm-pm2250-regulators", .data = &rpm_pm2250_regulators },
1359 { .compatible = "qcom,rpm-pm6125-regulators", .data = &rpm_pm6125_regulators },
1360 { .compatible = "qcom,rpm-pm660-regulators", .data = &rpm_pm660_regulators },
1361 { .compatible = "qcom,rpm-pm660l-regulators", .data = &rpm_pm660l_regulators },
1362 { .compatible = "qcom,rpm-pm8226-regulators", .data = &rpm_pm8226_regulators },
1363 { .compatible = "qcom,rpm-pm8841-regulators", .data = &rpm_pm8841_regulators },
1364 { .compatible = "qcom,rpm-pm8909-regulators", .data = &rpm_pm8909_regulators },
1365 { .compatible = "qcom,rpm-pm8916-regulators", .data = &rpm_pm8916_regulators },
1366 { .compatible = "qcom,rpm-pm8937-regulators", .data = &rpm_pm8937_regulators },
1367 { .compatible = "qcom,rpm-pm8941-regulators", .data = &rpm_pm8941_regulators },
1368 { .compatible = "qcom,rpm-pm8950-regulators", .data = &rpm_pm8950_regulators },
1369 { .compatible = "qcom,rpm-pm8953-regulators", .data = &rpm_pm8953_regulators },
1370 { .compatible = "qcom,rpm-pm8994-regulators", .data = &rpm_pm8994_regulators },
1371 { .compatible = "qcom,rpm-pm8998-regulators", .data = &rpm_pm8998_regulators },
1372 { .compatible = "qcom,rpm-pma8084-regulators", .data = &rpm_pma8084_regulators },
1373 { .compatible = "qcom,rpm-pmi8994-regulators", .data = &rpm_pmi8994_regulators },
1374 { .compatible = "qcom,rpm-pmi8998-regulators", .data = &rpm_pmi8998_regulators },
1375 { .compatible = "qcom,rpm-pmr735a-regulators", .data = &rpm_pmr735a_regulators },
1376 { .compatible = "qcom,rpm-pms405-regulators", .data = &rpm_pms405_regulators },
1377 {}
1378};
1379MODULE_DEVICE_TABLE(of, rpm_of_match);
1380
1381/**
1382 * rpm_regulator_init_vreg() - initialize all attributes of a qcom_smd-regulator
1383 * @vreg: Pointer to the individual qcom_smd-regulator resource
1384 * @dev: Pointer to the top level qcom_smd-regulator PMIC device
1385 * @node: Pointer to the individual qcom_smd-regulator resource
1386 * device node
1387 * @rpm: Pointer to the rpm bus node
1388 * @pmic_rpm_data: Pointer to a null-terminated array of qcom_smd-regulator
1389 * resources defined for the top level PMIC device
1390 *
1391 * Return: 0 on success, errno on failure
1392 */
1393static int rpm_regulator_init_vreg(struct qcom_rpm_reg *vreg, struct device *dev,
1394 struct device_node *node, struct qcom_smd_rpm *rpm,
1395 const struct rpm_regulator_data *pmic_rpm_data)
1396{
1397 struct regulator_config config = {};
1398 const struct rpm_regulator_data *rpm_data;
1399 struct regulator_dev *rdev;
1400 int ret;
1401
1402 for (rpm_data = pmic_rpm_data; rpm_data->name; rpm_data++)
1403 if (of_node_name_eq(node, rpm_data->name))
1404 break;
1405
1406 if (!rpm_data->name) {
1407 dev_err(dev, "Unknown regulator %pOFn\n", node);
1408 return -EINVAL;
1409 }
1410
1411 vreg->dev = dev;
1412 vreg->rpm = rpm;
1413 vreg->type = rpm_data->type;
1414 vreg->id = rpm_data->id;
1415
1416 memcpy(&vreg->desc, rpm_data->desc, sizeof(vreg->desc));
1417 vreg->desc.name = rpm_data->name;
1418 vreg->desc.supply_name = rpm_data->supply;
1419 vreg->desc.owner = THIS_MODULE;
1420 vreg->desc.type = REGULATOR_VOLTAGE;
1421 vreg->desc.of_match = rpm_data->name;
1422
1423 config.dev = dev;
1424 config.of_node = node;
1425 config.driver_data = vreg;
1426
1427 rdev = devm_regulator_register(dev, &vreg->desc, &config);
1428 if (IS_ERR(rdev)) {
1429 ret = PTR_ERR(rdev);
1430 dev_err(dev, "%pOFn: devm_regulator_register() failed, ret=%d\n", node, ret);
1431 return ret;
1432 }
1433
1434 return 0;
1435}
1436
1437static int rpm_reg_probe(struct platform_device *pdev)
1438{
1439 struct device *dev = &pdev->dev;
1440 const struct rpm_regulator_data *vreg_data;
1441 struct device_node *node;
1442 struct qcom_rpm_reg *vreg;
1443 struct qcom_smd_rpm *rpm;
1444 int ret;
1445
1446 rpm = dev_get_drvdata(pdev->dev.parent);
1447 if (!rpm) {
1448 dev_err(&pdev->dev, "Unable to retrieve handle to rpm\n");
1449 return -ENODEV;
1450 }
1451
1452 vreg_data = of_device_get_match_data(dev);
1453 if (!vreg_data)
1454 return -ENODEV;
1455
1456 for_each_available_child_of_node(dev->of_node, node) {
1457 vreg = devm_kzalloc(&pdev->dev, sizeof(*vreg), GFP_KERNEL);
1458 if (!vreg) {
1459 of_node_put(node);
1460 return -ENOMEM;
1461 }
1462
1463 ret = rpm_regulator_init_vreg(vreg, dev, node, rpm, vreg_data);
1464
1465 if (ret < 0) {
1466 of_node_put(node);
1467 return ret;
1468 }
1469 }
1470
1471 return 0;
1472}
1473
1474static struct platform_driver rpm_reg_driver = {
1475 .probe = rpm_reg_probe,
1476 .driver = {
1477 .name = "qcom_rpm_smd_regulator",
1478 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1479 .of_match_table = rpm_of_match,
1480 },
1481};
1482
1483static int __init rpm_reg_init(void)
1484{
1485 return platform_driver_register(&rpm_reg_driver);
1486}
1487subsys_initcall(rpm_reg_init);
1488
1489static void __exit rpm_reg_exit(void)
1490{
1491 platform_driver_unregister(&rpm_reg_driver);
1492}
1493module_exit(rpm_reg_exit)
1494
1495MODULE_DESCRIPTION("Qualcomm RPM regulator driver");
1496MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015, Sony Mobile Communications AB.
4 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
5 */
6
7#include <linux/module.h>
8#include <linux/of.h>
9#include <linux/of_device.h>
10#include <linux/platform_device.h>
11#include <linux/regulator/driver.h>
12#include <linux/soc/qcom/smd-rpm.h>
13
14struct qcom_rpm_reg {
15 struct device *dev;
16
17 struct qcom_smd_rpm *rpm;
18
19 u32 type;
20 u32 id;
21
22 struct regulator_desc desc;
23
24 int is_enabled;
25 int uV;
26 u32 load;
27
28 unsigned int enabled_updated:1;
29 unsigned int uv_updated:1;
30 unsigned int load_updated:1;
31};
32
33struct rpm_regulator_req {
34 __le32 key;
35 __le32 nbytes;
36 __le32 value;
37};
38
39#define RPM_KEY_SWEN 0x6e657773 /* "swen" */
40#define RPM_KEY_UV 0x00007675 /* "uv" */
41#define RPM_KEY_MA 0x0000616d /* "ma" */
42
43static int rpm_reg_write_active(struct qcom_rpm_reg *vreg)
44{
45 struct rpm_regulator_req req[3];
46 int reqlen = 0;
47 int ret;
48
49 if (vreg->enabled_updated) {
50 req[reqlen].key = cpu_to_le32(RPM_KEY_SWEN);
51 req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
52 req[reqlen].value = cpu_to_le32(vreg->is_enabled);
53 reqlen++;
54 }
55
56 if (vreg->uv_updated && vreg->is_enabled) {
57 req[reqlen].key = cpu_to_le32(RPM_KEY_UV);
58 req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
59 req[reqlen].value = cpu_to_le32(vreg->uV);
60 reqlen++;
61 }
62
63 if (vreg->load_updated && vreg->is_enabled) {
64 req[reqlen].key = cpu_to_le32(RPM_KEY_MA);
65 req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
66 req[reqlen].value = cpu_to_le32(vreg->load / 1000);
67 reqlen++;
68 }
69
70 if (!reqlen)
71 return 0;
72
73 ret = qcom_rpm_smd_write(vreg->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
74 vreg->type, vreg->id,
75 req, sizeof(req[0]) * reqlen);
76 if (!ret) {
77 vreg->enabled_updated = 0;
78 vreg->uv_updated = 0;
79 vreg->load_updated = 0;
80 }
81
82 return ret;
83}
84
85static int rpm_reg_enable(struct regulator_dev *rdev)
86{
87 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
88 int ret;
89
90 vreg->is_enabled = 1;
91 vreg->enabled_updated = 1;
92
93 ret = rpm_reg_write_active(vreg);
94 if (ret)
95 vreg->is_enabled = 0;
96
97 return ret;
98}
99
100static int rpm_reg_is_enabled(struct regulator_dev *rdev)
101{
102 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
103
104 return vreg->is_enabled;
105}
106
107static int rpm_reg_disable(struct regulator_dev *rdev)
108{
109 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
110 int ret;
111
112 vreg->is_enabled = 0;
113 vreg->enabled_updated = 1;
114
115 ret = rpm_reg_write_active(vreg);
116 if (ret)
117 vreg->is_enabled = 1;
118
119 return ret;
120}
121
122static int rpm_reg_get_voltage(struct regulator_dev *rdev)
123{
124 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
125
126 return vreg->uV;
127}
128
129static int rpm_reg_set_voltage(struct regulator_dev *rdev,
130 int min_uV,
131 int max_uV,
132 unsigned *selector)
133{
134 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
135 int ret;
136 int old_uV = vreg->uV;
137
138 vreg->uV = min_uV;
139 vreg->uv_updated = 1;
140
141 ret = rpm_reg_write_active(vreg);
142 if (ret)
143 vreg->uV = old_uV;
144
145 return ret;
146}
147
148static int rpm_reg_set_load(struct regulator_dev *rdev, int load_uA)
149{
150 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
151 u32 old_load = vreg->load;
152 int ret;
153
154 vreg->load = load_uA;
155 vreg->load_updated = 1;
156 ret = rpm_reg_write_active(vreg);
157 if (ret)
158 vreg->load = old_load;
159
160 return ret;
161}
162
163static const struct regulator_ops rpm_smps_ldo_ops = {
164 .enable = rpm_reg_enable,
165 .disable = rpm_reg_disable,
166 .is_enabled = rpm_reg_is_enabled,
167 .list_voltage = regulator_list_voltage_linear_range,
168
169 .get_voltage = rpm_reg_get_voltage,
170 .set_voltage = rpm_reg_set_voltage,
171
172 .set_load = rpm_reg_set_load,
173};
174
175static const struct regulator_ops rpm_smps_ldo_ops_fixed = {
176 .enable = rpm_reg_enable,
177 .disable = rpm_reg_disable,
178 .is_enabled = rpm_reg_is_enabled,
179
180 .get_voltage = rpm_reg_get_voltage,
181 .set_voltage = rpm_reg_set_voltage,
182
183 .set_load = rpm_reg_set_load,
184};
185
186static const struct regulator_ops rpm_switch_ops = {
187 .enable = rpm_reg_enable,
188 .disable = rpm_reg_disable,
189 .is_enabled = rpm_reg_is_enabled,
190};
191
192static const struct regulator_ops rpm_bob_ops = {
193 .enable = rpm_reg_enable,
194 .disable = rpm_reg_disable,
195 .is_enabled = rpm_reg_is_enabled,
196
197 .get_voltage = rpm_reg_get_voltage,
198 .set_voltage = rpm_reg_set_voltage,
199};
200
201static const struct regulator_desc pma8084_hfsmps = {
202 .linear_ranges = (struct regulator_linear_range[]) {
203 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
204 REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000),
205 },
206 .n_linear_ranges = 2,
207 .n_voltages = 159,
208 .ops = &rpm_smps_ldo_ops,
209};
210
211static const struct regulator_desc pma8084_ftsmps = {
212 .linear_ranges = (struct regulator_linear_range[]) {
213 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
214 REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
215 },
216 .n_linear_ranges = 2,
217 .n_voltages = 262,
218 .ops = &rpm_smps_ldo_ops,
219};
220
221static const struct regulator_desc pma8084_pldo = {
222 .linear_ranges = (struct regulator_linear_range[]) {
223 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
224 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
225 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
226 },
227 .n_linear_ranges = 3,
228 .n_voltages = 164,
229 .ops = &rpm_smps_ldo_ops,
230};
231
232static const struct regulator_desc pma8084_nldo = {
233 .linear_ranges = (struct regulator_linear_range[]) {
234 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
235 },
236 .n_linear_ranges = 1,
237 .n_voltages = 64,
238 .ops = &rpm_smps_ldo_ops,
239};
240
241static const struct regulator_desc pma8084_switch = {
242 .ops = &rpm_switch_ops,
243};
244
245static const struct regulator_desc pm8x41_hfsmps = {
246 .linear_ranges = (struct regulator_linear_range[]) {
247 REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500),
248 REGULATOR_LINEAR_RANGE(1575000, 96, 158, 25000),
249 },
250 .n_linear_ranges = 2,
251 .n_voltages = 159,
252 .ops = &rpm_smps_ldo_ops,
253};
254
255static const struct regulator_desc pm8841_ftsmps = {
256 .linear_ranges = (struct regulator_linear_range[]) {
257 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
258 REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
259 },
260 .n_linear_ranges = 2,
261 .n_voltages = 262,
262 .ops = &rpm_smps_ldo_ops,
263};
264
265static const struct regulator_desc pm8941_boost = {
266 .linear_ranges = (struct regulator_linear_range[]) {
267 REGULATOR_LINEAR_RANGE(4000000, 0, 30, 50000),
268 },
269 .n_linear_ranges = 1,
270 .n_voltages = 31,
271 .ops = &rpm_smps_ldo_ops,
272};
273
274static const struct regulator_desc pm8941_pldo = {
275 .linear_ranges = (struct regulator_linear_range[]) {
276 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
277 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
278 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
279 },
280 .n_linear_ranges = 3,
281 .n_voltages = 164,
282 .ops = &rpm_smps_ldo_ops,
283};
284
285static const struct regulator_desc pm8941_nldo = {
286 .linear_ranges = (struct regulator_linear_range[]) {
287 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
288 },
289 .n_linear_ranges = 1,
290 .n_voltages = 64,
291 .ops = &rpm_smps_ldo_ops,
292};
293
294static const struct regulator_desc pm8941_lnldo = {
295 .fixed_uV = 1740000,
296 .n_voltages = 1,
297 .ops = &rpm_smps_ldo_ops_fixed,
298};
299
300static const struct regulator_desc pm8941_switch = {
301 .ops = &rpm_switch_ops,
302};
303
304static const struct regulator_desc pm8916_pldo = {
305 .linear_ranges = (struct regulator_linear_range[]) {
306 REGULATOR_LINEAR_RANGE(750000, 0, 208, 12500),
307 },
308 .n_linear_ranges = 1,
309 .n_voltages = 209,
310 .ops = &rpm_smps_ldo_ops,
311};
312
313static const struct regulator_desc pm8916_nldo = {
314 .linear_ranges = (struct regulator_linear_range[]) {
315 REGULATOR_LINEAR_RANGE(375000, 0, 93, 12500),
316 },
317 .n_linear_ranges = 1,
318 .n_voltages = 94,
319 .ops = &rpm_smps_ldo_ops,
320};
321
322static const struct regulator_desc pm8916_buck_lvo_smps = {
323 .linear_ranges = (struct regulator_linear_range[]) {
324 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
325 REGULATOR_LINEAR_RANGE(750000, 96, 127, 25000),
326 },
327 .n_linear_ranges = 2,
328 .n_voltages = 128,
329 .ops = &rpm_smps_ldo_ops,
330};
331
332static const struct regulator_desc pm8916_buck_hvo_smps = {
333 .linear_ranges = (struct regulator_linear_range[]) {
334 REGULATOR_LINEAR_RANGE(1550000, 0, 31, 25000),
335 },
336 .n_linear_ranges = 1,
337 .n_voltages = 32,
338 .ops = &rpm_smps_ldo_ops,
339};
340
341static const struct regulator_desc pm8994_hfsmps = {
342 .linear_ranges = (struct regulator_linear_range[]) {
343 REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500),
344 REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000),
345 },
346 .n_linear_ranges = 2,
347 .n_voltages = 159,
348 .ops = &rpm_smps_ldo_ops,
349};
350
351static const struct regulator_desc pm8994_ftsmps = {
352 .linear_ranges = (struct regulator_linear_range[]) {
353 REGULATOR_LINEAR_RANGE(350000, 0, 199, 5000),
354 REGULATOR_LINEAR_RANGE(700000, 200, 349, 10000),
355 },
356 .n_linear_ranges = 2,
357 .n_voltages = 350,
358 .ops = &rpm_smps_ldo_ops,
359};
360
361static const struct regulator_desc pm8994_nldo = {
362 .linear_ranges = (struct regulator_linear_range[]) {
363 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
364 },
365 .n_linear_ranges = 1,
366 .n_voltages = 64,
367 .ops = &rpm_smps_ldo_ops,
368};
369
370static const struct regulator_desc pm8994_pldo = {
371 .linear_ranges = (struct regulator_linear_range[]) {
372 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
373 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
374 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
375 },
376 .n_linear_ranges = 3,
377 .n_voltages = 164,
378 .ops = &rpm_smps_ldo_ops,
379};
380
381static const struct regulator_desc pm8994_switch = {
382 .ops = &rpm_switch_ops,
383};
384
385static const struct regulator_desc pm8994_lnldo = {
386 .fixed_uV = 1740000,
387 .n_voltages = 1,
388 .ops = &rpm_smps_ldo_ops_fixed,
389};
390
391static const struct regulator_desc pm8998_ftsmps = {
392 .linear_ranges = (struct regulator_linear_range[]) {
393 REGULATOR_LINEAR_RANGE(320000, 0, 258, 4000),
394 },
395 .n_linear_ranges = 1,
396 .n_voltages = 259,
397 .ops = &rpm_smps_ldo_ops,
398};
399
400static const struct regulator_desc pm8998_hfsmps = {
401 .linear_ranges = (struct regulator_linear_range[]) {
402 REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000),
403 },
404 .n_linear_ranges = 1,
405 .n_voltages = 216,
406 .ops = &rpm_smps_ldo_ops,
407};
408
409static const struct regulator_desc pm8998_nldo = {
410 .linear_ranges = (struct regulator_linear_range[]) {
411 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
412 },
413 .n_linear_ranges = 1,
414 .n_voltages = 128,
415 .ops = &rpm_smps_ldo_ops,
416};
417
418static const struct regulator_desc pm8998_pldo = {
419 .linear_ranges = (struct regulator_linear_range[]) {
420 REGULATOR_LINEAR_RANGE(1664000, 0, 255, 8000),
421 },
422 .n_linear_ranges = 1,
423 .n_voltages = 256,
424 .ops = &rpm_smps_ldo_ops,
425};
426
427static const struct regulator_desc pm8998_pldo_lv = {
428 .linear_ranges = (struct regulator_linear_range[]) {
429 REGULATOR_LINEAR_RANGE(1256000, 0, 127, 8000),
430 },
431 .n_linear_ranges = 1,
432 .n_voltages = 128,
433 .ops = &rpm_smps_ldo_ops,
434};
435
436static const struct regulator_desc pm8998_switch = {
437 .ops = &rpm_switch_ops,
438};
439
440static const struct regulator_desc pmi8998_bob = {
441 .linear_ranges = (struct regulator_linear_range[]) {
442 REGULATOR_LINEAR_RANGE(1824000, 0, 83, 32000),
443 },
444 .n_linear_ranges = 1,
445 .n_voltages = 84,
446 .ops = &rpm_bob_ops,
447};
448
449static const struct regulator_desc pms405_hfsmps3 = {
450 .linear_ranges = (struct regulator_linear_range[]) {
451 REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000),
452 },
453 .n_linear_ranges = 1,
454 .n_voltages = 216,
455 .ops = &rpm_smps_ldo_ops,
456};
457
458static const struct regulator_desc pms405_nldo300 = {
459 .linear_ranges = (struct regulator_linear_range[]) {
460 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
461 },
462 .n_linear_ranges = 1,
463 .n_voltages = 128,
464 .ops = &rpm_smps_ldo_ops,
465};
466
467static const struct regulator_desc pms405_nldo1200 = {
468 .linear_ranges = (struct regulator_linear_range[]) {
469 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
470 },
471 .n_linear_ranges = 1,
472 .n_voltages = 128,
473 .ops = &rpm_smps_ldo_ops,
474};
475
476static const struct regulator_desc pms405_pldo50 = {
477 .linear_ranges = (struct regulator_linear_range[]) {
478 REGULATOR_LINEAR_RANGE(1664000, 0, 128, 16000),
479 },
480 .n_linear_ranges = 1,
481 .n_voltages = 129,
482 .ops = &rpm_smps_ldo_ops,
483};
484
485static const struct regulator_desc pms405_pldo150 = {
486 .linear_ranges = (struct regulator_linear_range[]) {
487 REGULATOR_LINEAR_RANGE(1664000, 0, 128, 16000),
488 },
489 .n_linear_ranges = 1,
490 .n_voltages = 129,
491 .ops = &rpm_smps_ldo_ops,
492};
493
494static const struct regulator_desc pms405_pldo600 = {
495 .linear_ranges = (struct regulator_linear_range[]) {
496 REGULATOR_LINEAR_RANGE(1256000, 0, 98, 8000),
497 },
498 .n_linear_ranges = 1,
499 .n_voltages = 99,
500 .ops = &rpm_smps_ldo_ops,
501};
502
503struct rpm_regulator_data {
504 const char *name;
505 u32 type;
506 u32 id;
507 const struct regulator_desc *desc;
508 const char *supply;
509};
510
511static const struct rpm_regulator_data rpm_pm8841_regulators[] = {
512 { "s1", QCOM_SMD_RPM_SMPB, 1, &pm8x41_hfsmps, "vdd_s1" },
513 { "s2", QCOM_SMD_RPM_SMPB, 2, &pm8841_ftsmps, "vdd_s2" },
514 { "s3", QCOM_SMD_RPM_SMPB, 3, &pm8x41_hfsmps, "vdd_s3" },
515 { "s4", QCOM_SMD_RPM_SMPB, 4, &pm8841_ftsmps, "vdd_s4" },
516 { "s5", QCOM_SMD_RPM_SMPB, 5, &pm8841_ftsmps, "vdd_s5" },
517 { "s6", QCOM_SMD_RPM_SMPB, 6, &pm8841_ftsmps, "vdd_s6" },
518 { "s7", QCOM_SMD_RPM_SMPB, 7, &pm8841_ftsmps, "vdd_s7" },
519 { "s8", QCOM_SMD_RPM_SMPB, 8, &pm8841_ftsmps, "vdd_s8" },
520 {}
521};
522
523static const struct rpm_regulator_data rpm_pm8916_regulators[] = {
524 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8916_buck_lvo_smps, "vdd_s1" },
525 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8916_buck_lvo_smps, "vdd_s2" },
526 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8916_buck_lvo_smps, "vdd_s3" },
527 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8916_buck_hvo_smps, "vdd_s4" },
528 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8916_nldo, "vdd_l1_l2_l3" },
529 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8916_nldo, "vdd_l1_l2_l3" },
530 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8916_nldo, "vdd_l1_l2_l3" },
531 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8916_pldo, "vdd_l4_l5_l6" },
532 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8916_pldo, "vdd_l4_l5_l6" },
533 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8916_pldo, "vdd_l4_l5_l6" },
534 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8916_pldo, "vdd_l7" },
535 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" },
536 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" },
537 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
538 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
539 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
540 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
541 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
542 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
543 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
544 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
545 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
546 {}
547};
548
549static const struct rpm_regulator_data rpm_pm8941_regulators[] = {
550 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8x41_hfsmps, "vdd_s1" },
551 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8x41_hfsmps, "vdd_s2" },
552 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8x41_hfsmps, "vdd_s3" },
553 { "s4", QCOM_SMD_RPM_BOOST, 1, &pm8941_boost },
554
555 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8941_nldo, "vdd_l1_l3" },
556 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8941_nldo, "vdd_l2_lvs1_2_3" },
557 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8941_nldo, "vdd_l1_l3" },
558 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8941_nldo, "vdd_l4_l11" },
559 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8941_lnldo, "vdd_l5_l7" },
560 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
561 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8941_lnldo, "vdd_l5_l7" },
562 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
563 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
564 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
565 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8941_nldo, "vdd_l4_l11" },
566 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
567 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
568 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
569 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
570 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
571 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
572 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
573 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
574 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
575 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8941_pldo, "vdd_l21" },
576 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
577 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
578 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
579
580 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8941_switch, "vdd_l2_lvs1_2_3" },
581 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8941_switch, "vdd_l2_lvs1_2_3" },
582 { "lvs3", QCOM_SMD_RPM_VSA, 3, &pm8941_switch, "vdd_l2_lvs1_2_3" },
583
584 { "5vs1", QCOM_SMD_RPM_VSA, 4, &pm8941_switch, "vin_5vs" },
585 { "5vs2", QCOM_SMD_RPM_VSA, 5, &pm8941_switch, "vin_5vs" },
586
587 {}
588};
589
590static const struct rpm_regulator_data rpm_pma8084_regulators[] = {
591 { "s1", QCOM_SMD_RPM_SMPA, 1, &pma8084_ftsmps, "vdd_s1" },
592 { "s2", QCOM_SMD_RPM_SMPA, 2, &pma8084_ftsmps, "vdd_s2" },
593 { "s3", QCOM_SMD_RPM_SMPA, 3, &pma8084_hfsmps, "vdd_s3" },
594 { "s4", QCOM_SMD_RPM_SMPA, 4, &pma8084_hfsmps, "vdd_s4" },
595 { "s5", QCOM_SMD_RPM_SMPA, 5, &pma8084_hfsmps, "vdd_s5" },
596 { "s6", QCOM_SMD_RPM_SMPA, 6, &pma8084_ftsmps, "vdd_s6" },
597 { "s7", QCOM_SMD_RPM_SMPA, 7, &pma8084_ftsmps, "vdd_s7" },
598 { "s8", QCOM_SMD_RPM_SMPA, 8, &pma8084_ftsmps, "vdd_s8" },
599 { "s9", QCOM_SMD_RPM_SMPA, 9, &pma8084_ftsmps, "vdd_s9" },
600 { "s10", QCOM_SMD_RPM_SMPA, 10, &pma8084_ftsmps, "vdd_s10" },
601 { "s11", QCOM_SMD_RPM_SMPA, 11, &pma8084_ftsmps, "vdd_s11" },
602 { "s12", QCOM_SMD_RPM_SMPA, 12, &pma8084_ftsmps, "vdd_s12" },
603
604 { "l1", QCOM_SMD_RPM_LDOA, 1, &pma8084_nldo, "vdd_l1_l11" },
605 { "l2", QCOM_SMD_RPM_LDOA, 2, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
606 { "l3", QCOM_SMD_RPM_LDOA, 3, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
607 { "l4", QCOM_SMD_RPM_LDOA, 4, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
608 { "l5", QCOM_SMD_RPM_LDOA, 5, &pma8084_pldo, "vdd_l5_l7" },
609 { "l6", QCOM_SMD_RPM_LDOA, 6, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
610 { "l7", QCOM_SMD_RPM_LDOA, 7, &pma8084_pldo, "vdd_l5_l7" },
611 { "l8", QCOM_SMD_RPM_LDOA, 8, &pma8084_pldo, "vdd_l8" },
612 { "l9", QCOM_SMD_RPM_LDOA, 9, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
613 { "l10", QCOM_SMD_RPM_LDOA, 10, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
614 { "l11", QCOM_SMD_RPM_LDOA, 11, &pma8084_nldo, "vdd_l1_l11" },
615 { "l12", QCOM_SMD_RPM_LDOA, 12, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
616 { "l13", QCOM_SMD_RPM_LDOA, 13, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
617 { "l14", QCOM_SMD_RPM_LDOA, 14, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
618 { "l15", QCOM_SMD_RPM_LDOA, 15, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
619 { "l16", QCOM_SMD_RPM_LDOA, 16, &pma8084_pldo, "vdd_l16_l25" },
620 { "l17", QCOM_SMD_RPM_LDOA, 17, &pma8084_pldo, "vdd_l17" },
621 { "l18", QCOM_SMD_RPM_LDOA, 18, &pma8084_pldo, "vdd_l18" },
622 { "l19", QCOM_SMD_RPM_LDOA, 19, &pma8084_pldo, "vdd_l19" },
623 { "l20", QCOM_SMD_RPM_LDOA, 20, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
624 { "l21", QCOM_SMD_RPM_LDOA, 21, &pma8084_pldo, "vdd_l21" },
625 { "l22", QCOM_SMD_RPM_LDOA, 22, &pma8084_pldo, "vdd_l22" },
626 { "l23", QCOM_SMD_RPM_LDOA, 23, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
627 { "l24", QCOM_SMD_RPM_LDOA, 24, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
628 { "l25", QCOM_SMD_RPM_LDOA, 25, &pma8084_pldo, "vdd_l16_l25" },
629 { "l26", QCOM_SMD_RPM_LDOA, 26, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
630 { "l27", QCOM_SMD_RPM_LDOA, 27, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
631
632 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pma8084_switch },
633 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pma8084_switch },
634 { "lvs3", QCOM_SMD_RPM_VSA, 3, &pma8084_switch },
635 { "lvs4", QCOM_SMD_RPM_VSA, 4, &pma8084_switch },
636 { "5vs1", QCOM_SMD_RPM_VSA, 5, &pma8084_switch },
637
638 {}
639};
640
641static const struct rpm_regulator_data rpm_pm8994_regulators[] = {
642 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8994_ftsmps, "vdd_s1" },
643 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8994_ftsmps, "vdd_s2" },
644 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8994_hfsmps, "vdd_s3" },
645 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8994_hfsmps, "vdd_s4" },
646 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8994_hfsmps, "vdd_s5" },
647 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8994_ftsmps, "vdd_s6" },
648 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8994_hfsmps, "vdd_s7" },
649 { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8994_ftsmps, "vdd_s8" },
650 { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8994_ftsmps, "vdd_s9" },
651 { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8994_ftsmps, "vdd_s10" },
652 { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8994_ftsmps, "vdd_s11" },
653 { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8994_ftsmps, "vdd_s12" },
654 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8994_nldo, "vdd_l1" },
655 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8994_nldo, "vdd_l2_l26_l28" },
656 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8994_nldo, "vdd_l3_l11" },
657 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8994_nldo, "vdd_l4_l27_l31" },
658 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8994_lnldo, "vdd_l5_l7" },
659 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8994_pldo, "vdd_l6_l12_l32" },
660 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8994_lnldo, "vdd_l5_l7" },
661 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8994_pldo, "vdd_l8_l16_l30" },
662 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
663 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
664 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8994_nldo, "vdd_l3_l11" },
665 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8994_pldo, "vdd_l6_l12_l32" },
666 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
667 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8994_pldo, "vdd_l14_l15" },
668 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8994_pldo, "vdd_l14_l15" },
669 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8994_pldo, "vdd_l8_l16_l30" },
670 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8994_pldo, "vdd_l17_l29" },
671 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
672 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
673 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8994_pldo, "vdd_l20_l21" },
674 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8994_pldo, "vdd_l20_l21" },
675 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
676 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
677 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
678 { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8994_pldo, "vdd_l25" },
679 { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8994_nldo, "vdd_l2_l26_l28" },
680 { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8994_nldo, "vdd_l4_l27_l31" },
681 { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8994_nldo, "vdd_l2_l26_l28" },
682 { "l29", QCOM_SMD_RPM_LDOA, 29, &pm8994_pldo, "vdd_l17_l29" },
683 { "l30", QCOM_SMD_RPM_LDOA, 30, &pm8994_pldo, "vdd_l8_l16_l30" },
684 { "l31", QCOM_SMD_RPM_LDOA, 31, &pm8994_nldo, "vdd_l4_l27_l31" },
685 { "l32", QCOM_SMD_RPM_LDOA, 32, &pm8994_pldo, "vdd_l6_l12_l32" },
686 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8994_switch, "vdd_lvs1_2" },
687 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8994_switch, "vdd_lvs1_2" },
688
689 {}
690};
691
692static const struct rpm_regulator_data rpm_pm8998_regulators[] = {
693 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8998_ftsmps, "vdd_s1" },
694 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8998_ftsmps, "vdd_s2" },
695 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8998_hfsmps, "vdd_s3" },
696 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8998_hfsmps, "vdd_s4" },
697 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8998_hfsmps, "vdd_s5" },
698 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8998_ftsmps, "vdd_s6" },
699 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_ftsmps, "vdd_s7" },
700 { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8998_ftsmps, "vdd_s8" },
701 { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8998_ftsmps, "vdd_s9" },
702 { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8998_ftsmps, "vdd_s10" },
703 { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8998_ftsmps, "vdd_s11" },
704 { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8998_ftsmps, "vdd_s12" },
705 { "s13", QCOM_SMD_RPM_SMPA, 13, &pm8998_ftsmps, "vdd_s13" },
706 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8998_nldo, "vdd_l1_l27" },
707 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8998_nldo, "vdd_l2_l8_l17" },
708 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8998_nldo, "vdd_l3_l11" },
709 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8998_nldo, "vdd_l4_l5" },
710 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8998_nldo, "vdd_l4_l5" },
711 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8998_pldo, "vdd_l6" },
712 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
713 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8998_nldo, "vdd_l2_l8_l17" },
714 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8998_pldo, "vdd_l9" },
715 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8998_pldo, "vdd_l10_l23_l25" },
716 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8998_nldo, "vdd_l3_l11" },
717 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
718 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8998_pldo, "vdd_l13_l19_l21" },
719 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
720 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
721 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8998_pldo, "vdd_l16_l28" },
722 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8998_nldo, "vdd_l2_l8_l17" },
723 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8998_pldo, "vdd_l18_l22" },
724 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8998_pldo, "vdd_l13_l19_l21" },
725 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8998_pldo, "vdd_l20_l24" },
726 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8998_pldo, "vdd_l13_l19_l21" },
727 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8998_pldo, "vdd_l18_l22" },
728 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8998_pldo, "vdd_l10_l23_l25" },
729 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8998_pldo, "vdd_l20_l24" },
730 { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8998_pldo, "vdd_l10_l23_l25" },
731 { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8998_nldo, "vdd_l26" },
732 { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8998_nldo, "vdd_l1_l27" },
733 { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8998_pldo, "vdd_l16_l28" },
734 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8998_switch, "vdd_lvs1_lvs2" },
735 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8998_switch, "vdd_lvs1_lvs2" },
736 {}
737};
738
739static const struct rpm_regulator_data rpm_pmi8998_regulators[] = {
740 { "bob", QCOM_SMD_RPM_BOBB, 1, &pmi8998_bob, "vdd_bob" },
741 {}
742};
743
744static const struct rpm_regulator_data rpm_pms405_regulators[] = {
745 { "s1", QCOM_SMD_RPM_SMPA, 1, &pms405_hfsmps3, "vdd_s1" },
746 { "s2", QCOM_SMD_RPM_SMPA, 2, &pms405_hfsmps3, "vdd_s2" },
747 { "s3", QCOM_SMD_RPM_SMPA, 3, &pms405_hfsmps3, "vdd_s3" },
748 { "s4", QCOM_SMD_RPM_SMPA, 4, &pms405_hfsmps3, "vdd_s4" },
749 { "s5", QCOM_SMD_RPM_SMPA, 5, &pms405_hfsmps3, "vdd_s5" },
750 { "l1", QCOM_SMD_RPM_LDOA, 1, &pms405_nldo1200, "vdd_l1_l2" },
751 { "l2", QCOM_SMD_RPM_LDOA, 2, &pms405_nldo1200, "vdd_l1_l2" },
752 { "l3", QCOM_SMD_RPM_LDOA, 3, &pms405_nldo1200, "vdd_l3_l8" },
753 { "l4", QCOM_SMD_RPM_LDOA, 4, &pms405_nldo300, "vdd_l4" },
754 { "l5", QCOM_SMD_RPM_LDOA, 5, &pms405_pldo600, "vdd_l5_l6" },
755 { "l6", QCOM_SMD_RPM_LDOA, 6, &pms405_pldo600, "vdd_l5_l6" },
756 { "l7", QCOM_SMD_RPM_LDOA, 7, &pms405_pldo150, "vdd_l7" },
757 { "l8", QCOM_SMD_RPM_LDOA, 8, &pms405_nldo1200, "vdd_l3_l8" },
758 { "l9", QCOM_SMD_RPM_LDOA, 9, &pms405_nldo1200, "vdd_l9" },
759 { "l10", QCOM_SMD_RPM_LDOA, 10, &pms405_pldo50, "vdd_l10_l11_l12_l13" },
760 { "l11", QCOM_SMD_RPM_LDOA, 11, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
761 { "l12", QCOM_SMD_RPM_LDOA, 12, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
762 { "l13", QCOM_SMD_RPM_LDOA, 13, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
763 {}
764};
765
766static const struct of_device_id rpm_of_match[] = {
767 { .compatible = "qcom,rpm-pm8841-regulators", .data = &rpm_pm8841_regulators },
768 { .compatible = "qcom,rpm-pm8916-regulators", .data = &rpm_pm8916_regulators },
769 { .compatible = "qcom,rpm-pm8941-regulators", .data = &rpm_pm8941_regulators },
770 { .compatible = "qcom,rpm-pm8994-regulators", .data = &rpm_pm8994_regulators },
771 { .compatible = "qcom,rpm-pm8998-regulators", .data = &rpm_pm8998_regulators },
772 { .compatible = "qcom,rpm-pma8084-regulators", .data = &rpm_pma8084_regulators },
773 { .compatible = "qcom,rpm-pmi8998-regulators", .data = &rpm_pmi8998_regulators },
774 { .compatible = "qcom,rpm-pms405-regulators", .data = &rpm_pms405_regulators },
775 {}
776};
777MODULE_DEVICE_TABLE(of, rpm_of_match);
778
779static int rpm_reg_probe(struct platform_device *pdev)
780{
781 const struct rpm_regulator_data *reg;
782 const struct of_device_id *match;
783 struct regulator_config config = { };
784 struct regulator_dev *rdev;
785 struct qcom_rpm_reg *vreg;
786 struct qcom_smd_rpm *rpm;
787
788 rpm = dev_get_drvdata(pdev->dev.parent);
789 if (!rpm) {
790 dev_err(&pdev->dev, "unable to retrieve handle to rpm\n");
791 return -ENODEV;
792 }
793
794 match = of_match_device(rpm_of_match, &pdev->dev);
795 if (!match) {
796 dev_err(&pdev->dev, "failed to match device\n");
797 return -ENODEV;
798 }
799
800 for (reg = match->data; reg->name; reg++) {
801 vreg = devm_kzalloc(&pdev->dev, sizeof(*vreg), GFP_KERNEL);
802 if (!vreg)
803 return -ENOMEM;
804
805 vreg->dev = &pdev->dev;
806 vreg->type = reg->type;
807 vreg->id = reg->id;
808 vreg->rpm = rpm;
809
810 memcpy(&vreg->desc, reg->desc, sizeof(vreg->desc));
811
812 vreg->desc.id = -1;
813 vreg->desc.owner = THIS_MODULE;
814 vreg->desc.type = REGULATOR_VOLTAGE;
815 vreg->desc.name = reg->name;
816 vreg->desc.supply_name = reg->supply;
817 vreg->desc.of_match = reg->name;
818
819 config.dev = &pdev->dev;
820 config.driver_data = vreg;
821 rdev = devm_regulator_register(&pdev->dev, &vreg->desc, &config);
822 if (IS_ERR(rdev)) {
823 dev_err(&pdev->dev, "failed to register %s\n", reg->name);
824 return PTR_ERR(rdev);
825 }
826 }
827
828 return 0;
829}
830
831static struct platform_driver rpm_reg_driver = {
832 .probe = rpm_reg_probe,
833 .driver = {
834 .name = "qcom_rpm_smd_regulator",
835 .of_match_table = rpm_of_match,
836 },
837};
838
839static int __init rpm_reg_init(void)
840{
841 return platform_driver_register(&rpm_reg_driver);
842}
843subsys_initcall(rpm_reg_init);
844
845static void __exit rpm_reg_exit(void)
846{
847 platform_driver_unregister(&rpm_reg_driver);
848}
849module_exit(rpm_reg_exit)
850
851MODULE_DESCRIPTION("Qualcomm RPM regulator driver");
852MODULE_LICENSE("GPL v2");