1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * AMD Platform Management Framework Driver
  4 *
  5 * Copyright (c) 2022, Advanced Micro Devices, Inc.
  6 * All Rights Reserved.
  7 *
  8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
  9 */
 10
 11#ifndef PMF_H
 12#define PMF_H
 13
 14#include <linux/acpi.h>
 15#include <linux/platform_profile.h>
 16
 17#define POLICY_BUF_MAX_SZ		0x4b000
 18#define POLICY_SIGN_COOKIE		0x31535024
 19#define POLICY_COOKIE_OFFSET		0x10
 20#define POLICY_COOKIE_LEN		0x14
 21
 22/* APMF Functions */
 23#define APMF_FUNC_VERIFY_INTERFACE			0
 24#define APMF_FUNC_GET_SYS_PARAMS			1
 25#define APMF_FUNC_SBIOS_REQUESTS			2
 26#define APMF_FUNC_SBIOS_HEARTBEAT			4
 27#define APMF_FUNC_AUTO_MODE					5
 28#define APMF_FUNC_SET_FAN_IDX				7
 29#define APMF_FUNC_OS_POWER_SLIDER_UPDATE		8
 30#define APMF_FUNC_STATIC_SLIDER_GRANULAR       9
 31#define APMF_FUNC_DYN_SLIDER_AC				11
 32#define APMF_FUNC_DYN_SLIDER_DC				12
 33
 34/* Message Definitions */
 35#define SET_SPL				0x03 /* SPL: Sustained Power Limit */
 36#define SET_SPPT			0x05 /* SPPT: Slow Package Power Tracking */
 37#define SET_FPPT			0x07 /* FPPT: Fast Package Power Tracking */
 38#define GET_SPL				0x0B
 39#define GET_SPPT			0x0D
 40#define GET_FPPT			0x0F
 41#define SET_DRAM_ADDR_HIGH	0x14
 42#define SET_DRAM_ADDR_LOW	0x15
 43#define SET_TRANSFER_TABLE	0x16
 44#define SET_STT_MIN_LIMIT	0x18 /* STT: Skin Temperature Tracking */
 45#define SET_STT_LIMIT_APU	0x19
 46#define SET_STT_LIMIT_HS2	0x1A
 47#define SET_SPPT_APU_ONLY	0x1D
 48#define GET_SPPT_APU_ONLY	0x1E
 49#define GET_STT_MIN_LIMIT	0x1F
 50#define GET_STT_LIMIT_APU	0x20
 51#define GET_STT_LIMIT_HS2	0x21
 52#define SET_P3T				0x23 /* P3T: Peak Package Power Limit */
 53
 54/* OS slider update notification */
 55#define DC_BEST_PERF		0
 56#define DC_BETTER_PERF		1
 57#define DC_BATTERY_SAVER	3
 58#define AC_BEST_PERF		4
 59#define AC_BETTER_PERF		5
 60#define AC_BETTER_BATTERY	6
 61
 62/* Fan Index for Auto Mode */
 63#define FAN_INDEX_AUTO		0xFFFFFFFF
 64
 65#define ARG_NONE 0
 66#define AVG_SAMPLE_SIZE 3
 67
 68/* Policy Actions */
 69#define PMF_POLICY_SPL						2
 70#define PMF_POLICY_SPPT						3
 71#define PMF_POLICY_FPPT						4
 72#define PMF_POLICY_SPPT_APU_ONLY				5
 73#define PMF_POLICY_STT_MIN					6
 74#define PMF_POLICY_STT_SKINTEMP_APU				7
 75#define PMF_POLICY_STT_SKINTEMP_HS2				8
 76#define PMF_POLICY_SYSTEM_STATE					9
 77#define PMF_POLICY_P3T						38
 78
 79/* TA macros */
 80#define PMF_TA_IF_VERSION_MAJOR				1
 81#define TA_PMF_ACTION_MAX					32
 82#define TA_PMF_UNDO_MAX						8
 83#define TA_OUTPUT_RESERVED_MEM				906
 84#define MAX_OPERATION_PARAMS					4
 85
 86/* AMD PMF BIOS interfaces */
 87struct apmf_verify_interface {
 88	u16 size;
 89	u16 version;
 90	u32 notification_mask;
 91	u32 supported_functions;
 92} __packed;
 93
 94struct apmf_system_params {
 95	u16 size;
 96	u32 valid_mask;
 97	u32 flags;
 98	u8 command_code;
 99	u32 heartbeat_int;
100} __packed;
101
102struct apmf_sbios_req {
103	u16 size;
104	u32 pending_req;
105	u8 rsd;
106	u8 cql_event;
107	u8 amt_event;
108	u32 fppt;
109	u32 sppt;
110	u32 fppt_apu_only;
111	u32 spl;
112	u32 stt_min_limit;
113	u8 skin_temp_apu;
114	u8 skin_temp_hs2;
115} __packed;
116
117struct apmf_fan_idx {
118	u16 size;
119	u8 fan_ctl_mode;
120	u32 fan_ctl_idx;
121} __packed;
122
123struct smu_pmf_metrics {
124	u16 gfxclk_freq; /* in MHz */
125	u16 socclk_freq; /* in MHz */
126	u16 vclk_freq; /* in MHz */
127	u16 dclk_freq; /* in MHz */
128	u16 memclk_freq; /* in MHz */
129	u16 spare;
130	u16 gfx_activity; /* in Centi */
131	u16 uvd_activity; /* in Centi */
132	u16 voltage[2]; /* in mV */
133	u16 currents[2]; /* in mA */
134	u16 power[2];/* in mW */
135	u16 core_freq[8]; /* in MHz */
136	u16 core_power[8]; /* in mW */
137	u16 core_temp[8]; /* in centi-Celsius */
138	u16 l3_freq; /* in MHz */
139	u16 l3_temp; /* in centi-Celsius */
140	u16 gfx_temp; /* in centi-Celsius */
141	u16 soc_temp; /* in centi-Celsius */
142	u16 throttler_status;
143	u16 current_socketpower; /* in mW */
144	u16 stapm_orig_limit; /* in W */
145	u16 stapm_cur_limit; /* in W */
146	u32 apu_power; /* in mW */
147	u32 dgpu_power; /* in mW */
148	u16 vdd_tdc_val; /* in mA */
149	u16 soc_tdc_val; /* in mA */
150	u16 vdd_edc_val; /* in mA */
151	u16 soc_edcv_al; /* in mA */
152	u16 infra_cpu_maxfreq; /* in MHz */
153	u16 infra_gfx_maxfreq; /* in MHz */
154	u16 skin_temp; /* in centi-Celsius */
155	u16 device_state;
156	u16 curtemp; /* in centi-Celsius */
157	u16 filter_alpha_value;
158	u16 avg_gfx_clkfrequency;
159	u16 avg_fclk_frequency;
160	u16 avg_gfx_activity;
161	u16 avg_socclk_frequency;
162	u16 avg_vclk_frequency;
163	u16 avg_vcn_activity;
164	u16 avg_dram_reads;
165	u16 avg_dram_writes;
166	u16 avg_socket_power;
167	u16 avg_core_power[2];
168	u16 avg_core_c0residency[16];
169	u16 spare1;
170	u32 metrics_counter;
171} __packed;
172
173enum amd_stt_skin_temp {
174	STT_TEMP_APU,
175	STT_TEMP_HS2,
176	STT_TEMP_COUNT,
177};
178
179enum amd_slider_op {
180	SLIDER_OP_GET,
181	SLIDER_OP_SET,
182};
183
184enum power_source {
185	POWER_SOURCE_AC,
186	POWER_SOURCE_DC,
187	POWER_SOURCE_MAX,
188};
189
190enum power_modes {
191	POWER_MODE_PERFORMANCE,
192	POWER_MODE_BALANCED_POWER,
193	POWER_MODE_POWER_SAVER,
194	POWER_MODE_MAX,
195};
196
197struct amd_pmf_dev {
198	void __iomem *regbase;
199	void __iomem *smu_virt_addr;
200	void *buf;
201	u32 base_addr;
202	u32 cpu_id;
203	struct device *dev;
204	struct mutex lock; /* protects the PMF interface */
205	u32 supported_func;
206	enum platform_profile_option current_profile;
207	struct platform_profile_handler pprof;
208	struct dentry *dbgfs_dir;
209	int hb_interval; /* SBIOS heartbeat interval */
210	struct delayed_work heart_beat;
211	struct smu_pmf_metrics m_table;
212	struct delayed_work work_buffer;
213	ktime_t start_time;
214	int socket_power_history[AVG_SAMPLE_SIZE];
215	int socket_power_history_idx;
216	bool amt_enabled;
217	struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */
218	bool cnqf_enabled;
219	bool cnqf_supported;
220	struct notifier_block pwr_src_notifier;
221	/* Smart PC solution builder */
222	struct dentry *esbin;
223	unsigned char *policy_buf;
224	u32 policy_sz;
225	struct tee_context *tee_ctx;
226	struct tee_shm *fw_shm_pool;
227	u32 session_id;
228	void *shbuf;
229	struct delayed_work pb_work;
230	struct pmf_action_table *prev_data;
231	u64 policy_addr;
232	void *policy_base;
233	bool smart_pc_enabled;
234};
235
236struct apmf_sps_prop_granular {
237	u32 fppt;
238	u32 sppt;
239	u32 sppt_apu_only;
240	u32 spl;
241	u32 stt_min;
242	u8 stt_skin_temp[STT_TEMP_COUNT];
243	u32 fan_id;
244} __packed;
245
246/* Static Slider */
247struct apmf_static_slider_granular_output {
248	u16 size;
249	struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX];
250} __packed;
251
252struct amd_pmf_static_slider_granular {
253	u16 size;
254	struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX];
255};
256
257struct os_power_slider {
258	u16 size;
259	u8 slider_event;
260} __packed;
261
262struct fan_table_control {
263	bool manual;
264	unsigned long fan_id;
265};
266
267struct power_table_control {
268	u32 spl;
269	u32 sppt;
270	u32 fppt;
271	u32 sppt_apu_only;
272	u32 stt_min;
273	u32 stt_skin_temp[STT_TEMP_COUNT];
274	u32 reserved[16];
275};
276
277/* Auto Mode Layer */
278enum auto_mode_transition_priority {
279	AUTO_TRANSITION_TO_PERFORMANCE, /* Any other mode to Performance Mode */
280	AUTO_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */
281	AUTO_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */
282	AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance Mode to Balance Mode */
283	AUTO_TRANSITION_MAX,
284};
285
286enum auto_mode_mode {
287	AUTO_QUIET,
288	AUTO_BALANCE,
289	AUTO_PERFORMANCE_ON_LAP,
290	AUTO_PERFORMANCE,
291	AUTO_MODE_MAX,
292};
293
294struct auto_mode_trans_params {
295	u32 time_constant; /* minimum time required to switch to next mode */
296	u32 power_delta; /* delta power to shift mode */
297	u32 power_threshold;
298	u32 timer; /* elapsed time. if timer > TimeThreshold, it will move to next mode */
299	u32 applied;
300	enum auto_mode_mode target_mode;
301	u32 shifting_up;
302};
303
304struct auto_mode_mode_settings {
305	struct power_table_control power_control;
306	struct fan_table_control fan_control;
307	u32 power_floor;
308};
309
310struct auto_mode_mode_config {
311	struct auto_mode_trans_params transition[AUTO_TRANSITION_MAX];
312	struct auto_mode_mode_settings mode_set[AUTO_MODE_MAX];
313	enum auto_mode_mode current_mode;
314};
315
316struct apmf_auto_mode {
317	u16 size;
318	/* time constant */
319	u32 balanced_to_perf;
320	u32 perf_to_balanced;
321	u32 quiet_to_balanced;
322	u32 balanced_to_quiet;
323	/* power floor */
324	u32 pfloor_perf;
325	u32 pfloor_balanced;
326	u32 pfloor_quiet;
327	/* Power delta for mode change */
328	u32 pd_balanced_to_perf;
329	u32 pd_perf_to_balanced;
330	u32 pd_quiet_to_balanced;
331	u32 pd_balanced_to_quiet;
332	/* skin temperature limits */
333	u8 stt_apu_perf_on_lap; /* CQL ON */
334	u8 stt_hs2_perf_on_lap; /* CQL ON */
335	u8 stt_apu_perf;
336	u8 stt_hs2_perf;
337	u8 stt_apu_balanced;
338	u8 stt_hs2_balanced;
339	u8 stt_apu_quiet;
340	u8 stt_hs2_quiet;
341	u32 stt_min_limit_perf_on_lap; /* CQL ON */
342	u32 stt_min_limit_perf;
343	u32 stt_min_limit_balanced;
344	u32 stt_min_limit_quiet;
345	/* SPL based */
346	u32 fppt_perf_on_lap; /* CQL ON */
347	u32 sppt_perf_on_lap; /* CQL ON */
348	u32 spl_perf_on_lap; /* CQL ON */
349	u32 sppt_apu_only_perf_on_lap; /* CQL ON */
350	u32 fppt_perf;
351	u32 sppt_perf;
352	u32 spl_perf;
353	u32 sppt_apu_only_perf;
354	u32 fppt_balanced;
355	u32 sppt_balanced;
356	u32 spl_balanced;
357	u32 sppt_apu_only_balanced;
358	u32 fppt_quiet;
359	u32 sppt_quiet;
360	u32 spl_quiet;
361	u32 sppt_apu_only_quiet;
362	/* Fan ID */
363	u32 fan_id_perf;
364	u32 fan_id_balanced;
365	u32 fan_id_quiet;
366} __packed;
367
368/* CnQF Layer */
369enum cnqf_trans_priority {
370	CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */
371	CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE, /* quiet/balance to Performance Mode */
372	CNQF_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */
373	CNQF_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */
374	CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance/Turbo to Balance Mode */
375	CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE, /* Turbo mode to Performance Mode */
376	CNQF_TRANSITION_MAX,
377};
378
379enum cnqf_mode {
380	CNQF_MODE_QUIET,
381	CNQF_MODE_BALANCE,
382	CNQF_MODE_PERFORMANCE,
383	CNQF_MODE_TURBO,
384	CNQF_MODE_MAX,
385};
386
387enum apmf_cnqf_pos {
388	APMF_CNQF_TURBO,
389	APMF_CNQF_PERFORMANCE,
390	APMF_CNQF_BALANCE,
391	APMF_CNQF_QUIET,
392	APMF_CNQF_MAX,
393};
394
395struct cnqf_mode_settings {
396	struct power_table_control power_control;
397	struct fan_table_control fan_control;
398	u32 power_floor;
399};
400
401struct cnqf_tran_params {
402	u32 time_constant; /* minimum time required to switch to next mode */
403	u32 power_threshold;
404	u32 timer; /* elapsed time. if timer > timethreshold, it will move to next mode */
405	u32 total_power;
406	u32 count;
407	bool priority;
408	bool shifting_up;
409	enum cnqf_mode target_mode;
410};
411
412struct cnqf_config {
413	struct cnqf_tran_params trans_param[POWER_SOURCE_MAX][CNQF_TRANSITION_MAX];
414	struct cnqf_mode_settings mode_set[POWER_SOURCE_MAX][CNQF_MODE_MAX];
415	struct power_table_control defaults;
416	enum cnqf_mode current_mode;
417	u32 power_src;
418	u32 avg_power;
419};
420
421struct apmf_cnqf_power_set {
422	u32 pfloor;
423	u32 fppt;
424	u32 sppt;
425	u32 sppt_apu_only;
426	u32 spl;
427	u32 stt_min_limit;
428	u8 stt_skintemp[STT_TEMP_COUNT];
429	u32 fan_id;
430} __packed;
431
432struct apmf_dyn_slider_output {
433	u16 size;
434	u16 flags;
435	u32 t_perf_to_turbo;
436	u32 t_balanced_to_perf;
437	u32 t_quiet_to_balanced;
438	u32 t_balanced_to_quiet;
439	u32 t_perf_to_balanced;
440	u32 t_turbo_to_perf;
441	struct apmf_cnqf_power_set ps[APMF_CNQF_MAX];
442} __packed;
443
444/* Smart PC - TA internals */
445enum system_state {
446	SYSTEM_STATE_S0i3,
447	SYSTEM_STATE_S4,
448	SYSTEM_STATE_SCREEN_LOCK,
449	SYSTEM_STATE_MAX,
450};
451
452enum ta_slider {
453	TA_BEST_BATTERY,
454	TA_BETTER_BATTERY,
455	TA_BETTER_PERFORMANCE,
456	TA_BEST_PERFORMANCE,
457	TA_MAX,
458};
459
460/* Command ids for TA communication */
461enum ta_pmf_command {
462	TA_PMF_COMMAND_POLICY_BUILDER_INITIALIZE,
463	TA_PMF_COMMAND_POLICY_BUILDER_ENACT_POLICIES,
464};
465
466enum ta_pmf_error_type {
467	TA_PMF_TYPE_SUCCESS,
468	TA_PMF_ERROR_TYPE_GENERIC,
469	TA_PMF_ERROR_TYPE_CRYPTO,
470	TA_PMF_ERROR_TYPE_CRYPTO_VALIDATE,
471	TA_PMF_ERROR_TYPE_CRYPTO_VERIFY_OEM,
472	TA_PMF_ERROR_TYPE_POLICY_BUILDER,
473	TA_PMF_ERROR_TYPE_PB_CONVERT,
474	TA_PMF_ERROR_TYPE_PB_SETUP,
475	TA_PMF_ERROR_TYPE_PB_ENACT,
476	TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_INFO,
477	TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_PCIE_INFO,
478	TA_PMF_ERROR_TYPE_SYS_DRV_FW_VALIDATION,
479	TA_PMF_ERROR_TYPE_MAX,
480};
481
482struct pmf_action_table {
483	enum system_state system_state;
484	u32 spl;		/* in mW */
485	u32 sppt;		/* in mW */
486	u32 sppt_apuonly;	/* in mW */
487	u32 fppt;		/* in mW */
488	u32 stt_minlimit;	/* in mW */
489	u32 stt_skintemp_apu;	/* in C */
490	u32 stt_skintemp_hs2;	/* in C */
491	u32 p3t_limit;		/* in mW */
492};
493
494/* Input conditions */
495struct ta_pmf_condition_info {
496	u32 power_source;
497	u32 bat_percentage;
498	u32 power_slider;
499	u32 lid_state;
500	bool user_present;
501	u32 rsvd1[2];
502	u32 monitor_count;
503	u32 rsvd2[2];
504	u32 bat_design;
505	u32 full_charge_capacity;
506	int drain_rate;
507	bool user_engaged;
508	u32 device_state;
509	u32 socket_power;
510	u32 skin_temperature;
511	u32 rsvd3[5];
512	u32 ambient_light;
513	u32 length;
514	u32 avg_c0residency;
515	u32 max_c0residency;
516	u32 s0i3_entry;
517	u32 gfx_busy;
518	u32 rsvd4[7];
519	bool camera_state;
520	u32 workload_type;
521	u32 display_type;
522	u32 display_state;
523	u32 rsvd5[150];
524};
525
526struct ta_pmf_load_policy_table {
527	u32 table_size;
528	u8 table[POLICY_BUF_MAX_SZ];
529};
530
531/* TA initialization params */
532struct ta_pmf_init_table {
533	u32 frequency; /* SMU sampling frequency */
534	bool validate;
535	bool sku_check;
536	bool metadata_macrocheck;
537	struct ta_pmf_load_policy_table policies_table;
538};
539
540/* Everything the TA needs to Enact Policies */
541struct ta_pmf_enact_table {
542	struct ta_pmf_condition_info ev_info;
543	u32 name;
544};
545
546struct ta_pmf_action {
547	u32 action_index;
548	u32 value;
549};
550
551/* Output actions from TA */
552struct ta_pmf_enact_result {
553	u32 actions_count;
554	struct ta_pmf_action actions_list[TA_PMF_ACTION_MAX];
555	u32 undo_count;
556	struct ta_pmf_action undo_list[TA_PMF_UNDO_MAX];
557};
558
559union ta_pmf_input {
560	struct ta_pmf_enact_table enact_table;
561	struct ta_pmf_init_table init_table;
562};
563
564union ta_pmf_output {
565	struct ta_pmf_enact_result policy_apply_table;
566	u32 rsvd[TA_OUTPUT_RESERVED_MEM];
567};
568
569struct ta_pmf_shared_memory {
570	int command_id;
571	int resp_id;
572	u32 pmf_result;
573	u32 if_version;
574	union ta_pmf_output pmf_output;
575	union ta_pmf_input pmf_input;
576};
577
578/* Core Layer */
579int apmf_acpi_init(struct amd_pmf_dev *pmf_dev);
580void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev);
581int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index);
582int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data);
583int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev);
584int amd_pmf_get_power_source(void);
585int apmf_install_handler(struct amd_pmf_dev *pmf_dev);
586int apmf_os_power_slider_update(struct amd_pmf_dev *dev, u8 flag);
587int amd_pmf_set_dram_addr(struct amd_pmf_dev *dev, bool alloc_buffer);
588
589/* SPS Layer */
590int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf);
591void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx,
592			   struct amd_pmf_static_slider_granular *table);
593int amd_pmf_init_sps(struct amd_pmf_dev *dev);
594void amd_pmf_deinit_sps(struct amd_pmf_dev *dev);
595int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev,
596				    struct apmf_static_slider_granular_output *output);
597bool is_pprof_balanced(struct amd_pmf_dev *pmf);
598int amd_pmf_power_slider_update_event(struct amd_pmf_dev *dev);
599const char *amd_pmf_source_as_str(unsigned int state);
600
601const char *amd_pmf_source_as_str(unsigned int state);
602
603int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx);
604int amd_pmf_set_sps_power_limits(struct amd_pmf_dev *pmf);
605
606/* Auto Mode Layer */
607int apmf_get_auto_mode_def(struct amd_pmf_dev *pdev, struct apmf_auto_mode *data);
608void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev);
609void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev);
610void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms);
611int apmf_get_sbios_requests(struct amd_pmf_dev *pdev, struct apmf_sbios_req *req);
612
613void amd_pmf_update_2_cql(struct amd_pmf_dev *dev, bool is_cql_event);
614int amd_pmf_reset_amt(struct amd_pmf_dev *dev);
615void amd_pmf_handle_amt(struct amd_pmf_dev *dev);
616
617/* CnQF Layer */
618int apmf_get_dyn_slider_def_ac(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data);
619int apmf_get_dyn_slider_def_dc(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data);
620int amd_pmf_init_cnqf(struct amd_pmf_dev *dev);
621void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev);
622int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms);
623extern const struct attribute_group cnqf_feature_attribute_group;
624
625/* Smart PC builder Layer */
626int amd_pmf_init_smart_pc(struct amd_pmf_dev *dev);
627void amd_pmf_deinit_smart_pc(struct amd_pmf_dev *dev);
628int apmf_check_smart_pc(struct amd_pmf_dev *pmf_dev);
629
630/* Smart PC - TA interfaces */
631void amd_pmf_populate_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in);
632void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in);
633
634#endif /* PMF_H */