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1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * Copyright (C) 2003-2014, 2018-2021, 2023 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
7#include <linux/etherdevice.h>
8#include <linux/ieee80211.h>
9#include <linux/slab.h>
10#include <linux/sched.h>
11#include <net/ip6_checksum.h>
12#include <net/tso.h>
13
14#include "iwl-debug.h"
15#include "iwl-csr.h"
16#include "iwl-prph.h"
17#include "iwl-io.h"
18#include "iwl-scd.h"
19#include "iwl-op-mode.h"
20#include "internal.h"
21#include "fw/api/tx.h"
22
23/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
24 * DMA services
25 *
26 * Theory of operation
27 *
28 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
29 * of buffer descriptors, each of which points to one or more data buffers for
30 * the device to read from or fill. Driver and device exchange status of each
31 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
32 * entries in each circular buffer, to protect against confusing empty and full
33 * queue states.
34 *
35 * The device reads or writes the data in the queues via the device's several
36 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
37 *
38 * For Tx queue, there are low mark and high mark limits. If, after queuing
39 * the packet for Tx, free space become < low mark, Tx queue stopped. When
40 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
41 * Tx queue resumed.
42 *
43 ***************************************************/
44
45
46int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
47 struct iwl_dma_ptr *ptr, size_t size)
48{
49 if (WARN_ON(ptr->addr))
50 return -EINVAL;
51
52 ptr->addr = dma_alloc_coherent(trans->dev, size,
53 &ptr->dma, GFP_KERNEL);
54 if (!ptr->addr)
55 return -ENOMEM;
56 ptr->size = size;
57 return 0;
58}
59
60void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr)
61{
62 if (unlikely(!ptr->addr))
63 return;
64
65 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
66 memset(ptr, 0, sizeof(*ptr));
67}
68
69/*
70 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
71 */
72static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
73 struct iwl_txq *txq)
74{
75 u32 reg = 0;
76 int txq_id = txq->id;
77
78 lockdep_assert_held(&txq->lock);
79
80 /*
81 * explicitly wake up the NIC if:
82 * 1. shadow registers aren't enabled
83 * 2. NIC is woken up for CMD regardless of shadow outside this function
84 * 3. there is a chance that the NIC is asleep
85 */
86 if (!trans->trans_cfg->base_params->shadow_reg_enable &&
87 txq_id != trans->txqs.cmd.q_id &&
88 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
89 /*
90 * wake up nic if it's powered down ...
91 * uCode will wake up, and interrupt us again, so next
92 * time we'll skip this part.
93 */
94 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
95
96 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
97 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
98 txq_id, reg);
99 iwl_set_bit(trans, CSR_GP_CNTRL,
100 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
101 txq->need_update = true;
102 return;
103 }
104 }
105
106 /*
107 * if not in power-save mode, uCode will never sleep when we're
108 * trying to tx (during RFKILL, we're not trying to tx).
109 */
110 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr);
111 if (!txq->block)
112 iwl_write32(trans, HBUS_TARG_WRPTR,
113 txq->write_ptr | (txq_id << 8));
114}
115
116void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
117{
118 int i;
119
120 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
121 struct iwl_txq *txq = trans->txqs.txq[i];
122
123 if (!test_bit(i, trans->txqs.queue_used))
124 continue;
125
126 spin_lock_bh(&txq->lock);
127 if (txq->need_update) {
128 iwl_pcie_txq_inc_wr_ptr(trans, txq);
129 txq->need_update = false;
130 }
131 spin_unlock_bh(&txq->lock);
132 }
133}
134
135static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
136 dma_addr_t addr, u16 len, bool reset)
137{
138 void *tfd;
139 u32 num_tbs;
140
141 tfd = (u8 *)txq->tfds + trans->txqs.tfd.size * txq->write_ptr;
142
143 if (reset)
144 memset(tfd, 0, trans->txqs.tfd.size);
145
146 num_tbs = iwl_txq_gen1_tfd_get_num_tbs(trans, tfd);
147
148 /* Each TFD can point to a maximum max_tbs Tx buffers */
149 if (num_tbs >= trans->txqs.tfd.max_tbs) {
150 IWL_ERR(trans, "Error can not send more than %d chunks\n",
151 trans->txqs.tfd.max_tbs);
152 return -EINVAL;
153 }
154
155 if (WARN(addr & ~IWL_TX_DMA_MASK,
156 "Unaligned address = %llx\n", (unsigned long long)addr))
157 return -EINVAL;
158
159 iwl_pcie_gen1_tfd_set_tb(trans, tfd, num_tbs, addr, len);
160
161 return num_tbs;
162}
163
164static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
165{
166 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
167
168 if (!trans->trans_cfg->base_params->apmg_wake_up_wa)
169 return;
170
171 spin_lock(&trans_pcie->reg_lock);
172
173 if (WARN_ON(!trans_pcie->cmd_hold_nic_awake)) {
174 spin_unlock(&trans_pcie->reg_lock);
175 return;
176 }
177
178 trans_pcie->cmd_hold_nic_awake = false;
179 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
180 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
181 spin_unlock(&trans_pcie->reg_lock);
182}
183
184/*
185 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
186 */
187static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
188{
189 struct iwl_txq *txq = trans->txqs.txq[txq_id];
190
191 if (!txq) {
192 IWL_ERR(trans, "Trying to free a queue that wasn't allocated?\n");
193 return;
194 }
195
196 spin_lock_bh(&txq->lock);
197 while (txq->write_ptr != txq->read_ptr) {
198 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
199 txq_id, txq->read_ptr);
200
201 if (txq_id != trans->txqs.cmd.q_id) {
202 struct sk_buff *skb = txq->entries[txq->read_ptr].skb;
203
204 if (WARN_ON_ONCE(!skb))
205 continue;
206
207 iwl_txq_free_tso_page(trans, skb);
208 }
209 iwl_txq_free_tfd(trans, txq);
210 txq->read_ptr = iwl_txq_inc_wrap(trans, txq->read_ptr);
211
212 if (txq->read_ptr == txq->write_ptr &&
213 txq_id == trans->txqs.cmd.q_id)
214 iwl_pcie_clear_cmd_in_flight(trans);
215 }
216
217 while (!skb_queue_empty(&txq->overflow_q)) {
218 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q);
219
220 iwl_op_mode_free_skb(trans->op_mode, skb);
221 }
222
223 spin_unlock_bh(&txq->lock);
224
225 /* just in case - this queue may have been stopped */
226 iwl_wake_queue(trans, txq);
227}
228
229/*
230 * iwl_pcie_txq_free - Deallocate DMA queue.
231 * @txq: Transmit queue to deallocate.
232 *
233 * Empty queue by removing and destroying all BD's.
234 * Free all buffers.
235 * 0-fill, but do not free "txq" descriptor structure.
236 */
237static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
238{
239 struct iwl_txq *txq = trans->txqs.txq[txq_id];
240 struct device *dev = trans->dev;
241 int i;
242
243 if (WARN_ON(!txq))
244 return;
245
246 iwl_pcie_txq_unmap(trans, txq_id);
247
248 /* De-alloc array of command/tx buffers */
249 if (txq_id == trans->txqs.cmd.q_id)
250 for (i = 0; i < txq->n_window; i++) {
251 kfree_sensitive(txq->entries[i].cmd);
252 kfree_sensitive(txq->entries[i].free_buf);
253 }
254
255 /* De-alloc circular buffer of TFDs */
256 if (txq->tfds) {
257 dma_free_coherent(dev,
258 trans->txqs.tfd.size *
259 trans->trans_cfg->base_params->max_tfd_queue_size,
260 txq->tfds, txq->dma_addr);
261 txq->dma_addr = 0;
262 txq->tfds = NULL;
263
264 dma_free_coherent(dev,
265 sizeof(*txq->first_tb_bufs) * txq->n_window,
266 txq->first_tb_bufs, txq->first_tb_dma);
267 }
268
269 kfree(txq->entries);
270 txq->entries = NULL;
271
272 del_timer_sync(&txq->stuck_timer);
273
274 /* 0-fill queue descriptor structure */
275 memset(txq, 0, sizeof(*txq));
276}
277
278void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
279{
280 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
281 int nq = trans->trans_cfg->base_params->num_of_queues;
282 int chan;
283 u32 reg_val;
284 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
285 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
286
287 /* make sure all queue are not stopped/used */
288 memset(trans->txqs.queue_stopped, 0,
289 sizeof(trans->txqs.queue_stopped));
290 memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used));
291
292 trans_pcie->scd_base_addr =
293 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
294
295 WARN_ON(scd_base_addr != 0 &&
296 scd_base_addr != trans_pcie->scd_base_addr);
297
298 /* reset context data, TX status and translation data */
299 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
300 SCD_CONTEXT_MEM_LOWER_BOUND,
301 NULL, clear_dwords);
302
303 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
304 trans->txqs.scd_bc_tbls.dma >> 10);
305
306 /* The chain extension of the SCD doesn't work well. This feature is
307 * enabled by default by the HW, so we need to disable it manually.
308 */
309 if (trans->trans_cfg->base_params->scd_chain_ext_wa)
310 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
311
312 iwl_trans_ac_txq_enable(trans, trans->txqs.cmd.q_id,
313 trans->txqs.cmd.fifo,
314 trans->txqs.cmd.wdg_timeout);
315
316 /* Activate all Tx DMA/FIFO channels */
317 iwl_scd_activate_fifos(trans);
318
319 /* Enable DMA channel */
320 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
321 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
322 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
323 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
324
325 /* Update FH chicken bits */
326 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
327 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
328 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
329
330 /* Enable L1-Active */
331 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
332 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
333 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
334}
335
336void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
337{
338 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
339 int txq_id;
340
341 /*
342 * we should never get here in gen2 trans mode return early to avoid
343 * having invalid accesses
344 */
345 if (WARN_ON_ONCE(trans->trans_cfg->gen2))
346 return;
347
348 for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
349 txq_id++) {
350 struct iwl_txq *txq = trans->txqs.txq[txq_id];
351 if (trans->trans_cfg->gen2)
352 iwl_write_direct64(trans,
353 FH_MEM_CBBC_QUEUE(trans, txq_id),
354 txq->dma_addr);
355 else
356 iwl_write_direct32(trans,
357 FH_MEM_CBBC_QUEUE(trans, txq_id),
358 txq->dma_addr >> 8);
359 iwl_pcie_txq_unmap(trans, txq_id);
360 txq->read_ptr = 0;
361 txq->write_ptr = 0;
362 }
363
364 /* Tell NIC where to find the "keep warm" buffer */
365 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
366 trans_pcie->kw.dma >> 4);
367
368 /*
369 * Send 0 as the scd_base_addr since the device may have be reset
370 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
371 * contain garbage.
372 */
373 iwl_pcie_tx_start(trans, 0);
374}
375
376static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
377{
378 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
379 int ch, ret;
380 u32 mask = 0;
381
382 spin_lock_bh(&trans_pcie->irq_lock);
383
384 if (!iwl_trans_grab_nic_access(trans))
385 goto out;
386
387 /* Stop each Tx DMA channel */
388 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
389 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
390 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
391 }
392
393 /* Wait for DMA channels to be idle */
394 ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
395 if (ret < 0)
396 IWL_ERR(trans,
397 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
398 ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
399
400 iwl_trans_release_nic_access(trans);
401
402out:
403 spin_unlock_bh(&trans_pcie->irq_lock);
404}
405
406/*
407 * iwl_pcie_tx_stop - Stop all Tx DMA channels
408 */
409int iwl_pcie_tx_stop(struct iwl_trans *trans)
410{
411 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
412 int txq_id;
413
414 /* Turn off all Tx DMA fifos */
415 iwl_scd_deactivate_fifos(trans);
416
417 /* Turn off all Tx DMA channels */
418 iwl_pcie_tx_stop_fh(trans);
419
420 /*
421 * This function can be called before the op_mode disabled the
422 * queues. This happens when we have an rfkill interrupt.
423 * Since we stop Tx altogether - mark the queues as stopped.
424 */
425 memset(trans->txqs.queue_stopped, 0,
426 sizeof(trans->txqs.queue_stopped));
427 memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used));
428
429 /* This can happen: start_hw, stop_device */
430 if (!trans_pcie->txq_memory)
431 return 0;
432
433 /* Unmap DMA from host system and free skb's */
434 for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
435 txq_id++)
436 iwl_pcie_txq_unmap(trans, txq_id);
437
438 return 0;
439}
440
441/*
442 * iwl_trans_tx_free - Free TXQ Context
443 *
444 * Destroy all TX DMA queues and structures
445 */
446void iwl_pcie_tx_free(struct iwl_trans *trans)
447{
448 int txq_id;
449 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
450
451 memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used));
452
453 /* Tx queues */
454 if (trans_pcie->txq_memory) {
455 for (txq_id = 0;
456 txq_id < trans->trans_cfg->base_params->num_of_queues;
457 txq_id++) {
458 iwl_pcie_txq_free(trans, txq_id);
459 trans->txqs.txq[txq_id] = NULL;
460 }
461 }
462
463 kfree(trans_pcie->txq_memory);
464 trans_pcie->txq_memory = NULL;
465
466 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
467
468 iwl_pcie_free_dma_ptr(trans, &trans->txqs.scd_bc_tbls);
469}
470
471/*
472 * iwl_pcie_tx_alloc - allocate TX context
473 * Allocate all Tx DMA structures and initialize them
474 */
475static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
476{
477 int ret;
478 int txq_id, slots_num;
479 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
480 u16 bc_tbls_size = trans->trans_cfg->base_params->num_of_queues;
481
482 if (WARN_ON(trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))
483 return -EINVAL;
484
485 bc_tbls_size *= sizeof(struct iwlagn_scd_bc_tbl);
486
487 /*It is not allowed to alloc twice, so warn when this happens.
488 * We cannot rely on the previous allocation, so free and fail */
489 if (WARN_ON(trans_pcie->txq_memory)) {
490 ret = -EINVAL;
491 goto error;
492 }
493
494 ret = iwl_pcie_alloc_dma_ptr(trans, &trans->txqs.scd_bc_tbls,
495 bc_tbls_size);
496 if (ret) {
497 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
498 goto error;
499 }
500
501 /* Alloc keep-warm buffer */
502 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
503 if (ret) {
504 IWL_ERR(trans, "Keep Warm allocation failed\n");
505 goto error;
506 }
507
508 trans_pcie->txq_memory =
509 kcalloc(trans->trans_cfg->base_params->num_of_queues,
510 sizeof(struct iwl_txq), GFP_KERNEL);
511 if (!trans_pcie->txq_memory) {
512 IWL_ERR(trans, "Not enough memory for txq\n");
513 ret = -ENOMEM;
514 goto error;
515 }
516
517 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
518 for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
519 txq_id++) {
520 bool cmd_queue = (txq_id == trans->txqs.cmd.q_id);
521
522 if (cmd_queue)
523 slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE,
524 trans->cfg->min_txq_size);
525 else
526 slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE,
527 trans->cfg->min_ba_txq_size);
528 trans->txqs.txq[txq_id] = &trans_pcie->txq_memory[txq_id];
529 ret = iwl_txq_alloc(trans, trans->txqs.txq[txq_id], slots_num,
530 cmd_queue);
531 if (ret) {
532 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
533 goto error;
534 }
535 trans->txqs.txq[txq_id]->id = txq_id;
536 }
537
538 return 0;
539
540error:
541 iwl_pcie_tx_free(trans);
542
543 return ret;
544}
545
546int iwl_pcie_tx_init(struct iwl_trans *trans)
547{
548 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
549 int ret;
550 int txq_id, slots_num;
551 bool alloc = false;
552
553 if (!trans_pcie->txq_memory) {
554 ret = iwl_pcie_tx_alloc(trans);
555 if (ret)
556 goto error;
557 alloc = true;
558 }
559
560 spin_lock_bh(&trans_pcie->irq_lock);
561
562 /* Turn off all Tx DMA fifos */
563 iwl_scd_deactivate_fifos(trans);
564
565 /* Tell NIC where to find the "keep warm" buffer */
566 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
567 trans_pcie->kw.dma >> 4);
568
569 spin_unlock_bh(&trans_pcie->irq_lock);
570
571 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
572 for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
573 txq_id++) {
574 bool cmd_queue = (txq_id == trans->txqs.cmd.q_id);
575
576 if (cmd_queue)
577 slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE,
578 trans->cfg->min_txq_size);
579 else
580 slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE,
581 trans->cfg->min_ba_txq_size);
582 ret = iwl_txq_init(trans, trans->txqs.txq[txq_id], slots_num,
583 cmd_queue);
584 if (ret) {
585 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
586 goto error;
587 }
588
589 /*
590 * Tell nic where to find circular buffer of TFDs for a
591 * given Tx queue, and enable the DMA channel used for that
592 * queue.
593 * Circular buffer (TFD queue in DRAM) physical base address
594 */
595 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id),
596 trans->txqs.txq[txq_id]->dma_addr >> 8);
597 }
598
599 iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
600 if (trans->trans_cfg->base_params->num_of_queues > 20)
601 iwl_set_bits_prph(trans, SCD_GP_CTRL,
602 SCD_GP_CTRL_ENABLE_31_QUEUES);
603
604 return 0;
605error:
606 /*Upon error, free only if we allocated something */
607 if (alloc)
608 iwl_pcie_tx_free(trans);
609 return ret;
610}
611
612static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
613 const struct iwl_host_cmd *cmd)
614{
615 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
616
617 /* Make sure the NIC is still alive in the bus */
618 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
619 return -ENODEV;
620
621 if (!trans->trans_cfg->base_params->apmg_wake_up_wa)
622 return 0;
623
624 /*
625 * wake up the NIC to make sure that the firmware will see the host
626 * command - we will let the NIC sleep once all the host commands
627 * returned. This needs to be done only on NICs that have
628 * apmg_wake_up_wa set (see above.)
629 */
630 if (!_iwl_trans_pcie_grab_nic_access(trans))
631 return -EIO;
632
633 /*
634 * In iwl_trans_grab_nic_access(), we've acquired the reg_lock.
635 * There, we also returned immediately if cmd_hold_nic_awake is
636 * already true, so it's OK to unconditionally set it to true.
637 */
638 trans_pcie->cmd_hold_nic_awake = true;
639 spin_unlock(&trans_pcie->reg_lock);
640
641 return 0;
642}
643
644/*
645 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
646 *
647 * When FW advances 'R' index, all entries between old and new 'R' index
648 * need to be reclaimed. As result, some free space forms. If there is
649 * enough free space (> low mark), wake the stack that feeds us.
650 */
651static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
652{
653 struct iwl_txq *txq = trans->txqs.txq[txq_id];
654 int nfreed = 0;
655 u16 r;
656
657 lockdep_assert_held(&txq->lock);
658
659 idx = iwl_txq_get_cmd_index(txq, idx);
660 r = iwl_txq_get_cmd_index(txq, txq->read_ptr);
661
662 if (idx >= trans->trans_cfg->base_params->max_tfd_queue_size ||
663 (!iwl_txq_used(txq, idx))) {
664 WARN_ONCE(test_bit(txq_id, trans->txqs.queue_used),
665 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
666 __func__, txq_id, idx,
667 trans->trans_cfg->base_params->max_tfd_queue_size,
668 txq->write_ptr, txq->read_ptr);
669 return;
670 }
671
672 for (idx = iwl_txq_inc_wrap(trans, idx); r != idx;
673 r = iwl_txq_inc_wrap(trans, r)) {
674 txq->read_ptr = iwl_txq_inc_wrap(trans, txq->read_ptr);
675
676 if (nfreed++ > 0) {
677 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
678 idx, txq->write_ptr, r);
679 iwl_force_nmi(trans);
680 }
681 }
682
683 if (txq->read_ptr == txq->write_ptr)
684 iwl_pcie_clear_cmd_in_flight(trans);
685
686 iwl_txq_progress(txq);
687}
688
689static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
690 u16 txq_id)
691{
692 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
693 u32 tbl_dw_addr;
694 u32 tbl_dw;
695 u16 scd_q2ratid;
696
697 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
698
699 tbl_dw_addr = trans_pcie->scd_base_addr +
700 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
701
702 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
703
704 if (txq_id & 0x1)
705 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
706 else
707 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
708
709 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
710
711 return 0;
712}
713
714/* Receiver address (actually, Rx station's index into station table),
715 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
716#define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
717
718bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
719 const struct iwl_trans_txq_scd_cfg *cfg,
720 unsigned int wdg_timeout)
721{
722 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
723 struct iwl_txq *txq = trans->txqs.txq[txq_id];
724 int fifo = -1;
725 bool scd_bug = false;
726
727 if (test_and_set_bit(txq_id, trans->txqs.queue_used))
728 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
729
730 txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
731
732 if (cfg) {
733 fifo = cfg->fifo;
734
735 /* Disable the scheduler prior configuring the cmd queue */
736 if (txq_id == trans->txqs.cmd.q_id &&
737 trans_pcie->scd_set_active)
738 iwl_scd_enable_set_active(trans, 0);
739
740 /* Stop this Tx queue before configuring it */
741 iwl_scd_txq_set_inactive(trans, txq_id);
742
743 /* Set this queue as a chain-building queue unless it is CMD */
744 if (txq_id != trans->txqs.cmd.q_id)
745 iwl_scd_txq_set_chain(trans, txq_id);
746
747 if (cfg->aggregate) {
748 u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
749
750 /* Map receiver-address / traffic-ID to this queue */
751 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
752
753 /* enable aggregations for the queue */
754 iwl_scd_txq_enable_agg(trans, txq_id);
755 txq->ampdu = true;
756 } else {
757 /*
758 * disable aggregations for the queue, this will also
759 * make the ra_tid mapping configuration irrelevant
760 * since it is now a non-AGG queue.
761 */
762 iwl_scd_txq_disable_agg(trans, txq_id);
763
764 ssn = txq->read_ptr;
765 }
766 } else {
767 /*
768 * If we need to move the SCD write pointer by steps of
769 * 0x40, 0x80 or 0xc0, it gets stuck. Avoids this and let
770 * the op_mode know by returning true later.
771 * Do this only in case cfg is NULL since this trick can
772 * be done only if we have DQA enabled which is true for mvm
773 * only. And mvm never sets a cfg pointer.
774 * This is really ugly, but this is the easiest way out for
775 * this sad hardware issue.
776 * This bug has been fixed on devices 9000 and up.
777 */
778 scd_bug = !trans->trans_cfg->mq_rx_supported &&
779 !((ssn - txq->write_ptr) & 0x3f) &&
780 (ssn != txq->write_ptr);
781 if (scd_bug)
782 ssn++;
783 }
784
785 /* Place first TFD at index corresponding to start sequence number.
786 * Assumes that ssn_idx is valid (!= 0xFFF) */
787 txq->read_ptr = (ssn & 0xff);
788 txq->write_ptr = (ssn & 0xff);
789 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
790 (ssn & 0xff) | (txq_id << 8));
791
792 if (cfg) {
793 u8 frame_limit = cfg->frame_limit;
794
795 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
796
797 /* Set up Tx window size and frame limit for this queue */
798 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
799 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
800 iwl_trans_write_mem32(trans,
801 trans_pcie->scd_base_addr +
802 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
803 SCD_QUEUE_CTX_REG2_VAL(WIN_SIZE, frame_limit) |
804 SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit));
805
806 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
807 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
808 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
809 (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
810 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
811 SCD_QUEUE_STTS_REG_MSK);
812
813 /* enable the scheduler for this queue (only) */
814 if (txq_id == trans->txqs.cmd.q_id &&
815 trans_pcie->scd_set_active)
816 iwl_scd_enable_set_active(trans, BIT(txq_id));
817
818 IWL_DEBUG_TX_QUEUES(trans,
819 "Activate queue %d on FIFO %d WrPtr: %d\n",
820 txq_id, fifo, ssn & 0xff);
821 } else {
822 IWL_DEBUG_TX_QUEUES(trans,
823 "Activate queue %d WrPtr: %d\n",
824 txq_id, ssn & 0xff);
825 }
826
827 return scd_bug;
828}
829
830void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
831 bool shared_mode)
832{
833 struct iwl_txq *txq = trans->txqs.txq[txq_id];
834
835 txq->ampdu = !shared_mode;
836}
837
838void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
839 bool configure_scd)
840{
841 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
842 u32 stts_addr = trans_pcie->scd_base_addr +
843 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
844 static const u32 zero_val[4] = {};
845
846 trans->txqs.txq[txq_id]->frozen_expiry_remainder = 0;
847 trans->txqs.txq[txq_id]->frozen = false;
848
849 /*
850 * Upon HW Rfkill - we stop the device, and then stop the queues
851 * in the op_mode. Just for the sake of the simplicity of the op_mode,
852 * allow the op_mode to call txq_disable after it already called
853 * stop_device.
854 */
855 if (!test_and_clear_bit(txq_id, trans->txqs.queue_used)) {
856 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
857 "queue %d not used", txq_id);
858 return;
859 }
860
861 if (configure_scd) {
862 iwl_scd_txq_set_inactive(trans, txq_id);
863
864 iwl_trans_write_mem(trans, stts_addr, (const void *)zero_val,
865 ARRAY_SIZE(zero_val));
866 }
867
868 iwl_pcie_txq_unmap(trans, txq_id);
869 trans->txqs.txq[txq_id]->ampdu = false;
870
871 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
872}
873
874/*************** HOST COMMAND QUEUE FUNCTIONS *****/
875
876static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
877{
878 int i;
879
880 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
881 struct iwl_txq *txq = trans->txqs.txq[i];
882
883 if (i == trans->txqs.cmd.q_id)
884 continue;
885
886 /* we skip the command queue (obviously) so it's OK to nest */
887 spin_lock_nested(&txq->lock, 1);
888
889 if (!block && !(WARN_ON_ONCE(!txq->block))) {
890 txq->block--;
891 if (!txq->block) {
892 iwl_write32(trans, HBUS_TARG_WRPTR,
893 txq->write_ptr | (i << 8));
894 }
895 } else if (block) {
896 txq->block++;
897 }
898
899 spin_unlock(&txq->lock);
900 }
901}
902
903/*
904 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
905 * @priv: device private data point
906 * @cmd: a pointer to the ucode command structure
907 *
908 * The function returns < 0 values to indicate the operation
909 * failed. On success, it returns the index (>= 0) of command in the
910 * command queue.
911 */
912int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
913 struct iwl_host_cmd *cmd)
914{
915 struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id];
916 struct iwl_device_cmd *out_cmd;
917 struct iwl_cmd_meta *out_meta;
918 void *dup_buf = NULL;
919 dma_addr_t phys_addr;
920 int idx;
921 u16 copy_size, cmd_size, tb0_size;
922 bool had_nocopy = false;
923 u8 group_id = iwl_cmd_groupid(cmd->id);
924 int i, ret;
925 u32 cmd_pos;
926 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
927 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
928 unsigned long flags;
929
930 if (WARN(!trans->wide_cmd_header &&
931 group_id > IWL_ALWAYS_LONG_GROUP,
932 "unsupported wide command %#x\n", cmd->id))
933 return -EINVAL;
934
935 if (group_id != 0) {
936 copy_size = sizeof(struct iwl_cmd_header_wide);
937 cmd_size = sizeof(struct iwl_cmd_header_wide);
938 } else {
939 copy_size = sizeof(struct iwl_cmd_header);
940 cmd_size = sizeof(struct iwl_cmd_header);
941 }
942
943 /* need one for the header if the first is NOCOPY */
944 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
945
946 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
947 cmddata[i] = cmd->data[i];
948 cmdlen[i] = cmd->len[i];
949
950 if (!cmd->len[i])
951 continue;
952
953 /* need at least IWL_FIRST_TB_SIZE copied */
954 if (copy_size < IWL_FIRST_TB_SIZE) {
955 int copy = IWL_FIRST_TB_SIZE - copy_size;
956
957 if (copy > cmdlen[i])
958 copy = cmdlen[i];
959 cmdlen[i] -= copy;
960 cmddata[i] += copy;
961 copy_size += copy;
962 }
963
964 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
965 had_nocopy = true;
966 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
967 idx = -EINVAL;
968 goto free_dup_buf;
969 }
970 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
971 /*
972 * This is also a chunk that isn't copied
973 * to the static buffer so set had_nocopy.
974 */
975 had_nocopy = true;
976
977 /* only allowed once */
978 if (WARN_ON(dup_buf)) {
979 idx = -EINVAL;
980 goto free_dup_buf;
981 }
982
983 dup_buf = kmemdup(cmddata[i], cmdlen[i],
984 GFP_ATOMIC);
985 if (!dup_buf)
986 return -ENOMEM;
987 } else {
988 /* NOCOPY must not be followed by normal! */
989 if (WARN_ON(had_nocopy)) {
990 idx = -EINVAL;
991 goto free_dup_buf;
992 }
993 copy_size += cmdlen[i];
994 }
995 cmd_size += cmd->len[i];
996 }
997
998 /*
999 * If any of the command structures end up being larger than
1000 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1001 * allocated into separate TFDs, then we will need to
1002 * increase the size of the buffers.
1003 */
1004 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1005 "Command %s (%#x) is too large (%d bytes)\n",
1006 iwl_get_cmd_string(trans, cmd->id),
1007 cmd->id, copy_size)) {
1008 idx = -EINVAL;
1009 goto free_dup_buf;
1010 }
1011
1012 spin_lock_irqsave(&txq->lock, flags);
1013
1014 if (iwl_txq_space(trans, txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1015 spin_unlock_irqrestore(&txq->lock, flags);
1016
1017 IWL_ERR(trans, "No space in command queue\n");
1018 iwl_op_mode_cmd_queue_full(trans->op_mode);
1019 idx = -ENOSPC;
1020 goto free_dup_buf;
1021 }
1022
1023 idx = iwl_txq_get_cmd_index(txq, txq->write_ptr);
1024 out_cmd = txq->entries[idx].cmd;
1025 out_meta = &txq->entries[idx].meta;
1026
1027 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1028 if (cmd->flags & CMD_WANT_SKB)
1029 out_meta->source = cmd;
1030
1031 /* set up the header */
1032 if (group_id != 0) {
1033 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
1034 out_cmd->hdr_wide.group_id = group_id;
1035 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
1036 out_cmd->hdr_wide.length =
1037 cpu_to_le16(cmd_size -
1038 sizeof(struct iwl_cmd_header_wide));
1039 out_cmd->hdr_wide.reserved = 0;
1040 out_cmd->hdr_wide.sequence =
1041 cpu_to_le16(QUEUE_TO_SEQ(trans->txqs.cmd.q_id) |
1042 INDEX_TO_SEQ(txq->write_ptr));
1043
1044 cmd_pos = sizeof(struct iwl_cmd_header_wide);
1045 copy_size = sizeof(struct iwl_cmd_header_wide);
1046 } else {
1047 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id);
1048 out_cmd->hdr.sequence =
1049 cpu_to_le16(QUEUE_TO_SEQ(trans->txqs.cmd.q_id) |
1050 INDEX_TO_SEQ(txq->write_ptr));
1051 out_cmd->hdr.group_id = 0;
1052
1053 cmd_pos = sizeof(struct iwl_cmd_header);
1054 copy_size = sizeof(struct iwl_cmd_header);
1055 }
1056
1057 /* and copy the data that needs to be copied */
1058 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1059 int copy;
1060
1061 if (!cmd->len[i])
1062 continue;
1063
1064 /* copy everything if not nocopy/dup */
1065 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1066 IWL_HCMD_DFL_DUP))) {
1067 copy = cmd->len[i];
1068
1069 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1070 cmd_pos += copy;
1071 copy_size += copy;
1072 continue;
1073 }
1074
1075 /*
1076 * Otherwise we need at least IWL_FIRST_TB_SIZE copied
1077 * in total (for bi-directional DMA), but copy up to what
1078 * we can fit into the payload for debug dump purposes.
1079 */
1080 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1081
1082 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1083 cmd_pos += copy;
1084
1085 /* However, treat copy_size the proper way, we need it below */
1086 if (copy_size < IWL_FIRST_TB_SIZE) {
1087 copy = IWL_FIRST_TB_SIZE - copy_size;
1088
1089 if (copy > cmd->len[i])
1090 copy = cmd->len[i];
1091 copy_size += copy;
1092 }
1093 }
1094
1095 IWL_DEBUG_HC(trans,
1096 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1097 iwl_get_cmd_string(trans, cmd->id),
1098 group_id, out_cmd->hdr.cmd,
1099 le16_to_cpu(out_cmd->hdr.sequence),
1100 cmd_size, txq->write_ptr, idx, trans->txqs.cmd.q_id);
1101
1102 /* start the TFD with the minimum copy bytes */
1103 tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE);
1104 memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size);
1105 iwl_pcie_txq_build_tfd(trans, txq,
1106 iwl_txq_get_first_tb_dma(txq, idx),
1107 tb0_size, true);
1108
1109 /* map first command fragment, if any remains */
1110 if (copy_size > tb0_size) {
1111 phys_addr = dma_map_single(trans->dev,
1112 ((u8 *)&out_cmd->hdr) + tb0_size,
1113 copy_size - tb0_size,
1114 DMA_TO_DEVICE);
1115 if (dma_mapping_error(trans->dev, phys_addr)) {
1116 iwl_txq_gen1_tfd_unmap(trans, out_meta, txq,
1117 txq->write_ptr);
1118 idx = -ENOMEM;
1119 goto out;
1120 }
1121
1122 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1123 copy_size - tb0_size, false);
1124 }
1125
1126 /* map the remaining (adjusted) nocopy/dup fragments */
1127 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1128 void *data = (void *)(uintptr_t)cmddata[i];
1129
1130 if (!cmdlen[i])
1131 continue;
1132 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1133 IWL_HCMD_DFL_DUP)))
1134 continue;
1135 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1136 data = dup_buf;
1137 phys_addr = dma_map_single(trans->dev, data,
1138 cmdlen[i], DMA_TO_DEVICE);
1139 if (dma_mapping_error(trans->dev, phys_addr)) {
1140 iwl_txq_gen1_tfd_unmap(trans, out_meta, txq,
1141 txq->write_ptr);
1142 idx = -ENOMEM;
1143 goto out;
1144 }
1145
1146 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1147 }
1148
1149 BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE);
1150 out_meta->flags = cmd->flags;
1151 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1152 kfree_sensitive(txq->entries[idx].free_buf);
1153 txq->entries[idx].free_buf = dup_buf;
1154
1155 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
1156
1157 /* start timer if queue currently empty */
1158 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
1159 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1160
1161 ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1162 if (ret < 0) {
1163 idx = ret;
1164 goto out;
1165 }
1166
1167 if (cmd->flags & CMD_BLOCK_TXQS)
1168 iwl_trans_pcie_block_txq_ptrs(trans, true);
1169
1170 /* Increment and update queue's write index */
1171 txq->write_ptr = iwl_txq_inc_wrap(trans, txq->write_ptr);
1172 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1173
1174 out:
1175 spin_unlock_irqrestore(&txq->lock, flags);
1176 free_dup_buf:
1177 if (idx < 0)
1178 kfree(dup_buf);
1179 return idx;
1180}
1181
1182/*
1183 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1184 * @rxb: Rx buffer to reclaim
1185 */
1186void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1187 struct iwl_rx_cmd_buffer *rxb)
1188{
1189 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1190 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1191 u8 group_id;
1192 u32 cmd_id;
1193 int txq_id = SEQ_TO_QUEUE(sequence);
1194 int index = SEQ_TO_INDEX(sequence);
1195 int cmd_index;
1196 struct iwl_device_cmd *cmd;
1197 struct iwl_cmd_meta *meta;
1198 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1199 struct iwl_txq *txq = trans->txqs.txq[trans->txqs.cmd.q_id];
1200
1201 /* If a Tx command is being handled and it isn't in the actual
1202 * command queue then there a command routing bug has been introduced
1203 * in the queue management code. */
1204 if (WARN(txq_id != trans->txqs.cmd.q_id,
1205 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1206 txq_id, trans->txqs.cmd.q_id, sequence, txq->read_ptr,
1207 txq->write_ptr)) {
1208 iwl_print_hex_error(trans, pkt, 32);
1209 return;
1210 }
1211
1212 spin_lock_bh(&txq->lock);
1213
1214 cmd_index = iwl_txq_get_cmd_index(txq, index);
1215 cmd = txq->entries[cmd_index].cmd;
1216 meta = &txq->entries[cmd_index].meta;
1217 group_id = cmd->hdr.group_id;
1218 cmd_id = WIDE_ID(group_id, cmd->hdr.cmd);
1219
1220 if (trans->trans_cfg->gen2)
1221 iwl_txq_gen2_tfd_unmap(trans, meta,
1222 iwl_txq_get_tfd(trans, txq, index));
1223 else
1224 iwl_txq_gen1_tfd_unmap(trans, meta, txq, index);
1225
1226 /* Input error checking is done when commands are added to queue. */
1227 if (meta->flags & CMD_WANT_SKB) {
1228 struct page *p = rxb_steal_page(rxb);
1229
1230 meta->source->resp_pkt = pkt;
1231 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1232 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1233 }
1234
1235 if (meta->flags & CMD_BLOCK_TXQS)
1236 iwl_trans_pcie_block_txq_ptrs(trans, false);
1237
1238 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1239
1240 if (!(meta->flags & CMD_ASYNC)) {
1241 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1242 IWL_WARN(trans,
1243 "HCMD_ACTIVE already clear for command %s\n",
1244 iwl_get_cmd_string(trans, cmd_id));
1245 }
1246 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1247 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1248 iwl_get_cmd_string(trans, cmd_id));
1249 wake_up(&trans->wait_command_queue);
1250 }
1251
1252 meta->flags = 0;
1253
1254 spin_unlock_bh(&txq->lock);
1255}
1256
1257static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb,
1258 struct iwl_txq *txq, u8 hdr_len,
1259 struct iwl_cmd_meta *out_meta)
1260{
1261 u16 head_tb_len;
1262 int i;
1263
1264 /*
1265 * Set up TFD's third entry to point directly to remainder
1266 * of skb's head, if any
1267 */
1268 head_tb_len = skb_headlen(skb) - hdr_len;
1269
1270 if (head_tb_len > 0) {
1271 dma_addr_t tb_phys = dma_map_single(trans->dev,
1272 skb->data + hdr_len,
1273 head_tb_len, DMA_TO_DEVICE);
1274 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
1275 return -EINVAL;
1276 trace_iwlwifi_dev_tx_tb(trans->dev, skb, skb->data + hdr_len,
1277 tb_phys, head_tb_len);
1278 iwl_pcie_txq_build_tfd(trans, txq, tb_phys, head_tb_len, false);
1279 }
1280
1281 /* set up the remaining entries to point to the data */
1282 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1283 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1284 dma_addr_t tb_phys;
1285 int tb_idx;
1286
1287 if (!skb_frag_size(frag))
1288 continue;
1289
1290 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
1291 skb_frag_size(frag), DMA_TO_DEVICE);
1292
1293 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
1294 return -EINVAL;
1295 trace_iwlwifi_dev_tx_tb(trans->dev, skb, skb_frag_address(frag),
1296 tb_phys, skb_frag_size(frag));
1297 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
1298 skb_frag_size(frag), false);
1299 if (tb_idx < 0)
1300 return tb_idx;
1301
1302 out_meta->tbs |= BIT(tb_idx);
1303 }
1304
1305 return 0;
1306}
1307
1308#ifdef CONFIG_INET
1309static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
1310 struct iwl_txq *txq, u8 hdr_len,
1311 struct iwl_cmd_meta *out_meta,
1312 struct iwl_device_tx_cmd *dev_cmd,
1313 u16 tb1_len)
1314{
1315 struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload;
1316 struct ieee80211_hdr *hdr = (void *)skb->data;
1317 unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room;
1318 unsigned int mss = skb_shinfo(skb)->gso_size;
1319 u16 length, iv_len, amsdu_pad;
1320 u8 *start_hdr;
1321 struct iwl_tso_hdr_page *hdr_page;
1322 struct tso_t tso;
1323
1324 /* if the packet is protected, then it must be CCMP or GCMP */
1325 BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN);
1326 iv_len = ieee80211_has_protected(hdr->frame_control) ?
1327 IEEE80211_CCMP_HDR_LEN : 0;
1328
1329 trace_iwlwifi_dev_tx(trans->dev, skb,
1330 iwl_txq_get_tfd(trans, txq, txq->write_ptr),
1331 trans->txqs.tfd.size,
1332 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 0);
1333
1334 ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb);
1335 snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb);
1336 total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len;
1337 amsdu_pad = 0;
1338
1339 /* total amount of header we may need for this A-MSDU */
1340 hdr_room = DIV_ROUND_UP(total_len, mss) *
1341 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len;
1342
1343 /* Our device supports 9 segments at most, it will fit in 1 page */
1344 hdr_page = get_page_hdr(trans, hdr_room, skb);
1345 if (!hdr_page)
1346 return -ENOMEM;
1347
1348 start_hdr = hdr_page->pos;
1349 memcpy(hdr_page->pos, skb->data + hdr_len, iv_len);
1350 hdr_page->pos += iv_len;
1351
1352 /*
1353 * Pull the ieee80211 header + IV to be able to use TSO core,
1354 * we will restore it for the tx_status flow.
1355 */
1356 skb_pull(skb, hdr_len + iv_len);
1357
1358 /*
1359 * Remove the length of all the headers that we don't actually
1360 * have in the MPDU by themselves, but that we duplicate into
1361 * all the different MSDUs inside the A-MSDU.
1362 */
1363 le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen);
1364
1365 tso_start(skb, &tso);
1366
1367 while (total_len) {
1368 /* this is the data left for this subframe */
1369 unsigned int data_left =
1370 min_t(unsigned int, mss, total_len);
1371 unsigned int hdr_tb_len;
1372 dma_addr_t hdr_tb_phys;
1373 u8 *subf_hdrs_start = hdr_page->pos;
1374
1375 total_len -= data_left;
1376
1377 memset(hdr_page->pos, 0, amsdu_pad);
1378 hdr_page->pos += amsdu_pad;
1379 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen +
1380 data_left)) & 0x3;
1381 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr));
1382 hdr_page->pos += ETH_ALEN;
1383 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr));
1384 hdr_page->pos += ETH_ALEN;
1385
1386 length = snap_ip_tcp_hdrlen + data_left;
1387 *((__be16 *)hdr_page->pos) = cpu_to_be16(length);
1388 hdr_page->pos += sizeof(length);
1389
1390 /*
1391 * This will copy the SNAP as well which will be considered
1392 * as MAC header.
1393 */
1394 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len);
1395
1396 hdr_page->pos += snap_ip_tcp_hdrlen;
1397
1398 hdr_tb_len = hdr_page->pos - start_hdr;
1399 hdr_tb_phys = dma_map_single(trans->dev, start_hdr,
1400 hdr_tb_len, DMA_TO_DEVICE);
1401 if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys)))
1402 return -EINVAL;
1403 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys,
1404 hdr_tb_len, false);
1405 trace_iwlwifi_dev_tx_tb(trans->dev, skb, start_hdr,
1406 hdr_tb_phys, hdr_tb_len);
1407 /* add this subframe's headers' length to the tx_cmd */
1408 le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start);
1409
1410 /* prepare the start_hdr for the next subframe */
1411 start_hdr = hdr_page->pos;
1412
1413 /* put the payload */
1414 while (data_left) {
1415 unsigned int size = min_t(unsigned int, tso.size,
1416 data_left);
1417 dma_addr_t tb_phys;
1418
1419 tb_phys = dma_map_single(trans->dev, tso.data,
1420 size, DMA_TO_DEVICE);
1421 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
1422 return -EINVAL;
1423
1424 iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
1425 size, false);
1426 trace_iwlwifi_dev_tx_tb(trans->dev, skb, tso.data,
1427 tb_phys, size);
1428
1429 data_left -= size;
1430 tso_build_data(skb, &tso, size);
1431 }
1432 }
1433
1434 /* re -add the WiFi header and IV */
1435 skb_push(skb, hdr_len + iv_len);
1436
1437 return 0;
1438}
1439#else /* CONFIG_INET */
1440static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
1441 struct iwl_txq *txq, u8 hdr_len,
1442 struct iwl_cmd_meta *out_meta,
1443 struct iwl_device_tx_cmd *dev_cmd,
1444 u16 tb1_len)
1445{
1446 /* No A-MSDU without CONFIG_INET */
1447 WARN_ON(1);
1448
1449 return -1;
1450}
1451#endif /* CONFIG_INET */
1452
1453int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1454 struct iwl_device_tx_cmd *dev_cmd, int txq_id)
1455{
1456 struct ieee80211_hdr *hdr;
1457 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
1458 struct iwl_cmd_meta *out_meta;
1459 struct iwl_txq *txq;
1460 dma_addr_t tb0_phys, tb1_phys, scratch_phys;
1461 void *tb1_addr;
1462 void *tfd;
1463 u16 len, tb1_len;
1464 bool wait_write_ptr;
1465 __le16 fc;
1466 u8 hdr_len;
1467 u16 wifi_seq;
1468 bool amsdu;
1469
1470 txq = trans->txqs.txq[txq_id];
1471
1472 if (WARN_ONCE(!test_bit(txq_id, trans->txqs.queue_used),
1473 "TX on unused queue %d\n", txq_id))
1474 return -EINVAL;
1475
1476 if (skb_is_nonlinear(skb) &&
1477 skb_shinfo(skb)->nr_frags > IWL_TRANS_MAX_FRAGS(trans) &&
1478 __skb_linearize(skb))
1479 return -ENOMEM;
1480
1481 /* mac80211 always puts the full header into the SKB's head,
1482 * so there's no need to check if it's readable there
1483 */
1484 hdr = (struct ieee80211_hdr *)skb->data;
1485 fc = hdr->frame_control;
1486 hdr_len = ieee80211_hdrlen(fc);
1487
1488 spin_lock(&txq->lock);
1489
1490 if (iwl_txq_space(trans, txq) < txq->high_mark) {
1491 iwl_txq_stop(trans, txq);
1492
1493 /* don't put the packet on the ring, if there is no room */
1494 if (unlikely(iwl_txq_space(trans, txq) < 3)) {
1495 struct iwl_device_tx_cmd **dev_cmd_ptr;
1496
1497 dev_cmd_ptr = (void *)((u8 *)skb->cb +
1498 trans->txqs.dev_cmd_offs);
1499
1500 *dev_cmd_ptr = dev_cmd;
1501 __skb_queue_tail(&txq->overflow_q, skb);
1502
1503 spin_unlock(&txq->lock);
1504 return 0;
1505 }
1506 }
1507
1508 /* In AGG mode, the index in the ring must correspond to the WiFi
1509 * sequence number. This is a HW requirements to help the SCD to parse
1510 * the BA.
1511 * Check here that the packets are in the right place on the ring.
1512 */
1513 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1514 WARN_ONCE(txq->ampdu &&
1515 (wifi_seq & 0xff) != txq->write_ptr,
1516 "Q: %d WiFi Seq %d tfdNum %d",
1517 txq_id, wifi_seq, txq->write_ptr);
1518
1519 /* Set up driver data for this TFD */
1520 txq->entries[txq->write_ptr].skb = skb;
1521 txq->entries[txq->write_ptr].cmd = dev_cmd;
1522
1523 dev_cmd->hdr.sequence =
1524 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1525 INDEX_TO_SEQ(txq->write_ptr)));
1526
1527 tb0_phys = iwl_txq_get_first_tb_dma(txq, txq->write_ptr);
1528 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
1529 offsetof(struct iwl_tx_cmd, scratch);
1530
1531 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1532 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1533
1534 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1535 out_meta = &txq->entries[txq->write_ptr].meta;
1536 out_meta->flags = 0;
1537
1538 /*
1539 * The second TB (tb1) points to the remainder of the TX command
1540 * and the 802.11 header - dword aligned size
1541 * (This calculation modifies the TX command, so do it before the
1542 * setup of the first TB)
1543 */
1544 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
1545 hdr_len - IWL_FIRST_TB_SIZE;
1546 /* do not align A-MSDU to dword as the subframe header aligns it */
1547 amsdu = ieee80211_is_data_qos(fc) &&
1548 (*ieee80211_get_qos_ctl(hdr) &
1549 IEEE80211_QOS_CTL_A_MSDU_PRESENT);
1550 if (!amsdu) {
1551 tb1_len = ALIGN(len, 4);
1552 /* Tell NIC about any 2-byte padding after MAC header */
1553 if (tb1_len != len)
1554 tx_cmd->tx_flags |= cpu_to_le32(TX_CMD_FLG_MH_PAD);
1555 } else {
1556 tb1_len = len;
1557 }
1558
1559 /*
1560 * The first TB points to bi-directional DMA data, we'll
1561 * memcpy the data into it later.
1562 */
1563 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
1564 IWL_FIRST_TB_SIZE, true);
1565
1566 /* there must be data left over for TB1 or this code must be changed */
1567 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE);
1568 BUILD_BUG_ON(sizeof(struct iwl_cmd_header) +
1569 offsetofend(struct iwl_tx_cmd, scratch) >
1570 IWL_FIRST_TB_SIZE);
1571
1572 /* map the data for TB1 */
1573 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
1574 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
1575 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
1576 goto out_err;
1577 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
1578
1579 trace_iwlwifi_dev_tx(trans->dev, skb,
1580 iwl_txq_get_tfd(trans, txq, txq->write_ptr),
1581 trans->txqs.tfd.size,
1582 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len,
1583 hdr_len);
1584
1585 /*
1586 * If gso_size wasn't set, don't give the frame "amsdu treatment"
1587 * (adding subframes, etc.).
1588 * This can happen in some testing flows when the amsdu was already
1589 * pre-built, and we just need to send the resulting skb.
1590 */
1591 if (amsdu && skb_shinfo(skb)->gso_size) {
1592 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len,
1593 out_meta, dev_cmd,
1594 tb1_len)))
1595 goto out_err;
1596 } else {
1597 struct sk_buff *frag;
1598
1599 if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len,
1600 out_meta)))
1601 goto out_err;
1602
1603 skb_walk_frags(skb, frag) {
1604 if (unlikely(iwl_fill_data_tbs(trans, frag, txq, 0,
1605 out_meta)))
1606 goto out_err;
1607 }
1608 }
1609
1610 /* building the A-MSDU might have changed this data, so memcpy it now */
1611 memcpy(&txq->first_tb_bufs[txq->write_ptr], dev_cmd, IWL_FIRST_TB_SIZE);
1612
1613 tfd = iwl_txq_get_tfd(trans, txq, txq->write_ptr);
1614 /* Set up entry for this TFD in Tx byte-count array */
1615 iwl_txq_gen1_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len),
1616 iwl_txq_gen1_tfd_get_num_tbs(trans,
1617 tfd));
1618
1619 wait_write_ptr = ieee80211_has_morefrags(fc);
1620
1621 /* start timer if queue currently empty */
1622 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) {
1623 /*
1624 * If the TXQ is active, then set the timer, if not,
1625 * set the timer in remainder so that the timer will
1626 * be armed with the right value when the station will
1627 * wake up.
1628 */
1629 if (!txq->frozen)
1630 mod_timer(&txq->stuck_timer,
1631 jiffies + txq->wd_timeout);
1632 else
1633 txq->frozen_expiry_remainder = txq->wd_timeout;
1634 }
1635
1636 /* Tell device the write index *just past* this latest filled TFD */
1637 txq->write_ptr = iwl_txq_inc_wrap(trans, txq->write_ptr);
1638 if (!wait_write_ptr)
1639 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1640
1641 /*
1642 * At this point the frame is "transmitted" successfully
1643 * and we will get a TX status notification eventually.
1644 */
1645 spin_unlock(&txq->lock);
1646 return 0;
1647out_err:
1648 iwl_txq_gen1_tfd_unmap(trans, out_meta, txq, txq->write_ptr);
1649 spin_unlock(&txq->lock);
1650 return -1;
1651}
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11 * Copyright(c) 2018 - 2019 Intel Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * more details.
21 *
22 * The full GNU General Public License is included in this distribution in the
23 * file called COPYING.
24 *
25 * Contact Information:
26 * Intel Linux Wireless <linuxwifi@intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 * BSD LICENSE
30 *
31 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
34 * Copyright(c) 2018 - 2019 Intel Corporation
35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 *
41 * * Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * * Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in
45 * the documentation and/or other materials provided with the
46 * distribution.
47 * * Neither the name Intel Corporation nor the names of its
48 * contributors may be used to endorse or promote products derived
49 * from this software without specific prior written permission.
50 *
51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *
63 *****************************************************************************/
64#include <linux/etherdevice.h>
65#include <linux/ieee80211.h>
66#include <linux/slab.h>
67#include <linux/sched.h>
68#include <net/ip6_checksum.h>
69#include <net/tso.h>
70
71#include "iwl-debug.h"
72#include "iwl-csr.h"
73#include "iwl-prph.h"
74#include "iwl-io.h"
75#include "iwl-scd.h"
76#include "iwl-op-mode.h"
77#include "internal.h"
78#include "fw/api/tx.h"
79
80#define IWL_TX_CRC_SIZE 4
81#define IWL_TX_DELIMITER_SIZE 4
82
83/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
84 * DMA services
85 *
86 * Theory of operation
87 *
88 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
89 * of buffer descriptors, each of which points to one or more data buffers for
90 * the device to read from or fill. Driver and device exchange status of each
91 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
92 * entries in each circular buffer, to protect against confusing empty and full
93 * queue states.
94 *
95 * The device reads or writes the data in the queues via the device's several
96 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
97 *
98 * For Tx queue, there are low mark and high mark limits. If, after queuing
99 * the packet for Tx, free space become < low mark, Tx queue stopped. When
100 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
101 * Tx queue resumed.
102 *
103 ***************************************************/
104
105int iwl_queue_space(struct iwl_trans *trans, const struct iwl_txq *q)
106{
107 unsigned int max;
108 unsigned int used;
109
110 /*
111 * To avoid ambiguity between empty and completely full queues, there
112 * should always be less than max_tfd_queue_size elements in the queue.
113 * If q->n_window is smaller than max_tfd_queue_size, there is no need
114 * to reserve any queue entries for this purpose.
115 */
116 if (q->n_window < trans->trans_cfg->base_params->max_tfd_queue_size)
117 max = q->n_window;
118 else
119 max = trans->trans_cfg->base_params->max_tfd_queue_size - 1;
120
121 /*
122 * max_tfd_queue_size is a power of 2, so the following is equivalent to
123 * modulo by max_tfd_queue_size and is well defined.
124 */
125 used = (q->write_ptr - q->read_ptr) &
126 (trans->trans_cfg->base_params->max_tfd_queue_size - 1);
127
128 if (WARN_ON(used > max))
129 return 0;
130
131 return max - used;
132}
133
134/*
135 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
136 */
137static int iwl_queue_init(struct iwl_txq *q, int slots_num)
138{
139 q->n_window = slots_num;
140
141 /* slots_num must be power-of-two size, otherwise
142 * iwl_pcie_get_cmd_index is broken. */
143 if (WARN_ON(!is_power_of_2(slots_num)))
144 return -EINVAL;
145
146 q->low_mark = q->n_window / 4;
147 if (q->low_mark < 4)
148 q->low_mark = 4;
149
150 q->high_mark = q->n_window / 8;
151 if (q->high_mark < 2)
152 q->high_mark = 2;
153
154 q->write_ptr = 0;
155 q->read_ptr = 0;
156
157 return 0;
158}
159
160int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
161 struct iwl_dma_ptr *ptr, size_t size)
162{
163 if (WARN_ON(ptr->addr))
164 return -EINVAL;
165
166 ptr->addr = dma_alloc_coherent(trans->dev, size,
167 &ptr->dma, GFP_KERNEL);
168 if (!ptr->addr)
169 return -ENOMEM;
170 ptr->size = size;
171 return 0;
172}
173
174void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr)
175{
176 if (unlikely(!ptr->addr))
177 return;
178
179 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
180 memset(ptr, 0, sizeof(*ptr));
181}
182
183static void iwl_pcie_txq_stuck_timer(struct timer_list *t)
184{
185 struct iwl_txq *txq = from_timer(txq, t, stuck_timer);
186 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
187 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
188
189 spin_lock(&txq->lock);
190 /* check if triggered erroneously */
191 if (txq->read_ptr == txq->write_ptr) {
192 spin_unlock(&txq->lock);
193 return;
194 }
195 spin_unlock(&txq->lock);
196
197 iwl_trans_pcie_log_scd_error(trans, txq);
198
199 iwl_force_nmi(trans);
200}
201
202/*
203 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
204 */
205static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
206 struct iwl_txq *txq, u16 byte_cnt,
207 int num_tbs)
208{
209 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
210 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
211 int write_ptr = txq->write_ptr;
212 int txq_id = txq->id;
213 u8 sec_ctl = 0;
214 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
215 __le16 bc_ent;
216 struct iwl_tx_cmd *tx_cmd =
217 (void *)txq->entries[txq->write_ptr].cmd->payload;
218 u8 sta_id = tx_cmd->sta_id;
219
220 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
221
222 sec_ctl = tx_cmd->sec_ctl;
223
224 switch (sec_ctl & TX_CMD_SEC_MSK) {
225 case TX_CMD_SEC_CCM:
226 len += IEEE80211_CCMP_MIC_LEN;
227 break;
228 case TX_CMD_SEC_TKIP:
229 len += IEEE80211_TKIP_ICV_LEN;
230 break;
231 case TX_CMD_SEC_WEP:
232 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
233 break;
234 }
235 if (trans_pcie->bc_table_dword)
236 len = DIV_ROUND_UP(len, 4);
237
238 if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
239 return;
240
241 bc_ent = cpu_to_le16(len | (sta_id << 12));
242
243 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
244
245 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
246 scd_bc_tbl[txq_id].
247 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
248}
249
250static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
251 struct iwl_txq *txq)
252{
253 struct iwl_trans_pcie *trans_pcie =
254 IWL_TRANS_GET_PCIE_TRANS(trans);
255 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
256 int txq_id = txq->id;
257 int read_ptr = txq->read_ptr;
258 u8 sta_id = 0;
259 __le16 bc_ent;
260 struct iwl_tx_cmd *tx_cmd =
261 (void *)txq->entries[read_ptr].cmd->payload;
262
263 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
264
265 if (txq_id != trans_pcie->cmd_queue)
266 sta_id = tx_cmd->sta_id;
267
268 bc_ent = cpu_to_le16(1 | (sta_id << 12));
269
270 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
271
272 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
273 scd_bc_tbl[txq_id].
274 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
275}
276
277/*
278 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
279 */
280static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
281 struct iwl_txq *txq)
282{
283 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
284 u32 reg = 0;
285 int txq_id = txq->id;
286
287 lockdep_assert_held(&txq->lock);
288
289 /*
290 * explicitly wake up the NIC if:
291 * 1. shadow registers aren't enabled
292 * 2. NIC is woken up for CMD regardless of shadow outside this function
293 * 3. there is a chance that the NIC is asleep
294 */
295 if (!trans->trans_cfg->base_params->shadow_reg_enable &&
296 txq_id != trans_pcie->cmd_queue &&
297 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
298 /*
299 * wake up nic if it's powered down ...
300 * uCode will wake up, and interrupt us again, so next
301 * time we'll skip this part.
302 */
303 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
304
305 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
306 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
307 txq_id, reg);
308 iwl_set_bit(trans, CSR_GP_CNTRL,
309 BIT(trans->trans_cfg->csr->flag_mac_access_req));
310 txq->need_update = true;
311 return;
312 }
313 }
314
315 /*
316 * if not in power-save mode, uCode will never sleep when we're
317 * trying to tx (during RFKILL, we're not trying to tx).
318 */
319 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr);
320 if (!txq->block)
321 iwl_write32(trans, HBUS_TARG_WRPTR,
322 txq->write_ptr | (txq_id << 8));
323}
324
325void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
326{
327 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
328 int i;
329
330 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
331 struct iwl_txq *txq = trans_pcie->txq[i];
332
333 if (!test_bit(i, trans_pcie->queue_used))
334 continue;
335
336 spin_lock_bh(&txq->lock);
337 if (txq->need_update) {
338 iwl_pcie_txq_inc_wr_ptr(trans, txq);
339 txq->need_update = false;
340 }
341 spin_unlock_bh(&txq->lock);
342 }
343}
344
345static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans,
346 void *_tfd, u8 idx)
347{
348
349 if (trans->trans_cfg->use_tfh) {
350 struct iwl_tfh_tfd *tfd = _tfd;
351 struct iwl_tfh_tb *tb = &tfd->tbs[idx];
352
353 return (dma_addr_t)(le64_to_cpu(tb->addr));
354 } else {
355 struct iwl_tfd *tfd = _tfd;
356 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
357 dma_addr_t addr = get_unaligned_le32(&tb->lo);
358 dma_addr_t hi_len;
359
360 if (sizeof(dma_addr_t) <= sizeof(u32))
361 return addr;
362
363 hi_len = le16_to_cpu(tb->hi_n_len) & 0xF;
364
365 /*
366 * shift by 16 twice to avoid warnings on 32-bit
367 * (where this code never runs anyway due to the
368 * if statement above)
369 */
370 return addr | ((hi_len << 16) << 16);
371 }
372}
373
374static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd,
375 u8 idx, dma_addr_t addr, u16 len)
376{
377 struct iwl_tfd *tfd_fh = (void *)tfd;
378 struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx];
379
380 u16 hi_n_len = len << 4;
381
382 put_unaligned_le32(addr, &tb->lo);
383 hi_n_len |= iwl_get_dma_hi_addr(addr);
384
385 tb->hi_n_len = cpu_to_le16(hi_n_len);
386
387 tfd_fh->num_tbs = idx + 1;
388}
389
390static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_trans *trans, void *_tfd)
391{
392 if (trans->trans_cfg->use_tfh) {
393 struct iwl_tfh_tfd *tfd = _tfd;
394
395 return le16_to_cpu(tfd->num_tbs) & 0x1f;
396 } else {
397 struct iwl_tfd *tfd = _tfd;
398
399 return tfd->num_tbs & 0x1f;
400 }
401}
402
403static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
404 struct iwl_cmd_meta *meta,
405 struct iwl_txq *txq, int index)
406{
407 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
408 int i, num_tbs;
409 void *tfd = iwl_pcie_get_tfd(trans, txq, index);
410
411 /* Sanity check on number of chunks */
412 num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
413
414 if (num_tbs > trans_pcie->max_tbs) {
415 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
416 /* @todo issue fatal error, it is quite serious situation */
417 return;
418 }
419
420 /* first TB is never freed - it's the bidirectional DMA data */
421
422 for (i = 1; i < num_tbs; i++) {
423 if (meta->tbs & BIT(i))
424 dma_unmap_page(trans->dev,
425 iwl_pcie_tfd_tb_get_addr(trans, tfd, i),
426 iwl_pcie_tfd_tb_get_len(trans, tfd, i),
427 DMA_TO_DEVICE);
428 else
429 dma_unmap_single(trans->dev,
430 iwl_pcie_tfd_tb_get_addr(trans, tfd,
431 i),
432 iwl_pcie_tfd_tb_get_len(trans, tfd,
433 i),
434 DMA_TO_DEVICE);
435 }
436
437 meta->tbs = 0;
438
439 if (trans->trans_cfg->use_tfh) {
440 struct iwl_tfh_tfd *tfd_fh = (void *)tfd;
441
442 tfd_fh->num_tbs = 0;
443 } else {
444 struct iwl_tfd *tfd_fh = (void *)tfd;
445
446 tfd_fh->num_tbs = 0;
447 }
448
449}
450
451/*
452 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
453 * @trans - transport private data
454 * @txq - tx queue
455 * @dma_dir - the direction of the DMA mapping
456 *
457 * Does NOT advance any TFD circular buffer read/write indexes
458 * Does NOT free the TFD itself (which is within circular buffer)
459 */
460void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
461{
462 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
463 * idx is bounded by n_window
464 */
465 int rd_ptr = txq->read_ptr;
466 int idx = iwl_pcie_get_cmd_index(txq, rd_ptr);
467
468 lockdep_assert_held(&txq->lock);
469
470 /* We have only q->n_window txq->entries, but we use
471 * TFD_QUEUE_SIZE_MAX tfds
472 */
473 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr);
474
475 /* free SKB */
476 if (txq->entries) {
477 struct sk_buff *skb;
478
479 skb = txq->entries[idx].skb;
480
481 /* Can be called from irqs-disabled context
482 * If skb is not NULL, it means that the whole queue is being
483 * freed and that the queue is not empty - free the skb
484 */
485 if (skb) {
486 iwl_op_mode_free_skb(trans->op_mode, skb);
487 txq->entries[idx].skb = NULL;
488 }
489 }
490}
491
492static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
493 dma_addr_t addr, u16 len, bool reset)
494{
495 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
496 void *tfd;
497 u32 num_tbs;
498
499 tfd = txq->tfds + trans_pcie->tfd_size * txq->write_ptr;
500
501 if (reset)
502 memset(tfd, 0, trans_pcie->tfd_size);
503
504 num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
505
506 /* Each TFD can point to a maximum max_tbs Tx buffers */
507 if (num_tbs >= trans_pcie->max_tbs) {
508 IWL_ERR(trans, "Error can not send more than %d chunks\n",
509 trans_pcie->max_tbs);
510 return -EINVAL;
511 }
512
513 if (WARN(addr & ~IWL_TX_DMA_MASK,
514 "Unaligned address = %llx\n", (unsigned long long)addr))
515 return -EINVAL;
516
517 iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len);
518
519 return num_tbs;
520}
521
522int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq,
523 int slots_num, bool cmd_queue)
524{
525 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
526 size_t tfd_sz = trans_pcie->tfd_size *
527 trans->trans_cfg->base_params->max_tfd_queue_size;
528 size_t tb0_buf_sz;
529 int i;
530
531 if (WARN_ON(txq->entries || txq->tfds))
532 return -EINVAL;
533
534 if (trans->trans_cfg->use_tfh)
535 tfd_sz = trans_pcie->tfd_size * slots_num;
536
537 timer_setup(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, 0);
538 txq->trans_pcie = trans_pcie;
539
540 txq->n_window = slots_num;
541
542 txq->entries = kcalloc(slots_num,
543 sizeof(struct iwl_pcie_txq_entry),
544 GFP_KERNEL);
545
546 if (!txq->entries)
547 goto error;
548
549 if (cmd_queue)
550 for (i = 0; i < slots_num; i++) {
551 txq->entries[i].cmd =
552 kmalloc(sizeof(struct iwl_device_cmd),
553 GFP_KERNEL);
554 if (!txq->entries[i].cmd)
555 goto error;
556 }
557
558 /* Circular buffer of transmit frame descriptors (TFDs),
559 * shared with device */
560 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
561 &txq->dma_addr, GFP_KERNEL);
562 if (!txq->tfds)
563 goto error;
564
565 BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs));
566
567 tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num;
568
569 txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz,
570 &txq->first_tb_dma,
571 GFP_KERNEL);
572 if (!txq->first_tb_bufs)
573 goto err_free_tfds;
574
575 return 0;
576err_free_tfds:
577 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr);
578error:
579 if (txq->entries && cmd_queue)
580 for (i = 0; i < slots_num; i++)
581 kfree(txq->entries[i].cmd);
582 kfree(txq->entries);
583 txq->entries = NULL;
584
585 return -ENOMEM;
586
587}
588
589int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
590 int slots_num, bool cmd_queue)
591{
592 int ret;
593 u32 tfd_queue_max_size =
594 trans->trans_cfg->base_params->max_tfd_queue_size;
595
596 txq->need_update = false;
597
598 /* max_tfd_queue_size must be power-of-two size, otherwise
599 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
600 if (WARN_ONCE(tfd_queue_max_size & (tfd_queue_max_size - 1),
601 "Max tfd queue size must be a power of two, but is %d",
602 tfd_queue_max_size))
603 return -EINVAL;
604
605 /* Initialize queue's high/low-water marks, and head/tail indexes */
606 ret = iwl_queue_init(txq, slots_num);
607 if (ret)
608 return ret;
609
610 spin_lock_init(&txq->lock);
611
612 if (cmd_queue) {
613 static struct lock_class_key iwl_pcie_cmd_queue_lock_class;
614
615 lockdep_set_class(&txq->lock, &iwl_pcie_cmd_queue_lock_class);
616 }
617
618 __skb_queue_head_init(&txq->overflow_q);
619
620 return 0;
621}
622
623void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie,
624 struct sk_buff *skb)
625{
626 struct page **page_ptr;
627
628 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
629
630 if (*page_ptr) {
631 __free_page(*page_ptr);
632 *page_ptr = NULL;
633 }
634}
635
636static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
637{
638 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
639
640 lockdep_assert_held(&trans_pcie->reg_lock);
641
642 if (!trans->trans_cfg->base_params->apmg_wake_up_wa)
643 return;
644 if (WARN_ON(!trans_pcie->cmd_hold_nic_awake))
645 return;
646
647 trans_pcie->cmd_hold_nic_awake = false;
648 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
649 BIT(trans->trans_cfg->csr->flag_mac_access_req));
650}
651
652/*
653 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
654 */
655static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
656{
657 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
658 struct iwl_txq *txq = trans_pcie->txq[txq_id];
659
660 spin_lock_bh(&txq->lock);
661 while (txq->write_ptr != txq->read_ptr) {
662 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
663 txq_id, txq->read_ptr);
664
665 if (txq_id != trans_pcie->cmd_queue) {
666 struct sk_buff *skb = txq->entries[txq->read_ptr].skb;
667
668 if (WARN_ON_ONCE(!skb))
669 continue;
670
671 iwl_pcie_free_tso_page(trans_pcie, skb);
672 }
673 iwl_pcie_txq_free_tfd(trans, txq);
674 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr);
675
676 if (txq->read_ptr == txq->write_ptr) {
677 unsigned long flags;
678
679 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
680 if (txq_id == trans_pcie->cmd_queue)
681 iwl_pcie_clear_cmd_in_flight(trans);
682 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
683 }
684 }
685
686 while (!skb_queue_empty(&txq->overflow_q)) {
687 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q);
688
689 iwl_op_mode_free_skb(trans->op_mode, skb);
690 }
691
692 spin_unlock_bh(&txq->lock);
693
694 /* just in case - this queue may have been stopped */
695 iwl_wake_queue(trans, txq);
696}
697
698/*
699 * iwl_pcie_txq_free - Deallocate DMA queue.
700 * @txq: Transmit queue to deallocate.
701 *
702 * Empty queue by removing and destroying all BD's.
703 * Free all buffers.
704 * 0-fill, but do not free "txq" descriptor structure.
705 */
706static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
707{
708 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
709 struct iwl_txq *txq = trans_pcie->txq[txq_id];
710 struct device *dev = trans->dev;
711 int i;
712
713 if (WARN_ON(!txq))
714 return;
715
716 iwl_pcie_txq_unmap(trans, txq_id);
717
718 /* De-alloc array of command/tx buffers */
719 if (txq_id == trans_pcie->cmd_queue)
720 for (i = 0; i < txq->n_window; i++) {
721 kzfree(txq->entries[i].cmd);
722 kzfree(txq->entries[i].free_buf);
723 }
724
725 /* De-alloc circular buffer of TFDs */
726 if (txq->tfds) {
727 dma_free_coherent(dev,
728 trans_pcie->tfd_size *
729 trans->trans_cfg->base_params->max_tfd_queue_size,
730 txq->tfds, txq->dma_addr);
731 txq->dma_addr = 0;
732 txq->tfds = NULL;
733
734 dma_free_coherent(dev,
735 sizeof(*txq->first_tb_bufs) * txq->n_window,
736 txq->first_tb_bufs, txq->first_tb_dma);
737 }
738
739 kfree(txq->entries);
740 txq->entries = NULL;
741
742 del_timer_sync(&txq->stuck_timer);
743
744 /* 0-fill queue descriptor structure */
745 memset(txq, 0, sizeof(*txq));
746}
747
748void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
749{
750 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
751 int nq = trans->trans_cfg->base_params->num_of_queues;
752 int chan;
753 u32 reg_val;
754 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
755 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
756
757 /* make sure all queue are not stopped/used */
758 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
759 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
760
761 trans_pcie->scd_base_addr =
762 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
763
764 WARN_ON(scd_base_addr != 0 &&
765 scd_base_addr != trans_pcie->scd_base_addr);
766
767 /* reset context data, TX status and translation data */
768 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
769 SCD_CONTEXT_MEM_LOWER_BOUND,
770 NULL, clear_dwords);
771
772 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
773 trans_pcie->scd_bc_tbls.dma >> 10);
774
775 /* The chain extension of the SCD doesn't work well. This feature is
776 * enabled by default by the HW, so we need to disable it manually.
777 */
778 if (trans->trans_cfg->base_params->scd_chain_ext_wa)
779 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
780
781 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
782 trans_pcie->cmd_fifo,
783 trans_pcie->cmd_q_wdg_timeout);
784
785 /* Activate all Tx DMA/FIFO channels */
786 iwl_scd_activate_fifos(trans);
787
788 /* Enable DMA channel */
789 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
790 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
791 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
792 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
793
794 /* Update FH chicken bits */
795 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
796 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
797 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
798
799 /* Enable L1-Active */
800 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
801 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
802 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
803}
804
805void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
806{
807 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
808 int txq_id;
809
810 /*
811 * we should never get here in gen2 trans mode return early to avoid
812 * having invalid accesses
813 */
814 if (WARN_ON_ONCE(trans->trans_cfg->gen2))
815 return;
816
817 for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
818 txq_id++) {
819 struct iwl_txq *txq = trans_pcie->txq[txq_id];
820 if (trans->trans_cfg->use_tfh)
821 iwl_write_direct64(trans,
822 FH_MEM_CBBC_QUEUE(trans, txq_id),
823 txq->dma_addr);
824 else
825 iwl_write_direct32(trans,
826 FH_MEM_CBBC_QUEUE(trans, txq_id),
827 txq->dma_addr >> 8);
828 iwl_pcie_txq_unmap(trans, txq_id);
829 txq->read_ptr = 0;
830 txq->write_ptr = 0;
831 }
832
833 /* Tell NIC where to find the "keep warm" buffer */
834 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
835 trans_pcie->kw.dma >> 4);
836
837 /*
838 * Send 0 as the scd_base_addr since the device may have be reset
839 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
840 * contain garbage.
841 */
842 iwl_pcie_tx_start(trans, 0);
843}
844
845static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
846{
847 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
848 unsigned long flags;
849 int ch, ret;
850 u32 mask = 0;
851
852 spin_lock(&trans_pcie->irq_lock);
853
854 if (!iwl_trans_grab_nic_access(trans, &flags))
855 goto out;
856
857 /* Stop each Tx DMA channel */
858 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
859 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
860 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
861 }
862
863 /* Wait for DMA channels to be idle */
864 ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
865 if (ret < 0)
866 IWL_ERR(trans,
867 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
868 ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
869
870 iwl_trans_release_nic_access(trans, &flags);
871
872out:
873 spin_unlock(&trans_pcie->irq_lock);
874}
875
876/*
877 * iwl_pcie_tx_stop - Stop all Tx DMA channels
878 */
879int iwl_pcie_tx_stop(struct iwl_trans *trans)
880{
881 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
882 int txq_id;
883
884 /* Turn off all Tx DMA fifos */
885 iwl_scd_deactivate_fifos(trans);
886
887 /* Turn off all Tx DMA channels */
888 iwl_pcie_tx_stop_fh(trans);
889
890 /*
891 * This function can be called before the op_mode disabled the
892 * queues. This happens when we have an rfkill interrupt.
893 * Since we stop Tx altogether - mark the queues as stopped.
894 */
895 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
896 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
897
898 /* This can happen: start_hw, stop_device */
899 if (!trans_pcie->txq_memory)
900 return 0;
901
902 /* Unmap DMA from host system and free skb's */
903 for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
904 txq_id++)
905 iwl_pcie_txq_unmap(trans, txq_id);
906
907 return 0;
908}
909
910/*
911 * iwl_trans_tx_free - Free TXQ Context
912 *
913 * Destroy all TX DMA queues and structures
914 */
915void iwl_pcie_tx_free(struct iwl_trans *trans)
916{
917 int txq_id;
918 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
919
920 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
921
922 /* Tx queues */
923 if (trans_pcie->txq_memory) {
924 for (txq_id = 0;
925 txq_id < trans->trans_cfg->base_params->num_of_queues;
926 txq_id++) {
927 iwl_pcie_txq_free(trans, txq_id);
928 trans_pcie->txq[txq_id] = NULL;
929 }
930 }
931
932 kfree(trans_pcie->txq_memory);
933 trans_pcie->txq_memory = NULL;
934
935 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
936
937 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
938}
939
940/*
941 * iwl_pcie_tx_alloc - allocate TX context
942 * Allocate all Tx DMA structures and initialize them
943 */
944static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
945{
946 int ret;
947 int txq_id, slots_num;
948 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
949 u16 bc_tbls_size = trans->trans_cfg->base_params->num_of_queues;
950
951 bc_tbls_size *= (trans->trans_cfg->device_family >=
952 IWL_DEVICE_FAMILY_22560) ?
953 sizeof(struct iwl_gen3_bc_tbl) :
954 sizeof(struct iwlagn_scd_bc_tbl);
955
956 /*It is not allowed to alloc twice, so warn when this happens.
957 * We cannot rely on the previous allocation, so free and fail */
958 if (WARN_ON(trans_pcie->txq_memory)) {
959 ret = -EINVAL;
960 goto error;
961 }
962
963 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
964 bc_tbls_size);
965 if (ret) {
966 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
967 goto error;
968 }
969
970 /* Alloc keep-warm buffer */
971 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
972 if (ret) {
973 IWL_ERR(trans, "Keep Warm allocation failed\n");
974 goto error;
975 }
976
977 trans_pcie->txq_memory =
978 kcalloc(trans->trans_cfg->base_params->num_of_queues,
979 sizeof(struct iwl_txq), GFP_KERNEL);
980 if (!trans_pcie->txq_memory) {
981 IWL_ERR(trans, "Not enough memory for txq\n");
982 ret = -ENOMEM;
983 goto error;
984 }
985
986 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
987 for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
988 txq_id++) {
989 bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
990
991 if (cmd_queue)
992 slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE,
993 trans->cfg->min_txq_size);
994 else
995 slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE,
996 trans->cfg->min_256_ba_txq_size);
997 trans_pcie->txq[txq_id] = &trans_pcie->txq_memory[txq_id];
998 ret = iwl_pcie_txq_alloc(trans, trans_pcie->txq[txq_id],
999 slots_num, cmd_queue);
1000 if (ret) {
1001 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
1002 goto error;
1003 }
1004 trans_pcie->txq[txq_id]->id = txq_id;
1005 }
1006
1007 return 0;
1008
1009error:
1010 iwl_pcie_tx_free(trans);
1011
1012 return ret;
1013}
1014
1015int iwl_pcie_tx_init(struct iwl_trans *trans)
1016{
1017 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1018 int ret;
1019 int txq_id, slots_num;
1020 bool alloc = false;
1021
1022 if (!trans_pcie->txq_memory) {
1023 ret = iwl_pcie_tx_alloc(trans);
1024 if (ret)
1025 goto error;
1026 alloc = true;
1027 }
1028
1029 spin_lock(&trans_pcie->irq_lock);
1030
1031 /* Turn off all Tx DMA fifos */
1032 iwl_scd_deactivate_fifos(trans);
1033
1034 /* Tell NIC where to find the "keep warm" buffer */
1035 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
1036 trans_pcie->kw.dma >> 4);
1037
1038 spin_unlock(&trans_pcie->irq_lock);
1039
1040 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
1041 for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
1042 txq_id++) {
1043 bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
1044
1045 if (cmd_queue)
1046 slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE,
1047 trans->cfg->min_txq_size);
1048 else
1049 slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE,
1050 trans->cfg->min_256_ba_txq_size);
1051 ret = iwl_pcie_txq_init(trans, trans_pcie->txq[txq_id],
1052 slots_num, cmd_queue);
1053 if (ret) {
1054 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
1055 goto error;
1056 }
1057
1058 /*
1059 * Tell nic where to find circular buffer of TFDs for a
1060 * given Tx queue, and enable the DMA channel used for that
1061 * queue.
1062 * Circular buffer (TFD queue in DRAM) physical base address
1063 */
1064 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id),
1065 trans_pcie->txq[txq_id]->dma_addr >> 8);
1066 }
1067
1068 iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
1069 if (trans->trans_cfg->base_params->num_of_queues > 20)
1070 iwl_set_bits_prph(trans, SCD_GP_CTRL,
1071 SCD_GP_CTRL_ENABLE_31_QUEUES);
1072
1073 return 0;
1074error:
1075 /*Upon error, free only if we allocated something */
1076 if (alloc)
1077 iwl_pcie_tx_free(trans);
1078 return ret;
1079}
1080
1081static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
1082{
1083 lockdep_assert_held(&txq->lock);
1084
1085 if (!txq->wd_timeout)
1086 return;
1087
1088 /*
1089 * station is asleep and we send data - that must
1090 * be uAPSD or PS-Poll. Don't rearm the timer.
1091 */
1092 if (txq->frozen)
1093 return;
1094
1095 /*
1096 * if empty delete timer, otherwise move timer forward
1097 * since we're making progress on this queue
1098 */
1099 if (txq->read_ptr == txq->write_ptr)
1100 del_timer(&txq->stuck_timer);
1101 else
1102 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1103}
1104
1105/* Frees buffers until index _not_ inclusive */
1106void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1107 struct sk_buff_head *skbs)
1108{
1109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1110 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1111 int tfd_num = iwl_pcie_get_cmd_index(txq, ssn);
1112 int read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
1113 int last_to_free;
1114
1115 /* This function is not meant to release cmd queue*/
1116 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
1117 return;
1118
1119 spin_lock_bh(&txq->lock);
1120
1121 if (!test_bit(txq_id, trans_pcie->queue_used)) {
1122 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
1123 txq_id, ssn);
1124 goto out;
1125 }
1126
1127 if (read_ptr == tfd_num)
1128 goto out;
1129
1130 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1131 txq_id, txq->read_ptr, tfd_num, ssn);
1132
1133 /*Since we free until index _not_ inclusive, the one before index is
1134 * the last we will free. This one must be used */
1135 last_to_free = iwl_queue_dec_wrap(trans, tfd_num);
1136
1137 if (!iwl_queue_used(txq, last_to_free)) {
1138 IWL_ERR(trans,
1139 "%s: Read index for txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
1140 __func__, txq_id, last_to_free,
1141 trans->trans_cfg->base_params->max_tfd_queue_size,
1142 txq->write_ptr, txq->read_ptr);
1143 goto out;
1144 }
1145
1146 if (WARN_ON(!skb_queue_empty(skbs)))
1147 goto out;
1148
1149 for (;
1150 read_ptr != tfd_num;
1151 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr),
1152 read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr)) {
1153 struct sk_buff *skb = txq->entries[read_ptr].skb;
1154
1155 if (WARN_ON_ONCE(!skb))
1156 continue;
1157
1158 iwl_pcie_free_tso_page(trans_pcie, skb);
1159
1160 __skb_queue_tail(skbs, skb);
1161
1162 txq->entries[read_ptr].skb = NULL;
1163
1164 if (!trans->trans_cfg->use_tfh)
1165 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
1166
1167 iwl_pcie_txq_free_tfd(trans, txq);
1168 }
1169
1170 iwl_pcie_txq_progress(txq);
1171
1172 if (iwl_queue_space(trans, txq) > txq->low_mark &&
1173 test_bit(txq_id, trans_pcie->queue_stopped)) {
1174 struct sk_buff_head overflow_skbs;
1175
1176 __skb_queue_head_init(&overflow_skbs);
1177 skb_queue_splice_init(&txq->overflow_q, &overflow_skbs);
1178
1179 /*
1180 * We are going to transmit from the overflow queue.
1181 * Remember this state so that wait_for_txq_empty will know we
1182 * are adding more packets to the TFD queue. It cannot rely on
1183 * the state of &txq->overflow_q, as we just emptied it, but
1184 * haven't TXed the content yet.
1185 */
1186 txq->overflow_tx = true;
1187
1188 /*
1189 * This is tricky: we are in reclaim path which is non
1190 * re-entrant, so noone will try to take the access the
1191 * txq data from that path. We stopped tx, so we can't
1192 * have tx as well. Bottom line, we can unlock and re-lock
1193 * later.
1194 */
1195 spin_unlock_bh(&txq->lock);
1196
1197 while (!skb_queue_empty(&overflow_skbs)) {
1198 struct sk_buff *skb = __skb_dequeue(&overflow_skbs);
1199 struct iwl_device_cmd *dev_cmd_ptr;
1200
1201 dev_cmd_ptr = *(void **)((u8 *)skb->cb +
1202 trans_pcie->dev_cmd_offs);
1203
1204 /*
1205 * Note that we can very well be overflowing again.
1206 * In that case, iwl_queue_space will be small again
1207 * and we won't wake mac80211's queue.
1208 */
1209 iwl_trans_tx(trans, skb, dev_cmd_ptr, txq_id);
1210 }
1211
1212 if (iwl_queue_space(trans, txq) > txq->low_mark)
1213 iwl_wake_queue(trans, txq);
1214
1215 spin_lock_bh(&txq->lock);
1216 txq->overflow_tx = false;
1217 }
1218
1219out:
1220 spin_unlock_bh(&txq->lock);
1221}
1222
1223/* Set wr_ptr of specific device and txq */
1224void iwl_trans_pcie_set_q_ptrs(struct iwl_trans *trans, int txq_id, int ptr)
1225{
1226 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1227 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1228
1229 spin_lock_bh(&txq->lock);
1230
1231 txq->write_ptr = ptr;
1232 txq->read_ptr = txq->write_ptr;
1233
1234 spin_unlock_bh(&txq->lock);
1235}
1236
1237static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1238 const struct iwl_host_cmd *cmd)
1239{
1240 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1241 int ret;
1242
1243 lockdep_assert_held(&trans_pcie->reg_lock);
1244
1245 /* Make sure the NIC is still alive in the bus */
1246 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
1247 return -ENODEV;
1248
1249 /*
1250 * wake up the NIC to make sure that the firmware will see the host
1251 * command - we will let the NIC sleep once all the host commands
1252 * returned. This needs to be done only on NICs that have
1253 * apmg_wake_up_wa set.
1254 */
1255 if (trans->trans_cfg->base_params->apmg_wake_up_wa &&
1256 !trans_pcie->cmd_hold_nic_awake) {
1257 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1258 BIT(trans->trans_cfg->csr->flag_mac_access_req));
1259
1260 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1261 BIT(trans->trans_cfg->csr->flag_val_mac_access_en),
1262 (BIT(trans->trans_cfg->csr->flag_mac_clock_ready) |
1263 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1264 15000);
1265 if (ret < 0) {
1266 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1267 BIT(trans->trans_cfg->csr->flag_mac_access_req));
1268 IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1269 return -EIO;
1270 }
1271 trans_pcie->cmd_hold_nic_awake = true;
1272 }
1273
1274 return 0;
1275}
1276
1277/*
1278 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1279 *
1280 * When FW advances 'R' index, all entries between old and new 'R' index
1281 * need to be reclaimed. As result, some free space forms. If there is
1282 * enough free space (> low mark), wake the stack that feeds us.
1283 */
1284void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1285{
1286 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1287 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1288 unsigned long flags;
1289 int nfreed = 0;
1290 u16 r;
1291
1292 lockdep_assert_held(&txq->lock);
1293
1294 idx = iwl_pcie_get_cmd_index(txq, idx);
1295 r = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
1296
1297 if (idx >= trans->trans_cfg->base_params->max_tfd_queue_size ||
1298 (!iwl_queue_used(txq, idx))) {
1299 WARN_ONCE(test_bit(txq_id, trans_pcie->queue_used),
1300 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1301 __func__, txq_id, idx,
1302 trans->trans_cfg->base_params->max_tfd_queue_size,
1303 txq->write_ptr, txq->read_ptr);
1304 return;
1305 }
1306
1307 for (idx = iwl_queue_inc_wrap(trans, idx); r != idx;
1308 r = iwl_queue_inc_wrap(trans, r)) {
1309 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr);
1310
1311 if (nfreed++ > 0) {
1312 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1313 idx, txq->write_ptr, r);
1314 iwl_force_nmi(trans);
1315 }
1316 }
1317
1318 if (txq->read_ptr == txq->write_ptr) {
1319 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1320 iwl_pcie_clear_cmd_in_flight(trans);
1321 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1322 }
1323
1324 iwl_pcie_txq_progress(txq);
1325}
1326
1327static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1328 u16 txq_id)
1329{
1330 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1331 u32 tbl_dw_addr;
1332 u32 tbl_dw;
1333 u16 scd_q2ratid;
1334
1335 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1336
1337 tbl_dw_addr = trans_pcie->scd_base_addr +
1338 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1339
1340 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1341
1342 if (txq_id & 0x1)
1343 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1344 else
1345 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1346
1347 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1348
1349 return 0;
1350}
1351
1352/* Receiver address (actually, Rx station's index into station table),
1353 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1354#define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1355
1356bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1357 const struct iwl_trans_txq_scd_cfg *cfg,
1358 unsigned int wdg_timeout)
1359{
1360 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1361 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1362 int fifo = -1;
1363 bool scd_bug = false;
1364
1365 if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1366 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1367
1368 txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1369
1370 if (cfg) {
1371 fifo = cfg->fifo;
1372
1373 /* Disable the scheduler prior configuring the cmd queue */
1374 if (txq_id == trans_pcie->cmd_queue &&
1375 trans_pcie->scd_set_active)
1376 iwl_scd_enable_set_active(trans, 0);
1377
1378 /* Stop this Tx queue before configuring it */
1379 iwl_scd_txq_set_inactive(trans, txq_id);
1380
1381 /* Set this queue as a chain-building queue unless it is CMD */
1382 if (txq_id != trans_pcie->cmd_queue)
1383 iwl_scd_txq_set_chain(trans, txq_id);
1384
1385 if (cfg->aggregate) {
1386 u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1387
1388 /* Map receiver-address / traffic-ID to this queue */
1389 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1390
1391 /* enable aggregations for the queue */
1392 iwl_scd_txq_enable_agg(trans, txq_id);
1393 txq->ampdu = true;
1394 } else {
1395 /*
1396 * disable aggregations for the queue, this will also
1397 * make the ra_tid mapping configuration irrelevant
1398 * since it is now a non-AGG queue.
1399 */
1400 iwl_scd_txq_disable_agg(trans, txq_id);
1401
1402 ssn = txq->read_ptr;
1403 }
1404 } else {
1405 /*
1406 * If we need to move the SCD write pointer by steps of
1407 * 0x40, 0x80 or 0xc0, it gets stuck. Avoids this and let
1408 * the op_mode know by returning true later.
1409 * Do this only in case cfg is NULL since this trick can
1410 * be done only if we have DQA enabled which is true for mvm
1411 * only. And mvm never sets a cfg pointer.
1412 * This is really ugly, but this is the easiest way out for
1413 * this sad hardware issue.
1414 * This bug has been fixed on devices 9000 and up.
1415 */
1416 scd_bug = !trans->trans_cfg->mq_rx_supported &&
1417 !((ssn - txq->write_ptr) & 0x3f) &&
1418 (ssn != txq->write_ptr);
1419 if (scd_bug)
1420 ssn++;
1421 }
1422
1423 /* Place first TFD at index corresponding to start sequence number.
1424 * Assumes that ssn_idx is valid (!= 0xFFF) */
1425 txq->read_ptr = (ssn & 0xff);
1426 txq->write_ptr = (ssn & 0xff);
1427 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1428 (ssn & 0xff) | (txq_id << 8));
1429
1430 if (cfg) {
1431 u8 frame_limit = cfg->frame_limit;
1432
1433 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1434
1435 /* Set up Tx window size and frame limit for this queue */
1436 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1437 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1438 iwl_trans_write_mem32(trans,
1439 trans_pcie->scd_base_addr +
1440 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1441 SCD_QUEUE_CTX_REG2_VAL(WIN_SIZE, frame_limit) |
1442 SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit));
1443
1444 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1445 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1446 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1447 (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1448 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1449 SCD_QUEUE_STTS_REG_MSK);
1450
1451 /* enable the scheduler for this queue (only) */
1452 if (txq_id == trans_pcie->cmd_queue &&
1453 trans_pcie->scd_set_active)
1454 iwl_scd_enable_set_active(trans, BIT(txq_id));
1455
1456 IWL_DEBUG_TX_QUEUES(trans,
1457 "Activate queue %d on FIFO %d WrPtr: %d\n",
1458 txq_id, fifo, ssn & 0xff);
1459 } else {
1460 IWL_DEBUG_TX_QUEUES(trans,
1461 "Activate queue %d WrPtr: %d\n",
1462 txq_id, ssn & 0xff);
1463 }
1464
1465 return scd_bug;
1466}
1467
1468void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
1469 bool shared_mode)
1470{
1471 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1472 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1473
1474 txq->ampdu = !shared_mode;
1475}
1476
1477void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1478 bool configure_scd)
1479{
1480 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1481 u32 stts_addr = trans_pcie->scd_base_addr +
1482 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1483 static const u32 zero_val[4] = {};
1484
1485 trans_pcie->txq[txq_id]->frozen_expiry_remainder = 0;
1486 trans_pcie->txq[txq_id]->frozen = false;
1487
1488 /*
1489 * Upon HW Rfkill - we stop the device, and then stop the queues
1490 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1491 * allow the op_mode to call txq_disable after it already called
1492 * stop_device.
1493 */
1494 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1495 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1496 "queue %d not used", txq_id);
1497 return;
1498 }
1499
1500 if (configure_scd) {
1501 iwl_scd_txq_set_inactive(trans, txq_id);
1502
1503 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1504 ARRAY_SIZE(zero_val));
1505 }
1506
1507 iwl_pcie_txq_unmap(trans, txq_id);
1508 trans_pcie->txq[txq_id]->ampdu = false;
1509
1510 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1511}
1512
1513/*************** HOST COMMAND QUEUE FUNCTIONS *****/
1514
1515/*
1516 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1517 * @priv: device private data point
1518 * @cmd: a pointer to the ucode command structure
1519 *
1520 * The function returns < 0 values to indicate the operation
1521 * failed. On success, it returns the index (>= 0) of command in the
1522 * command queue.
1523 */
1524static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1525 struct iwl_host_cmd *cmd)
1526{
1527 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1528 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1529 struct iwl_device_cmd *out_cmd;
1530 struct iwl_cmd_meta *out_meta;
1531 unsigned long flags;
1532 void *dup_buf = NULL;
1533 dma_addr_t phys_addr;
1534 int idx;
1535 u16 copy_size, cmd_size, tb0_size;
1536 bool had_nocopy = false;
1537 u8 group_id = iwl_cmd_groupid(cmd->id);
1538 int i, ret;
1539 u32 cmd_pos;
1540 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1541 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1542
1543 if (WARN(!trans->wide_cmd_header &&
1544 group_id > IWL_ALWAYS_LONG_GROUP,
1545 "unsupported wide command %#x\n", cmd->id))
1546 return -EINVAL;
1547
1548 if (group_id != 0) {
1549 copy_size = sizeof(struct iwl_cmd_header_wide);
1550 cmd_size = sizeof(struct iwl_cmd_header_wide);
1551 } else {
1552 copy_size = sizeof(struct iwl_cmd_header);
1553 cmd_size = sizeof(struct iwl_cmd_header);
1554 }
1555
1556 /* need one for the header if the first is NOCOPY */
1557 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1558
1559 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1560 cmddata[i] = cmd->data[i];
1561 cmdlen[i] = cmd->len[i];
1562
1563 if (!cmd->len[i])
1564 continue;
1565
1566 /* need at least IWL_FIRST_TB_SIZE copied */
1567 if (copy_size < IWL_FIRST_TB_SIZE) {
1568 int copy = IWL_FIRST_TB_SIZE - copy_size;
1569
1570 if (copy > cmdlen[i])
1571 copy = cmdlen[i];
1572 cmdlen[i] -= copy;
1573 cmddata[i] += copy;
1574 copy_size += copy;
1575 }
1576
1577 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1578 had_nocopy = true;
1579 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1580 idx = -EINVAL;
1581 goto free_dup_buf;
1582 }
1583 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1584 /*
1585 * This is also a chunk that isn't copied
1586 * to the static buffer so set had_nocopy.
1587 */
1588 had_nocopy = true;
1589
1590 /* only allowed once */
1591 if (WARN_ON(dup_buf)) {
1592 idx = -EINVAL;
1593 goto free_dup_buf;
1594 }
1595
1596 dup_buf = kmemdup(cmddata[i], cmdlen[i],
1597 GFP_ATOMIC);
1598 if (!dup_buf)
1599 return -ENOMEM;
1600 } else {
1601 /* NOCOPY must not be followed by normal! */
1602 if (WARN_ON(had_nocopy)) {
1603 idx = -EINVAL;
1604 goto free_dup_buf;
1605 }
1606 copy_size += cmdlen[i];
1607 }
1608 cmd_size += cmd->len[i];
1609 }
1610
1611 /*
1612 * If any of the command structures end up being larger than
1613 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1614 * allocated into separate TFDs, then we will need to
1615 * increase the size of the buffers.
1616 */
1617 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1618 "Command %s (%#x) is too large (%d bytes)\n",
1619 iwl_get_cmd_string(trans, cmd->id),
1620 cmd->id, copy_size)) {
1621 idx = -EINVAL;
1622 goto free_dup_buf;
1623 }
1624
1625 spin_lock_bh(&txq->lock);
1626
1627 if (iwl_queue_space(trans, txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1628 spin_unlock_bh(&txq->lock);
1629
1630 IWL_ERR(trans, "No space in command queue\n");
1631 iwl_op_mode_cmd_queue_full(trans->op_mode);
1632 idx = -ENOSPC;
1633 goto free_dup_buf;
1634 }
1635
1636 idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
1637 out_cmd = txq->entries[idx].cmd;
1638 out_meta = &txq->entries[idx].meta;
1639
1640 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1641 if (cmd->flags & CMD_WANT_SKB)
1642 out_meta->source = cmd;
1643
1644 /* set up the header */
1645 if (group_id != 0) {
1646 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
1647 out_cmd->hdr_wide.group_id = group_id;
1648 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
1649 out_cmd->hdr_wide.length =
1650 cpu_to_le16(cmd_size -
1651 sizeof(struct iwl_cmd_header_wide));
1652 out_cmd->hdr_wide.reserved = 0;
1653 out_cmd->hdr_wide.sequence =
1654 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1655 INDEX_TO_SEQ(txq->write_ptr));
1656
1657 cmd_pos = sizeof(struct iwl_cmd_header_wide);
1658 copy_size = sizeof(struct iwl_cmd_header_wide);
1659 } else {
1660 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id);
1661 out_cmd->hdr.sequence =
1662 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1663 INDEX_TO_SEQ(txq->write_ptr));
1664 out_cmd->hdr.group_id = 0;
1665
1666 cmd_pos = sizeof(struct iwl_cmd_header);
1667 copy_size = sizeof(struct iwl_cmd_header);
1668 }
1669
1670 /* and copy the data that needs to be copied */
1671 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1672 int copy;
1673
1674 if (!cmd->len[i])
1675 continue;
1676
1677 /* copy everything if not nocopy/dup */
1678 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1679 IWL_HCMD_DFL_DUP))) {
1680 copy = cmd->len[i];
1681
1682 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1683 cmd_pos += copy;
1684 copy_size += copy;
1685 continue;
1686 }
1687
1688 /*
1689 * Otherwise we need at least IWL_FIRST_TB_SIZE copied
1690 * in total (for bi-directional DMA), but copy up to what
1691 * we can fit into the payload for debug dump purposes.
1692 */
1693 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1694
1695 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1696 cmd_pos += copy;
1697
1698 /* However, treat copy_size the proper way, we need it below */
1699 if (copy_size < IWL_FIRST_TB_SIZE) {
1700 copy = IWL_FIRST_TB_SIZE - copy_size;
1701
1702 if (copy > cmd->len[i])
1703 copy = cmd->len[i];
1704 copy_size += copy;
1705 }
1706 }
1707
1708 IWL_DEBUG_HC(trans,
1709 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1710 iwl_get_cmd_string(trans, cmd->id),
1711 group_id, out_cmd->hdr.cmd,
1712 le16_to_cpu(out_cmd->hdr.sequence),
1713 cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue);
1714
1715 /* start the TFD with the minimum copy bytes */
1716 tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE);
1717 memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size);
1718 iwl_pcie_txq_build_tfd(trans, txq,
1719 iwl_pcie_get_first_tb_dma(txq, idx),
1720 tb0_size, true);
1721
1722 /* map first command fragment, if any remains */
1723 if (copy_size > tb0_size) {
1724 phys_addr = dma_map_single(trans->dev,
1725 ((u8 *)&out_cmd->hdr) + tb0_size,
1726 copy_size - tb0_size,
1727 DMA_TO_DEVICE);
1728 if (dma_mapping_error(trans->dev, phys_addr)) {
1729 iwl_pcie_tfd_unmap(trans, out_meta, txq,
1730 txq->write_ptr);
1731 idx = -ENOMEM;
1732 goto out;
1733 }
1734
1735 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1736 copy_size - tb0_size, false);
1737 }
1738
1739 /* map the remaining (adjusted) nocopy/dup fragments */
1740 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1741 const void *data = cmddata[i];
1742
1743 if (!cmdlen[i])
1744 continue;
1745 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1746 IWL_HCMD_DFL_DUP)))
1747 continue;
1748 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1749 data = dup_buf;
1750 phys_addr = dma_map_single(trans->dev, (void *)data,
1751 cmdlen[i], DMA_TO_DEVICE);
1752 if (dma_mapping_error(trans->dev, phys_addr)) {
1753 iwl_pcie_tfd_unmap(trans, out_meta, txq,
1754 txq->write_ptr);
1755 idx = -ENOMEM;
1756 goto out;
1757 }
1758
1759 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1760 }
1761
1762 BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE);
1763 out_meta->flags = cmd->flags;
1764 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1765 kzfree(txq->entries[idx].free_buf);
1766 txq->entries[idx].free_buf = dup_buf;
1767
1768 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
1769
1770 /* start timer if queue currently empty */
1771 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
1772 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1773
1774 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1775 ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1776 if (ret < 0) {
1777 idx = ret;
1778 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1779 goto out;
1780 }
1781
1782 /* Increment and update queue's write index */
1783 txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr);
1784 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1785
1786 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1787
1788 out:
1789 spin_unlock_bh(&txq->lock);
1790 free_dup_buf:
1791 if (idx < 0)
1792 kfree(dup_buf);
1793 return idx;
1794}
1795
1796/*
1797 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1798 * @rxb: Rx buffer to reclaim
1799 */
1800void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1801 struct iwl_rx_cmd_buffer *rxb)
1802{
1803 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1804 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1805 u8 group_id;
1806 u32 cmd_id;
1807 int txq_id = SEQ_TO_QUEUE(sequence);
1808 int index = SEQ_TO_INDEX(sequence);
1809 int cmd_index;
1810 struct iwl_device_cmd *cmd;
1811 struct iwl_cmd_meta *meta;
1812 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1813 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1814
1815 /* If a Tx command is being handled and it isn't in the actual
1816 * command queue then there a command routing bug has been introduced
1817 * in the queue management code. */
1818 if (WARN(txq_id != trans_pcie->cmd_queue,
1819 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1820 txq_id, trans_pcie->cmd_queue, sequence, txq->read_ptr,
1821 txq->write_ptr)) {
1822 iwl_print_hex_error(trans, pkt, 32);
1823 return;
1824 }
1825
1826 spin_lock_bh(&txq->lock);
1827
1828 cmd_index = iwl_pcie_get_cmd_index(txq, index);
1829 cmd = txq->entries[cmd_index].cmd;
1830 meta = &txq->entries[cmd_index].meta;
1831 group_id = cmd->hdr.group_id;
1832 cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0);
1833
1834 iwl_pcie_tfd_unmap(trans, meta, txq, index);
1835
1836 /* Input error checking is done when commands are added to queue. */
1837 if (meta->flags & CMD_WANT_SKB) {
1838 struct page *p = rxb_steal_page(rxb);
1839
1840 meta->source->resp_pkt = pkt;
1841 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1842 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1843 }
1844
1845 if (meta->flags & CMD_WANT_ASYNC_CALLBACK)
1846 iwl_op_mode_async_cb(trans->op_mode, cmd);
1847
1848 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1849
1850 if (!(meta->flags & CMD_ASYNC)) {
1851 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1852 IWL_WARN(trans,
1853 "HCMD_ACTIVE already clear for command %s\n",
1854 iwl_get_cmd_string(trans, cmd_id));
1855 }
1856 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1857 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1858 iwl_get_cmd_string(trans, cmd_id));
1859 wake_up(&trans_pcie->wait_command_queue);
1860 }
1861
1862 meta->flags = 0;
1863
1864 spin_unlock_bh(&txq->lock);
1865}
1866
1867#define HOST_COMPLETE_TIMEOUT (2 * HZ)
1868
1869static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1870 struct iwl_host_cmd *cmd)
1871{
1872 int ret;
1873
1874 /* An asynchronous command can not expect an SKB to be set. */
1875 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1876 return -EINVAL;
1877
1878 ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1879 if (ret < 0) {
1880 IWL_ERR(trans,
1881 "Error sending %s: enqueue_hcmd failed: %d\n",
1882 iwl_get_cmd_string(trans, cmd->id), ret);
1883 return ret;
1884 }
1885 return 0;
1886}
1887
1888static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1889 struct iwl_host_cmd *cmd)
1890{
1891 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1892 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1893 int cmd_idx;
1894 int ret;
1895
1896 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1897 iwl_get_cmd_string(trans, cmd->id));
1898
1899 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1900 &trans->status),
1901 "Command %s: a command is already active!\n",
1902 iwl_get_cmd_string(trans, cmd->id)))
1903 return -EIO;
1904
1905 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1906 iwl_get_cmd_string(trans, cmd->id));
1907
1908 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1909 if (cmd_idx < 0) {
1910 ret = cmd_idx;
1911 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1912 IWL_ERR(trans,
1913 "Error sending %s: enqueue_hcmd failed: %d\n",
1914 iwl_get_cmd_string(trans, cmd->id), ret);
1915 return ret;
1916 }
1917
1918 ret = wait_event_timeout(trans_pcie->wait_command_queue,
1919 !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1920 &trans->status),
1921 HOST_COMPLETE_TIMEOUT);
1922 if (!ret) {
1923 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1924 iwl_get_cmd_string(trans, cmd->id),
1925 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1926
1927 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1928 txq->read_ptr, txq->write_ptr);
1929
1930 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1931 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1932 iwl_get_cmd_string(trans, cmd->id));
1933 ret = -ETIMEDOUT;
1934
1935 iwl_trans_pcie_sync_nmi(trans);
1936 goto cancel;
1937 }
1938
1939 if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1940 iwl_trans_pcie_dump_regs(trans);
1941 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1942 iwl_get_cmd_string(trans, cmd->id));
1943 dump_stack();
1944 ret = -EIO;
1945 goto cancel;
1946 }
1947
1948 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1949 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
1950 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1951 ret = -ERFKILL;
1952 goto cancel;
1953 }
1954
1955 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1956 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1957 iwl_get_cmd_string(trans, cmd->id));
1958 ret = -EIO;
1959 goto cancel;
1960 }
1961
1962 return 0;
1963
1964cancel:
1965 if (cmd->flags & CMD_WANT_SKB) {
1966 /*
1967 * Cancel the CMD_WANT_SKB flag for the cmd in the
1968 * TX cmd queue. Otherwise in case the cmd comes
1969 * in later, it will possibly set an invalid
1970 * address (cmd->meta.source).
1971 */
1972 txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1973 }
1974
1975 if (cmd->resp_pkt) {
1976 iwl_free_resp(cmd);
1977 cmd->resp_pkt = NULL;
1978 }
1979
1980 return ret;
1981}
1982
1983int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1984{
1985 /* Make sure the NIC is still alive in the bus */
1986 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
1987 return -ENODEV;
1988
1989 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1990 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
1991 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1992 cmd->id);
1993 return -ERFKILL;
1994 }
1995
1996 if (cmd->flags & CMD_ASYNC)
1997 return iwl_pcie_send_hcmd_async(trans, cmd);
1998
1999 /* We still can fail on RFKILL that can be asserted while we wait */
2000 return iwl_pcie_send_hcmd_sync(trans, cmd);
2001}
2002
2003static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb,
2004 struct iwl_txq *txq, u8 hdr_len,
2005 struct iwl_cmd_meta *out_meta)
2006{
2007 u16 head_tb_len;
2008 int i;
2009
2010 /*
2011 * Set up TFD's third entry to point directly to remainder
2012 * of skb's head, if any
2013 */
2014 head_tb_len = skb_headlen(skb) - hdr_len;
2015
2016 if (head_tb_len > 0) {
2017 dma_addr_t tb_phys = dma_map_single(trans->dev,
2018 skb->data + hdr_len,
2019 head_tb_len, DMA_TO_DEVICE);
2020 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
2021 return -EINVAL;
2022 trace_iwlwifi_dev_tx_tb(trans->dev, skb,
2023 skb->data + hdr_len,
2024 head_tb_len);
2025 iwl_pcie_txq_build_tfd(trans, txq, tb_phys, head_tb_len, false);
2026 }
2027
2028 /* set up the remaining entries to point to the data */
2029 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2030 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2031 dma_addr_t tb_phys;
2032 int tb_idx;
2033
2034 if (!skb_frag_size(frag))
2035 continue;
2036
2037 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
2038 skb_frag_size(frag), DMA_TO_DEVICE);
2039
2040 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
2041 return -EINVAL;
2042 trace_iwlwifi_dev_tx_tb(trans->dev, skb,
2043 skb_frag_address(frag),
2044 skb_frag_size(frag));
2045 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2046 skb_frag_size(frag), false);
2047 if (tb_idx < 0)
2048 return tb_idx;
2049
2050 out_meta->tbs |= BIT(tb_idx);
2051 }
2052
2053 return 0;
2054}
2055
2056#ifdef CONFIG_INET
2057struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len)
2058{
2059 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2060 struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page);
2061
2062 if (!p->page)
2063 goto alloc;
2064
2065 /* enough room on this page */
2066 if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE)
2067 return p;
2068
2069 /* We don't have enough room on this page, get a new one. */
2070 __free_page(p->page);
2071
2072alloc:
2073 p->page = alloc_page(GFP_ATOMIC);
2074 if (!p->page)
2075 return NULL;
2076 p->pos = page_address(p->page);
2077 return p;
2078}
2079
2080static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph,
2081 bool ipv6, unsigned int len)
2082{
2083 if (ipv6) {
2084 struct ipv6hdr *iphv6 = iph;
2085
2086 tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr,
2087 len + tcph->doff * 4,
2088 IPPROTO_TCP, 0);
2089 } else {
2090 struct iphdr *iphv4 = iph;
2091
2092 ip_send_check(iphv4);
2093 tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr,
2094 len + tcph->doff * 4,
2095 IPPROTO_TCP, 0);
2096 }
2097}
2098
2099static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2100 struct iwl_txq *txq, u8 hdr_len,
2101 struct iwl_cmd_meta *out_meta,
2102 struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2103{
2104 struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload;
2105 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
2106 struct ieee80211_hdr *hdr = (void *)skb->data;
2107 unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room;
2108 unsigned int mss = skb_shinfo(skb)->gso_size;
2109 u16 length, iv_len, amsdu_pad;
2110 u8 *start_hdr;
2111 struct iwl_tso_hdr_page *hdr_page;
2112 struct page **page_ptr;
2113 struct tso_t tso;
2114
2115 /* if the packet is protected, then it must be CCMP or GCMP */
2116 BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN);
2117 iv_len = ieee80211_has_protected(hdr->frame_control) ?
2118 IEEE80211_CCMP_HDR_LEN : 0;
2119
2120 trace_iwlwifi_dev_tx(trans->dev, skb,
2121 iwl_pcie_get_tfd(trans, txq, txq->write_ptr),
2122 trans_pcie->tfd_size,
2123 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 0);
2124
2125 ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb);
2126 snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb);
2127 total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len;
2128 amsdu_pad = 0;
2129
2130 /* total amount of header we may need for this A-MSDU */
2131 hdr_room = DIV_ROUND_UP(total_len, mss) *
2132 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len;
2133
2134 /* Our device supports 9 segments at most, it will fit in 1 page */
2135 hdr_page = get_page_hdr(trans, hdr_room);
2136 if (!hdr_page)
2137 return -ENOMEM;
2138
2139 get_page(hdr_page->page);
2140 start_hdr = hdr_page->pos;
2141 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
2142 *page_ptr = hdr_page->page;
2143 memcpy(hdr_page->pos, skb->data + hdr_len, iv_len);
2144 hdr_page->pos += iv_len;
2145
2146 /*
2147 * Pull the ieee80211 header + IV to be able to use TSO core,
2148 * we will restore it for the tx_status flow.
2149 */
2150 skb_pull(skb, hdr_len + iv_len);
2151
2152 /*
2153 * Remove the length of all the headers that we don't actually
2154 * have in the MPDU by themselves, but that we duplicate into
2155 * all the different MSDUs inside the A-MSDU.
2156 */
2157 le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen);
2158
2159 tso_start(skb, &tso);
2160
2161 while (total_len) {
2162 /* this is the data left for this subframe */
2163 unsigned int data_left =
2164 min_t(unsigned int, mss, total_len);
2165 struct sk_buff *csum_skb = NULL;
2166 unsigned int hdr_tb_len;
2167 dma_addr_t hdr_tb_phys;
2168 struct tcphdr *tcph;
2169 u8 *iph, *subf_hdrs_start = hdr_page->pos;
2170
2171 total_len -= data_left;
2172
2173 memset(hdr_page->pos, 0, amsdu_pad);
2174 hdr_page->pos += amsdu_pad;
2175 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen +
2176 data_left)) & 0x3;
2177 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr));
2178 hdr_page->pos += ETH_ALEN;
2179 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr));
2180 hdr_page->pos += ETH_ALEN;
2181
2182 length = snap_ip_tcp_hdrlen + data_left;
2183 *((__be16 *)hdr_page->pos) = cpu_to_be16(length);
2184 hdr_page->pos += sizeof(length);
2185
2186 /*
2187 * This will copy the SNAP as well which will be considered
2188 * as MAC header.
2189 */
2190 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len);
2191 iph = hdr_page->pos + 8;
2192 tcph = (void *)(iph + ip_hdrlen);
2193
2194 /* For testing on current hardware only */
2195 if (trans_pcie->sw_csum_tx) {
2196 csum_skb = alloc_skb(data_left + tcp_hdrlen(skb),
2197 GFP_ATOMIC);
2198 if (!csum_skb)
2199 return -ENOMEM;
2200
2201 iwl_compute_pseudo_hdr_csum(iph, tcph,
2202 skb->protocol ==
2203 htons(ETH_P_IPV6),
2204 data_left);
2205
2206 skb_put_data(csum_skb, tcph, tcp_hdrlen(skb));
2207 skb_reset_transport_header(csum_skb);
2208 csum_skb->csum_start =
2209 (unsigned char *)tcp_hdr(csum_skb) -
2210 csum_skb->head;
2211 }
2212
2213 hdr_page->pos += snap_ip_tcp_hdrlen;
2214
2215 hdr_tb_len = hdr_page->pos - start_hdr;
2216 hdr_tb_phys = dma_map_single(trans->dev, start_hdr,
2217 hdr_tb_len, DMA_TO_DEVICE);
2218 if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) {
2219 dev_kfree_skb(csum_skb);
2220 return -EINVAL;
2221 }
2222 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys,
2223 hdr_tb_len, false);
2224 trace_iwlwifi_dev_tx_tb(trans->dev, skb, start_hdr,
2225 hdr_tb_len);
2226 /* add this subframe's headers' length to the tx_cmd */
2227 le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start);
2228
2229 /* prepare the start_hdr for the next subframe */
2230 start_hdr = hdr_page->pos;
2231
2232 /* put the payload */
2233 while (data_left) {
2234 unsigned int size = min_t(unsigned int, tso.size,
2235 data_left);
2236 dma_addr_t tb_phys;
2237
2238 if (trans_pcie->sw_csum_tx)
2239 skb_put_data(csum_skb, tso.data, size);
2240
2241 tb_phys = dma_map_single(trans->dev, tso.data,
2242 size, DMA_TO_DEVICE);
2243 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
2244 dev_kfree_skb(csum_skb);
2245 return -EINVAL;
2246 }
2247
2248 iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2249 size, false);
2250 trace_iwlwifi_dev_tx_tb(trans->dev, skb, tso.data,
2251 size);
2252
2253 data_left -= size;
2254 tso_build_data(skb, &tso, size);
2255 }
2256
2257 /* For testing on early hardware only */
2258 if (trans_pcie->sw_csum_tx) {
2259 __wsum csum;
2260
2261 csum = skb_checksum(csum_skb,
2262 skb_checksum_start_offset(csum_skb),
2263 csum_skb->len -
2264 skb_checksum_start_offset(csum_skb),
2265 0);
2266 dev_kfree_skb(csum_skb);
2267 dma_sync_single_for_cpu(trans->dev, hdr_tb_phys,
2268 hdr_tb_len, DMA_TO_DEVICE);
2269 tcph->check = csum_fold(csum);
2270 dma_sync_single_for_device(trans->dev, hdr_tb_phys,
2271 hdr_tb_len, DMA_TO_DEVICE);
2272 }
2273 }
2274
2275 /* re -add the WiFi header and IV */
2276 skb_push(skb, hdr_len + iv_len);
2277
2278 return 0;
2279}
2280#else /* CONFIG_INET */
2281static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2282 struct iwl_txq *txq, u8 hdr_len,
2283 struct iwl_cmd_meta *out_meta,
2284 struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2285{
2286 /* No A-MSDU without CONFIG_INET */
2287 WARN_ON(1);
2288
2289 return -1;
2290}
2291#endif /* CONFIG_INET */
2292
2293int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
2294 struct iwl_device_cmd *dev_cmd, int txq_id)
2295{
2296 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2297 struct ieee80211_hdr *hdr;
2298 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
2299 struct iwl_cmd_meta *out_meta;
2300 struct iwl_txq *txq;
2301 dma_addr_t tb0_phys, tb1_phys, scratch_phys;
2302 void *tb1_addr;
2303 void *tfd;
2304 u16 len, tb1_len;
2305 bool wait_write_ptr;
2306 __le16 fc;
2307 u8 hdr_len;
2308 u16 wifi_seq;
2309 bool amsdu;
2310
2311 txq = trans_pcie->txq[txq_id];
2312
2313 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
2314 "TX on unused queue %d\n", txq_id))
2315 return -EINVAL;
2316
2317 if (unlikely(trans_pcie->sw_csum_tx &&
2318 skb->ip_summed == CHECKSUM_PARTIAL)) {
2319 int offs = skb_checksum_start_offset(skb);
2320 int csum_offs = offs + skb->csum_offset;
2321 __wsum csum;
2322
2323 if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16)))
2324 return -1;
2325
2326 csum = skb_checksum(skb, offs, skb->len - offs, 0);
2327 *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum);
2328
2329 skb->ip_summed = CHECKSUM_UNNECESSARY;
2330 }
2331
2332 if (skb_is_nonlinear(skb) &&
2333 skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) &&
2334 __skb_linearize(skb))
2335 return -ENOMEM;
2336
2337 /* mac80211 always puts the full header into the SKB's head,
2338 * so there's no need to check if it's readable there
2339 */
2340 hdr = (struct ieee80211_hdr *)skb->data;
2341 fc = hdr->frame_control;
2342 hdr_len = ieee80211_hdrlen(fc);
2343
2344 spin_lock(&txq->lock);
2345
2346 if (iwl_queue_space(trans, txq) < txq->high_mark) {
2347 iwl_stop_queue(trans, txq);
2348
2349 /* don't put the packet on the ring, if there is no room */
2350 if (unlikely(iwl_queue_space(trans, txq) < 3)) {
2351 struct iwl_device_cmd **dev_cmd_ptr;
2352
2353 dev_cmd_ptr = (void *)((u8 *)skb->cb +
2354 trans_pcie->dev_cmd_offs);
2355
2356 *dev_cmd_ptr = dev_cmd;
2357 __skb_queue_tail(&txq->overflow_q, skb);
2358
2359 spin_unlock(&txq->lock);
2360 return 0;
2361 }
2362 }
2363
2364 /* In AGG mode, the index in the ring must correspond to the WiFi
2365 * sequence number. This is a HW requirements to help the SCD to parse
2366 * the BA.
2367 * Check here that the packets are in the right place on the ring.
2368 */
2369 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
2370 WARN_ONCE(txq->ampdu &&
2371 (wifi_seq & 0xff) != txq->write_ptr,
2372 "Q: %d WiFi Seq %d tfdNum %d",
2373 txq_id, wifi_seq, txq->write_ptr);
2374
2375 /* Set up driver data for this TFD */
2376 txq->entries[txq->write_ptr].skb = skb;
2377 txq->entries[txq->write_ptr].cmd = dev_cmd;
2378
2379 dev_cmd->hdr.sequence =
2380 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
2381 INDEX_TO_SEQ(txq->write_ptr)));
2382
2383 tb0_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr);
2384 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
2385 offsetof(struct iwl_tx_cmd, scratch);
2386
2387 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
2388 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
2389
2390 /* Set up first empty entry in queue's array of Tx/cmd buffers */
2391 out_meta = &txq->entries[txq->write_ptr].meta;
2392 out_meta->flags = 0;
2393
2394 /*
2395 * The second TB (tb1) points to the remainder of the TX command
2396 * and the 802.11 header - dword aligned size
2397 * (This calculation modifies the TX command, so do it before the
2398 * setup of the first TB)
2399 */
2400 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
2401 hdr_len - IWL_FIRST_TB_SIZE;
2402 /* do not align A-MSDU to dword as the subframe header aligns it */
2403 amsdu = ieee80211_is_data_qos(fc) &&
2404 (*ieee80211_get_qos_ctl(hdr) &
2405 IEEE80211_QOS_CTL_A_MSDU_PRESENT);
2406 if (trans_pcie->sw_csum_tx || !amsdu) {
2407 tb1_len = ALIGN(len, 4);
2408 /* Tell NIC about any 2-byte padding after MAC header */
2409 if (tb1_len != len)
2410 tx_cmd->tx_flags |= cpu_to_le32(TX_CMD_FLG_MH_PAD);
2411 } else {
2412 tb1_len = len;
2413 }
2414
2415 /*
2416 * The first TB points to bi-directional DMA data, we'll
2417 * memcpy the data into it later.
2418 */
2419 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
2420 IWL_FIRST_TB_SIZE, true);
2421
2422 /* there must be data left over for TB1 or this code must be changed */
2423 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE);
2424
2425 /* map the data for TB1 */
2426 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
2427 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
2428 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
2429 goto out_err;
2430 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
2431
2432 trace_iwlwifi_dev_tx(trans->dev, skb,
2433 iwl_pcie_get_tfd(trans, txq,
2434 txq->write_ptr),
2435 trans_pcie->tfd_size,
2436 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len,
2437 hdr_len);
2438
2439 /*
2440 * If gso_size wasn't set, don't give the frame "amsdu treatment"
2441 * (adding subframes, etc.).
2442 * This can happen in some testing flows when the amsdu was already
2443 * pre-built, and we just need to send the resulting skb.
2444 */
2445 if (amsdu && skb_shinfo(skb)->gso_size) {
2446 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len,
2447 out_meta, dev_cmd,
2448 tb1_len)))
2449 goto out_err;
2450 } else {
2451 struct sk_buff *frag;
2452
2453 if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len,
2454 out_meta)))
2455 goto out_err;
2456
2457 skb_walk_frags(skb, frag) {
2458 if (unlikely(iwl_fill_data_tbs(trans, frag, txq, 0,
2459 out_meta)))
2460 goto out_err;
2461 }
2462 }
2463
2464 /* building the A-MSDU might have changed this data, so memcpy it now */
2465 memcpy(&txq->first_tb_bufs[txq->write_ptr], dev_cmd, IWL_FIRST_TB_SIZE);
2466
2467 tfd = iwl_pcie_get_tfd(trans, txq, txq->write_ptr);
2468 /* Set up entry for this TFD in Tx byte-count array */
2469 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len),
2470 iwl_pcie_tfd_get_num_tbs(trans, tfd));
2471
2472 wait_write_ptr = ieee80211_has_morefrags(fc);
2473
2474 /* start timer if queue currently empty */
2475 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) {
2476 /*
2477 * If the TXQ is active, then set the timer, if not,
2478 * set the timer in remainder so that the timer will
2479 * be armed with the right value when the station will
2480 * wake up.
2481 */
2482 if (!txq->frozen)
2483 mod_timer(&txq->stuck_timer,
2484 jiffies + txq->wd_timeout);
2485 else
2486 txq->frozen_expiry_remainder = txq->wd_timeout;
2487 }
2488
2489 /* Tell device the write index *just past* this latest filled TFD */
2490 txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr);
2491 if (!wait_write_ptr)
2492 iwl_pcie_txq_inc_wr_ptr(trans, txq);
2493
2494 /*
2495 * At this point the frame is "transmitted" successfully
2496 * and we will get a TX status notification eventually.
2497 */
2498 spin_unlock(&txq->lock);
2499 return 0;
2500out_err:
2501 iwl_pcie_tfd_unmap(trans, out_meta, txq, txq->write_ptr);
2502 spin_unlock(&txq->lock);
2503 return -1;
2504}