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1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * Copyright (C) 2003-2014, 2018-2022 Intel Corporation
4 * Copyright (C) 2015-2016 Intel Deutschland GmbH
5 */
6#include <linux/delay.h>
7#include <linux/device.h>
8#include <linux/export.h>
9
10#include "iwl-drv.h"
11#include "iwl-io.h"
12#include "iwl-csr.h"
13#include "iwl-debug.h"
14#include "iwl-prph.h"
15#include "iwl-fh.h"
16
17void iwl_write8(struct iwl_trans *trans, u32 ofs, u8 val)
18{
19 trace_iwlwifi_dev_iowrite8(trans->dev, ofs, val);
20 iwl_trans_write8(trans, ofs, val);
21}
22IWL_EXPORT_SYMBOL(iwl_write8);
23
24void iwl_write32(struct iwl_trans *trans, u32 ofs, u32 val)
25{
26 trace_iwlwifi_dev_iowrite32(trans->dev, ofs, val);
27 iwl_trans_write32(trans, ofs, val);
28}
29IWL_EXPORT_SYMBOL(iwl_write32);
30
31void iwl_write64(struct iwl_trans *trans, u64 ofs, u64 val)
32{
33 trace_iwlwifi_dev_iowrite64(trans->dev, ofs, val);
34 iwl_trans_write32(trans, ofs, lower_32_bits(val));
35 iwl_trans_write32(trans, ofs + 4, upper_32_bits(val));
36}
37IWL_EXPORT_SYMBOL(iwl_write64);
38
39u32 iwl_read32(struct iwl_trans *trans, u32 ofs)
40{
41 u32 val = iwl_trans_read32(trans, ofs);
42
43 trace_iwlwifi_dev_ioread32(trans->dev, ofs, val);
44 return val;
45}
46IWL_EXPORT_SYMBOL(iwl_read32);
47
48#define IWL_POLL_INTERVAL 10 /* microseconds */
49
50int iwl_poll_bit(struct iwl_trans *trans, u32 addr,
51 u32 bits, u32 mask, int timeout)
52{
53 int t = 0;
54
55 do {
56 if ((iwl_read32(trans, addr) & mask) == (bits & mask))
57 return t;
58 udelay(IWL_POLL_INTERVAL);
59 t += IWL_POLL_INTERVAL;
60 } while (t < timeout);
61
62 return -ETIMEDOUT;
63}
64IWL_EXPORT_SYMBOL(iwl_poll_bit);
65
66u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
67{
68 if (iwl_trans_grab_nic_access(trans)) {
69 u32 value = iwl_read32(trans, reg);
70
71 iwl_trans_release_nic_access(trans);
72 return value;
73 }
74
75 /* return as if we have a HW timeout/failure */
76 return 0x5a5a5a5a;
77}
78IWL_EXPORT_SYMBOL(iwl_read_direct32);
79
80void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)
81{
82 if (iwl_trans_grab_nic_access(trans)) {
83 iwl_write32(trans, reg, value);
84 iwl_trans_release_nic_access(trans);
85 }
86}
87IWL_EXPORT_SYMBOL(iwl_write_direct32);
88
89void iwl_write_direct64(struct iwl_trans *trans, u64 reg, u64 value)
90{
91 if (iwl_trans_grab_nic_access(trans)) {
92 iwl_write64(trans, reg, value);
93 iwl_trans_release_nic_access(trans);
94 }
95}
96IWL_EXPORT_SYMBOL(iwl_write_direct64);
97
98int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
99 int timeout)
100{
101 int t = 0;
102
103 do {
104 if ((iwl_read_direct32(trans, addr) & mask) == mask)
105 return t;
106 udelay(IWL_POLL_INTERVAL);
107 t += IWL_POLL_INTERVAL;
108 } while (t < timeout);
109
110 return -ETIMEDOUT;
111}
112IWL_EXPORT_SYMBOL(iwl_poll_direct_bit);
113
114u32 iwl_read_prph_no_grab(struct iwl_trans *trans, u32 ofs)
115{
116 u32 val = iwl_trans_read_prph(trans, ofs);
117 trace_iwlwifi_dev_ioread_prph32(trans->dev, ofs, val);
118 return val;
119}
120IWL_EXPORT_SYMBOL(iwl_read_prph_no_grab);
121
122void iwl_write_prph_no_grab(struct iwl_trans *trans, u32 ofs, u32 val)
123{
124 trace_iwlwifi_dev_iowrite_prph32(trans->dev, ofs, val);
125 iwl_trans_write_prph(trans, ofs, val);
126}
127IWL_EXPORT_SYMBOL(iwl_write_prph_no_grab);
128
129void iwl_write_prph64_no_grab(struct iwl_trans *trans, u64 ofs, u64 val)
130{
131 trace_iwlwifi_dev_iowrite_prph64(trans->dev, ofs, val);
132 iwl_write_prph_no_grab(trans, ofs, val & 0xffffffff);
133 iwl_write_prph_no_grab(trans, ofs + 4, val >> 32);
134}
135IWL_EXPORT_SYMBOL(iwl_write_prph64_no_grab);
136
137u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs)
138{
139 if (iwl_trans_grab_nic_access(trans)) {
140 u32 val = iwl_read_prph_no_grab(trans, ofs);
141
142 iwl_trans_release_nic_access(trans);
143
144 return val;
145 }
146
147 /* return as if we have a HW timeout/failure */
148 return 0x5a5a5a5a;
149}
150IWL_EXPORT_SYMBOL(iwl_read_prph);
151
152void iwl_write_prph_delay(struct iwl_trans *trans, u32 ofs, u32 val, u32 delay_ms)
153{
154 if (iwl_trans_grab_nic_access(trans)) {
155 mdelay(delay_ms);
156 iwl_write_prph_no_grab(trans, ofs, val);
157 iwl_trans_release_nic_access(trans);
158 }
159}
160IWL_EXPORT_SYMBOL(iwl_write_prph_delay);
161
162int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr,
163 u32 bits, u32 mask, int timeout)
164{
165 int t = 0;
166
167 do {
168 if ((iwl_read_prph(trans, addr) & mask) == (bits & mask))
169 return t;
170 udelay(IWL_POLL_INTERVAL);
171 t += IWL_POLL_INTERVAL;
172 } while (t < timeout);
173
174 return -ETIMEDOUT;
175}
176
177void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
178{
179 if (iwl_trans_grab_nic_access(trans)) {
180 iwl_write_prph_no_grab(trans, ofs,
181 iwl_read_prph_no_grab(trans, ofs) |
182 mask);
183 iwl_trans_release_nic_access(trans);
184 }
185}
186IWL_EXPORT_SYMBOL(iwl_set_bits_prph);
187
188void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,
189 u32 bits, u32 mask)
190{
191 if (iwl_trans_grab_nic_access(trans)) {
192 iwl_write_prph_no_grab(trans, ofs,
193 (iwl_read_prph_no_grab(trans, ofs) &
194 mask) | bits);
195 iwl_trans_release_nic_access(trans);
196 }
197}
198IWL_EXPORT_SYMBOL(iwl_set_bits_mask_prph);
199
200void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
201{
202 u32 val;
203
204 if (iwl_trans_grab_nic_access(trans)) {
205 val = iwl_read_prph_no_grab(trans, ofs);
206 iwl_write_prph_no_grab(trans, ofs, (val & ~mask));
207 iwl_trans_release_nic_access(trans);
208 }
209}
210IWL_EXPORT_SYMBOL(iwl_clear_bits_prph);
211
212void iwl_force_nmi(struct iwl_trans *trans)
213{
214 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_9000)
215 iwl_write_prph_delay(trans, DEVICE_SET_NMI_REG,
216 DEVICE_SET_NMI_VAL_DRV, 1);
217 else if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
218 iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,
219 UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER);
220 else if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_BZ)
221 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
222 UREG_DOORBELL_TO_ISR6_NMI_BIT);
223 else
224 iwl_write32(trans, CSR_DOORBELL_VECTOR,
225 UREG_DOORBELL_TO_ISR6_NMI_BIT);
226}
227IWL_EXPORT_SYMBOL(iwl_force_nmi);
228
229static const char *get_rfh_string(int cmd)
230{
231#define IWL_CMD(x) case x: return #x
232#define IWL_CMD_MQ(arg, reg, q) { if (arg == reg(q)) return #reg; }
233
234 int i;
235
236 for (i = 0; i < IWL_MAX_RX_HW_QUEUES; i++) {
237 IWL_CMD_MQ(cmd, RFH_Q_FRBDCB_BA_LSB, i);
238 IWL_CMD_MQ(cmd, RFH_Q_FRBDCB_WIDX, i);
239 IWL_CMD_MQ(cmd, RFH_Q_FRBDCB_RIDX, i);
240 IWL_CMD_MQ(cmd, RFH_Q_URBD_STTS_WPTR_LSB, i);
241 }
242
243 switch (cmd) {
244 IWL_CMD(RFH_RXF_DMA_CFG);
245 IWL_CMD(RFH_GEN_CFG);
246 IWL_CMD(RFH_GEN_STATUS);
247 IWL_CMD(FH_TSSR_TX_STATUS_REG);
248 IWL_CMD(FH_TSSR_TX_ERROR_REG);
249 default:
250 return "UNKNOWN";
251 }
252#undef IWL_CMD_MQ
253}
254
255struct reg {
256 u32 addr;
257 bool is64;
258};
259
260static int iwl_dump_rfh(struct iwl_trans *trans, char **buf)
261{
262 int i, q;
263 int num_q = trans->num_rx_queues;
264 static const u32 rfh_tbl[] = {
265 RFH_RXF_DMA_CFG,
266 RFH_GEN_CFG,
267 RFH_GEN_STATUS,
268 FH_TSSR_TX_STATUS_REG,
269 FH_TSSR_TX_ERROR_REG,
270 };
271 static const struct reg rfh_mq_tbl[] = {
272 { RFH_Q0_FRBDCB_BA_LSB, true },
273 { RFH_Q0_FRBDCB_WIDX, false },
274 { RFH_Q0_FRBDCB_RIDX, false },
275 { RFH_Q0_URBD_STTS_WPTR_LSB, true },
276 };
277
278#ifdef CONFIG_IWLWIFI_DEBUGFS
279 if (buf) {
280 int pos = 0;
281 /*
282 * Register (up to 34 for name + 8 blank/q for MQ): 40 chars
283 * Colon + space: 2 characters
284 * 0X%08x: 10 characters
285 * New line: 1 character
286 * Total of 53 characters
287 */
288 size_t bufsz = ARRAY_SIZE(rfh_tbl) * 53 +
289 ARRAY_SIZE(rfh_mq_tbl) * 53 * num_q + 40;
290
291 *buf = kmalloc(bufsz, GFP_KERNEL);
292 if (!*buf)
293 return -ENOMEM;
294
295 pos += scnprintf(*buf + pos, bufsz - pos,
296 "RFH register values:\n");
297
298 for (i = 0; i < ARRAY_SIZE(rfh_tbl); i++)
299 pos += scnprintf(*buf + pos, bufsz - pos,
300 "%40s: 0X%08x\n",
301 get_rfh_string(rfh_tbl[i]),
302 iwl_read_prph(trans, rfh_tbl[i]));
303
304 for (i = 0; i < ARRAY_SIZE(rfh_mq_tbl); i++)
305 for (q = 0; q < num_q; q++) {
306 u32 addr = rfh_mq_tbl[i].addr;
307
308 addr += q * (rfh_mq_tbl[i].is64 ? 8 : 4);
309 pos += scnprintf(*buf + pos, bufsz - pos,
310 "%34s(q %2d): 0X%08x\n",
311 get_rfh_string(addr), q,
312 iwl_read_prph(trans, addr));
313 }
314
315 return pos;
316 }
317#endif
318
319 IWL_ERR(trans, "RFH register values:\n");
320 for (i = 0; i < ARRAY_SIZE(rfh_tbl); i++)
321 IWL_ERR(trans, " %34s: 0X%08x\n",
322 get_rfh_string(rfh_tbl[i]),
323 iwl_read_prph(trans, rfh_tbl[i]));
324
325 for (i = 0; i < ARRAY_SIZE(rfh_mq_tbl); i++)
326 for (q = 0; q < num_q; q++) {
327 u32 addr = rfh_mq_tbl[i].addr;
328
329 addr += q * (rfh_mq_tbl[i].is64 ? 8 : 4);
330 IWL_ERR(trans, " %34s(q %d): 0X%08x\n",
331 get_rfh_string(addr), q,
332 iwl_read_prph(trans, addr));
333 }
334
335 return 0;
336}
337
338static const char *get_fh_string(int cmd)
339{
340 switch (cmd) {
341 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
342 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
343 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
344 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
345 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
346 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
347 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
348 IWL_CMD(FH_TSSR_TX_STATUS_REG);
349 IWL_CMD(FH_TSSR_TX_ERROR_REG);
350 default:
351 return "UNKNOWN";
352 }
353#undef IWL_CMD
354}
355
356int iwl_dump_fh(struct iwl_trans *trans, char **buf)
357{
358 int i;
359 static const u32 fh_tbl[] = {
360 FH_RSCSR_CHNL0_STTS_WPTR_REG,
361 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
362 FH_RSCSR_CHNL0_WPTR,
363 FH_MEM_RCSR_CHNL0_CONFIG_REG,
364 FH_MEM_RSSR_SHARED_CTRL_REG,
365 FH_MEM_RSSR_RX_STATUS_REG,
366 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
367 FH_TSSR_TX_STATUS_REG,
368 FH_TSSR_TX_ERROR_REG
369 };
370
371 if (trans->trans_cfg->mq_rx_supported)
372 return iwl_dump_rfh(trans, buf);
373
374#ifdef CONFIG_IWLWIFI_DEBUGFS
375 if (buf) {
376 int pos = 0;
377 size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
378
379 *buf = kmalloc(bufsz, GFP_KERNEL);
380 if (!*buf)
381 return -ENOMEM;
382
383 pos += scnprintf(*buf + pos, bufsz - pos,
384 "FH register values:\n");
385
386 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
387 pos += scnprintf(*buf + pos, bufsz - pos,
388 " %34s: 0X%08x\n",
389 get_fh_string(fh_tbl[i]),
390 iwl_read_direct32(trans, fh_tbl[i]));
391
392 return pos;
393 }
394#endif
395
396 IWL_ERR(trans, "FH register values:\n");
397 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
398 IWL_ERR(trans, " %34s: 0X%08x\n",
399 get_fh_string(fh_tbl[i]),
400 iwl_read_direct32(trans, fh_tbl[i]));
401
402 return 0;
403}
404
405#define IWL_HOST_MON_BLOCK_PEMON 0x00
406#define IWL_HOST_MON_BLOCK_HIPM 0x22
407
408#define IWL_HOST_MON_BLOCK_PEMON_VEC0 0x00
409#define IWL_HOST_MON_BLOCK_PEMON_VEC1 0x01
410#define IWL_HOST_MON_BLOCK_PEMON_WFPM 0x06
411
412static void iwl_dump_host_monitor_block(struct iwl_trans *trans,
413 u32 block, u32 vec, u32 iter)
414{
415 int i;
416
417 IWL_ERR(trans, "Host monitor block 0x%x vector 0x%x\n", block, vec);
418 iwl_write32(trans, CSR_MONITOR_CFG_REG, (block << 8) | vec);
419 for (i = 0; i < iter; i++)
420 IWL_ERR(trans, " value [iter %d]: 0x%08x\n",
421 i, iwl_read32(trans, CSR_MONITOR_STATUS_REG));
422}
423
424static void iwl_dump_host_monitor(struct iwl_trans *trans)
425{
426 switch (trans->trans_cfg->device_family) {
427 case IWL_DEVICE_FAMILY_22000:
428 case IWL_DEVICE_FAMILY_AX210:
429 IWL_ERR(trans, "CSR_RESET = 0x%x\n",
430 iwl_read32(trans, CSR_RESET));
431 iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON,
432 IWL_HOST_MON_BLOCK_PEMON_VEC0, 15);
433 iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON,
434 IWL_HOST_MON_BLOCK_PEMON_VEC1, 15);
435 iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON,
436 IWL_HOST_MON_BLOCK_PEMON_WFPM, 15);
437 iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_HIPM,
438 IWL_HOST_MON_BLOCK_PEMON_VEC0, 1);
439 break;
440 default:
441 /* not supported yet */
442 return;
443 }
444}
445
446int iwl_finish_nic_init(struct iwl_trans *trans)
447{
448 const struct iwl_cfg_trans_params *cfg_trans = trans->trans_cfg;
449 u32 poll_ready;
450 int err;
451
452 if (cfg_trans->bisr_workaround) {
453 /* ensure the TOP FSM isn't still in previous reset */
454 mdelay(2);
455 }
456
457 /*
458 * Set "initialization complete" bit to move adapter from
459 * D0U* --> D0A* (powered-up active) state.
460 */
461 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_BZ) {
462 iwl_set_bit(trans, CSR_GP_CNTRL,
463 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
464 CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
465 poll_ready = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;
466 } else {
467 iwl_set_bit(trans, CSR_GP_CNTRL,
468 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
469 poll_ready = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY;
470 }
471
472 if (cfg_trans->device_family == IWL_DEVICE_FAMILY_8000)
473 udelay(2);
474
475 /*
476 * Wait for clock stabilization; once stabilized, access to
477 * device-internal resources is supported, e.g. iwl_write_prph()
478 * and accesses to uCode SRAM.
479 */
480 err = iwl_poll_bit(trans, CSR_GP_CNTRL, poll_ready, poll_ready, 25000);
481 if (err < 0) {
482 IWL_DEBUG_INFO(trans, "Failed to wake NIC\n");
483
484 iwl_dump_host_monitor(trans);
485 }
486
487 if (cfg_trans->bisr_workaround) {
488 /* ensure BISR shift has finished */
489 udelay(200);
490 }
491
492 return err < 0 ? err : 0;
493}
494IWL_EXPORT_SYMBOL(iwl_finish_nic_init);
495
496void iwl_trans_sync_nmi_with_addr(struct iwl_trans *trans, u32 inta_addr,
497 u32 sw_err_bit)
498{
499 unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT;
500 bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status);
501
502 /* if the interrupts were already disabled, there is no point in
503 * calling iwl_disable_interrupts
504 */
505 if (interrupts_enabled)
506 iwl_trans_interrupts(trans, false);
507
508 iwl_force_nmi(trans);
509 while (time_after(timeout, jiffies)) {
510 u32 inta_hw = iwl_read32(trans, inta_addr);
511
512 /* Error detected by uCode */
513 if (inta_hw & sw_err_bit) {
514 /* Clear causes register */
515 iwl_write32(trans, inta_addr, inta_hw & sw_err_bit);
516 break;
517 }
518
519 mdelay(1);
520 }
521
522 /* enable interrupts only if there were already enabled before this
523 * function to avoid a case were the driver enable interrupts before
524 * proper configurations were made
525 */
526 if (interrupts_enabled)
527 iwl_trans_interrupts(trans, true);
528
529 iwl_trans_fw_error(trans, false);
530}
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2015 - 2016 Intel Deutschland GmbH
10 * Copyright(C) 2018 - 2019 Intel Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called COPYING.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <linuxwifi@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 * BSD LICENSE
29 *
30 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
31 * Copyright(c) 2015 - 2016 Intel Deutschland GmbH
32 * Copyright (C) 2018 - 2019 Intel Corporation
33 * All rights reserved.
34 *
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
37 * are met:
38 *
39 * * Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * * Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in
43 * the documentation and/or other materials provided with the
44 * distribution.
45 * * Neither the name Intel Corporation nor the names of its
46 * contributors may be used to endorse or promote products derived
47 * from this software without specific prior written permission.
48 *
49 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
50 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
51 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
52 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
53 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
55 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
59 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
60 *
61 *****************************************************************************/
62#include <linux/delay.h>
63#include <linux/device.h>
64#include <linux/export.h>
65
66#include "iwl-drv.h"
67#include "iwl-io.h"
68#include "iwl-csr.h"
69#include "iwl-debug.h"
70#include "iwl-prph.h"
71#include "iwl-fh.h"
72
73const struct iwl_csr_params iwl_csr_v1 = {
74 .flag_mac_clock_ready = 0,
75 .flag_val_mac_access_en = 0,
76 .flag_init_done = 2,
77 .flag_mac_access_req = 3,
78 .flag_sw_reset = 7,
79 .flag_master_dis = 8,
80 .flag_stop_master = 9,
81 .addr_sw_reset = CSR_BASE + 0x020,
82 .mac_addr0_otp = 0x380,
83 .mac_addr1_otp = 0x384,
84 .mac_addr0_strap = 0x388,
85 .mac_addr1_strap = 0x38C
86};
87
88const struct iwl_csr_params iwl_csr_v2 = {
89 .flag_init_done = 6,
90 .flag_mac_clock_ready = 20,
91 .flag_val_mac_access_en = 20,
92 .flag_mac_access_req = 21,
93 .flag_master_dis = 28,
94 .flag_stop_master = 29,
95 .flag_sw_reset = 31,
96 .addr_sw_reset = CSR_BASE + 0x024,
97 .mac_addr0_otp = 0x30,
98 .mac_addr1_otp = 0x34,
99 .mac_addr0_strap = 0x38,
100 .mac_addr1_strap = 0x3C
101};
102
103void iwl_write8(struct iwl_trans *trans, u32 ofs, u8 val)
104{
105 trace_iwlwifi_dev_iowrite8(trans->dev, ofs, val);
106 iwl_trans_write8(trans, ofs, val);
107}
108IWL_EXPORT_SYMBOL(iwl_write8);
109
110void iwl_write32(struct iwl_trans *trans, u32 ofs, u32 val)
111{
112 trace_iwlwifi_dev_iowrite32(trans->dev, ofs, val);
113 iwl_trans_write32(trans, ofs, val);
114}
115IWL_EXPORT_SYMBOL(iwl_write32);
116
117void iwl_write64(struct iwl_trans *trans, u64 ofs, u64 val)
118{
119 trace_iwlwifi_dev_iowrite64(trans->dev, ofs, val);
120 iwl_trans_write32(trans, ofs, lower_32_bits(val));
121 iwl_trans_write32(trans, ofs + 4, upper_32_bits(val));
122}
123IWL_EXPORT_SYMBOL(iwl_write64);
124
125u32 iwl_read32(struct iwl_trans *trans, u32 ofs)
126{
127 u32 val = iwl_trans_read32(trans, ofs);
128
129 trace_iwlwifi_dev_ioread32(trans->dev, ofs, val);
130 return val;
131}
132IWL_EXPORT_SYMBOL(iwl_read32);
133
134#define IWL_POLL_INTERVAL 10 /* microseconds */
135
136int iwl_poll_bit(struct iwl_trans *trans, u32 addr,
137 u32 bits, u32 mask, int timeout)
138{
139 int t = 0;
140
141 do {
142 if ((iwl_read32(trans, addr) & mask) == (bits & mask))
143 return t;
144 udelay(IWL_POLL_INTERVAL);
145 t += IWL_POLL_INTERVAL;
146 } while (t < timeout);
147
148 return -ETIMEDOUT;
149}
150IWL_EXPORT_SYMBOL(iwl_poll_bit);
151
152u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
153{
154 u32 value = 0x5a5a5a5a;
155 unsigned long flags;
156 if (iwl_trans_grab_nic_access(trans, &flags)) {
157 value = iwl_read32(trans, reg);
158 iwl_trans_release_nic_access(trans, &flags);
159 }
160
161 return value;
162}
163IWL_EXPORT_SYMBOL(iwl_read_direct32);
164
165void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)
166{
167 unsigned long flags;
168
169 if (iwl_trans_grab_nic_access(trans, &flags)) {
170 iwl_write32(trans, reg, value);
171 iwl_trans_release_nic_access(trans, &flags);
172 }
173}
174IWL_EXPORT_SYMBOL(iwl_write_direct32);
175
176void iwl_write_direct64(struct iwl_trans *trans, u64 reg, u64 value)
177{
178 unsigned long flags;
179
180 if (iwl_trans_grab_nic_access(trans, &flags)) {
181 iwl_write64(trans, reg, value);
182 iwl_trans_release_nic_access(trans, &flags);
183 }
184}
185IWL_EXPORT_SYMBOL(iwl_write_direct64);
186
187int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
188 int timeout)
189{
190 int t = 0;
191
192 do {
193 if ((iwl_read_direct32(trans, addr) & mask) == mask)
194 return t;
195 udelay(IWL_POLL_INTERVAL);
196 t += IWL_POLL_INTERVAL;
197 } while (t < timeout);
198
199 return -ETIMEDOUT;
200}
201IWL_EXPORT_SYMBOL(iwl_poll_direct_bit);
202
203u32 iwl_read_prph_no_grab(struct iwl_trans *trans, u32 ofs)
204{
205 u32 val = iwl_trans_read_prph(trans, ofs);
206 trace_iwlwifi_dev_ioread_prph32(trans->dev, ofs, val);
207 return val;
208}
209IWL_EXPORT_SYMBOL(iwl_read_prph_no_grab);
210
211void iwl_write_prph_no_grab(struct iwl_trans *trans, u32 ofs, u32 val)
212{
213 trace_iwlwifi_dev_iowrite_prph32(trans->dev, ofs, val);
214 iwl_trans_write_prph(trans, ofs, val);
215}
216IWL_EXPORT_SYMBOL(iwl_write_prph_no_grab);
217
218void iwl_write_prph64_no_grab(struct iwl_trans *trans, u64 ofs, u64 val)
219{
220 trace_iwlwifi_dev_iowrite_prph64(trans->dev, ofs, val);
221 iwl_write_prph_no_grab(trans, ofs, val & 0xffffffff);
222 iwl_write_prph_no_grab(trans, ofs + 4, val >> 32);
223}
224IWL_EXPORT_SYMBOL(iwl_write_prph64_no_grab);
225
226u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs)
227{
228 unsigned long flags;
229 u32 val = 0x5a5a5a5a;
230
231 if (iwl_trans_grab_nic_access(trans, &flags)) {
232 val = iwl_read_prph_no_grab(trans, ofs);
233 iwl_trans_release_nic_access(trans, &flags);
234 }
235 return val;
236}
237IWL_EXPORT_SYMBOL(iwl_read_prph);
238
239void iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val)
240{
241 unsigned long flags;
242
243 if (iwl_trans_grab_nic_access(trans, &flags)) {
244 iwl_write_prph_no_grab(trans, ofs, val);
245 iwl_trans_release_nic_access(trans, &flags);
246 }
247}
248IWL_EXPORT_SYMBOL(iwl_write_prph);
249
250int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr,
251 u32 bits, u32 mask, int timeout)
252{
253 int t = 0;
254
255 do {
256 if ((iwl_read_prph(trans, addr) & mask) == (bits & mask))
257 return t;
258 udelay(IWL_POLL_INTERVAL);
259 t += IWL_POLL_INTERVAL;
260 } while (t < timeout);
261
262 return -ETIMEDOUT;
263}
264
265void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
266{
267 unsigned long flags;
268
269 if (iwl_trans_grab_nic_access(trans, &flags)) {
270 iwl_write_prph_no_grab(trans, ofs,
271 iwl_read_prph_no_grab(trans, ofs) |
272 mask);
273 iwl_trans_release_nic_access(trans, &flags);
274 }
275}
276IWL_EXPORT_SYMBOL(iwl_set_bits_prph);
277
278void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,
279 u32 bits, u32 mask)
280{
281 unsigned long flags;
282
283 if (iwl_trans_grab_nic_access(trans, &flags)) {
284 iwl_write_prph_no_grab(trans, ofs,
285 (iwl_read_prph_no_grab(trans, ofs) &
286 mask) | bits);
287 iwl_trans_release_nic_access(trans, &flags);
288 }
289}
290IWL_EXPORT_SYMBOL(iwl_set_bits_mask_prph);
291
292void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
293{
294 unsigned long flags;
295 u32 val;
296
297 if (iwl_trans_grab_nic_access(trans, &flags)) {
298 val = iwl_read_prph_no_grab(trans, ofs);
299 iwl_write_prph_no_grab(trans, ofs, (val & ~mask));
300 iwl_trans_release_nic_access(trans, &flags);
301 }
302}
303IWL_EXPORT_SYMBOL(iwl_clear_bits_prph);
304
305void iwl_force_nmi(struct iwl_trans *trans)
306{
307 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_9000)
308 iwl_write_prph(trans, DEVICE_SET_NMI_REG,
309 DEVICE_SET_NMI_VAL_DRV);
310 else if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
311 iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,
312 UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER_MSK);
313 else
314 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
315 UREG_DOORBELL_TO_ISR6_NMI_BIT);
316}
317IWL_EXPORT_SYMBOL(iwl_force_nmi);
318
319static const char *get_rfh_string(int cmd)
320{
321#define IWL_CMD(x) case x: return #x
322#define IWL_CMD_MQ(arg, reg, q) { if (arg == reg(q)) return #reg; }
323
324 int i;
325
326 for (i = 0; i < IWL_MAX_RX_HW_QUEUES; i++) {
327 IWL_CMD_MQ(cmd, RFH_Q_FRBDCB_BA_LSB, i);
328 IWL_CMD_MQ(cmd, RFH_Q_FRBDCB_WIDX, i);
329 IWL_CMD_MQ(cmd, RFH_Q_FRBDCB_RIDX, i);
330 IWL_CMD_MQ(cmd, RFH_Q_URBD_STTS_WPTR_LSB, i);
331 }
332
333 switch (cmd) {
334 IWL_CMD(RFH_RXF_DMA_CFG);
335 IWL_CMD(RFH_GEN_CFG);
336 IWL_CMD(RFH_GEN_STATUS);
337 IWL_CMD(FH_TSSR_TX_STATUS_REG);
338 IWL_CMD(FH_TSSR_TX_ERROR_REG);
339 default:
340 return "UNKNOWN";
341 }
342#undef IWL_CMD_MQ
343}
344
345struct reg {
346 u32 addr;
347 bool is64;
348};
349
350static int iwl_dump_rfh(struct iwl_trans *trans, char **buf)
351{
352 int i, q;
353 int num_q = trans->num_rx_queues;
354 static const u32 rfh_tbl[] = {
355 RFH_RXF_DMA_CFG,
356 RFH_GEN_CFG,
357 RFH_GEN_STATUS,
358 FH_TSSR_TX_STATUS_REG,
359 FH_TSSR_TX_ERROR_REG,
360 };
361 static const struct reg rfh_mq_tbl[] = {
362 { RFH_Q0_FRBDCB_BA_LSB, true },
363 { RFH_Q0_FRBDCB_WIDX, false },
364 { RFH_Q0_FRBDCB_RIDX, false },
365 { RFH_Q0_URBD_STTS_WPTR_LSB, true },
366 };
367
368#ifdef CONFIG_IWLWIFI_DEBUGFS
369 if (buf) {
370 int pos = 0;
371 /*
372 * Register (up to 34 for name + 8 blank/q for MQ): 40 chars
373 * Colon + space: 2 characters
374 * 0X%08x: 10 characters
375 * New line: 1 character
376 * Total of 53 characters
377 */
378 size_t bufsz = ARRAY_SIZE(rfh_tbl) * 53 +
379 ARRAY_SIZE(rfh_mq_tbl) * 53 * num_q + 40;
380
381 *buf = kmalloc(bufsz, GFP_KERNEL);
382 if (!*buf)
383 return -ENOMEM;
384
385 pos += scnprintf(*buf + pos, bufsz - pos,
386 "RFH register values:\n");
387
388 for (i = 0; i < ARRAY_SIZE(rfh_tbl); i++)
389 pos += scnprintf(*buf + pos, bufsz - pos,
390 "%40s: 0X%08x\n",
391 get_rfh_string(rfh_tbl[i]),
392 iwl_read_prph(trans, rfh_tbl[i]));
393
394 for (i = 0; i < ARRAY_SIZE(rfh_mq_tbl); i++)
395 for (q = 0; q < num_q; q++) {
396 u32 addr = rfh_mq_tbl[i].addr;
397
398 addr += q * (rfh_mq_tbl[i].is64 ? 8 : 4);
399 pos += scnprintf(*buf + pos, bufsz - pos,
400 "%34s(q %2d): 0X%08x\n",
401 get_rfh_string(addr), q,
402 iwl_read_prph(trans, addr));
403 }
404
405 return pos;
406 }
407#endif
408
409 IWL_ERR(trans, "RFH register values:\n");
410 for (i = 0; i < ARRAY_SIZE(rfh_tbl); i++)
411 IWL_ERR(trans, " %34s: 0X%08x\n",
412 get_rfh_string(rfh_tbl[i]),
413 iwl_read_prph(trans, rfh_tbl[i]));
414
415 for (i = 0; i < ARRAY_SIZE(rfh_mq_tbl); i++)
416 for (q = 0; q < num_q; q++) {
417 u32 addr = rfh_mq_tbl[i].addr;
418
419 addr += q * (rfh_mq_tbl[i].is64 ? 8 : 4);
420 IWL_ERR(trans, " %34s(q %d): 0X%08x\n",
421 get_rfh_string(addr), q,
422 iwl_read_prph(trans, addr));
423 }
424
425 return 0;
426}
427
428static const char *get_fh_string(int cmd)
429{
430 switch (cmd) {
431 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
432 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
433 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
434 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
435 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
436 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
437 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
438 IWL_CMD(FH_TSSR_TX_STATUS_REG);
439 IWL_CMD(FH_TSSR_TX_ERROR_REG);
440 default:
441 return "UNKNOWN";
442 }
443#undef IWL_CMD
444}
445
446int iwl_dump_fh(struct iwl_trans *trans, char **buf)
447{
448 int i;
449 static const u32 fh_tbl[] = {
450 FH_RSCSR_CHNL0_STTS_WPTR_REG,
451 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
452 FH_RSCSR_CHNL0_WPTR,
453 FH_MEM_RCSR_CHNL0_CONFIG_REG,
454 FH_MEM_RSSR_SHARED_CTRL_REG,
455 FH_MEM_RSSR_RX_STATUS_REG,
456 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
457 FH_TSSR_TX_STATUS_REG,
458 FH_TSSR_TX_ERROR_REG
459 };
460
461 if (trans->trans_cfg->mq_rx_supported)
462 return iwl_dump_rfh(trans, buf);
463
464#ifdef CONFIG_IWLWIFI_DEBUGFS
465 if (buf) {
466 int pos = 0;
467 size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
468
469 *buf = kmalloc(bufsz, GFP_KERNEL);
470 if (!*buf)
471 return -ENOMEM;
472
473 pos += scnprintf(*buf + pos, bufsz - pos,
474 "FH register values:\n");
475
476 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
477 pos += scnprintf(*buf + pos, bufsz - pos,
478 " %34s: 0X%08x\n",
479 get_fh_string(fh_tbl[i]),
480 iwl_read_direct32(trans, fh_tbl[i]));
481
482 return pos;
483 }
484#endif
485
486 IWL_ERR(trans, "FH register values:\n");
487 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
488 IWL_ERR(trans, " %34s: 0X%08x\n",
489 get_fh_string(fh_tbl[i]),
490 iwl_read_direct32(trans, fh_tbl[i]));
491
492 return 0;
493}
494
495int iwl_finish_nic_init(struct iwl_trans *trans,
496 const struct iwl_cfg_trans_params *cfg_trans)
497{
498 int err;
499
500 if (cfg_trans->bisr_workaround) {
501 /* ensure the TOP FSM isn't still in previous reset */
502 mdelay(2);
503 }
504
505 /*
506 * Set "initialization complete" bit to move adapter from
507 * D0U* --> D0A* (powered-up active) state.
508 */
509 iwl_set_bit(trans, CSR_GP_CNTRL,
510 BIT(cfg_trans->csr->flag_init_done));
511
512 if (cfg_trans->device_family == IWL_DEVICE_FAMILY_8000)
513 udelay(2);
514
515 /*
516 * Wait for clock stabilization; once stabilized, access to
517 * device-internal resources is supported, e.g. iwl_write_prph()
518 * and accesses to uCode SRAM.
519 */
520 err = iwl_poll_bit(trans, CSR_GP_CNTRL,
521 BIT(cfg_trans->csr->flag_mac_clock_ready),
522 BIT(cfg_trans->csr->flag_mac_clock_ready),
523 25000);
524 if (err < 0)
525 IWL_DEBUG_INFO(trans, "Failed to wake NIC\n");
526
527 if (cfg_trans->bisr_workaround) {
528 /* ensure BISR shift has finished */
529 udelay(200);
530 }
531
532 return err < 0 ? err : 0;
533}
534IWL_EXPORT_SYMBOL(iwl_finish_nic_init);