1// SPDX-License-Identifier: GPL-2.0-only
    2/*
    3 *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
    4 */
    5
    6#include <linux/signal.h>
    7#include <linux/slab.h>
    8#include <linux/module.h>
    9#include <linux/netdevice.h>
   10#include <linux/etherdevice.h>
   11#include <linux/mii.h>
   12#include <linux/ethtool.h>
   13#include <linux/usb.h>
   14#include <linux/crc32.h>
   15#include <linux/if_vlan.h>
   16#include <linux/uaccess.h>
   17#include <linux/list.h>
   18#include <linux/ip.h>
   19#include <linux/ipv6.h>
   20#include <net/ip6_checksum.h>
   21#include <uapi/linux/mdio.h>
   22#include <linux/mdio.h>
   23#include <linux/usb/cdc.h>
   24#include <linux/suspend.h>
   25#include <linux/atomic.h>
   26#include <linux/acpi.h>
   27#include <linux/firmware.h>
   28#include <crypto/hash.h>
   29#include <linux/usb/r8152.h>
   30#include <net/gso.h>
   31
   32/* Information for net-next */
   33#define NETNEXT_VERSION		"12"
   34
   35/* Information for net */
   36#define NET_VERSION		"13"
   37
   38#define DRIVER_VERSION		"v1." NETNEXT_VERSION "." NET_VERSION
   39#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
   40#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
   41#define MODULENAME "r8152"
   42
   43#define R8152_PHY_ID		32
   44
   45#define PLA_IDR			0xc000
   46#define PLA_RCR			0xc010
   47#define PLA_RCR1		0xc012
   48#define PLA_RMS			0xc016
   49#define PLA_RXFIFO_CTRL0	0xc0a0
   50#define PLA_RXFIFO_FULL		0xc0a2
   51#define PLA_RXFIFO_CTRL1	0xc0a4
   52#define PLA_RX_FIFO_FULL	0xc0a6
   53#define PLA_RXFIFO_CTRL2	0xc0a8
   54#define PLA_RX_FIFO_EMPTY	0xc0aa
   55#define PLA_DMY_REG0		0xc0b0
   56#define PLA_FMC			0xc0b4
   57#define PLA_CFG_WOL		0xc0b6
   58#define PLA_TEREDO_CFG		0xc0bc
   59#define PLA_TEREDO_WAKE_BASE	0xc0c4
   60#define PLA_MAR			0xcd00
   61#define PLA_BACKUP		0xd000
   62#define PLA_BDC_CR		0xd1a0
   63#define PLA_TEREDO_TIMER	0xd2cc
   64#define PLA_REALWOW_TIMER	0xd2e8
   65#define PLA_UPHY_TIMER		0xd388
   66#define PLA_SUSPEND_FLAG	0xd38a
   67#define PLA_INDICATE_FALG	0xd38c
   68#define PLA_MACDBG_PRE		0xd38c	/* RTL_VER_04 only */
   69#define PLA_MACDBG_POST		0xd38e	/* RTL_VER_04 only */
   70#define PLA_EXTRA_STATUS	0xd398
   71#define PLA_GPHY_CTRL		0xd3ae
   72#define PLA_POL_GPIO_CTRL	0xdc6a
   73#define PLA_EFUSE_DATA		0xdd00
   74#define PLA_EFUSE_CMD		0xdd02
   75#define PLA_LEDSEL		0xdd90
   76#define PLA_LED_FEATURE		0xdd92
   77#define PLA_PHYAR		0xde00
   78#define PLA_BOOT_CTRL		0xe004
   79#define PLA_LWAKE_CTRL_REG	0xe007
   80#define PLA_GPHY_INTR_IMR	0xe022
   81#define PLA_EEE_CR		0xe040
   82#define PLA_EEE_TXTWSYS		0xe04c
   83#define PLA_EEE_TXTWSYS_2P5G	0xe058
   84#define PLA_EEEP_CR		0xe080
   85#define PLA_MAC_PWR_CTRL	0xe0c0
   86#define PLA_MAC_PWR_CTRL2	0xe0ca
   87#define PLA_MAC_PWR_CTRL3	0xe0cc
   88#define PLA_MAC_PWR_CTRL4	0xe0ce
   89#define PLA_WDT6_CTRL		0xe428
   90#define PLA_TCR0		0xe610
   91#define PLA_TCR1		0xe612
   92#define PLA_MTPS		0xe615
   93#define PLA_TXFIFO_CTRL		0xe618
   94#define PLA_TXFIFO_FULL		0xe61a
   95#define PLA_RSTTALLY		0xe800
   96#define PLA_CR			0xe813
   97#define PLA_CRWECR		0xe81c
   98#define PLA_CONFIG12		0xe81e	/* CONFIG1, CONFIG2 */
   99#define PLA_CONFIG34		0xe820	/* CONFIG3, CONFIG4 */
  100#define PLA_CONFIG5		0xe822
  101#define PLA_PHY_PWR		0xe84c
  102#define PLA_OOB_CTRL		0xe84f
  103#define PLA_CPCR		0xe854
  104#define PLA_MISC_0		0xe858
  105#define PLA_MISC_1		0xe85a
  106#define PLA_OCP_GPHY_BASE	0xe86c
  107#define PLA_TALLYCNT		0xe890
  108#define PLA_SFF_STS_7		0xe8de
  109#define PLA_PHYSTATUS		0xe908
  110#define PLA_CONFIG6		0xe90a /* CONFIG6 */
  111#define PLA_USB_CFG		0xe952
  112#define PLA_BP_BA		0xfc26
  113#define PLA_BP_0		0xfc28
  114#define PLA_BP_1		0xfc2a
  115#define PLA_BP_2		0xfc2c
  116#define PLA_BP_3		0xfc2e
  117#define PLA_BP_4		0xfc30
  118#define PLA_BP_5		0xfc32
  119#define PLA_BP_6		0xfc34
  120#define PLA_BP_7		0xfc36
  121#define PLA_BP_EN		0xfc38
  122
  123#define USB_USB2PHY		0xb41e
  124#define USB_SSPHYLINK1		0xb426
  125#define USB_SSPHYLINK2		0xb428
  126#define USB_L1_CTRL		0xb45e
  127#define USB_U2P3_CTRL		0xb460
  128#define USB_CSR_DUMMY1		0xb464
  129#define USB_CSR_DUMMY2		0xb466
  130#define USB_DEV_STAT		0xb808
  131#define USB_CONNECT_TIMER	0xcbf8
  132#define USB_MSC_TIMER		0xcbfc
  133#define USB_BURST_SIZE		0xcfc0
  134#define USB_FW_FIX_EN0		0xcfca
  135#define USB_FW_FIX_EN1		0xcfcc
  136#define USB_LPM_CONFIG		0xcfd8
  137#define USB_ECM_OPTION		0xcfee
  138#define USB_CSTMR		0xcfef	/* RTL8153A */
  139#define USB_MISC_2		0xcfff
  140#define USB_ECM_OP		0xd26b
  141#define USB_GPHY_CTRL		0xd284
  142#define USB_SPEED_OPTION	0xd32a
  143#define USB_FW_CTRL		0xd334	/* RTL8153B */
  144#define USB_FC_TIMER		0xd340
  145#define USB_USB_CTRL		0xd406
  146#define USB_PHY_CTRL		0xd408
  147#define USB_TX_AGG		0xd40a
  148#define USB_RX_BUF_TH		0xd40c
  149#define USB_USB_TIMER		0xd428
  150#define USB_RX_EARLY_TIMEOUT	0xd42c
  151#define USB_RX_EARLY_SIZE	0xd42e
  152#define USB_PM_CTRL_STATUS	0xd432	/* RTL8153A */
  153#define USB_RX_EXTRA_AGGR_TMR	0xd432	/* RTL8153B */
  154#define USB_TX_DMA		0xd434
  155#define USB_UPT_RXDMA_OWN	0xd437
  156#define USB_UPHY3_MDCMDIO	0xd480
  157#define USB_TOLERANCE		0xd490
  158#define USB_LPM_CTRL		0xd41a
  159#define USB_BMU_RESET		0xd4b0
  160#define USB_BMU_CONFIG		0xd4b4
  161#define USB_U1U2_TIMER		0xd4da
  162#define USB_FW_TASK		0xd4e8	/* RTL8153B */
  163#define USB_RX_AGGR_NUM		0xd4ee
  164#define USB_UPS_CTRL		0xd800
  165#define USB_POWER_CUT		0xd80a
  166#define USB_MISC_0		0xd81a
  167#define USB_MISC_1		0xd81f
  168#define USB_AFE_CTRL2		0xd824
  169#define USB_UPHY_XTAL		0xd826
  170#define USB_UPS_CFG		0xd842
  171#define USB_UPS_FLAGS		0xd848
  172#define USB_WDT1_CTRL		0xe404
  173#define USB_WDT11_CTRL		0xe43c
  174#define USB_BP_BA		PLA_BP_BA
  175#define USB_BP_0		PLA_BP_0
  176#define USB_BP_1		PLA_BP_1
  177#define USB_BP_2		PLA_BP_2
  178#define USB_BP_3		PLA_BP_3
  179#define USB_BP_4		PLA_BP_4
  180#define USB_BP_5		PLA_BP_5
  181#define USB_BP_6		PLA_BP_6
  182#define USB_BP_7		PLA_BP_7
  183#define USB_BP_EN		PLA_BP_EN	/* RTL8153A */
  184#define USB_BP_8		0xfc38		/* RTL8153B */
  185#define USB_BP_9		0xfc3a
  186#define USB_BP_10		0xfc3c
  187#define USB_BP_11		0xfc3e
  188#define USB_BP_12		0xfc40
  189#define USB_BP_13		0xfc42
  190#define USB_BP_14		0xfc44
  191#define USB_BP_15		0xfc46
  192#define USB_BP2_EN		0xfc48
  193
  194/* OCP Registers */
  195#define OCP_ALDPS_CONFIG	0x2010
  196#define OCP_EEE_CONFIG1		0x2080
  197#define OCP_EEE_CONFIG2		0x2092
  198#define OCP_EEE_CONFIG3		0x2094
  199#define OCP_BASE_MII		0xa400
  200#define OCP_EEE_AR		0xa41a
  201#define OCP_EEE_DATA		0xa41c
  202#define OCP_PHY_STATUS		0xa420
  203#define OCP_INTR_EN		0xa424
  204#define OCP_NCTL_CFG		0xa42c
  205#define OCP_POWER_CFG		0xa430
  206#define OCP_EEE_CFG		0xa432
  207#define OCP_SRAM_ADDR		0xa436
  208#define OCP_SRAM_DATA		0xa438
  209#define OCP_DOWN_SPEED		0xa442
  210#define OCP_EEE_ABLE		0xa5c4
  211#define OCP_EEE_ADV		0xa5d0
  212#define OCP_EEE_LPABLE		0xa5d2
  213#define OCP_10GBT_CTRL		0xa5d4
  214#define OCP_10GBT_STAT		0xa5d6
  215#define OCP_EEE_ADV2		0xa6d4
  216#define OCP_PHY_STATE		0xa708		/* nway state for 8153 */
  217#define OCP_PHY_PATCH_STAT	0xb800
  218#define OCP_PHY_PATCH_CMD	0xb820
  219#define OCP_PHY_LOCK		0xb82e
  220#define OCP_ADC_IOFFSET		0xbcfc
  221#define OCP_ADC_CFG		0xbc06
  222#define OCP_SYSCLK_CFG		0xc416
  223
  224/* SRAM Register */
  225#define SRAM_GREEN_CFG		0x8011
  226#define SRAM_LPF_CFG		0x8012
  227#define SRAM_GPHY_FW_VER	0x801e
  228#define SRAM_10M_AMP1		0x8080
  229#define SRAM_10M_AMP2		0x8082
  230#define SRAM_IMPEDANCE		0x8084
  231#define SRAM_PHY_LOCK		0xb82e
  232
  233/* PLA_RCR */
  234#define RCR_AAP			0x00000001
  235#define RCR_APM			0x00000002
  236#define RCR_AM			0x00000004
  237#define RCR_AB			0x00000008
  238#define RCR_ACPT_ALL		(RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  239#define SLOT_EN			BIT(11)
  240
  241/* PLA_RCR1 */
  242#define OUTER_VLAN		BIT(7)
  243#define INNER_VLAN		BIT(6)
  244
  245/* PLA_RXFIFO_CTRL0 */
  246#define RXFIFO_THR1_NORMAL	0x00080002
  247#define RXFIFO_THR1_OOB		0x01800003
  248
  249/* PLA_RXFIFO_FULL */
  250#define RXFIFO_FULL_MASK	0xfff
  251
  252/* PLA_RXFIFO_CTRL1 */
  253#define RXFIFO_THR2_FULL	0x00000060
  254#define RXFIFO_THR2_HIGH	0x00000038
  255#define RXFIFO_THR2_OOB		0x0000004a
  256#define RXFIFO_THR2_NORMAL	0x00a0
  257
  258/* PLA_RXFIFO_CTRL2 */
  259#define RXFIFO_THR3_FULL	0x00000078
  260#define RXFIFO_THR3_HIGH	0x00000048
  261#define RXFIFO_THR3_OOB		0x0000005a
  262#define RXFIFO_THR3_NORMAL	0x0110
  263
  264/* PLA_TXFIFO_CTRL */
  265#define TXFIFO_THR_NORMAL	0x00400008
  266#define TXFIFO_THR_NORMAL2	0x01000008
  267
  268/* PLA_DMY_REG0 */
  269#define ECM_ALDPS		0x0002
  270
  271/* PLA_FMC */
  272#define FMC_FCR_MCU_EN		0x0001
  273
  274/* PLA_EEEP_CR */
  275#define EEEP_CR_EEEP_TX		0x0002
  276
  277/* PLA_WDT6_CTRL */
  278#define WDT6_SET_MODE		0x0010
  279
  280/* PLA_TCR0 */
  281#define TCR0_TX_EMPTY		0x0800
  282#define TCR0_AUTO_FIFO		0x0080
  283
  284/* PLA_TCR1 */
  285#define VERSION_MASK		0x7cf0
  286#define IFG_MASK		(BIT(3) | BIT(9) | BIT(8))
  287#define IFG_144NS		BIT(9)
  288#define IFG_96NS		(BIT(9) | BIT(8))
  289
  290/* PLA_MTPS */
  291#define MTPS_JUMBO		(12 * 1024 / 64)
  292#define MTPS_DEFAULT		(6 * 1024 / 64)
  293
  294/* PLA_RSTTALLY */
  295#define TALLY_RESET		0x0001
  296
  297/* PLA_CR */
  298#define CR_RST			0x10
  299#define CR_RE			0x08
  300#define CR_TE			0x04
  301
  302/* PLA_CRWECR */
  303#define CRWECR_NORAML		0x00
  304#define CRWECR_CONFIG		0xc0
  305
  306/* PLA_OOB_CTRL */
  307#define NOW_IS_OOB		0x80
  308#define TXFIFO_EMPTY		0x20
  309#define RXFIFO_EMPTY		0x10
  310#define LINK_LIST_READY		0x02
  311#define DIS_MCU_CLROOB		0x01
  312#define FIFO_EMPTY		(TXFIFO_EMPTY | RXFIFO_EMPTY)
  313
  314/* PLA_MISC_1 */
  315#define RXDY_GATED_EN		0x0008
  316
  317/* PLA_SFF_STS_7 */
  318#define RE_INIT_LL		0x8000
  319#define MCU_BORW_EN		0x4000
  320
  321/* PLA_CPCR */
  322#define FLOW_CTRL_EN		BIT(0)
  323#define CPCR_RX_VLAN		0x0040
  324
  325/* PLA_CFG_WOL */
  326#define MAGIC_EN		0x0001
  327
  328/* PLA_TEREDO_CFG */
  329#define TEREDO_SEL		0x8000
  330#define TEREDO_WAKE_MASK	0x7f00
  331#define TEREDO_RS_EVENT_MASK	0x00fe
  332#define OOB_TEREDO_EN		0x0001
  333
  334/* PLA_BDC_CR */
  335#define ALDPS_PROXY_MODE	0x0001
  336
  337/* PLA_EFUSE_CMD */
  338#define EFUSE_READ_CMD		BIT(15)
  339#define EFUSE_DATA_BIT16	BIT(7)
  340
  341/* PLA_CONFIG34 */
  342#define LINK_ON_WAKE_EN		0x0010
  343#define LINK_OFF_WAKE_EN	0x0008
  344
  345/* PLA_CONFIG6 */
  346#define LANWAKE_CLR_EN		BIT(0)
  347
  348/* PLA_USB_CFG */
  349#define EN_XG_LIP		BIT(1)
  350#define EN_G_LIP		BIT(2)
  351
  352/* PLA_CONFIG5 */
  353#define BWF_EN			0x0040
  354#define MWF_EN			0x0020
  355#define UWF_EN			0x0010
  356#define LAN_WAKE_EN		0x0002
  357
  358/* PLA_LED_FEATURE */
  359#define LED_MODE_MASK		0x0700
  360
  361/* PLA_PHY_PWR */
  362#define TX_10M_IDLE_EN		0x0080
  363#define PFM_PWM_SWITCH		0x0040
  364#define TEST_IO_OFF		BIT(4)
  365
  366/* PLA_MAC_PWR_CTRL */
  367#define D3_CLK_GATED_EN		0x00004000
  368#define MCU_CLK_RATIO		0x07010f07
  369#define MCU_CLK_RATIO_MASK	0x0f0f0f0f
  370#define ALDPS_SPDWN_RATIO	0x0f87
  371
  372/* PLA_MAC_PWR_CTRL2 */
  373#define EEE_SPDWN_RATIO		0x8007
  374#define MAC_CLK_SPDWN_EN	BIT(15)
  375#define EEE_SPDWN_RATIO_MASK	0xff
  376
  377/* PLA_MAC_PWR_CTRL3 */
  378#define PLA_MCU_SPDWN_EN	BIT(14)
  379#define PKT_AVAIL_SPDWN_EN	0x0100
  380#define SUSPEND_SPDWN_EN	0x0004
  381#define U1U2_SPDWN_EN		0x0002
  382#define L1_SPDWN_EN		0x0001
  383
  384/* PLA_MAC_PWR_CTRL4 */
  385#define PWRSAVE_SPDWN_EN	0x1000
  386#define RXDV_SPDWN_EN		0x0800
  387#define TX10MIDLE_EN		0x0100
  388#define IDLE_SPDWN_EN		BIT(6)
  389#define TP100_SPDWN_EN		0x0020
  390#define TP500_SPDWN_EN		0x0010
  391#define TP1000_SPDWN_EN		0x0008
  392#define EEE_SPDWN_EN		0x0001
  393
  394/* PLA_GPHY_INTR_IMR */
  395#define GPHY_STS_MSK		0x0001
  396#define SPEED_DOWN_MSK		0x0002
  397#define SPDWN_RXDV_MSK		0x0004
  398#define SPDWN_LINKCHG_MSK	0x0008
  399
  400/* PLA_PHYAR */
  401#define PHYAR_FLAG		0x80000000
  402
  403/* PLA_EEE_CR */
  404#define EEE_RX_EN		0x0001
  405#define EEE_TX_EN		0x0002
  406
  407/* PLA_BOOT_CTRL */
  408#define AUTOLOAD_DONE		0x0002
  409
  410/* PLA_LWAKE_CTRL_REG */
  411#define LANWAKE_PIN		BIT(7)
  412
  413/* PLA_SUSPEND_FLAG */
  414#define LINK_CHG_EVENT		BIT(0)
  415
  416/* PLA_INDICATE_FALG */
  417#define UPCOMING_RUNTIME_D3	BIT(0)
  418
  419/* PLA_MACDBG_PRE and PLA_MACDBG_POST */
  420#define DEBUG_OE		BIT(0)
  421#define DEBUG_LTSSM		0x0082
  422
  423/* PLA_EXTRA_STATUS */
  424#define CUR_LINK_OK		BIT(15)
  425#define U3P3_CHECK_EN		BIT(7)	/* RTL_VER_05 only */
  426#define LINK_CHANGE_FLAG	BIT(8)
  427#define POLL_LINK_CHG		BIT(0)
  428
  429/* PLA_GPHY_CTRL */
  430#define GPHY_FLASH		BIT(1)
  431
  432/* PLA_POL_GPIO_CTRL */
  433#define DACK_DET_EN		BIT(15)
  434#define POL_GPHY_PATCH		BIT(4)
  435
  436/* USB_USB2PHY */
  437#define USB2PHY_SUSPEND		0x0001
  438#define USB2PHY_L1		0x0002
  439
  440/* USB_SSPHYLINK1 */
  441#define DELAY_PHY_PWR_CHG	BIT(1)
  442
  443/* USB_SSPHYLINK2 */
  444#define pwd_dn_scale_mask	0x3ffe
  445#define pwd_dn_scale(x)		((x) << 1)
  446
  447/* USB_CSR_DUMMY1 */
  448#define DYNAMIC_BURST		0x0001
  449
  450/* USB_CSR_DUMMY2 */
  451#define EP4_FULL_FC		0x0001
  452
  453/* USB_DEV_STAT */
  454#define STAT_SPEED_MASK		0x0006
  455#define STAT_SPEED_HIGH		0x0000
  456#define STAT_SPEED_FULL		0x0002
  457
  458/* USB_FW_FIX_EN0 */
  459#define FW_FIX_SUSPEND		BIT(14)
  460
  461/* USB_FW_FIX_EN1 */
  462#define FW_IP_RESET_EN		BIT(9)
  463
  464/* USB_LPM_CONFIG */
  465#define LPM_U1U2_EN		BIT(0)
  466
  467/* USB_TX_AGG */
  468#define TX_AGG_MAX_THRESHOLD	0x03
  469
  470/* USB_RX_BUF_TH */
  471#define RX_THR_SUPPER		0x0c350180
  472#define RX_THR_HIGH		0x7a120180
  473#define RX_THR_SLOW		0xffff0180
  474#define RX_THR_B		0x00010001
  475
  476/* USB_TX_DMA */
  477#define TEST_MODE_DISABLE	0x00000001
  478#define TX_SIZE_ADJUST1		0x00000100
  479
  480/* USB_BMU_RESET */
  481#define BMU_RESET_EP_IN		0x01
  482#define BMU_RESET_EP_OUT	0x02
  483
  484/* USB_BMU_CONFIG */
  485#define ACT_ODMA		BIT(1)
  486
  487/* USB_UPT_RXDMA_OWN */
  488#define OWN_UPDATE		BIT(0)
  489#define OWN_CLEAR		BIT(1)
  490
  491/* USB_FW_TASK */
  492#define FC_PATCH_TASK		BIT(1)
  493
  494/* USB_RX_AGGR_NUM */
  495#define RX_AGGR_NUM_MASK	0x1ff
  496
  497/* USB_UPS_CTRL */
  498#define POWER_CUT		0x0100
  499
  500/* USB_PM_CTRL_STATUS */
  501#define RESUME_INDICATE		0x0001
  502
  503/* USB_ECM_OPTION */
  504#define BYPASS_MAC_RESET	BIT(5)
  505
  506/* USB_CSTMR */
  507#define FORCE_SUPER		BIT(0)
  508
  509/* USB_MISC_2 */
  510#define UPS_FORCE_PWR_DOWN	BIT(0)
  511
  512/* USB_ECM_OP */
  513#define	EN_ALL_SPEED		BIT(0)
  514
  515/* USB_GPHY_CTRL */
  516#define GPHY_PATCH_DONE		BIT(2)
  517#define BYPASS_FLASH		BIT(5)
  518#define BACKUP_RESTRORE		BIT(6)
  519
  520/* USB_SPEED_OPTION */
  521#define RG_PWRDN_EN		BIT(8)
  522#define ALL_SPEED_OFF		BIT(9)
  523
  524/* USB_FW_CTRL */
  525#define FLOW_CTRL_PATCH_OPT	BIT(1)
  526#define AUTO_SPEEDUP		BIT(3)
  527#define FLOW_CTRL_PATCH_2	BIT(8)
  528
  529/* USB_FC_TIMER */
  530#define CTRL_TIMER_EN		BIT(15)
  531
  532/* USB_USB_CTRL */
  533#define CDC_ECM_EN		BIT(3)
  534#define RX_AGG_DISABLE		0x0010
  535#define RX_ZERO_EN		0x0080
  536
  537/* USB_U2P3_CTRL */
  538#define U2P3_ENABLE		0x0001
  539#define RX_DETECT8		BIT(3)
  540
  541/* USB_POWER_CUT */
  542#define PWR_EN			0x0001
  543#define PHASE2_EN		0x0008
  544#define UPS_EN			BIT(4)
  545#define USP_PREWAKE		BIT(5)
  546
  547/* USB_MISC_0 */
  548#define PCUT_STATUS		0x0001
  549
  550/* USB_RX_EARLY_TIMEOUT */
  551#define COALESCE_SUPER		 85000U
  552#define COALESCE_HIGH		250000U
  553#define COALESCE_SLOW		524280U
  554
  555/* USB_WDT1_CTRL */
  556#define WTD1_EN			BIT(0)
  557
  558/* USB_WDT11_CTRL */
  559#define TIMER11_EN		0x0001
  560
  561/* USB_LPM_CTRL */
  562/* bit 4 ~ 5: fifo empty boundary */
  563#define FIFO_EMPTY_1FB		0x30	/* 0x1fb * 64 = 32448 bytes */
  564/* bit 2 ~ 3: LMP timer */
  565#define LPM_TIMER_MASK		0x0c
  566#define LPM_TIMER_500MS		0x04	/* 500 ms */
  567#define LPM_TIMER_500US		0x0c	/* 500 us */
  568#define ROK_EXIT_LPM		0x02
  569
  570/* USB_AFE_CTRL2 */
  571#define SEN_VAL_MASK		0xf800
  572#define SEN_VAL_NORMAL		0xa000
  573#define SEL_RXIDLE		0x0100
  574
  575/* USB_UPHY_XTAL */
  576#define OOBS_POLLING		BIT(8)
  577
  578/* USB_UPS_CFG */
  579#define SAW_CNT_1MS_MASK	0x0fff
  580#define MID_REVERSE		BIT(5)	/* RTL8156A */
  581
  582/* USB_UPS_FLAGS */
  583#define UPS_FLAGS_R_TUNE		BIT(0)
  584#define UPS_FLAGS_EN_10M_CKDIV		BIT(1)
  585#define UPS_FLAGS_250M_CKDIV		BIT(2)
  586#define UPS_FLAGS_EN_ALDPS		BIT(3)
  587#define UPS_FLAGS_CTAP_SHORT_DIS	BIT(4)
  588#define UPS_FLAGS_SPEED_MASK		(0xf << 16)
  589#define ups_flags_speed(x)		((x) << 16)
  590#define UPS_FLAGS_EN_EEE		BIT(20)
  591#define UPS_FLAGS_EN_500M_EEE		BIT(21)
  592#define UPS_FLAGS_EN_EEE_CKDIV		BIT(22)
  593#define UPS_FLAGS_EEE_PLLOFF_100	BIT(23)
  594#define UPS_FLAGS_EEE_PLLOFF_GIGA	BIT(24)
  595#define UPS_FLAGS_EEE_CMOD_LV_EN	BIT(25)
  596#define UPS_FLAGS_EN_GREEN		BIT(26)
  597#define UPS_FLAGS_EN_FLOW_CTR		BIT(27)
  598
  599enum spd_duplex {
  600	NWAY_10M_HALF,
  601	NWAY_10M_FULL,
  602	NWAY_100M_HALF,
  603	NWAY_100M_FULL,
  604	NWAY_1000M_FULL,
  605	FORCE_10M_HALF,
  606	FORCE_10M_FULL,
  607	FORCE_100M_HALF,
  608	FORCE_100M_FULL,
  609	FORCE_1000M_FULL,
  610	NWAY_2500M_FULL,
  611};
  612
  613/* OCP_ALDPS_CONFIG */
  614#define ENPWRSAVE		0x8000
  615#define ENPDNPS			0x0200
  616#define LINKENA			0x0100
  617#define DIS_SDSAVE		0x0010
  618
  619/* OCP_PHY_STATUS */
  620#define PHY_STAT_MASK		0x0007
  621#define PHY_STAT_EXT_INIT	2
  622#define PHY_STAT_LAN_ON		3
  623#define PHY_STAT_PWRDN		5
  624
  625/* OCP_INTR_EN */
  626#define INTR_SPEED_FORCE	BIT(3)
  627
  628/* OCP_NCTL_CFG */
  629#define PGA_RETURN_EN		BIT(1)
  630
  631/* OCP_POWER_CFG */
  632#define EEE_CLKDIV_EN		0x8000
  633#define EN_ALDPS		0x0004
  634#define EN_10M_PLLOFF		0x0001
  635
  636/* OCP_EEE_CONFIG1 */
  637#define RG_TXLPI_MSK_HFDUP	0x8000
  638#define RG_MATCLR_EN		0x4000
  639#define EEE_10_CAP		0x2000
  640#define EEE_NWAY_EN		0x1000
  641#define TX_QUIET_EN		0x0200
  642#define RX_QUIET_EN		0x0100
  643#define sd_rise_time_mask	0x0070
  644#define sd_rise_time(x)		(min(x, 7) << 4)	/* bit 4 ~ 6 */
  645#define RG_RXLPI_MSK_HFDUP	0x0008
  646#define SDFALLTIME		0x0007	/* bit 0 ~ 2 */
  647
  648/* OCP_EEE_CONFIG2 */
  649#define RG_LPIHYS_NUM		0x7000	/* bit 12 ~ 15 */
  650#define RG_DACQUIET_EN		0x0400
  651#define RG_LDVQUIET_EN		0x0200
  652#define RG_CKRSEL		0x0020
  653#define RG_EEEPRG_EN		0x0010
  654
  655/* OCP_EEE_CONFIG3 */
  656#define fast_snr_mask		0xff80
  657#define fast_snr(x)		(min(x, 0x1ff) << 7)	/* bit 7 ~ 15 */
  658#define RG_LFS_SEL		0x0060	/* bit 6 ~ 5 */
  659#define MSK_PH			0x0006	/* bit 0 ~ 3 */
  660
  661/* OCP_EEE_AR */
  662/* bit[15:14] function */
  663#define FUN_ADDR		0x0000
  664#define FUN_DATA		0x4000
  665/* bit[4:0] device addr */
  666
  667/* OCP_EEE_CFG */
  668#define CTAP_SHORT_EN		0x0040
  669#define EEE10_EN		0x0010
  670
  671/* OCP_DOWN_SPEED */
  672#define EN_EEE_CMODE		BIT(14)
  673#define EN_EEE_1000		BIT(13)
  674#define EN_EEE_100		BIT(12)
  675#define EN_10M_CLKDIV		BIT(11)
  676#define EN_10M_BGOFF		0x0080
  677
  678/* OCP_10GBT_CTRL */
  679#define RTL_ADV2_5G_F_R		BIT(5)	/* Advertise 2.5GBASE-T fast-retrain */
  680
  681/* OCP_PHY_STATE */
  682#define TXDIS_STATE		0x01
  683#define ABD_STATE		0x02
  684
  685/* OCP_PHY_PATCH_STAT */
  686#define PATCH_READY		BIT(6)
  687
  688/* OCP_PHY_PATCH_CMD */
  689#define PATCH_REQUEST		BIT(4)
  690
  691/* OCP_PHY_LOCK */
  692#define PATCH_LOCK		BIT(0)
  693
  694/* OCP_ADC_CFG */
  695#define CKADSEL_L		0x0100
  696#define ADC_EN			0x0080
  697#define EN_EMI_L		0x0040
  698
  699/* OCP_SYSCLK_CFG */
  700#define sysclk_div_expo(x)	(min(x, 5) << 8)
  701#define clk_div_expo(x)		(min(x, 5) << 4)
  702
  703/* SRAM_GREEN_CFG */
  704#define GREEN_ETH_EN		BIT(15)
  705#define R_TUNE_EN		BIT(11)
  706
  707/* SRAM_LPF_CFG */
  708#define LPF_AUTO_TUNE		0x8000
  709
  710/* SRAM_10M_AMP1 */
  711#define GDAC_IB_UPALL		0x0008
  712
  713/* SRAM_10M_AMP2 */
  714#define AMP_DN			0x0200
  715
  716/* SRAM_IMPEDANCE */
  717#define RX_DRIVING_MASK		0x6000
  718
  719/* SRAM_PHY_LOCK */
  720#define PHY_PATCH_LOCK		0x0001
  721
  722/* MAC PASSTHRU */
  723#define AD_MASK			0xfee0
  724#define BND_MASK		0x0004
  725#define BD_MASK			0x0001
  726#define EFUSE			0xcfdb
  727#define PASS_THRU_MASK		0x1
  728
  729#define BP4_SUPER_ONLY		0x1578	/* RTL_VER_04 only */
  730
  731enum rtl_register_content {
  732	_2500bps	= BIT(10),
  733	_1250bps	= BIT(9),
  734	_500bps		= BIT(8),
  735	_tx_flow	= BIT(6),
  736	_rx_flow	= BIT(5),
  737	_1000bps	= 0x10,
  738	_100bps		= 0x08,
  739	_10bps		= 0x04,
  740	LINK_STATUS	= 0x02,
  741	FULL_DUP	= 0x01,
  742};
  743
  744#define is_speed_2500(_speed)	(((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))
  745#define is_flow_control(_speed)	(((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))
  746
  747#define RTL8152_MAX_TX		4
  748#define RTL8152_MAX_RX		10
  749#define INTBUFSIZE		2
  750#define TX_ALIGN		4
  751#define RX_ALIGN		8
  752
  753#define RTL8152_RX_MAX_PENDING	4096
  754#define RTL8152_RXFG_HEADSZ	256
  755
  756#define INTR_LINK		0x0004
  757
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  758#define RTL8152_RMS		(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
  759#define RTL8153_RMS		RTL8153_MAX_PACKET
  760#define RTL8152_TX_TIMEOUT	(5 * HZ)
  761#define mtu_to_size(m)		((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)
  762#define size_to_mtu(s)		((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)
  763#define rx_reserved_size(x)	(mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)
  764
  765/* rtl8152 flags */
  766enum rtl8152_flags {
  767	RTL8152_INACCESSIBLE = 0,
  768	RTL8152_SET_RX_MODE,
  769	WORK_ENABLE,
  770	RTL8152_LINK_CHG,
  771	SELECTIVE_SUSPEND,
  772	PHY_RESET,
  773	SCHEDULE_TASKLET,
  774	GREEN_ETHERNET,
  775	RX_EPROTO,
  776	IN_PRE_RESET,
  777	PROBED_WITH_NO_ERRORS,
  778	PROBE_SHOULD_RETRY,
  779};
  780
  781#define DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB		0x721e
  782#define DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK		0x3054
  783#define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2	0x3082
  784#define DEVICE_ID_THINKPAD_USB_C_DONGLE			0x720c
  785#define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2		0xa387
  786#define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3		0x3062
 
 
 
 
 
  787
  788struct tally_counter {
  789	__le64	tx_packets;
  790	__le64	rx_packets;
  791	__le64	tx_errors;
  792	__le32	rx_errors;
  793	__le16	rx_missed;
  794	__le16	align_errors;
  795	__le32	tx_one_collision;
  796	__le32	tx_multi_collision;
  797	__le64	rx_unicast;
  798	__le64	rx_broadcast;
  799	__le32	rx_multicast;
  800	__le16	tx_aborted;
  801	__le16	tx_underrun;
  802};
  803
  804struct rx_desc {
  805	__le32 opts1;
  806#define RX_LEN_MASK			0x7fff
  807
  808	__le32 opts2;
  809#define RD_UDP_CS			BIT(23)
  810#define RD_TCP_CS			BIT(22)
  811#define RD_IPV6_CS			BIT(20)
  812#define RD_IPV4_CS			BIT(19)
  813
  814	__le32 opts3;
  815#define IPF				BIT(23) /* IP checksum fail */
  816#define UDPF				BIT(22) /* UDP checksum fail */
  817#define TCPF				BIT(21) /* TCP checksum fail */
  818#define RX_VLAN_TAG			BIT(16)
  819
  820	__le32 opts4;
  821	__le32 opts5;
  822	__le32 opts6;
  823};
  824
  825struct tx_desc {
  826	__le32 opts1;
  827#define TX_FS			BIT(31) /* First segment of a packet */
  828#define TX_LS			BIT(30) /* Final segment of a packet */
  829#define GTSENDV4		BIT(28)
  830#define GTSENDV6		BIT(27)
  831#define GTTCPHO_SHIFT		18
  832#define GTTCPHO_MAX		0x7fU
  833#define TX_LEN_MAX		0x3ffffU
  834
  835	__le32 opts2;
  836#define UDP_CS			BIT(31) /* Calculate UDP/IP checksum */
  837#define TCP_CS			BIT(30) /* Calculate TCP/IP checksum */
  838#define IPV4_CS			BIT(29) /* Calculate IPv4 checksum */
  839#define IPV6_CS			BIT(28) /* Calculate IPv6 checksum */
  840#define MSS_SHIFT		17
  841#define MSS_MAX			0x7ffU
  842#define TCPHO_SHIFT		17
  843#define TCPHO_MAX		0x7ffU
  844#define TX_VLAN_TAG		BIT(16)
  845};
  846
  847struct r8152;
  848
  849struct rx_agg {
  850	struct list_head list, info_list;
  851	struct urb *urb;
  852	struct r8152 *context;
  853	struct page *page;
  854	void *buffer;
  855};
  856
  857struct tx_agg {
  858	struct list_head list;
  859	struct urb *urb;
  860	struct r8152 *context;
  861	void *buffer;
  862	void *head;
  863	u32 skb_num;
  864	u32 skb_len;
  865};
  866
  867struct r8152 {
  868	unsigned long flags;
  869	struct usb_device *udev;
  870	struct napi_struct napi;
  871	struct usb_interface *intf;
  872	struct net_device *netdev;
  873	struct urb *intr_urb;
  874	struct tx_agg tx_info[RTL8152_MAX_TX];
  875	struct list_head rx_info, rx_used;
  876	struct list_head rx_done, tx_free;
  877	struct sk_buff_head tx_queue, rx_queue;
  878	spinlock_t rx_lock, tx_lock;
  879	struct delayed_work schedule, hw_phy_work;
  880	struct mii_if_info mii;
  881	struct mutex control;	/* use for hw setting */
  882#ifdef CONFIG_PM_SLEEP
  883	struct notifier_block pm_notifier;
  884#endif
  885	struct tasklet_struct tx_tl;
  886
  887	struct rtl_ops {
  888		void (*init)(struct r8152 *tp);
  889		int (*enable)(struct r8152 *tp);
  890		void (*disable)(struct r8152 *tp);
  891		void (*up)(struct r8152 *tp);
  892		void (*down)(struct r8152 *tp);
  893		void (*unload)(struct r8152 *tp);
  894		int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
  895		int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
  896		bool (*in_nway)(struct r8152 *tp);
  897		void (*hw_phy_cfg)(struct r8152 *tp);
  898		void (*autosuspend_en)(struct r8152 *tp, bool enable);
  899		void (*change_mtu)(struct r8152 *tp);
  900	} rtl_ops;
  901
  902	struct ups_info {
  903		u32 r_tune:1;
  904		u32 _10m_ckdiv:1;
  905		u32 _250m_ckdiv:1;
  906		u32 aldps:1;
  907		u32 lite_mode:2;
  908		u32 speed_duplex:4;
  909		u32 eee:1;
  910		u32 eee_lite:1;
  911		u32 eee_ckdiv:1;
  912		u32 eee_plloff_100:1;
  913		u32 eee_plloff_giga:1;
  914		u32 eee_cmod_lv:1;
  915		u32 green:1;
  916		u32 flow_control:1;
  917		u32 ctap_short_off:1;
  918	} ups_info;
  919
  920#define RTL_VER_SIZE		32
  921
  922	struct rtl_fw {
  923		const char *fw_name;
  924		const struct firmware *fw;
  925
  926		char version[RTL_VER_SIZE];
  927		int (*pre_fw)(struct r8152 *tp);
  928		int (*post_fw)(struct r8152 *tp);
  929
  930		bool retry;
  931	} rtl_fw;
  932
  933	atomic_t rx_count;
  934
  935	bool eee_en;
  936	int intr_interval;
  937	u32 saved_wolopts;
  938	u32 msg_enable;
  939	u32 tx_qlen;
  940	u32 coalesce;
  941	u32 advertising;
  942	u32 rx_buf_sz;
  943	u32 rx_copybreak;
  944	u32 rx_pending;
  945	u32 fc_pause_on, fc_pause_off;
  946
  947	unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out;
  948
  949	u32 support_2500full:1;
  950	u32 lenovo_macpassthru:1;
  951	u32 dell_tb_rx_agg_bug:1;
  952	u16 ocp_base;
  953	u16 speed;
  954	u16 eee_adv;
  955	u8 *intr_buff;
  956	u8 version;
  957	u8 duplex;
  958	u8 autoneg;
  959
  960	unsigned int reg_access_reset_count;
  961};
  962
  963/**
  964 * struct fw_block - block type and total length
  965 * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
  966 *	RTL_FW_USB and so on.
  967 * @length: total length of the current block.
  968 */
  969struct fw_block {
  970	__le32 type;
  971	__le32 length;
  972} __packed;
  973
  974/**
  975 * struct fw_header - header of the firmware file
  976 * @checksum: checksum of sha256 which is calculated from the whole file
  977 *	except the checksum field of the file. That is, calculate sha256
  978 *	from the version field to the end of the file.
  979 * @version: version of this firmware.
  980 * @blocks: the first firmware block of the file
  981 */
  982struct fw_header {
  983	u8 checksum[32];
  984	char version[RTL_VER_SIZE];
  985	struct fw_block blocks[];
  986} __packed;
  987
  988enum rtl8152_fw_flags {
  989	FW_FLAGS_USB = 0,
  990	FW_FLAGS_PLA,
  991	FW_FLAGS_START,
  992	FW_FLAGS_STOP,
  993	FW_FLAGS_NC,
  994	FW_FLAGS_NC1,
  995	FW_FLAGS_NC2,
  996	FW_FLAGS_UC2,
  997	FW_FLAGS_UC,
  998	FW_FLAGS_SPEED_UP,
  999	FW_FLAGS_VER,
 1000};
 1001
 1002enum rtl8152_fw_fixup_cmd {
 1003	FW_FIXUP_AND = 0,
 1004	FW_FIXUP_OR,
 1005	FW_FIXUP_NOT,
 1006	FW_FIXUP_XOR,
 1007};
 1008
 1009struct fw_phy_set {
 1010	__le16 addr;
 1011	__le16 data;
 1012} __packed;
 1013
 1014struct fw_phy_speed_up {
 1015	struct fw_block blk_hdr;
 1016	__le16 fw_offset;
 1017	__le16 version;
 1018	__le16 fw_reg;
 1019	__le16 reserved;
 1020	char info[];
 1021} __packed;
 1022
 1023struct fw_phy_ver {
 1024	struct fw_block blk_hdr;
 1025	struct fw_phy_set ver;
 1026	__le32 reserved;
 1027} __packed;
 1028
 1029struct fw_phy_fixup {
 1030	struct fw_block blk_hdr;
 1031	struct fw_phy_set setting;
 1032	__le16 bit_cmd;
 1033	__le16 reserved;
 1034} __packed;
 1035
 1036struct fw_phy_union {
 1037	struct fw_block blk_hdr;
 1038	__le16 fw_offset;
 1039	__le16 fw_reg;
 1040	struct fw_phy_set pre_set[2];
 1041	struct fw_phy_set bp[8];
 1042	struct fw_phy_set bp_en;
 1043	u8 pre_num;
 1044	u8 bp_num;
 1045	char info[];
 1046} __packed;
 1047
 1048/**
 1049 * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
 1050 *	The layout of the firmware block is:
 1051 *	<struct fw_mac> + <info> + <firmware data>.
 1052 * @blk_hdr: firmware descriptor (type, length)
 1053 * @fw_offset: offset of the firmware binary data. The start address of
 1054 *	the data would be the address of struct fw_mac + @fw_offset.
 1055 * @fw_reg: the register to load the firmware. Depends on chip.
 1056 * @bp_ba_addr: the register to write break point base address. Depends on
 1057 *	chip.
 1058 * @bp_ba_value: break point base address. Depends on chip.
 1059 * @bp_en_addr: the register to write break point enabled mask. Depends
 1060 *	on chip.
 1061 * @bp_en_value: break point enabled mask. Depends on the firmware.
 1062 * @bp_start: the start register of break points. Depends on chip.
 1063 * @bp_num: the break point number which needs to be set for this firmware.
 1064 *	Depends on the firmware.
 1065 * @bp: break points. Depends on firmware.
 1066 * @reserved: reserved space (unused)
 1067 * @fw_ver_reg: the register to store the fw version.
 1068 * @fw_ver_data: the firmware version of the current type.
 1069 * @info: additional information for debugging, and is followed by the
 1070 *	binary data of firmware.
 1071 */
 1072struct fw_mac {
 1073	struct fw_block blk_hdr;
 1074	__le16 fw_offset;
 1075	__le16 fw_reg;
 1076	__le16 bp_ba_addr;
 1077	__le16 bp_ba_value;
 1078	__le16 bp_en_addr;
 1079	__le16 bp_en_value;
 1080	__le16 bp_start;
 1081	__le16 bp_num;
 1082	__le16 bp[16]; /* any value determined by firmware */
 1083	__le32 reserved;
 1084	__le16 fw_ver_reg;
 1085	u8 fw_ver_data;
 1086	char info[];
 1087} __packed;
 1088
 1089/**
 1090 * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
 1091 *	This is used to set patch key when loading the firmware of PHY.
 1092 * @blk_hdr: firmware descriptor (type, length)
 1093 * @key_reg: the register to write the patch key.
 1094 * @key_data: patch key.
 1095 * @reserved: reserved space (unused)
 1096 */
 1097struct fw_phy_patch_key {
 1098	struct fw_block blk_hdr;
 1099	__le16 key_reg;
 1100	__le16 key_data;
 1101	__le32 reserved;
 1102} __packed;
 1103
 1104/**
 1105 * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
 1106 *	The layout of the firmware block is:
 1107 *	<struct fw_phy_nc> + <info> + <firmware data>.
 1108 * @blk_hdr: firmware descriptor (type, length)
 1109 * @fw_offset: offset of the firmware binary data. The start address of
 1110 *	the data would be the address of struct fw_phy_nc + @fw_offset.
 1111 * @fw_reg: the register to load the firmware. Depends on chip.
 1112 * @ba_reg: the register to write the base address. Depends on chip.
 1113 * @ba_data: base address. Depends on chip.
 1114 * @patch_en_addr: the register of enabling patch mode. Depends on chip.
 1115 * @patch_en_value: patch mode enabled mask. Depends on the firmware.
 1116 * @mode_reg: the regitster of switching the mode.
 1117 * @mode_pre: the mode needing to be set before loading the firmware.
 1118 * @mode_post: the mode to be set when finishing to load the firmware.
 1119 * @reserved: reserved space (unused)
 1120 * @bp_start: the start register of break points. Depends on chip.
 1121 * @bp_num: the break point number which needs to be set for this firmware.
 1122 *	Depends on the firmware.
 1123 * @bp: break points. Depends on firmware.
 1124 * @info: additional information for debugging, and is followed by the
 1125 *	binary data of firmware.
 1126 */
 1127struct fw_phy_nc {
 1128	struct fw_block blk_hdr;
 1129	__le16 fw_offset;
 1130	__le16 fw_reg;
 1131	__le16 ba_reg;
 1132	__le16 ba_data;
 1133	__le16 patch_en_addr;
 1134	__le16 patch_en_value;
 1135	__le16 mode_reg;
 1136	__le16 mode_pre;
 1137	__le16 mode_post;
 1138	__le16 reserved;
 1139	__le16 bp_start;
 1140	__le16 bp_num;
 1141	__le16 bp[4];
 1142	char info[];
 1143} __packed;
 1144
 1145enum rtl_fw_type {
 1146	RTL_FW_END = 0,
 1147	RTL_FW_PLA,
 1148	RTL_FW_USB,
 1149	RTL_FW_PHY_START,
 1150	RTL_FW_PHY_STOP,
 1151	RTL_FW_PHY_NC,
 1152	RTL_FW_PHY_FIXUP,
 1153	RTL_FW_PHY_UNION_NC,
 1154	RTL_FW_PHY_UNION_NC1,
 1155	RTL_FW_PHY_UNION_NC2,
 1156	RTL_FW_PHY_UNION_UC2,
 1157	RTL_FW_PHY_UNION_UC,
 1158	RTL_FW_PHY_UNION_MISC,
 1159	RTL_FW_PHY_SPEED_UP,
 1160	RTL_FW_PHY_VER,
 1161};
 1162
 1163enum rtl_version {
 1164	RTL_VER_UNKNOWN = 0,
 1165	RTL_VER_01,
 1166	RTL_VER_02,
 1167	RTL_VER_03,
 1168	RTL_VER_04,
 1169	RTL_VER_05,
 1170	RTL_VER_06,
 1171	RTL_VER_07,
 1172	RTL_VER_08,
 1173	RTL_VER_09,
 1174
 1175	RTL_TEST_01,
 1176	RTL_VER_10,
 1177	RTL_VER_11,
 1178	RTL_VER_12,
 1179	RTL_VER_13,
 1180	RTL_VER_14,
 1181	RTL_VER_15,
 1182
 1183	RTL_VER_MAX
 1184};
 1185
 1186enum tx_csum_stat {
 1187	TX_CSUM_SUCCESS = 0,
 1188	TX_CSUM_TSO,
 1189	TX_CSUM_NONE
 1190};
 1191
 1192#define RTL_ADVERTISED_10_HALF			BIT(0)
 1193#define RTL_ADVERTISED_10_FULL			BIT(1)
 1194#define RTL_ADVERTISED_100_HALF			BIT(2)
 1195#define RTL_ADVERTISED_100_FULL			BIT(3)
 1196#define RTL_ADVERTISED_1000_HALF		BIT(4)
 1197#define RTL_ADVERTISED_1000_FULL		BIT(5)
 1198#define RTL_ADVERTISED_2500_FULL		BIT(6)
 1199
 1200/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
 1201 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
 1202 */
 1203static const int multicast_filter_limit = 32;
 1204static unsigned int agg_buf_sz = 16384;
 1205
 1206#define RTL_LIMITED_TSO_SIZE	(size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc))
 1207
 1208/* If register access fails then we block access and issue a reset. If this
 1209 * happens too many times in a row without a successful access then we stop
 1210 * trying to reset and just leave access blocked.
 1211 */
 1212#define REGISTER_ACCESS_MAX_RESETS	3
 1213
 1214static void rtl_set_inaccessible(struct r8152 *tp)
 1215{
 1216	set_bit(RTL8152_INACCESSIBLE, &tp->flags);
 1217	smp_mb__after_atomic();
 1218}
 1219
 1220static void rtl_set_accessible(struct r8152 *tp)
 1221{
 1222	clear_bit(RTL8152_INACCESSIBLE, &tp->flags);
 1223	smp_mb__after_atomic();
 1224}
 1225
 1226static
 1227int r8152_control_msg(struct r8152 *tp, unsigned int pipe, __u8 request,
 1228		      __u8 requesttype, __u16 value, __u16 index, void *data,
 1229		      __u16 size, const char *msg_tag)
 1230{
 1231	struct usb_device *udev = tp->udev;
 1232	int ret;
 1233
 1234	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 1235		return -ENODEV;
 1236
 1237	ret = usb_control_msg(udev, pipe, request, requesttype,
 1238			      value, index, data, size,
 1239			      USB_CTRL_GET_TIMEOUT);
 1240
 1241	/* No need to issue a reset to report an error if the USB device got
 1242	 * unplugged; just return immediately.
 1243	 */
 1244	if (ret == -ENODEV)
 1245		return ret;
 1246
 1247	/* If the write was successful then we're done */
 1248	if (ret >= 0) {
 1249		tp->reg_access_reset_count = 0;
 1250		return ret;
 1251	}
 1252
 1253	dev_err(&udev->dev,
 1254		"Failed to %s %d bytes at %#06x/%#06x (%d)\n",
 1255		msg_tag, size, value, index, ret);
 1256
 1257	/* Block all future register access until we reset. Much of the code
 1258	 * in the driver doesn't check for errors. Notably, many parts of the
 1259	 * driver do a read/modify/write of a register value without
 1260	 * confirming that the read succeeded. Writing back modified garbage
 1261	 * like this can fully wedge the adapter, requiring a power cycle.
 1262	 */
 1263	rtl_set_inaccessible(tp);
 1264
 1265	/* If probe hasn't yet finished, then we'll request a retry of the
 1266	 * whole probe routine if we get any control transfer errors. We
 1267	 * never have to clear this bit since we free/reallocate the whole "tp"
 1268	 * structure if we retry probe.
 1269	 */
 1270	if (!test_bit(PROBED_WITH_NO_ERRORS, &tp->flags)) {
 1271		set_bit(PROBE_SHOULD_RETRY, &tp->flags);
 1272		return ret;
 1273	}
 1274
 1275	/* Failing to access registers in pre-reset is not surprising since we
 1276	 * wouldn't be resetting if things were behaving normally. The register
 1277	 * access we do in pre-reset isn't truly mandatory--we're just reusing
 1278	 * the disable() function and trying to be nice by powering the
 1279	 * adapter down before resetting it. Thus, if we're in pre-reset,
 1280	 * we'll return right away and not try to queue up yet another reset.
 1281	 * We know the post-reset is already coming.
 1282	 */
 1283	if (test_bit(IN_PRE_RESET, &tp->flags))
 1284		return ret;
 1285
 1286	if (tp->reg_access_reset_count < REGISTER_ACCESS_MAX_RESETS) {
 1287		usb_queue_reset_device(tp->intf);
 1288		tp->reg_access_reset_count++;
 1289	} else if (tp->reg_access_reset_count == REGISTER_ACCESS_MAX_RESETS) {
 1290		dev_err(&udev->dev,
 1291			"Tried to reset %d times; giving up.\n",
 1292			REGISTER_ACCESS_MAX_RESETS);
 1293	}
 1294
 1295	return ret;
 1296}
 1297
 1298static
 1299int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
 1300{
 1301	int ret;
 1302	void *tmp;
 1303
 1304	tmp = kmalloc(size, GFP_KERNEL);
 1305	if (!tmp)
 1306		return -ENOMEM;
 1307
 1308	ret = r8152_control_msg(tp, tp->pipe_ctrl_in,
 1309				RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
 1310				value, index, tmp, size, "read");
 1311
 1312	if (ret < 0)
 1313		memset(data, 0xff, size);
 1314	else
 1315		memcpy(data, tmp, size);
 1316
 1317	kfree(tmp);
 1318
 1319	return ret;
 1320}
 1321
 1322static
 1323int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
 1324{
 1325	int ret;
 1326	void *tmp;
 1327
 1328	tmp = kmemdup(data, size, GFP_KERNEL);
 1329	if (!tmp)
 1330		return -ENOMEM;
 1331
 1332	ret = r8152_control_msg(tp, tp->pipe_ctrl_out,
 1333				RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
 1334				value, index, tmp, size, "write");
 1335
 1336	kfree(tmp);
 1337
 1338	return ret;
 1339}
 1340
 1341static void rtl_set_unplug(struct r8152 *tp)
 1342{
 1343	if (tp->udev->state == USB_STATE_NOTATTACHED)
 1344		rtl_set_inaccessible(tp);
 
 
 1345}
 1346
 1347static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
 1348			    void *data, u16 type)
 1349{
 1350	u16 limit = 64;
 1351	int ret = 0;
 1352
 1353	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 1354		return -ENODEV;
 1355
 1356	/* both size and indix must be 4 bytes align */
 1357	if ((size & 3) || !size || (index & 3) || !data)
 1358		return -EPERM;
 1359
 1360	if ((u32)index + (u32)size > 0xffff)
 1361		return -EPERM;
 1362
 1363	while (size) {
 1364		if (size > limit) {
 1365			ret = get_registers(tp, index, type, limit, data);
 1366			if (ret < 0)
 1367				break;
 1368
 1369			index += limit;
 1370			data += limit;
 1371			size -= limit;
 1372		} else {
 1373			ret = get_registers(tp, index, type, size, data);
 1374			if (ret < 0)
 1375				break;
 1376
 1377			index += size;
 1378			data += size;
 1379			size = 0;
 1380			break;
 1381		}
 1382	}
 1383
 1384	if (ret == -ENODEV)
 1385		rtl_set_unplug(tp);
 1386
 1387	return ret;
 1388}
 1389
 1390static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
 1391			     u16 size, void *data, u16 type)
 1392{
 1393	int ret;
 1394	u16 byteen_start, byteen_end, byen;
 1395	u16 limit = 512;
 1396
 1397	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 1398		return -ENODEV;
 1399
 1400	/* both size and indix must be 4 bytes align */
 1401	if ((size & 3) || !size || (index & 3) || !data)
 1402		return -EPERM;
 1403
 1404	if ((u32)index + (u32)size > 0xffff)
 1405		return -EPERM;
 1406
 1407	byteen_start = byteen & BYTE_EN_START_MASK;
 1408	byteen_end = byteen & BYTE_EN_END_MASK;
 1409
 1410	byen = byteen_start | (byteen_start << 4);
 
 
 
 1411
 1412	/* Split the first DWORD if the byte_en is not 0xff */
 1413	if (byen != BYTE_EN_DWORD) {
 1414		ret = set_registers(tp, index, type | byen, 4, data);
 1415		if (ret < 0)
 1416			goto error1;
 1417
 1418		index += 4;
 1419		data += 4;
 1420		size -= 4;
 1421	}
 1422
 1423	if (size) {
 1424		byen = byteen_end | (byteen_end >> 4);
 1425
 1426		/* Split the last DWORD if the byte_en is not 0xff */
 1427		if (byen != BYTE_EN_DWORD)
 1428			size -= 4;
 1429
 1430		while (size) {
 1431			if (size > limit) {
 1432				ret = set_registers(tp, index,
 1433						    type | BYTE_EN_DWORD,
 1434						    limit, data);
 1435				if (ret < 0)
 1436					goto error1;
 1437
 1438				index += limit;
 1439				data += limit;
 1440				size -= limit;
 1441			} else {
 1442				ret = set_registers(tp, index,
 1443						    type | BYTE_EN_DWORD,
 1444						    size, data);
 1445				if (ret < 0)
 1446					goto error1;
 1447
 1448				index += size;
 1449				data += size;
 1450				size = 0;
 1451				break;
 1452			}
 1453		}
 1454
 1455		/* Set the last DWORD */
 1456		if (byen != BYTE_EN_DWORD)
 1457			ret = set_registers(tp, index, type | byen, 4, data);
 
 1458	}
 1459
 1460error1:
 1461	if (ret == -ENODEV)
 1462		rtl_set_unplug(tp);
 1463
 1464	return ret;
 1465}
 1466
 1467static inline
 1468int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
 1469{
 1470	return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
 1471}
 1472
 1473static inline
 1474int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
 1475{
 1476	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
 1477}
 1478
 1479static inline
 1480int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
 1481{
 1482	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
 1483}
 1484
 1485static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
 1486{
 1487	__le32 data;
 1488
 1489	generic_ocp_read(tp, index, sizeof(data), &data, type);
 1490
 1491	return __le32_to_cpu(data);
 1492}
 1493
 1494static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
 1495{
 1496	__le32 tmp = __cpu_to_le32(data);
 1497
 1498	generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
 1499}
 1500
 1501static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
 1502{
 1503	u32 data;
 1504	__le32 tmp;
 1505	u16 byen = BYTE_EN_WORD;
 1506	u8 shift = index & 2;
 1507
 1508	index &= ~3;
 1509	byen <<= shift;
 1510
 1511	generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
 1512
 1513	data = __le32_to_cpu(tmp);
 1514	data >>= (shift * 8);
 1515	data &= 0xffff;
 1516
 1517	return (u16)data;
 1518}
 1519
 1520static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
 1521{
 1522	u32 mask = 0xffff;
 1523	__le32 tmp;
 1524	u16 byen = BYTE_EN_WORD;
 1525	u8 shift = index & 2;
 1526
 1527	data &= mask;
 1528
 1529	if (index & 2) {
 1530		byen <<= shift;
 1531		mask <<= (shift * 8);
 1532		data <<= (shift * 8);
 1533		index &= ~3;
 1534	}
 1535
 1536	tmp = __cpu_to_le32(data);
 1537
 1538	generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
 1539}
 1540
 1541static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
 1542{
 1543	u32 data;
 1544	__le32 tmp;
 1545	u8 shift = index & 3;
 1546
 1547	index &= ~3;
 1548
 1549	generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
 1550
 1551	data = __le32_to_cpu(tmp);
 1552	data >>= (shift * 8);
 1553	data &= 0xff;
 1554
 1555	return (u8)data;
 1556}
 1557
 1558static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
 1559{
 1560	u32 mask = 0xff;
 1561	__le32 tmp;
 1562	u16 byen = BYTE_EN_BYTE;
 1563	u8 shift = index & 3;
 1564
 1565	data &= mask;
 1566
 1567	if (index & 3) {
 1568		byen <<= shift;
 1569		mask <<= (shift * 8);
 1570		data <<= (shift * 8);
 1571		index &= ~3;
 1572	}
 1573
 1574	tmp = __cpu_to_le32(data);
 1575
 1576	generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
 1577}
 1578
 1579static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
 1580{
 1581	u16 ocp_base, ocp_index;
 1582
 1583	ocp_base = addr & 0xf000;
 1584	if (ocp_base != tp->ocp_base) {
 1585		ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
 1586		tp->ocp_base = ocp_base;
 1587	}
 1588
 1589	ocp_index = (addr & 0x0fff) | 0xb000;
 1590	return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
 1591}
 1592
 1593static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
 1594{
 1595	u16 ocp_base, ocp_index;
 1596
 1597	ocp_base = addr & 0xf000;
 1598	if (ocp_base != tp->ocp_base) {
 1599		ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
 1600		tp->ocp_base = ocp_base;
 1601	}
 1602
 1603	ocp_index = (addr & 0x0fff) | 0xb000;
 1604	ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
 1605}
 1606
 1607static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
 1608{
 1609	ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
 1610}
 1611
 1612static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
 1613{
 1614	return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
 1615}
 1616
 1617static void sram_write(struct r8152 *tp, u16 addr, u16 data)
 1618{
 1619	ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
 1620	ocp_reg_write(tp, OCP_SRAM_DATA, data);
 1621}
 1622
 1623static u16 sram_read(struct r8152 *tp, u16 addr)
 1624{
 1625	ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
 1626	return ocp_reg_read(tp, OCP_SRAM_DATA);
 1627}
 1628
 1629static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
 1630{
 1631	struct r8152 *tp = netdev_priv(netdev);
 1632	int ret;
 1633
 1634	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 1635		return -ENODEV;
 1636
 1637	if (phy_id != R8152_PHY_ID)
 1638		return -EINVAL;
 1639
 1640	ret = r8152_mdio_read(tp, reg);
 1641
 1642	return ret;
 1643}
 1644
 1645static
 1646void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
 1647{
 1648	struct r8152 *tp = netdev_priv(netdev);
 1649
 1650	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 1651		return;
 1652
 1653	if (phy_id != R8152_PHY_ID)
 1654		return;
 1655
 1656	r8152_mdio_write(tp, reg, val);
 1657}
 1658
 1659static int
 1660r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
 1661
 1662static int
 1663rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
 1664		  u32 advertising);
 1665
 1666static int __rtl8152_set_mac_address(struct net_device *netdev, void *p,
 1667				     bool in_resume)
 1668{
 1669	struct r8152 *tp = netdev_priv(netdev);
 1670	struct sockaddr *addr = p;
 1671	int ret = -EADDRNOTAVAIL;
 1672
 1673	if (!is_valid_ether_addr(addr->sa_data))
 1674		goto out1;
 1675
 1676	if (!in_resume) {
 1677		ret = usb_autopm_get_interface(tp->intf);
 1678		if (ret < 0)
 1679			goto out1;
 1680	}
 1681
 1682	mutex_lock(&tp->control);
 1683
 1684	eth_hw_addr_set(netdev, addr->sa_data);
 1685
 1686	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
 1687	pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
 1688	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
 1689
 1690	mutex_unlock(&tp->control);
 1691
 1692	if (!in_resume)
 1693		usb_autopm_put_interface(tp->intf);
 1694out1:
 1695	return ret;
 1696}
 1697
 1698static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
 1699{
 1700	return __rtl8152_set_mac_address(netdev, p, false);
 1701}
 1702
 1703/* Devices containing proper chips can support a persistent
 1704 * host system provided MAC address.
 1705 * Examples of this are Dell TB15 and Dell WD15 docks
 1706 */
 1707static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
 1708{
 1709	acpi_status status;
 1710	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
 1711	union acpi_object *obj;
 1712	int ret = -EINVAL;
 1713	u32 ocp_data;
 1714	unsigned char buf[6];
 1715	char *mac_obj_name;
 1716	acpi_object_type mac_obj_type;
 1717	int mac_strlen;
 1718
 1719	if (tp->lenovo_macpassthru) {
 1720		mac_obj_name = "\\MACA";
 1721		mac_obj_type = ACPI_TYPE_STRING;
 1722		mac_strlen = 0x16;
 
 
 
 1723	} else {
 1724		/* test for -AD variant of RTL8153 */
 1725		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
 1726		if ((ocp_data & AD_MASK) == 0x1000) {
 1727			/* test for MAC address pass-through bit */
 1728			ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
 1729			if ((ocp_data & PASS_THRU_MASK) != 1) {
 1730				netif_dbg(tp, probe, tp->netdev,
 1731						"No efuse for RTL8153-AD MAC pass through\n");
 1732				return -ENODEV;
 1733			}
 1734		} else {
 1735			/* test for RTL8153-BND and RTL8153-BD */
 1736			ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
 1737			if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
 1738				netif_dbg(tp, probe, tp->netdev,
 1739						"Invalid variant for MAC pass through\n");
 1740				return -ENODEV;
 1741			}
 1742		}
 1743
 1744		mac_obj_name = "\\_SB.AMAC";
 1745		mac_obj_type = ACPI_TYPE_BUFFER;
 1746		mac_strlen = 0x17;
 1747	}
 1748
 1749	/* returns _AUXMAC_#AABBCCDDEEFF# */
 1750	status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
 1751	obj = (union acpi_object *)buffer.pointer;
 1752	if (!ACPI_SUCCESS(status))
 1753		return -ENODEV;
 1754	if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
 1755		netif_warn(tp, probe, tp->netdev,
 1756			   "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
 1757			   obj->type, obj->string.length);
 1758		goto amacout;
 1759	}
 1760
 1761	if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
 1762	    strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
 1763		netif_warn(tp, probe, tp->netdev,
 1764			   "Invalid header when reading pass-thru MAC addr\n");
 1765		goto amacout;
 1766	}
 1767	ret = hex2bin(buf, obj->string.pointer + 9, 6);
 1768	if (!(ret == 0 && is_valid_ether_addr(buf))) {
 1769		netif_warn(tp, probe, tp->netdev,
 1770			   "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
 1771			   ret, buf);
 1772		ret = -EINVAL;
 1773		goto amacout;
 1774	}
 1775	memcpy(sa->sa_data, buf, 6);
 1776	netif_info(tp, probe, tp->netdev,
 1777		   "Using pass-thru MAC addr %pM\n", sa->sa_data);
 1778
 1779amacout:
 1780	kfree(obj);
 1781	return ret;
 1782}
 1783
 1784static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
 1785{
 1786	struct net_device *dev = tp->netdev;
 1787	int ret;
 1788
 1789	sa->sa_family = dev->type;
 1790
 1791	ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
 1792	if (ret < 0) {
 1793		if (tp->version == RTL_VER_01) {
 1794			ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
 1795		} else {
 1796			/* if device doesn't support MAC pass through this will
 1797			 * be expected to be non-zero
 1798			 */
 1799			ret = vendor_mac_passthru_addr_read(tp, sa);
 1800			if (ret < 0)
 1801				ret = pla_ocp_read(tp, PLA_BACKUP, 8,
 1802						   sa->sa_data);
 1803		}
 1804	}
 1805
 1806	if (ret < 0) {
 1807		netif_err(tp, probe, dev, "Get ether addr fail\n");
 1808	} else if (!is_valid_ether_addr(sa->sa_data)) {
 1809		netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
 1810			  sa->sa_data);
 1811		eth_hw_addr_random(dev);
 1812		ether_addr_copy(sa->sa_data, dev->dev_addr);
 1813		netif_info(tp, probe, dev, "Random ether addr %pM\n",
 1814			   sa->sa_data);
 1815		return 0;
 1816	}
 1817
 1818	return ret;
 1819}
 1820
 1821static int set_ethernet_addr(struct r8152 *tp, bool in_resume)
 1822{
 1823	struct net_device *dev = tp->netdev;
 1824	struct sockaddr sa;
 1825	int ret;
 1826
 1827	ret = determine_ethernet_addr(tp, &sa);
 1828	if (ret < 0)
 1829		return ret;
 1830
 1831	if (tp->version == RTL_VER_01)
 1832		eth_hw_addr_set(dev, sa.sa_data);
 1833	else
 1834		ret = __rtl8152_set_mac_address(dev, &sa, in_resume);
 1835
 1836	return ret;
 1837}
 1838
 1839static void read_bulk_callback(struct urb *urb)
 1840{
 1841	struct net_device *netdev;
 1842	int status = urb->status;
 1843	struct rx_agg *agg;
 1844	struct r8152 *tp;
 1845	unsigned long flags;
 1846
 1847	agg = urb->context;
 1848	if (!agg)
 1849		return;
 1850
 1851	tp = agg->context;
 1852	if (!tp)
 1853		return;
 1854
 1855	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 1856		return;
 1857
 1858	if (!test_bit(WORK_ENABLE, &tp->flags))
 1859		return;
 1860
 1861	netdev = tp->netdev;
 1862
 1863	/* When link down, the driver would cancel all bulks. */
 1864	/* This avoid the re-submitting bulk */
 1865	if (!netif_carrier_ok(netdev))
 1866		return;
 1867
 1868	usb_mark_last_busy(tp->udev);
 1869
 1870	switch (status) {
 1871	case 0:
 1872		if (urb->actual_length < ETH_ZLEN)
 1873			break;
 1874
 1875		spin_lock_irqsave(&tp->rx_lock, flags);
 1876		list_add_tail(&agg->list, &tp->rx_done);
 1877		spin_unlock_irqrestore(&tp->rx_lock, flags);
 1878		napi_schedule(&tp->napi);
 1879		return;
 1880	case -ESHUTDOWN:
 1881		rtl_set_unplug(tp);
 1882		netif_device_detach(tp->netdev);
 1883		return;
 1884	case -EPROTO:
 1885		urb->actual_length = 0;
 1886		spin_lock_irqsave(&tp->rx_lock, flags);
 1887		list_add_tail(&agg->list, &tp->rx_done);
 1888		spin_unlock_irqrestore(&tp->rx_lock, flags);
 1889		set_bit(RX_EPROTO, &tp->flags);
 1890		schedule_delayed_work(&tp->schedule, 1);
 1891		return;
 1892	case -ENOENT:
 1893		return;	/* the urb is in unlink state */
 1894	case -ETIME:
 1895		if (net_ratelimit())
 1896			netdev_warn(netdev, "maybe reset is needed?\n");
 1897		break;
 1898	default:
 1899		if (net_ratelimit())
 1900			netdev_warn(netdev, "Rx status %d\n", status);
 1901		break;
 1902	}
 1903
 1904	r8152_submit_rx(tp, agg, GFP_ATOMIC);
 1905}
 1906
 1907static void write_bulk_callback(struct urb *urb)
 1908{
 1909	struct net_device_stats *stats;
 1910	struct net_device *netdev;
 1911	struct tx_agg *agg;
 1912	struct r8152 *tp;
 1913	unsigned long flags;
 1914	int status = urb->status;
 1915
 1916	agg = urb->context;
 1917	if (!agg)
 1918		return;
 1919
 1920	tp = agg->context;
 1921	if (!tp)
 1922		return;
 1923
 1924	netdev = tp->netdev;
 1925	stats = &netdev->stats;
 1926	if (status) {
 1927		if (net_ratelimit())
 1928			netdev_warn(netdev, "Tx status %d\n", status);
 1929		stats->tx_errors += agg->skb_num;
 1930	} else {
 1931		stats->tx_packets += agg->skb_num;
 1932		stats->tx_bytes += agg->skb_len;
 1933	}
 1934
 1935	spin_lock_irqsave(&tp->tx_lock, flags);
 1936	list_add_tail(&agg->list, &tp->tx_free);
 1937	spin_unlock_irqrestore(&tp->tx_lock, flags);
 1938
 1939	usb_autopm_put_interface_async(tp->intf);
 1940
 1941	if (!netif_carrier_ok(netdev))
 1942		return;
 1943
 1944	if (!test_bit(WORK_ENABLE, &tp->flags))
 1945		return;
 1946
 1947	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 1948		return;
 1949
 1950	if (!skb_queue_empty(&tp->tx_queue))
 1951		tasklet_schedule(&tp->tx_tl);
 1952}
 1953
 1954static void intr_callback(struct urb *urb)
 1955{
 1956	struct r8152 *tp;
 1957	__le16 *d;
 1958	int status = urb->status;
 1959	int res;
 1960
 1961	tp = urb->context;
 1962	if (!tp)
 1963		return;
 1964
 1965	if (!test_bit(WORK_ENABLE, &tp->flags))
 1966		return;
 1967
 1968	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 1969		return;
 1970
 1971	switch (status) {
 1972	case 0:			/* success */
 1973		break;
 1974	case -ECONNRESET:	/* unlink */
 1975	case -ESHUTDOWN:
 1976		netif_device_detach(tp->netdev);
 1977		fallthrough;
 1978	case -ENOENT:
 1979	case -EPROTO:
 1980		netif_info(tp, intr, tp->netdev,
 1981			   "Stop submitting intr, status %d\n", status);
 1982		return;
 1983	case -EOVERFLOW:
 1984		if (net_ratelimit())
 1985			netif_info(tp, intr, tp->netdev,
 1986				   "intr status -EOVERFLOW\n");
 1987		goto resubmit;
 1988	/* -EPIPE:  should clear the halt */
 1989	default:
 1990		netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
 1991		goto resubmit;
 1992	}
 1993
 1994	d = urb->transfer_buffer;
 1995	if (INTR_LINK & __le16_to_cpu(d[0])) {
 1996		if (!netif_carrier_ok(tp->netdev)) {
 1997			set_bit(RTL8152_LINK_CHG, &tp->flags);
 1998			schedule_delayed_work(&tp->schedule, 0);
 1999		}
 2000	} else {
 2001		if (netif_carrier_ok(tp->netdev)) {
 2002			netif_stop_queue(tp->netdev);
 2003			set_bit(RTL8152_LINK_CHG, &tp->flags);
 2004			schedule_delayed_work(&tp->schedule, 0);
 2005		}
 2006	}
 2007
 2008resubmit:
 2009	res = usb_submit_urb(urb, GFP_ATOMIC);
 2010	if (res == -ENODEV) {
 2011		rtl_set_unplug(tp);
 2012		netif_device_detach(tp->netdev);
 2013	} else if (res) {
 2014		netif_err(tp, intr, tp->netdev,
 2015			  "can't resubmit intr, status %d\n", res);
 2016	}
 2017}
 2018
 2019static inline void *rx_agg_align(void *data)
 2020{
 2021	return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
 2022}
 2023
 2024static inline void *tx_agg_align(void *data)
 2025{
 2026	return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
 2027}
 2028
 2029static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
 2030{
 2031	list_del(&agg->info_list);
 2032
 2033	usb_free_urb(agg->urb);
 2034	put_page(agg->page);
 2035	kfree(agg);
 2036
 2037	atomic_dec(&tp->rx_count);
 2038}
 2039
 2040static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
 2041{
 2042	struct net_device *netdev = tp->netdev;
 2043	int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
 2044	unsigned int order = get_order(tp->rx_buf_sz);
 2045	struct rx_agg *rx_agg;
 2046	unsigned long flags;
 2047
 2048	rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
 2049	if (!rx_agg)
 2050		return NULL;
 2051
 2052	rx_agg->page = alloc_pages(mflags | __GFP_COMP | __GFP_NOWARN, order);
 2053	if (!rx_agg->page)
 2054		goto free_rx;
 2055
 2056	rx_agg->buffer = page_address(rx_agg->page);
 2057
 2058	rx_agg->urb = usb_alloc_urb(0, mflags);
 2059	if (!rx_agg->urb)
 2060		goto free_buf;
 2061
 2062	rx_agg->context = tp;
 2063
 2064	INIT_LIST_HEAD(&rx_agg->list);
 2065	INIT_LIST_HEAD(&rx_agg->info_list);
 2066	spin_lock_irqsave(&tp->rx_lock, flags);
 2067	list_add_tail(&rx_agg->info_list, &tp->rx_info);
 2068	spin_unlock_irqrestore(&tp->rx_lock, flags);
 2069
 2070	atomic_inc(&tp->rx_count);
 2071
 2072	return rx_agg;
 2073
 2074free_buf:
 2075	__free_pages(rx_agg->page, order);
 2076free_rx:
 2077	kfree(rx_agg);
 2078	return NULL;
 2079}
 2080
 2081static void free_all_mem(struct r8152 *tp)
 2082{
 2083	struct rx_agg *agg, *agg_next;
 2084	unsigned long flags;
 2085	int i;
 2086
 2087	spin_lock_irqsave(&tp->rx_lock, flags);
 2088
 2089	list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
 2090		free_rx_agg(tp, agg);
 2091
 2092	spin_unlock_irqrestore(&tp->rx_lock, flags);
 2093
 2094	WARN_ON(atomic_read(&tp->rx_count));
 2095
 2096	for (i = 0; i < RTL8152_MAX_TX; i++) {
 2097		usb_free_urb(tp->tx_info[i].urb);
 2098		tp->tx_info[i].urb = NULL;
 2099
 2100		kfree(tp->tx_info[i].buffer);
 2101		tp->tx_info[i].buffer = NULL;
 2102		tp->tx_info[i].head = NULL;
 2103	}
 2104
 2105	usb_free_urb(tp->intr_urb);
 2106	tp->intr_urb = NULL;
 2107
 2108	kfree(tp->intr_buff);
 2109	tp->intr_buff = NULL;
 2110}
 2111
 2112static int alloc_all_mem(struct r8152 *tp)
 2113{
 2114	struct net_device *netdev = tp->netdev;
 2115	struct usb_interface *intf = tp->intf;
 2116	struct usb_host_interface *alt = intf->cur_altsetting;
 2117	struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
 2118	int node, i;
 2119
 2120	node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
 2121
 2122	spin_lock_init(&tp->rx_lock);
 2123	spin_lock_init(&tp->tx_lock);
 2124	INIT_LIST_HEAD(&tp->rx_info);
 2125	INIT_LIST_HEAD(&tp->tx_free);
 2126	INIT_LIST_HEAD(&tp->rx_done);
 2127	skb_queue_head_init(&tp->tx_queue);
 2128	skb_queue_head_init(&tp->rx_queue);
 2129	atomic_set(&tp->rx_count, 0);
 2130
 2131	for (i = 0; i < RTL8152_MAX_RX; i++) {
 2132		if (!alloc_rx_agg(tp, GFP_KERNEL))
 2133			goto err1;
 2134	}
 2135
 2136	for (i = 0; i < RTL8152_MAX_TX; i++) {
 2137		struct urb *urb;
 2138		u8 *buf;
 2139
 2140		buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
 2141		if (!buf)
 2142			goto err1;
 2143
 2144		if (buf != tx_agg_align(buf)) {
 2145			kfree(buf);
 2146			buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
 2147					   node);
 2148			if (!buf)
 2149				goto err1;
 2150		}
 2151
 2152		urb = usb_alloc_urb(0, GFP_KERNEL);
 2153		if (!urb) {
 2154			kfree(buf);
 2155			goto err1;
 2156		}
 2157
 2158		INIT_LIST_HEAD(&tp->tx_info[i].list);
 2159		tp->tx_info[i].context = tp;
 2160		tp->tx_info[i].urb = urb;
 2161		tp->tx_info[i].buffer = buf;
 2162		tp->tx_info[i].head = tx_agg_align(buf);
 2163
 2164		list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
 2165	}
 2166
 2167	tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
 2168	if (!tp->intr_urb)
 2169		goto err1;
 2170
 2171	tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
 2172	if (!tp->intr_buff)
 2173		goto err1;
 2174
 2175	tp->intr_interval = (int)ep_intr->desc.bInterval;
 2176	usb_fill_int_urb(tp->intr_urb, tp->udev, tp->pipe_intr,
 2177			 tp->intr_buff, INTBUFSIZE, intr_callback,
 2178			 tp, tp->intr_interval);
 2179
 2180	return 0;
 2181
 2182err1:
 2183	free_all_mem(tp);
 2184	return -ENOMEM;
 2185}
 2186
 2187static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
 2188{
 2189	struct tx_agg *agg = NULL;
 2190	unsigned long flags;
 2191
 2192	if (list_empty(&tp->tx_free))
 2193		return NULL;
 2194
 2195	spin_lock_irqsave(&tp->tx_lock, flags);
 2196	if (!list_empty(&tp->tx_free)) {
 2197		struct list_head *cursor;
 2198
 2199		cursor = tp->tx_free.next;
 2200		list_del_init(cursor);
 2201		agg = list_entry(cursor, struct tx_agg, list);
 2202	}
 2203	spin_unlock_irqrestore(&tp->tx_lock, flags);
 2204
 2205	return agg;
 2206}
 2207
 2208/* r8152_csum_workaround()
 2209 * The hw limits the value of the transport offset. When the offset is out of
 2210 * range, calculate the checksum by sw.
 2211 */
 2212static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
 2213				  struct sk_buff_head *list)
 2214{
 2215	if (skb_shinfo(skb)->gso_size) {
 2216		netdev_features_t features = tp->netdev->features;
 2217		struct sk_buff *segs, *seg, *next;
 2218		struct sk_buff_head seg_list;
 
 2219
 2220		features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
 2221		segs = skb_gso_segment(skb, features);
 2222		if (IS_ERR(segs) || !segs)
 2223			goto drop;
 2224
 2225		__skb_queue_head_init(&seg_list);
 2226
 2227		skb_list_walk_safe(segs, seg, next) {
 2228			skb_mark_not_on_list(seg);
 2229			__skb_queue_tail(&seg_list, seg);
 2230		}
 
 
 2231
 2232		skb_queue_splice(&seg_list, list);
 2233		dev_kfree_skb(skb);
 2234	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 2235		if (skb_checksum_help(skb) < 0)
 2236			goto drop;
 2237
 2238		__skb_queue_head(list, skb);
 2239	} else {
 2240		struct net_device_stats *stats;
 2241
 2242drop:
 2243		stats = &tp->netdev->stats;
 2244		stats->tx_dropped++;
 2245		dev_kfree_skb(skb);
 2246	}
 2247}
 2248
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 2249static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
 2250{
 2251	if (skb_vlan_tag_present(skb)) {
 2252		u32 opts2;
 2253
 2254		opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
 2255		desc->opts2 |= cpu_to_le32(opts2);
 2256	}
 2257}
 2258
 2259static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
 2260{
 2261	u32 opts2 = le32_to_cpu(desc->opts2);
 2262
 2263	if (opts2 & RX_VLAN_TAG)
 2264		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
 2265				       swab16(opts2 & 0xffff));
 2266}
 2267
 2268static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
 2269			 struct sk_buff *skb, u32 len)
 2270{
 2271	u32 mss = skb_shinfo(skb)->gso_size;
 2272	u32 opts1, opts2 = 0;
 2273	int ret = TX_CSUM_SUCCESS;
 2274
 2275	WARN_ON_ONCE(len > TX_LEN_MAX);
 2276
 2277	opts1 = len | TX_FS | TX_LS;
 2278
 2279	if (mss) {
 2280		u32 transport_offset = (u32)skb_transport_offset(skb);
 2281
 2282		if (transport_offset > GTTCPHO_MAX) {
 2283			netif_warn(tp, tx_err, tp->netdev,
 2284				   "Invalid transport offset 0x%x for TSO\n",
 2285				   transport_offset);
 2286			ret = TX_CSUM_TSO;
 2287			goto unavailable;
 2288		}
 2289
 2290		switch (vlan_get_protocol(skb)) {
 2291		case htons(ETH_P_IP):
 2292			opts1 |= GTSENDV4;
 2293			break;
 2294
 2295		case htons(ETH_P_IPV6):
 2296			if (skb_cow_head(skb, 0)) {
 2297				ret = TX_CSUM_TSO;
 2298				goto unavailable;
 2299			}
 2300			tcp_v6_gso_csum_prep(skb);
 2301			opts1 |= GTSENDV6;
 2302			break;
 2303
 2304		default:
 2305			WARN_ON_ONCE(1);
 2306			break;
 2307		}
 2308
 2309		opts1 |= transport_offset << GTTCPHO_SHIFT;
 2310		opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
 2311	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 2312		u32 transport_offset = (u32)skb_transport_offset(skb);
 2313		u8 ip_protocol;
 2314
 2315		if (transport_offset > TCPHO_MAX) {
 2316			netif_warn(tp, tx_err, tp->netdev,
 2317				   "Invalid transport offset 0x%x\n",
 2318				   transport_offset);
 2319			ret = TX_CSUM_NONE;
 2320			goto unavailable;
 2321		}
 2322
 2323		switch (vlan_get_protocol(skb)) {
 2324		case htons(ETH_P_IP):
 2325			opts2 |= IPV4_CS;
 2326			ip_protocol = ip_hdr(skb)->protocol;
 2327			break;
 2328
 2329		case htons(ETH_P_IPV6):
 2330			opts2 |= IPV6_CS;
 2331			ip_protocol = ipv6_hdr(skb)->nexthdr;
 2332			break;
 2333
 2334		default:
 2335			ip_protocol = IPPROTO_RAW;
 2336			break;
 2337		}
 2338
 2339		if (ip_protocol == IPPROTO_TCP)
 2340			opts2 |= TCP_CS;
 2341		else if (ip_protocol == IPPROTO_UDP)
 2342			opts2 |= UDP_CS;
 2343		else
 2344			WARN_ON_ONCE(1);
 2345
 2346		opts2 |= transport_offset << TCPHO_SHIFT;
 2347	}
 2348
 2349	desc->opts2 = cpu_to_le32(opts2);
 2350	desc->opts1 = cpu_to_le32(opts1);
 2351
 2352unavailable:
 2353	return ret;
 2354}
 2355
 2356static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
 2357{
 2358	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
 2359	int remain, ret;
 2360	u8 *tx_data;
 2361
 2362	__skb_queue_head_init(&skb_head);
 2363	spin_lock(&tx_queue->lock);
 2364	skb_queue_splice_init(tx_queue, &skb_head);
 2365	spin_unlock(&tx_queue->lock);
 2366
 2367	tx_data = agg->head;
 2368	agg->skb_num = 0;
 2369	agg->skb_len = 0;
 2370	remain = agg_buf_sz;
 2371
 2372	while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
 2373		struct tx_desc *tx_desc;
 2374		struct sk_buff *skb;
 2375		unsigned int len;
 
 2376
 2377		skb = __skb_dequeue(&skb_head);
 2378		if (!skb)
 2379			break;
 2380
 2381		len = skb->len + sizeof(*tx_desc);
 2382
 2383		if (len > remain) {
 2384			__skb_queue_head(&skb_head, skb);
 2385			break;
 2386		}
 2387
 2388		tx_data = tx_agg_align(tx_data);
 2389		tx_desc = (struct tx_desc *)tx_data;
 2390
 2391		if (r8152_tx_csum(tp, tx_desc, skb, skb->len)) {
 
 
 2392			r8152_csum_workaround(tp, skb, &skb_head);
 2393			continue;
 2394		}
 2395
 2396		rtl_tx_vlan_tag(tx_desc, skb);
 2397
 2398		tx_data += sizeof(*tx_desc);
 2399
 2400		len = skb->len;
 2401		if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
 2402			struct net_device_stats *stats = &tp->netdev->stats;
 2403
 2404			stats->tx_dropped++;
 2405			dev_kfree_skb_any(skb);
 2406			tx_data -= sizeof(*tx_desc);
 2407			continue;
 2408		}
 2409
 2410		tx_data += len;
 2411		agg->skb_len += len;
 2412		agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
 2413
 2414		dev_kfree_skb_any(skb);
 2415
 2416		remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
 2417
 2418		if (tp->dell_tb_rx_agg_bug)
 2419			break;
 2420	}
 2421
 2422	if (!skb_queue_empty(&skb_head)) {
 2423		spin_lock(&tx_queue->lock);
 2424		skb_queue_splice(&skb_head, tx_queue);
 2425		spin_unlock(&tx_queue->lock);
 2426	}
 2427
 2428	netif_tx_lock(tp->netdev);
 2429
 2430	if (netif_queue_stopped(tp->netdev) &&
 2431	    skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
 2432		netif_wake_queue(tp->netdev);
 2433
 2434	netif_tx_unlock(tp->netdev);
 2435
 2436	ret = usb_autopm_get_interface_async(tp->intf);
 2437	if (ret < 0)
 2438		goto out_tx_fill;
 2439
 2440	usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_out,
 2441			  agg->head, (int)(tx_data - (u8 *)agg->head),
 2442			  (usb_complete_t)write_bulk_callback, agg);
 2443
 2444	ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
 2445	if (ret < 0)
 2446		usb_autopm_put_interface_async(tp->intf);
 2447
 2448out_tx_fill:
 2449	return ret;
 2450}
 2451
 2452static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
 2453{
 2454	u8 checksum = CHECKSUM_NONE;
 2455	u32 opts2, opts3;
 2456
 2457	if (!(tp->netdev->features & NETIF_F_RXCSUM))
 2458		goto return_result;
 2459
 2460	opts2 = le32_to_cpu(rx_desc->opts2);
 2461	opts3 = le32_to_cpu(rx_desc->opts3);
 2462
 2463	if (opts2 & RD_IPV4_CS) {
 2464		if (opts3 & IPF)
 2465			checksum = CHECKSUM_NONE;
 2466		else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
 2467			checksum = CHECKSUM_UNNECESSARY;
 2468		else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
 2469			checksum = CHECKSUM_UNNECESSARY;
 2470	} else if (opts2 & RD_IPV6_CS) {
 2471		if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
 2472			checksum = CHECKSUM_UNNECESSARY;
 2473		else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
 2474			checksum = CHECKSUM_UNNECESSARY;
 2475	}
 2476
 2477return_result:
 2478	return checksum;
 2479}
 2480
 2481static inline bool rx_count_exceed(struct r8152 *tp)
 2482{
 2483	return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
 2484}
 2485
 2486static inline int agg_offset(struct rx_agg *agg, void *addr)
 2487{
 2488	return (int)(addr - agg->buffer);
 2489}
 2490
 2491static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
 2492{
 2493	struct rx_agg *agg, *agg_next, *agg_free = NULL;
 2494	unsigned long flags;
 2495
 2496	spin_lock_irqsave(&tp->rx_lock, flags);
 2497
 2498	list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
 2499		if (page_count(agg->page) == 1) {
 2500			if (!agg_free) {
 2501				list_del_init(&agg->list);
 2502				agg_free = agg;
 2503				continue;
 2504			}
 2505			if (rx_count_exceed(tp)) {
 2506				list_del_init(&agg->list);
 2507				free_rx_agg(tp, agg);
 2508			}
 2509			break;
 2510		}
 2511	}
 2512
 2513	spin_unlock_irqrestore(&tp->rx_lock, flags);
 2514
 2515	if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
 2516		agg_free = alloc_rx_agg(tp, mflags);
 2517
 2518	return agg_free;
 2519}
 2520
 2521static int rx_bottom(struct r8152 *tp, int budget)
 2522{
 2523	unsigned long flags;
 2524	struct list_head *cursor, *next, rx_queue;
 2525	int ret = 0, work_done = 0;
 2526	struct napi_struct *napi = &tp->napi;
 2527
 2528	if (!skb_queue_empty(&tp->rx_queue)) {
 2529		while (work_done < budget) {
 2530			struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
 2531			struct net_device *netdev = tp->netdev;
 2532			struct net_device_stats *stats = &netdev->stats;
 2533			unsigned int pkt_len;
 2534
 2535			if (!skb)
 2536				break;
 2537
 2538			pkt_len = skb->len;
 2539			napi_gro_receive(napi, skb);
 2540			work_done++;
 2541			stats->rx_packets++;
 2542			stats->rx_bytes += pkt_len;
 2543		}
 2544	}
 2545
 2546	if (list_empty(&tp->rx_done) || work_done >= budget)
 2547		goto out1;
 2548
 2549	clear_bit(RX_EPROTO, &tp->flags);
 2550	INIT_LIST_HEAD(&rx_queue);
 2551	spin_lock_irqsave(&tp->rx_lock, flags);
 2552	list_splice_init(&tp->rx_done, &rx_queue);
 2553	spin_unlock_irqrestore(&tp->rx_lock, flags);
 2554
 2555	list_for_each_safe(cursor, next, &rx_queue) {
 2556		struct rx_desc *rx_desc;
 2557		struct rx_agg *agg, *agg_free;
 2558		int len_used = 0;
 2559		struct urb *urb;
 2560		u8 *rx_data;
 2561
 2562		/* A bulk transfer of USB may contain may packets, so the
 2563		 * total packets may more than the budget. Deal with all
 2564		 * packets in current bulk transfer, and stop to handle the
 2565		 * next bulk transfer until next schedule, if budget is
 2566		 * exhausted.
 2567		 */
 2568		if (work_done >= budget)
 2569			break;
 2570
 2571		list_del_init(cursor);
 2572
 2573		agg = list_entry(cursor, struct rx_agg, list);
 2574		urb = agg->urb;
 2575		if (urb->status != 0 || urb->actual_length < ETH_ZLEN)
 2576			goto submit;
 2577
 2578		agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
 2579
 2580		rx_desc = agg->buffer;
 2581		rx_data = agg->buffer;
 2582		len_used += sizeof(struct rx_desc);
 2583
 2584		while (urb->actual_length > len_used) {
 2585			struct net_device *netdev = tp->netdev;
 2586			struct net_device_stats *stats = &netdev->stats;
 2587			unsigned int pkt_len, rx_frag_head_sz, len;
 2588			struct sk_buff *skb;
 2589			bool use_frags;
 2590
 2591			WARN_ON_ONCE(skb_queue_len(&tp->rx_queue) >= 1000);
 
 
 2592
 2593			pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
 2594			if (pkt_len < ETH_ZLEN)
 2595				break;
 2596
 2597			len_used += pkt_len;
 2598			if (urb->actual_length < len_used)
 2599				break;
 2600
 2601			pkt_len -= ETH_FCS_LEN;
 2602			len = pkt_len;
 2603			rx_data += sizeof(struct rx_desc);
 2604
 2605			if (!agg_free || tp->rx_copybreak > len)
 2606				use_frags = false;
 2607			else
 2608				use_frags = true;
 2609
 2610			if (use_frags) {
 2611				/* If the budget is exhausted, the packet
 2612				 * would be queued in the driver. That is,
 2613				 * napi_gro_frags() wouldn't be called, so
 2614				 * we couldn't use napi_get_frags().
 2615				 */
 2616				if (work_done >= budget) {
 2617					rx_frag_head_sz = tp->rx_copybreak;
 2618					skb = napi_alloc_skb(napi,
 2619							     rx_frag_head_sz);
 2620				} else {
 2621					rx_frag_head_sz = 0;
 2622					skb = napi_get_frags(napi);
 2623				}
 2624			} else {
 2625				rx_frag_head_sz = 0;
 2626				skb = napi_alloc_skb(napi, len);
 2627			}
 2628
 
 2629			if (!skb) {
 2630				stats->rx_dropped++;
 2631				goto find_next_rx;
 2632			}
 2633
 2634			skb->ip_summed = r8152_rx_csum(tp, rx_desc);
 2635			rtl_rx_vlan_tag(rx_desc, skb);
 2636
 2637			if (use_frags) {
 2638				if (rx_frag_head_sz) {
 2639					memcpy(skb->data, rx_data,
 2640					       rx_frag_head_sz);
 2641					skb_put(skb, rx_frag_head_sz);
 2642					len -= rx_frag_head_sz;
 2643					rx_data += rx_frag_head_sz;
 2644					skb->protocol = eth_type_trans(skb,
 2645								       netdev);
 2646				}
 2647
 2648				skb_add_rx_frag(skb, 0, agg->page,
 2649						agg_offset(agg, rx_data),
 2650						len, SKB_DATA_ALIGN(len));
 
 2651				get_page(agg->page);
 2652			} else {
 2653				memcpy(skb->data, rx_data, len);
 2654				skb_put(skb, len);
 2655				skb->protocol = eth_type_trans(skb, netdev);
 2656			}
 2657
 
 
 2658			if (work_done < budget) {
 2659				if (use_frags)
 2660					napi_gro_frags(napi);
 2661				else
 2662					napi_gro_receive(napi, skb);
 2663
 2664				work_done++;
 2665				stats->rx_packets++;
 2666				stats->rx_bytes += pkt_len;
 
 2667			} else {
 2668				__skb_queue_tail(&tp->rx_queue, skb);
 2669			}
 2670
 2671find_next_rx:
 2672			rx_data = rx_agg_align(rx_data + len + ETH_FCS_LEN);
 2673			rx_desc = (struct rx_desc *)rx_data;
 2674			len_used = agg_offset(agg, rx_data);
 2675			len_used += sizeof(struct rx_desc);
 2676		}
 2677
 2678		WARN_ON(!agg_free && page_count(agg->page) > 1);
 2679
 2680		if (agg_free) {
 2681			spin_lock_irqsave(&tp->rx_lock, flags);
 2682			if (page_count(agg->page) == 1) {
 2683				list_add(&agg_free->list, &tp->rx_used);
 2684			} else {
 2685				list_add_tail(&agg->list, &tp->rx_used);
 2686				agg = agg_free;
 2687				urb = agg->urb;
 2688			}
 2689			spin_unlock_irqrestore(&tp->rx_lock, flags);
 2690		}
 2691
 2692submit:
 2693		if (!ret) {
 2694			ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
 2695		} else {
 2696			urb->actual_length = 0;
 2697			list_add_tail(&agg->list, next);
 2698		}
 2699	}
 2700
 2701	/* Splice the remained list back to rx_done for next schedule */
 2702	if (!list_empty(&rx_queue)) {
 2703		spin_lock_irqsave(&tp->rx_lock, flags);
 2704		list_splice(&rx_queue, &tp->rx_done);
 2705		spin_unlock_irqrestore(&tp->rx_lock, flags);
 2706	}
 2707
 2708out1:
 2709	return work_done;
 2710}
 2711
 2712static void tx_bottom(struct r8152 *tp)
 2713{
 2714	int res;
 2715
 2716	do {
 2717		struct net_device *netdev = tp->netdev;
 2718		struct tx_agg *agg;
 2719
 2720		if (skb_queue_empty(&tp->tx_queue))
 2721			break;
 2722
 2723		agg = r8152_get_tx_agg(tp);
 2724		if (!agg)
 2725			break;
 2726
 2727		res = r8152_tx_agg_fill(tp, agg);
 2728		if (!res)
 2729			continue;
 2730
 2731		if (res == -ENODEV) {
 2732			rtl_set_unplug(tp);
 2733			netif_device_detach(netdev);
 2734		} else {
 2735			struct net_device_stats *stats = &netdev->stats;
 2736			unsigned long flags;
 2737
 2738			netif_warn(tp, tx_err, netdev,
 2739				   "failed tx_urb %d\n", res);
 2740			stats->tx_dropped += agg->skb_num;
 2741
 2742			spin_lock_irqsave(&tp->tx_lock, flags);
 2743			list_add_tail(&agg->list, &tp->tx_free);
 2744			spin_unlock_irqrestore(&tp->tx_lock, flags);
 
 2745		}
 2746	} while (res == 0);
 2747}
 2748
 2749static void bottom_half(struct tasklet_struct *t)
 2750{
 2751	struct r8152 *tp = from_tasklet(tp, t, tx_tl);
 2752
 2753	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 
 
 2754		return;
 2755
 2756	if (!test_bit(WORK_ENABLE, &tp->flags))
 2757		return;
 2758
 2759	/* When link down, the driver would cancel all bulks. */
 2760	/* This avoid the re-submitting bulk */
 2761	if (!netif_carrier_ok(tp->netdev))
 2762		return;
 2763
 2764	clear_bit(SCHEDULE_TASKLET, &tp->flags);
 2765
 2766	tx_bottom(tp);
 2767}
 2768
 2769static int r8152_poll(struct napi_struct *napi, int budget)
 2770{
 2771	struct r8152 *tp = container_of(napi, struct r8152, napi);
 2772	int work_done;
 2773
 2774	if (!budget)
 2775		return 0;
 2776
 2777	work_done = rx_bottom(tp, budget);
 2778
 2779	if (work_done < budget) {
 2780		if (!napi_complete_done(napi, work_done))
 2781			goto out;
 2782		if (!list_empty(&tp->rx_done))
 2783			napi_schedule(napi);
 2784	}
 2785
 2786out:
 2787	return work_done;
 2788}
 2789
 2790static
 2791int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
 2792{
 2793	int ret;
 2794
 2795	/* The rx would be stopped, so skip submitting */
 2796	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) ||
 2797	    !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
 2798		return 0;
 2799
 2800	usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_in,
 2801			  agg->buffer, tp->rx_buf_sz,
 2802			  (usb_complete_t)read_bulk_callback, agg);
 2803
 2804	ret = usb_submit_urb(agg->urb, mem_flags);
 2805	if (ret == -ENODEV) {
 2806		rtl_set_unplug(tp);
 2807		netif_device_detach(tp->netdev);
 2808	} else if (ret) {
 2809		struct urb *urb = agg->urb;
 2810		unsigned long flags;
 2811
 2812		urb->actual_length = 0;
 2813		spin_lock_irqsave(&tp->rx_lock, flags);
 2814		list_add_tail(&agg->list, &tp->rx_done);
 2815		spin_unlock_irqrestore(&tp->rx_lock, flags);
 2816
 2817		netif_err(tp, rx_err, tp->netdev,
 2818			  "Couldn't submit rx[%p], ret = %d\n", agg, ret);
 2819
 2820		napi_schedule(&tp->napi);
 2821	}
 2822
 2823	return ret;
 2824}
 2825
 2826static void rtl_drop_queued_tx(struct r8152 *tp)
 2827{
 2828	struct net_device_stats *stats = &tp->netdev->stats;
 2829	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
 2830	struct sk_buff *skb;
 2831
 2832	if (skb_queue_empty(tx_queue))
 2833		return;
 2834
 2835	__skb_queue_head_init(&skb_head);
 2836	spin_lock_bh(&tx_queue->lock);
 2837	skb_queue_splice_init(tx_queue, &skb_head);
 2838	spin_unlock_bh(&tx_queue->lock);
 2839
 2840	while ((skb = __skb_dequeue(&skb_head))) {
 2841		dev_kfree_skb(skb);
 2842		stats->tx_dropped++;
 2843	}
 2844}
 2845
 2846static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
 2847{
 2848	struct r8152 *tp = netdev_priv(netdev);
 2849
 2850	netif_warn(tp, tx_err, netdev, "Tx timeout\n");
 2851
 2852	usb_queue_reset_device(tp->intf);
 2853}
 2854
 2855static void rtl8152_set_rx_mode(struct net_device *netdev)
 2856{
 2857	struct r8152 *tp = netdev_priv(netdev);
 2858
 2859	if (netif_carrier_ok(netdev)) {
 2860		set_bit(RTL8152_SET_RX_MODE, &tp->flags);
 2861		schedule_delayed_work(&tp->schedule, 0);
 2862	}
 2863}
 2864
 2865static void _rtl8152_set_rx_mode(struct net_device *netdev)
 2866{
 2867	struct r8152 *tp = netdev_priv(netdev);
 2868	u32 mc_filter[2];	/* Multicast hash filter */
 2869	__le32 tmp[2];
 2870	u32 ocp_data;
 2871
 2872	netif_stop_queue(netdev);
 2873	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
 2874	ocp_data &= ~RCR_ACPT_ALL;
 2875	ocp_data |= RCR_AB | RCR_APM;
 2876
 2877	if (netdev->flags & IFF_PROMISC) {
 2878		/* Unconditionally log net taps. */
 2879		netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
 2880		ocp_data |= RCR_AM | RCR_AAP;
 2881		mc_filter[1] = 0xffffffff;
 2882		mc_filter[0] = 0xffffffff;
 2883	} else if ((netdev->flags & IFF_MULTICAST &&
 2884				netdev_mc_count(netdev) > multicast_filter_limit) ||
 2885			   (netdev->flags & IFF_ALLMULTI)) {
 2886		/* Too many to filter perfectly -- accept all multicasts. */
 2887		ocp_data |= RCR_AM;
 2888		mc_filter[1] = 0xffffffff;
 2889		mc_filter[0] = 0xffffffff;
 2890	} else {
 
 
 2891		mc_filter[1] = 0;
 2892		mc_filter[0] = 0;
 
 
 2893
 2894		if (netdev->flags & IFF_MULTICAST) {
 2895			struct netdev_hw_addr *ha;
 2896
 2897			netdev_for_each_mc_addr(ha, netdev) {
 2898				int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
 2899
 2900				mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
 2901				ocp_data |= RCR_AM;
 2902			}
 2903		}
 2904	}
 2905
 2906	tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
 2907	tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
 2908
 2909	pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
 2910	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
 2911	netif_wake_queue(netdev);
 2912}
 2913
 2914static netdev_features_t
 2915rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
 2916		       netdev_features_t features)
 2917{
 2918	u32 mss = skb_shinfo(skb)->gso_size;
 2919	int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
 
 2920
 2921	if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) &&
 2922	    skb_transport_offset(skb) > max_offset)
 2923		features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
 2924	else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
 2925		features &= ~NETIF_F_GSO_MASK;
 2926
 2927	return features;
 2928}
 2929
 2930static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
 2931				      struct net_device *netdev)
 2932{
 2933	struct r8152 *tp = netdev_priv(netdev);
 2934
 2935	skb_tx_timestamp(skb);
 2936
 2937	skb_queue_tail(&tp->tx_queue, skb);
 2938
 2939	if (!list_empty(&tp->tx_free)) {
 2940		if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
 2941			set_bit(SCHEDULE_TASKLET, &tp->flags);
 2942			schedule_delayed_work(&tp->schedule, 0);
 2943		} else {
 2944			usb_mark_last_busy(tp->udev);
 2945			tasklet_schedule(&tp->tx_tl);
 2946		}
 2947	} else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
 2948		netif_stop_queue(netdev);
 2949	}
 2950
 2951	return NETDEV_TX_OK;
 2952}
 2953
 2954static void r8152b_reset_packet_filter(struct r8152 *tp)
 2955{
 2956	u32 ocp_data;
 2957
 2958	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
 2959	ocp_data &= ~FMC_FCR_MCU_EN;
 2960	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
 2961	ocp_data |= FMC_FCR_MCU_EN;
 2962	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
 2963}
 2964
 2965static void rtl8152_nic_reset(struct r8152 *tp)
 2966{
 2967	u32 ocp_data;
 2968	int i;
 2969
 2970	switch (tp->version) {
 2971	case RTL_TEST_01:
 2972	case RTL_VER_10:
 2973	case RTL_VER_11:
 2974		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
 2975		ocp_data &= ~CR_TE;
 2976		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
 2977
 2978		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
 2979		ocp_data &= ~BMU_RESET_EP_IN;
 2980		ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
 2981
 2982		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
 2983		ocp_data |= CDC_ECM_EN;
 2984		ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
 2985
 2986		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
 2987		ocp_data &= ~CR_RE;
 2988		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
 2989
 2990		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
 2991		ocp_data |= BMU_RESET_EP_IN;
 2992		ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
 2993
 2994		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
 2995		ocp_data &= ~CDC_ECM_EN;
 2996		ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
 2997		break;
 2998
 2999	default:
 3000		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
 3001
 3002		for (i = 0; i < 1000; i++) {
 3003			if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 3004				break;
 3005			if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
 3006				break;
 3007			usleep_range(100, 400);
 3008		}
 3009		break;
 3010	}
 3011}
 3012
 3013static void set_tx_qlen(struct r8152 *tp)
 3014{
 3015	tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));
 
 
 
 3016}
 3017
 3018static inline u16 rtl8152_get_speed(struct r8152 *tp)
 3019{
 3020	return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
 3021}
 3022
 3023static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
 3024{
 3025	u32 ocp_data;
 
 3026
 3027	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
 3028	if (enable)
 
 3029		ocp_data |= EEEP_CR_EEEP_TX;
 3030	else
 
 
 3031		ocp_data &= ~EEEP_CR_EEEP_TX;
 3032	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
 3033}
 3034
 3035static void rtl_set_eee_plus(struct r8152 *tp)
 3036{
 3037	if (rtl8152_get_speed(tp) & _10bps)
 3038		rtl_eee_plus_en(tp, true);
 3039	else
 3040		rtl_eee_plus_en(tp, false);
 3041}
 3042
 3043static void rxdy_gated_en(struct r8152 *tp, bool enable)
 3044{
 3045	u32 ocp_data;
 3046
 3047	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
 3048	if (enable)
 3049		ocp_data |= RXDY_GATED_EN;
 3050	else
 3051		ocp_data &= ~RXDY_GATED_EN;
 3052	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
 3053}
 3054
 3055static int rtl_start_rx(struct r8152 *tp)
 3056{
 3057	struct rx_agg *agg, *agg_next;
 3058	struct list_head tmp_list;
 3059	unsigned long flags;
 3060	int ret = 0, i = 0;
 3061
 3062	INIT_LIST_HEAD(&tmp_list);
 3063
 3064	spin_lock_irqsave(&tp->rx_lock, flags);
 3065
 3066	INIT_LIST_HEAD(&tp->rx_done);
 3067	INIT_LIST_HEAD(&tp->rx_used);
 3068
 3069	list_splice_init(&tp->rx_info, &tmp_list);
 3070
 3071	spin_unlock_irqrestore(&tp->rx_lock, flags);
 3072
 3073	list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
 3074		INIT_LIST_HEAD(&agg->list);
 3075
 3076		/* Only RTL8152_MAX_RX rx_agg need to be submitted. */
 3077		if (++i > RTL8152_MAX_RX) {
 3078			spin_lock_irqsave(&tp->rx_lock, flags);
 3079			list_add_tail(&agg->list, &tp->rx_used);
 3080			spin_unlock_irqrestore(&tp->rx_lock, flags);
 3081		} else if (unlikely(ret < 0)) {
 3082			spin_lock_irqsave(&tp->rx_lock, flags);
 3083			list_add_tail(&agg->list, &tp->rx_done);
 3084			spin_unlock_irqrestore(&tp->rx_lock, flags);
 3085		} else {
 3086			ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
 3087		}
 3088	}
 3089
 3090	spin_lock_irqsave(&tp->rx_lock, flags);
 3091	WARN_ON(!list_empty(&tp->rx_info));
 3092	list_splice(&tmp_list, &tp->rx_info);
 3093	spin_unlock_irqrestore(&tp->rx_lock, flags);
 3094
 3095	return ret;
 3096}
 3097
 3098static int rtl_stop_rx(struct r8152 *tp)
 3099{
 3100	struct rx_agg *agg, *agg_next;
 3101	struct list_head tmp_list;
 3102	unsigned long flags;
 3103
 3104	INIT_LIST_HEAD(&tmp_list);
 3105
 3106	/* The usb_kill_urb() couldn't be used in atomic.
 3107	 * Therefore, move the list of rx_info to a tmp one.
 3108	 * Then, list_for_each_entry_safe could be used without
 3109	 * spin lock.
 3110	 */
 3111
 3112	spin_lock_irqsave(&tp->rx_lock, flags);
 3113	list_splice_init(&tp->rx_info, &tmp_list);
 3114	spin_unlock_irqrestore(&tp->rx_lock, flags);
 3115
 3116	list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
 3117		/* At least RTL8152_MAX_RX rx_agg have the page_count being
 3118		 * equal to 1, so the other ones could be freed safely.
 3119		 */
 3120		if (page_count(agg->page) > 1)
 3121			free_rx_agg(tp, agg);
 3122		else
 3123			usb_kill_urb(agg->urb);
 3124	}
 3125
 3126	/* Move back the list of temp to the rx_info */
 3127	spin_lock_irqsave(&tp->rx_lock, flags);
 3128	WARN_ON(!list_empty(&tp->rx_info));
 3129	list_splice(&tmp_list, &tp->rx_info);
 3130	spin_unlock_irqrestore(&tp->rx_lock, flags);
 3131
 3132	while (!skb_queue_empty(&tp->rx_queue))
 3133		dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
 3134
 3135	return 0;
 3136}
 3137
 3138static void rtl_set_ifg(struct r8152 *tp, u16 speed)
 3139{
 3140	u32 ocp_data;
 3141
 3142	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
 3143	ocp_data &= ~IFG_MASK;
 3144	if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) {
 3145		ocp_data |= IFG_144NS;
 3146		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
 3147
 3148		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
 3149		ocp_data &= ~TX10MIDLE_EN;
 3150		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
 3151	} else {
 3152		ocp_data |= IFG_96NS;
 3153		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
 3154
 3155		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
 3156		ocp_data |= TX10MIDLE_EN;
 3157		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
 3158	}
 3159}
 3160
 3161static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
 3162{
 3163	ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
 3164		       OWN_UPDATE | OWN_CLEAR);
 3165}
 3166
 3167static int rtl_enable(struct r8152 *tp)
 3168{
 3169	u32 ocp_data;
 3170
 3171	r8152b_reset_packet_filter(tp);
 3172
 3173	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
 3174	ocp_data |= CR_RE | CR_TE;
 3175	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
 3176
 3177	switch (tp->version) {
 3178	case RTL_VER_01:
 3179	case RTL_VER_02:
 3180	case RTL_VER_03:
 3181	case RTL_VER_04:
 3182	case RTL_VER_05:
 3183	case RTL_VER_06:
 3184	case RTL_VER_07:
 3185		break;
 3186	default:
 3187		r8153b_rx_agg_chg_indicate(tp);
 3188		break;
 3189	}
 3190
 3191	rxdy_gated_en(tp, false);
 3192
 3193	return 0;
 3194}
 3195
 3196static int rtl8152_enable(struct r8152 *tp)
 3197{
 3198	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 3199		return -ENODEV;
 3200
 3201	set_tx_qlen(tp);
 3202	rtl_set_eee_plus(tp);
 3203
 3204	return rtl_enable(tp);
 3205}
 3206
 3207static void r8153_set_rx_early_timeout(struct r8152 *tp)
 3208{
 3209	u32 ocp_data = tp->coalesce / 8;
 3210
 3211	switch (tp->version) {
 3212	case RTL_VER_03:
 3213	case RTL_VER_04:
 3214	case RTL_VER_05:
 3215	case RTL_VER_06:
 3216		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
 3217			       ocp_data);
 3218		break;
 3219
 3220	case RTL_VER_08:
 3221	case RTL_VER_09:
 3222	case RTL_VER_14:
 3223		/* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
 3224		 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
 3225		 */
 3226		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
 3227			       128 / 8);
 3228		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
 3229			       ocp_data);
 3230		break;
 3231
 3232	case RTL_VER_10:
 3233	case RTL_VER_11:
 3234	case RTL_VER_12:
 3235	case RTL_VER_13:
 3236	case RTL_VER_15:
 3237		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
 3238			       640 / 8);
 3239		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
 3240			       ocp_data);
 3241		break;
 3242
 3243	default:
 3244		break;
 3245	}
 3246}
 3247
 3248static void r8153_set_rx_early_size(struct r8152 *tp)
 3249{
 3250	u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
 3251
 3252	switch (tp->version) {
 3253	case RTL_VER_03:
 3254	case RTL_VER_04:
 3255	case RTL_VER_05:
 3256	case RTL_VER_06:
 3257		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
 3258			       ocp_data / 4);
 3259		break;
 3260	case RTL_VER_08:
 3261	case RTL_VER_09:
 3262	case RTL_VER_14:
 3263		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
 3264			       ocp_data / 8);
 3265		break;
 3266	case RTL_TEST_01:
 3267	case RTL_VER_10:
 3268	case RTL_VER_11:
 3269	case RTL_VER_12:
 3270	case RTL_VER_13:
 3271	case RTL_VER_15:
 3272		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
 3273			       ocp_data / 8);
 3274		break;
 3275	default:
 3276		WARN_ON_ONCE(1);
 3277		break;
 3278	}
 3279}
 3280
 3281static int rtl8153_enable(struct r8152 *tp)
 3282{
 3283	u32 ocp_data;
 3284
 3285	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 3286		return -ENODEV;
 3287
 3288	set_tx_qlen(tp);
 3289	rtl_set_eee_plus(tp);
 3290	r8153_set_rx_early_timeout(tp);
 3291	r8153_set_rx_early_size(tp);
 3292
 3293	rtl_set_ifg(tp, rtl8152_get_speed(tp));
 3294
 3295	switch (tp->version) {
 3296	case RTL_VER_09:
 3297	case RTL_VER_14:
 3298		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
 3299		ocp_data &= ~FC_PATCH_TASK;
 3300		ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
 3301		usleep_range(1000, 2000);
 3302		ocp_data |= FC_PATCH_TASK;
 3303		ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
 3304		break;
 3305	default:
 3306		break;
 3307	}
 3308
 3309	return rtl_enable(tp);
 3310}
 3311
 3312static void rtl_disable(struct r8152 *tp)
 3313{
 3314	u32 ocp_data;
 3315	int i;
 3316
 3317	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
 3318		rtl_drop_queued_tx(tp);
 3319		return;
 3320	}
 3321
 3322	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
 3323	ocp_data &= ~RCR_ACPT_ALL;
 3324	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
 3325
 3326	rtl_drop_queued_tx(tp);
 3327
 3328	for (i = 0; i < RTL8152_MAX_TX; i++)
 3329		usb_kill_urb(tp->tx_info[i].urb);
 3330
 3331	rxdy_gated_en(tp, true);
 3332
 3333	for (i = 0; i < 1000; i++) {
 3334		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 3335			break;
 3336		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
 3337		if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
 3338			break;
 3339		usleep_range(1000, 2000);
 3340	}
 3341
 3342	for (i = 0; i < 1000; i++) {
 3343		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 3344			break;
 3345		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
 3346			break;
 3347		usleep_range(1000, 2000);
 3348	}
 3349
 3350	rtl_stop_rx(tp);
 3351
 3352	rtl8152_nic_reset(tp);
 3353}
 3354
 3355static void r8152_power_cut_en(struct r8152 *tp, bool enable)
 3356{
 3357	u32 ocp_data;
 3358
 3359	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
 3360	if (enable)
 3361		ocp_data |= POWER_CUT;
 3362	else
 3363		ocp_data &= ~POWER_CUT;
 3364	ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
 3365
 3366	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
 3367	ocp_data &= ~RESUME_INDICATE;
 3368	ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
 3369}
 3370
 3371static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
 3372{
 3373	u32 ocp_data;
 3374
 3375	switch (tp->version) {
 3376	case RTL_VER_01:
 3377	case RTL_VER_02:
 3378	case RTL_VER_03:
 3379	case RTL_VER_04:
 3380	case RTL_VER_05:
 3381	case RTL_VER_06:
 3382	case RTL_VER_07:
 3383	case RTL_VER_08:
 3384	case RTL_VER_09:
 3385	case RTL_VER_14:
 3386		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
 3387		if (enable)
 3388			ocp_data |= CPCR_RX_VLAN;
 3389		else
 3390			ocp_data &= ~CPCR_RX_VLAN;
 3391		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
 3392		break;
 3393
 3394	case RTL_TEST_01:
 3395	case RTL_VER_10:
 3396	case RTL_VER_11:
 3397	case RTL_VER_12:
 3398	case RTL_VER_13:
 3399	case RTL_VER_15:
 3400	default:
 3401		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);
 3402		if (enable)
 3403			ocp_data |= OUTER_VLAN | INNER_VLAN;
 3404		else
 3405			ocp_data &= ~(OUTER_VLAN | INNER_VLAN);
 3406		ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data);
 3407		break;
 3408	}
 3409}
 3410
 3411static int rtl8152_set_features(struct net_device *dev,
 3412				netdev_features_t features)
 3413{
 3414	netdev_features_t changed = features ^ dev->features;
 3415	struct r8152 *tp = netdev_priv(dev);
 3416	int ret;
 3417
 3418	ret = usb_autopm_get_interface(tp->intf);
 3419	if (ret < 0)
 3420		goto out;
 3421
 3422	mutex_lock(&tp->control);
 3423
 3424	if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
 3425		if (features & NETIF_F_HW_VLAN_CTAG_RX)
 3426			rtl_rx_vlan_en(tp, true);
 3427		else
 3428			rtl_rx_vlan_en(tp, false);
 3429	}
 3430
 3431	mutex_unlock(&tp->control);
 3432
 3433	usb_autopm_put_interface(tp->intf);
 3434
 3435out:
 3436	return ret;
 3437}
 3438
 3439#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 3440
 3441static u32 __rtl_get_wol(struct r8152 *tp)
 3442{
 3443	u32 ocp_data;
 3444	u32 wolopts = 0;
 3445
 3446	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
 3447	if (ocp_data & LINK_ON_WAKE_EN)
 3448		wolopts |= WAKE_PHY;
 3449
 3450	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
 3451	if (ocp_data & UWF_EN)
 3452		wolopts |= WAKE_UCAST;
 3453	if (ocp_data & BWF_EN)
 3454		wolopts |= WAKE_BCAST;
 3455	if (ocp_data & MWF_EN)
 3456		wolopts |= WAKE_MCAST;
 3457
 3458	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
 3459	if (ocp_data & MAGIC_EN)
 3460		wolopts |= WAKE_MAGIC;
 3461
 3462	return wolopts;
 3463}
 3464
 3465static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
 3466{
 3467	u32 ocp_data;
 3468
 3469	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
 3470
 3471	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
 3472	ocp_data &= ~LINK_ON_WAKE_EN;
 3473	if (wolopts & WAKE_PHY)
 3474		ocp_data |= LINK_ON_WAKE_EN;
 3475	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
 3476
 3477	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
 3478	ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
 3479	if (wolopts & WAKE_UCAST)
 3480		ocp_data |= UWF_EN;
 3481	if (wolopts & WAKE_BCAST)
 3482		ocp_data |= BWF_EN;
 3483	if (wolopts & WAKE_MCAST)
 3484		ocp_data |= MWF_EN;
 3485	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
 3486
 3487	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
 3488
 3489	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
 3490	ocp_data &= ~MAGIC_EN;
 3491	if (wolopts & WAKE_MAGIC)
 3492		ocp_data |= MAGIC_EN;
 3493	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
 3494
 3495	if (wolopts & WAKE_ANY)
 3496		device_set_wakeup_enable(&tp->udev->dev, true);
 3497	else
 3498		device_set_wakeup_enable(&tp->udev->dev, false);
 3499}
 3500
 3501static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable)
 3502{
 3503	u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
 3504
 3505	/* MAC clock speed down */
 3506	if (enable)
 3507		ocp_data |= MAC_CLK_SPDWN_EN;
 3508	else
 3509		ocp_data &= ~MAC_CLK_SPDWN_EN;
 3510
 3511	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
 3512}
 3513
 3514static void r8156_mac_clk_spd(struct r8152 *tp, bool enable)
 3515{
 3516	u32 ocp_data;
 3517
 3518	/* MAC clock speed down */
 3519	if (enable) {
 3520		/* aldps_spdwn_ratio, tp10_spdwn_ratio */
 3521		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
 3522			       0x0403);
 3523
 3524		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
 3525		ocp_data &= ~EEE_SPDWN_RATIO_MASK;
 3526		ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */
 3527		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
 
 
 
 
 3528	} else {
 3529		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
 3530		ocp_data &= ~MAC_CLK_SPDWN_EN;
 3531		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
 
 3532	}
 3533}
 3534
 3535static void r8153_u1u2en(struct r8152 *tp, bool enable)
 3536{
 3537	u8 u1u2[8];
 3538
 3539	if (enable)
 3540		memset(u1u2, 0xff, sizeof(u1u2));
 3541	else
 3542		memset(u1u2, 0x00, sizeof(u1u2));
 3543
 3544	usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
 3545}
 3546
 3547static void r8153b_u1u2en(struct r8152 *tp, bool enable)
 3548{
 3549	u32 ocp_data;
 3550
 3551	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
 3552	if (enable)
 3553		ocp_data |= LPM_U1U2_EN;
 3554	else
 3555		ocp_data &= ~LPM_U1U2_EN;
 3556
 3557	ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
 3558}
 3559
 3560static void r8153_u2p3en(struct r8152 *tp, bool enable)
 3561{
 3562	u32 ocp_data;
 3563
 3564	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
 3565	if (enable)
 3566		ocp_data |= U2P3_ENABLE;
 3567	else
 3568		ocp_data &= ~U2P3_ENABLE;
 3569	ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
 3570}
 3571
 3572static void r8153b_ups_flags(struct r8152 *tp)
 3573{
 3574	u32 ups_flags = 0;
 3575
 3576	if (tp->ups_info.green)
 3577		ups_flags |= UPS_FLAGS_EN_GREEN;
 3578
 3579	if (tp->ups_info.aldps)
 3580		ups_flags |= UPS_FLAGS_EN_ALDPS;
 3581
 3582	if (tp->ups_info.eee)
 3583		ups_flags |= UPS_FLAGS_EN_EEE;
 3584
 3585	if (tp->ups_info.flow_control)
 3586		ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
 3587
 3588	if (tp->ups_info.eee_ckdiv)
 3589		ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
 3590
 3591	if (tp->ups_info.eee_cmod_lv)
 3592		ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
 3593
 3594	if (tp->ups_info.r_tune)
 3595		ups_flags |= UPS_FLAGS_R_TUNE;
 3596
 3597	if (tp->ups_info._10m_ckdiv)
 3598		ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
 3599
 3600	if (tp->ups_info.eee_plloff_100)
 3601		ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
 3602
 3603	if (tp->ups_info.eee_plloff_giga)
 3604		ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
 3605
 3606	if (tp->ups_info._250m_ckdiv)
 3607		ups_flags |= UPS_FLAGS_250M_CKDIV;
 3608
 3609	if (tp->ups_info.ctap_short_off)
 3610		ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
 3611
 3612	switch (tp->ups_info.speed_duplex) {
 3613	case NWAY_10M_HALF:
 3614		ups_flags |= ups_flags_speed(1);
 3615		break;
 3616	case NWAY_10M_FULL:
 3617		ups_flags |= ups_flags_speed(2);
 3618		break;
 3619	case NWAY_100M_HALF:
 3620		ups_flags |= ups_flags_speed(3);
 3621		break;
 3622	case NWAY_100M_FULL:
 3623		ups_flags |= ups_flags_speed(4);
 3624		break;
 3625	case NWAY_1000M_FULL:
 3626		ups_flags |= ups_flags_speed(5);
 3627		break;
 3628	case FORCE_10M_HALF:
 3629		ups_flags |= ups_flags_speed(6);
 3630		break;
 3631	case FORCE_10M_FULL:
 3632		ups_flags |= ups_flags_speed(7);
 3633		break;
 3634	case FORCE_100M_HALF:
 3635		ups_flags |= ups_flags_speed(8);
 3636		break;
 3637	case FORCE_100M_FULL:
 3638		ups_flags |= ups_flags_speed(9);
 3639		break;
 3640	default:
 3641		break;
 3642	}
 3643
 3644	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
 3645}
 3646
 3647static void r8156_ups_flags(struct r8152 *tp)
 3648{
 3649	u32 ups_flags = 0;
 3650
 3651	if (tp->ups_info.green)
 3652		ups_flags |= UPS_FLAGS_EN_GREEN;
 3653
 3654	if (tp->ups_info.aldps)
 3655		ups_flags |= UPS_FLAGS_EN_ALDPS;
 3656
 3657	if (tp->ups_info.eee)
 3658		ups_flags |= UPS_FLAGS_EN_EEE;
 3659
 3660	if (tp->ups_info.flow_control)
 3661		ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
 3662
 3663	if (tp->ups_info.eee_ckdiv)
 3664		ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
 3665
 3666	if (tp->ups_info._10m_ckdiv)
 3667		ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
 3668
 3669	if (tp->ups_info.eee_plloff_100)
 3670		ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
 3671
 3672	if (tp->ups_info.eee_plloff_giga)
 3673		ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
 3674
 3675	if (tp->ups_info._250m_ckdiv)
 3676		ups_flags |= UPS_FLAGS_250M_CKDIV;
 3677
 3678	switch (tp->ups_info.speed_duplex) {
 3679	case FORCE_10M_HALF:
 3680		ups_flags |= ups_flags_speed(0);
 3681		break;
 3682	case FORCE_10M_FULL:
 3683		ups_flags |= ups_flags_speed(1);
 3684		break;
 3685	case FORCE_100M_HALF:
 3686		ups_flags |= ups_flags_speed(2);
 3687		break;
 3688	case FORCE_100M_FULL:
 3689		ups_flags |= ups_flags_speed(3);
 3690		break;
 3691	case NWAY_10M_HALF:
 3692		ups_flags |= ups_flags_speed(4);
 3693		break;
 3694	case NWAY_10M_FULL:
 3695		ups_flags |= ups_flags_speed(5);
 3696		break;
 3697	case NWAY_100M_HALF:
 3698		ups_flags |= ups_flags_speed(6);
 3699		break;
 3700	case NWAY_100M_FULL:
 3701		ups_flags |= ups_flags_speed(7);
 3702		break;
 3703	case NWAY_1000M_FULL:
 3704		ups_flags |= ups_flags_speed(8);
 3705		break;
 3706	case NWAY_2500M_FULL:
 3707		ups_flags |= ups_flags_speed(9);
 3708		break;
 3709	default:
 3710		break;
 3711	}
 3712
 3713	switch (tp->ups_info.lite_mode) {
 3714	case 1:
 3715		ups_flags |= 0 << 5;
 3716		break;
 3717	case 2:
 3718		ups_flags |= 2 << 5;
 3719		break;
 3720	case 0:
 3721	default:
 3722		ups_flags |= 1 << 5;
 3723		break;
 3724	}
 3725
 3726	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
 3727}
 3728
 3729static void rtl_green_en(struct r8152 *tp, bool enable)
 3730{
 3731	u16 data;
 3732
 3733	data = sram_read(tp, SRAM_GREEN_CFG);
 3734	if (enable)
 3735		data |= GREEN_ETH_EN;
 3736	else
 3737		data &= ~GREEN_ETH_EN;
 3738	sram_write(tp, SRAM_GREEN_CFG, data);
 3739
 3740	tp->ups_info.green = enable;
 3741}
 3742
 3743static void r8153b_green_en(struct r8152 *tp, bool enable)
 3744{
 3745	if (enable) {
 3746		sram_write(tp, 0x8045, 0);	/* 10M abiq&ldvbias */
 3747		sram_write(tp, 0x804d, 0x1222);	/* 100M short abiq&ldvbias */
 3748		sram_write(tp, 0x805d, 0x0022);	/* 1000M short abiq&ldvbias */
 3749	} else {
 3750		sram_write(tp, 0x8045, 0x2444);	/* 10M abiq&ldvbias */
 3751		sram_write(tp, 0x804d, 0x2444);	/* 100M short abiq&ldvbias */
 3752		sram_write(tp, 0x805d, 0x2444);	/* 1000M short abiq&ldvbias */
 3753	}
 3754
 3755	rtl_green_en(tp, true);
 
 
 
 
 3756}
 3757
 3758static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
 3759{
 3760	u16 data;
 3761	int i;
 3762
 3763	for (i = 0; i < 500; i++) {
 3764		data = ocp_reg_read(tp, OCP_PHY_STATUS);
 3765		data &= PHY_STAT_MASK;
 3766		if (desired) {
 3767			if (data == desired)
 3768				break;
 3769		} else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
 3770			   data == PHY_STAT_EXT_INIT) {
 3771			break;
 3772		}
 3773
 3774		msleep(20);
 3775		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 3776			break;
 3777	}
 3778
 3779	return data;
 3780}
 3781
 3782static void r8153b_ups_en(struct r8152 *tp, bool enable)
 3783{
 3784	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
 3785
 3786	if (enable) {
 3787		r8153b_ups_flags(tp);
 3788
 3789		ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
 3790		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
 3791
 3792		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
 3793		ocp_data |= UPS_FORCE_PWR_DOWN;
 3794		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
 3795	} else {
 3796		ocp_data &= ~(UPS_EN | USP_PREWAKE);
 3797		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
 3798
 3799		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
 3800		ocp_data &= ~UPS_FORCE_PWR_DOWN;
 3801		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
 3802
 3803		if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
 3804			int i;
 3805
 3806			for (i = 0; i < 500; i++) {
 3807				if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 3808					return;
 3809				if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
 3810				    AUTOLOAD_DONE)
 3811					break;
 3812				msleep(20);
 3813			}
 3814
 3815			tp->rtl_ops.hw_phy_cfg(tp);
 3816
 3817			rtl8152_set_speed(tp, tp->autoneg, tp->speed,
 3818					  tp->duplex, tp->advertising);
 3819		}
 3820	}
 3821}
 3822
 3823static void r8153c_ups_en(struct r8152 *tp, bool enable)
 3824{
 3825	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
 3826
 3827	if (enable) {
 3828		r8153b_ups_flags(tp);
 3829
 3830		ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
 3831		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
 3832
 3833		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
 3834		ocp_data |= UPS_FORCE_PWR_DOWN;
 3835		ocp_data &= ~BIT(7);
 3836		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
 3837	} else {
 3838		ocp_data &= ~(UPS_EN | USP_PREWAKE);
 3839		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
 3840
 3841		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
 3842		ocp_data &= ~UPS_FORCE_PWR_DOWN;
 3843		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
 3844
 3845		if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
 3846			int i;
 3847
 3848			for (i = 0; i < 500; i++) {
 3849				if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 3850					return;
 3851				if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
 3852				    AUTOLOAD_DONE)
 3853					break;
 3854				msleep(20);
 3855			}
 3856
 3857			tp->rtl_ops.hw_phy_cfg(tp);
 3858
 3859			rtl8152_set_speed(tp, tp->autoneg, tp->speed,
 3860					  tp->duplex, tp->advertising);
 3861		}
 3862
 3863		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
 3864
 3865		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
 3866		ocp_data |= BIT(8);
 3867		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
 3868
 3869		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
 3870	}
 3871}
 3872
 3873static void r8156_ups_en(struct r8152 *tp, bool enable)
 3874{
 3875	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
 3876
 3877	if (enable) {
 3878		r8156_ups_flags(tp);
 3879
 3880		ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
 3881		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
 
 
 
 
 
 
 
 
 3882
 3883		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
 3884		ocp_data |= UPS_FORCE_PWR_DOWN;
 3885		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
 3886
 3887		switch (tp->version) {
 3888		case RTL_VER_13:
 3889		case RTL_VER_15:
 3890			ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);
 3891			ocp_data &= ~OOBS_POLLING;
 3892			ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data);
 3893			break;
 3894		default:
 
 
 
 3895			break;
 3896		}
 3897	} else {
 3898		ocp_data &= ~(UPS_EN | USP_PREWAKE);
 3899		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
 3900
 3901		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
 3902		ocp_data &= ~UPS_FORCE_PWR_DOWN;
 3903		ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
 3904
 3905		if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
 3906			tp->rtl_ops.hw_phy_cfg(tp);
 3907
 3908			rtl8152_set_speed(tp, tp->autoneg, tp->speed,
 3909					  tp->duplex, tp->advertising);
 3910		}
 3911	}
 3912}
 3913
 3914static void r8153_power_cut_en(struct r8152 *tp, bool enable)
 3915{
 3916	u32 ocp_data;
 3917
 3918	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
 3919	if (enable)
 3920		ocp_data |= PWR_EN | PHASE2_EN;
 3921	else
 3922		ocp_data &= ~(PWR_EN | PHASE2_EN);
 3923	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
 3924
 3925	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
 3926	ocp_data &= ~PCUT_STATUS;
 3927	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
 3928}
 3929
 3930static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
 3931{
 3932	u32 ocp_data;
 3933
 3934	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
 3935	if (enable)
 3936		ocp_data |= PWR_EN | PHASE2_EN;
 3937	else
 3938		ocp_data &= ~PWR_EN;
 3939	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
 3940
 3941	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
 3942	ocp_data &= ~PCUT_STATUS;
 3943	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
 3944}
 3945
 3946static void r8153_queue_wake(struct r8152 *tp, bool enable)
 3947{
 3948	u32 ocp_data;
 3949
 3950	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
 3951	if (enable)
 3952		ocp_data |= UPCOMING_RUNTIME_D3;
 3953	else
 3954		ocp_data &= ~UPCOMING_RUNTIME_D3;
 3955	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
 3956
 3957	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
 3958	ocp_data &= ~LINK_CHG_EVENT;
 3959	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
 3960
 3961	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
 3962	ocp_data &= ~LINK_CHANGE_FLAG;
 3963	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
 3964}
 3965
 3966static bool rtl_can_wakeup(struct r8152 *tp)
 3967{
 3968	struct usb_device *udev = tp->udev;
 3969
 3970	return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
 3971}
 3972
 3973static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
 3974{
 3975	if (enable) {
 3976		u32 ocp_data;
 3977
 3978		__rtl_set_wol(tp, WAKE_ANY);
 3979
 3980		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
 3981
 3982		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
 3983		ocp_data |= LINK_OFF_WAKE_EN;
 3984		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
 3985
 3986		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
 3987	} else {
 3988		u32 ocp_data;
 3989
 3990		__rtl_set_wol(tp, tp->saved_wolopts);
 3991
 3992		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
 3993
 3994		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
 3995		ocp_data &= ~LINK_OFF_WAKE_EN;
 3996		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
 3997
 3998		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
 3999	}
 4000}
 4001
 4002static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
 4003{
 4004	if (enable) {
 4005		r8153_u1u2en(tp, false);
 4006		r8153_u2p3en(tp, false);
 
 4007		rtl_runtime_suspend_enable(tp, true);
 4008	} else {
 4009		rtl_runtime_suspend_enable(tp, false);
 
 4010
 4011		switch (tp->version) {
 4012		case RTL_VER_03:
 4013		case RTL_VER_04:
 4014			break;
 4015		case RTL_VER_05:
 4016		case RTL_VER_06:
 4017		default:
 4018			r8153_u2p3en(tp, true);
 4019			break;
 4020		}
 4021
 4022		r8153_u1u2en(tp, true);
 4023	}
 4024}
 4025
 4026static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
 4027{
 4028	if (enable) {
 4029		r8153_queue_wake(tp, true);
 4030		r8153b_u1u2en(tp, false);
 4031		r8153_u2p3en(tp, false);
 4032		rtl_runtime_suspend_enable(tp, true);
 4033		r8153b_ups_en(tp, true);
 4034	} else {
 4035		r8153b_ups_en(tp, false);
 4036		r8153_queue_wake(tp, false);
 4037		rtl_runtime_suspend_enable(tp, false);
 4038		if (tp->udev->speed >= USB_SPEED_SUPER)
 4039			r8153b_u1u2en(tp, true);
 4040	}
 4041}
 4042
 4043static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable)
 4044{
 4045	if (enable) {
 4046		r8153_queue_wake(tp, true);
 4047		r8153b_u1u2en(tp, false);
 4048		r8153_u2p3en(tp, false);
 4049		rtl_runtime_suspend_enable(tp, true);
 4050		r8153c_ups_en(tp, true);
 4051	} else {
 4052		r8153c_ups_en(tp, false);
 4053		r8153_queue_wake(tp, false);
 4054		rtl_runtime_suspend_enable(tp, false);
 4055		r8153b_u1u2en(tp, true);
 4056	}
 4057}
 4058
 4059static void rtl8156_runtime_enable(struct r8152 *tp, bool enable)
 4060{
 4061	if (enable) {
 4062		r8153_queue_wake(tp, true);
 4063		r8153b_u1u2en(tp, false);
 4064		r8153_u2p3en(tp, false);
 4065		rtl_runtime_suspend_enable(tp, true);
 4066	} else {
 4067		r8153_queue_wake(tp, false);
 4068		rtl_runtime_suspend_enable(tp, false);
 4069		r8153_u2p3en(tp, true);
 4070		if (tp->udev->speed >= USB_SPEED_SUPER)
 4071			r8153b_u1u2en(tp, true);
 4072	}
 4073}
 4074
 4075static void r8153_teredo_off(struct r8152 *tp)
 4076{
 4077	u32 ocp_data;
 4078
 4079	switch (tp->version) {
 4080	case RTL_VER_01:
 4081	case RTL_VER_02:
 4082	case RTL_VER_03:
 4083	case RTL_VER_04:
 4084	case RTL_VER_05:
 4085	case RTL_VER_06:
 4086	case RTL_VER_07:
 4087		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
 4088		ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
 4089			      OOB_TEREDO_EN);
 4090		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
 4091		break;
 4092
 4093	case RTL_VER_08:
 4094	case RTL_VER_09:
 4095	case RTL_TEST_01:
 4096	case RTL_VER_10:
 4097	case RTL_VER_11:
 4098	case RTL_VER_12:
 4099	case RTL_VER_13:
 4100	case RTL_VER_14:
 4101	case RTL_VER_15:
 4102	default:
 4103		/* The bit 0 ~ 7 are relative with teredo settings. They are
 4104		 * W1C (write 1 to clear), so set all 1 to disable it.
 4105		 */
 4106		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
 4107		break;
 
 
 
 4108	}
 4109
 4110	ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
 4111	ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
 4112	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
 4113}
 4114
 4115static void rtl_reset_bmu(struct r8152 *tp)
 4116{
 4117	u32 ocp_data;
 4118
 4119	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
 4120	ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
 4121	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
 4122	ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
 4123	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
 4124}
 4125
 4126/* Clear the bp to stop the firmware before loading a new one */
 4127static void rtl_clear_bp(struct r8152 *tp, u16 type)
 4128{
 4129	u16 bp[16] = {0};
 4130	u16 bp_num;
 4131
 4132	switch (tp->version) {
 4133	case RTL_VER_08:
 4134	case RTL_VER_09:
 4135	case RTL_VER_10:
 4136	case RTL_VER_11:
 4137	case RTL_VER_12:
 4138	case RTL_VER_13:
 4139	case RTL_VER_15:
 4140		if (type == MCU_TYPE_USB) {
 4141			ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
 4142			bp_num = 16;
 4143			break;
 4144		}
 4145		fallthrough;
 4146	case RTL_VER_03:
 4147	case RTL_VER_04:
 4148	case RTL_VER_05:
 4149	case RTL_VER_06:
 4150		ocp_write_byte(tp, type, PLA_BP_EN, 0);
 4151		fallthrough;
 4152	case RTL_VER_01:
 4153	case RTL_VER_02:
 4154	case RTL_VER_07:
 4155		bp_num = 8;
 4156		break;
 4157	case RTL_VER_14:
 4158	default:
 4159		ocp_write_word(tp, type, USB_BP2_EN, 0);
 4160		bp_num = 16;
 4161		break;
 4162	}
 4163
 4164	generic_ocp_write(tp, PLA_BP_0, BYTE_EN_DWORD, bp_num << 1, bp, type);
 4165
 4166	/* wait 3 ms to make sure the firmware is stopped */
 4167	usleep_range(3000, 6000);
 4168	ocp_write_word(tp, type, PLA_BP_BA, 0);
 4169}
 4170
 4171static inline void rtl_reset_ocp_base(struct r8152 *tp)
 4172{
 4173	tp->ocp_base = -1;
 4174}
 4175
 4176static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)
 4177{
 4178	u16 data, check;
 4179	int i;
 4180
 4181	data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
 4182	if (request) {
 4183		data |= PATCH_REQUEST;
 4184		check = 0;
 4185	} else {
 4186		data &= ~PATCH_REQUEST;
 4187		check = PATCH_READY;
 4188	}
 4189	ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
 4190
 4191	for (i = 0; wait && i < 5000; i++) {
 4192		u32 ocp_data;
 4193
 4194		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 4195			return -ENODEV;
 4196
 4197		usleep_range(1000, 2000);
 4198		ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);
 4199		if ((ocp_data & PATCH_READY) ^ check)
 4200			break;
 4201	}
 4202
 4203	if (request && wait &&
 4204	    !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
 4205		dev_err(&tp->intf->dev, "PHY patch request fail\n");
 4206		rtl_phy_patch_request(tp, false, false);
 4207		return -ETIME;
 4208	} else {
 4209		return 0;
 4210	}
 4211}
 4212
 4213static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key)
 4214{
 4215	if (patch_key && key_addr) {
 4216		sram_write(tp, key_addr, patch_key);
 4217		sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
 4218	} else if (key_addr) {
 4219		u16 data;
 4220
 4221		sram_write(tp, 0x0000, 0x0000);
 4222
 4223		data = ocp_reg_read(tp, OCP_PHY_LOCK);
 4224		data &= ~PATCH_LOCK;
 4225		ocp_reg_write(tp, OCP_PHY_LOCK, data);
 4226
 4227		sram_write(tp, key_addr, 0x0000);
 4228	} else {
 4229		WARN_ON_ONCE(1);
 4230	}
 4231}
 4232
 4233static int
 4234rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait)
 4235{
 4236	if (rtl_phy_patch_request(tp, true, wait))
 4237		return -ETIME;
 4238
 4239	rtl_patch_key_set(tp, key_addr, patch_key);
 4240
 4241	return 0;
 4242}
 4243
 4244static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait)
 4245{
 4246	rtl_patch_key_set(tp, key_addr, 0);
 4247
 4248	rtl_phy_patch_request(tp, false, wait);
 4249
 4250	return 0;
 4251}
 4252
 4253static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy)
 4254{
 4255	u16 fw_offset;
 4256	u32 length;
 4257	bool rc = false;
 4258
 4259	switch (tp->version) {
 4260	case RTL_VER_01:
 4261	case RTL_VER_02:
 4262	case RTL_VER_03:
 4263	case RTL_VER_04:
 4264	case RTL_VER_05:
 4265	case RTL_VER_06:
 4266	case RTL_VER_07:
 4267	case RTL_VER_08:
 4268	case RTL_VER_09:
 4269	case RTL_VER_10:
 4270	case RTL_VER_11:
 4271	case RTL_VER_12:
 4272	case RTL_VER_14:
 4273		goto out;
 4274	case RTL_VER_13:
 4275	case RTL_VER_15:
 4276	default:
 4277		break;
 4278	}
 4279
 4280	fw_offset = __le16_to_cpu(phy->fw_offset);
 4281	length = __le32_to_cpu(phy->blk_hdr.length);
 4282	if (fw_offset < sizeof(*phy) || length <= fw_offset) {
 4283		dev_err(&tp->intf->dev, "invalid fw_offset\n");
 4284		goto out;
 4285	}
 4286
 4287	length -= fw_offset;
 4288	if (length & 3) {
 4289		dev_err(&tp->intf->dev, "invalid block length\n");
 4290		goto out;
 4291	}
 4292
 4293	if (__le16_to_cpu(phy->fw_reg) != 0x9A00) {
 4294		dev_err(&tp->intf->dev, "invalid register to load firmware\n");
 4295		goto out;
 4296	}
 4297
 4298	rc = true;
 4299out:
 4300	return rc;
 4301}
 4302
 4303static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver)
 4304{
 4305	bool rc = false;
 4306
 4307	switch (tp->version) {
 4308	case RTL_VER_10:
 4309	case RTL_VER_11:
 4310	case RTL_VER_12:
 4311	case RTL_VER_13:
 4312	case RTL_VER_15:
 4313		break;
 4314	default:
 4315		goto out;
 4316	}
 4317
 4318	if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) {
 4319		dev_err(&tp->intf->dev, "invalid block length\n");
 4320		goto out;
 4321	}
 4322
 4323	if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) {
 4324		dev_err(&tp->intf->dev, "invalid phy ver addr\n");
 4325		goto out;
 4326	}
 4327
 4328	rc = true;
 4329out:
 4330	return rc;
 4331}
 4332
 4333static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix)
 4334{
 4335	bool rc = false;
 4336
 4337	switch (tp->version) {
 4338	case RTL_VER_10:
 4339	case RTL_VER_11:
 4340	case RTL_VER_12:
 4341	case RTL_VER_13:
 4342	case RTL_VER_15:
 4343		break;
 4344	default:
 4345		goto out;
 4346	}
 4347
 4348	if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) {
 4349		dev_err(&tp->intf->dev, "invalid block length\n");
 4350		goto out;
 4351	}
 4352
 4353	if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD ||
 4354	    __le16_to_cpu(fix->setting.data) != BIT(7)) {
 4355		dev_err(&tp->intf->dev, "invalid phy fixup\n");
 4356		goto out;
 4357	}
 4358
 4359	rc = true;
 4360out:
 4361	return rc;
 4362}
 4363
 4364static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy)
 4365{
 4366	u16 fw_offset;
 4367	u32 length;
 4368	bool rc = false;
 4369
 4370	switch (tp->version) {
 4371	case RTL_VER_10:
 4372	case RTL_VER_11:
 4373	case RTL_VER_12:
 4374	case RTL_VER_13:
 4375	case RTL_VER_15:
 4376		break;
 4377	default:
 4378		goto out;
 4379	}
 4380
 4381	fw_offset = __le16_to_cpu(phy->fw_offset);
 4382	length = __le32_to_cpu(phy->blk_hdr.length);
 4383	if (fw_offset < sizeof(*phy) || length <= fw_offset) {
 4384		dev_err(&tp->intf->dev, "invalid fw_offset\n");
 4385		goto out;
 4386	}
 4387
 4388	length -= fw_offset;
 4389	if (length & 1) {
 4390		dev_err(&tp->intf->dev, "invalid block length\n");
 4391		goto out;
 4392	}
 4393
 4394	if (phy->pre_num > 2) {
 4395		dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num);
 4396		goto out;
 4397	}
 4398
 4399	if (phy->bp_num > 8) {
 4400		dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num);
 4401		goto out;
 4402	}
 4403
 4404	rc = true;
 4405out:
 4406	return rc;
 4407}
 4408
 4409static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
 4410{
 4411	u32 length;
 4412	u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
 4413	bool rc = false;
 4414
 4415	switch (tp->version) {
 4416	case RTL_VER_04:
 4417	case RTL_VER_05:
 4418	case RTL_VER_06:
 4419		fw_reg = 0xa014;
 4420		ba_reg = 0xa012;
 4421		patch_en_addr = 0xa01a;
 4422		mode_reg = 0xb820;
 4423		bp_start = 0xa000;
 4424		break;
 4425	default:
 4426		goto out;
 4427	}
 4428
 4429	fw_offset = __le16_to_cpu(phy->fw_offset);
 4430	if (fw_offset < sizeof(*phy)) {
 4431		dev_err(&tp->intf->dev, "fw_offset too small\n");
 4432		goto out;
 4433	}
 4434
 4435	length = __le32_to_cpu(phy->blk_hdr.length);
 4436	if (length < fw_offset) {
 4437		dev_err(&tp->intf->dev, "invalid fw_offset\n");
 4438		goto out;
 4439	}
 4440
 4441	length -= __le16_to_cpu(phy->fw_offset);
 4442	if (!length || (length & 1)) {
 4443		dev_err(&tp->intf->dev, "invalid block length\n");
 4444		goto out;
 4445	}
 4446
 4447	if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
 4448		dev_err(&tp->intf->dev, "invalid register to load firmware\n");
 4449		goto out;
 4450	}
 4451
 4452	if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
 4453		dev_err(&tp->intf->dev, "invalid base address register\n");
 4454		goto out;
 4455	}
 4456
 4457	if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
 4458		dev_err(&tp->intf->dev,
 4459			"invalid patch mode enabled register\n");
 4460		goto out;
 4461	}
 4462
 4463	if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
 4464		dev_err(&tp->intf->dev,
 4465			"invalid register to switch the mode\n");
 4466		goto out;
 4467	}
 4468
 4469	if (__le16_to_cpu(phy->bp_start) != bp_start) {
 4470		dev_err(&tp->intf->dev,
 4471			"invalid start register of break point\n");
 4472		goto out;
 4473	}
 4474
 4475	if (__le16_to_cpu(phy->bp_num) > 4) {
 4476		dev_err(&tp->intf->dev, "invalid break point number\n");
 4477		goto out;
 4478	}
 4479
 4480	rc = true;
 4481out:
 4482	return rc;
 4483}
 4484
 4485static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
 4486{
 4487	u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
 4488	bool rc = false;
 4489	u32 length, type;
 4490	int i, max_bp;
 4491
 4492	type = __le32_to_cpu(mac->blk_hdr.type);
 4493	if (type == RTL_FW_PLA) {
 4494		switch (tp->version) {
 4495		case RTL_VER_01:
 4496		case RTL_VER_02:
 4497		case RTL_VER_07:
 4498			fw_reg = 0xf800;
 4499			bp_ba_addr = PLA_BP_BA;
 4500			bp_en_addr = 0;
 4501			bp_start = PLA_BP_0;
 4502			max_bp = 8;
 4503			break;
 4504		case RTL_VER_03:
 4505		case RTL_VER_04:
 4506		case RTL_VER_05:
 4507		case RTL_VER_06:
 4508		case RTL_VER_08:
 4509		case RTL_VER_09:
 4510		case RTL_VER_11:
 4511		case RTL_VER_12:
 4512		case RTL_VER_13:
 4513		case RTL_VER_15:
 4514			fw_reg = 0xf800;
 4515			bp_ba_addr = PLA_BP_BA;
 4516			bp_en_addr = PLA_BP_EN;
 4517			bp_start = PLA_BP_0;
 4518			max_bp = 8;
 4519			break;
 4520		case RTL_VER_14:
 4521			fw_reg = 0xf800;
 4522			bp_ba_addr = PLA_BP_BA;
 4523			bp_en_addr = USB_BP2_EN;
 4524			bp_start = PLA_BP_0;
 4525			max_bp = 16;
 4526			break;
 4527		default:
 4528			goto out;
 4529		}
 4530	} else if (type == RTL_FW_USB) {
 4531		switch (tp->version) {
 4532		case RTL_VER_03:
 4533		case RTL_VER_04:
 4534		case RTL_VER_05:
 4535		case RTL_VER_06:
 4536			fw_reg = 0xf800;
 4537			bp_ba_addr = USB_BP_BA;
 4538			bp_en_addr = USB_BP_EN;
 4539			bp_start = USB_BP_0;
 4540			max_bp = 8;
 4541			break;
 4542		case RTL_VER_08:
 4543		case RTL_VER_09:
 4544		case RTL_VER_11:
 4545		case RTL_VER_12:
 4546		case RTL_VER_13:
 4547		case RTL_VER_14:
 4548		case RTL_VER_15:
 4549			fw_reg = 0xe600;
 4550			bp_ba_addr = USB_BP_BA;
 4551			bp_en_addr = USB_BP2_EN;
 4552			bp_start = USB_BP_0;
 4553			max_bp = 16;
 4554			break;
 4555		case RTL_VER_01:
 4556		case RTL_VER_02:
 4557		case RTL_VER_07:
 4558		default:
 4559			goto out;
 4560		}
 4561	} else {
 4562		goto out;
 4563	}
 4564
 4565	fw_offset = __le16_to_cpu(mac->fw_offset);
 4566	if (fw_offset < sizeof(*mac)) {
 4567		dev_err(&tp->intf->dev, "fw_offset too small\n");
 4568		goto out;
 4569	}
 4570
 4571	length = __le32_to_cpu(mac->blk_hdr.length);
 4572	if (length < fw_offset) {
 4573		dev_err(&tp->intf->dev, "invalid fw_offset\n");
 4574		goto out;
 4575	}
 4576
 4577	length -= fw_offset;
 4578	if (length < 4 || (length & 3)) {
 4579		dev_err(&tp->intf->dev, "invalid block length\n");
 4580		goto out;
 4581	}
 4582
 4583	if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
 4584		dev_err(&tp->intf->dev, "invalid register to load firmware\n");
 4585		goto out;
 4586	}
 4587
 4588	if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
 4589		dev_err(&tp->intf->dev, "invalid base address register\n");
 4590		goto out;
 4591	}
 4592
 4593	if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
 4594		dev_err(&tp->intf->dev, "invalid enabled mask register\n");
 4595		goto out;
 4596	}
 4597
 4598	if (__le16_to_cpu(mac->bp_start) != bp_start) {
 4599		dev_err(&tp->intf->dev,
 4600			"invalid start register of break point\n");
 4601		goto out;
 4602	}
 4603
 4604	if (__le16_to_cpu(mac->bp_num) > max_bp) {
 4605		dev_err(&tp->intf->dev, "invalid break point number\n");
 4606		goto out;
 4607	}
 4608
 4609	for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
 4610		if (mac->bp[i]) {
 4611			dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
 4612			goto out;
 4613		}
 4614	}
 4615
 4616	rc = true;
 4617out:
 4618	return rc;
 4619}
 4620
 4621/* Verify the checksum for the firmware file. It is calculated from the version
 4622 * field to the end of the file. Compare the result with the checksum field to
 4623 * make sure the file is correct.
 4624 */
 4625static long rtl8152_fw_verify_checksum(struct r8152 *tp,
 4626				       struct fw_header *fw_hdr, size_t size)
 4627{
 4628	unsigned char checksum[sizeof(fw_hdr->checksum)];
 4629	struct crypto_shash *alg;
 4630	struct shash_desc *sdesc;
 4631	size_t len;
 4632	long rc;
 4633
 4634	alg = crypto_alloc_shash("sha256", 0, 0);
 4635	if (IS_ERR(alg)) {
 4636		rc = PTR_ERR(alg);
 4637		goto out;
 4638	}
 4639
 4640	if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
 4641		rc = -EFAULT;
 4642		dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
 4643			crypto_shash_digestsize(alg));
 4644		goto free_shash;
 4645	}
 4646
 4647	len = sizeof(*sdesc) + crypto_shash_descsize(alg);
 4648	sdesc = kmalloc(len, GFP_KERNEL);
 4649	if (!sdesc) {
 4650		rc = -ENOMEM;
 4651		goto free_shash;
 4652	}
 4653	sdesc->tfm = alg;
 4654
 4655	len = size - sizeof(fw_hdr->checksum);
 4656	rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
 4657	kfree(sdesc);
 4658	if (rc)
 4659		goto free_shash;
 4660
 4661	if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
 4662		dev_err(&tp->intf->dev, "checksum fail\n");
 4663		rc = -EFAULT;
 4664	}
 4665
 4666free_shash:
 4667	crypto_free_shash(alg);
 4668out:
 4669	return rc;
 4670}
 4671
 4672static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
 4673{
 4674	const struct firmware *fw = rtl_fw->fw;
 4675	struct fw_header *fw_hdr = (struct fw_header *)fw->data;
 4676	unsigned long fw_flags = 0;
 4677	long ret = -EFAULT;
 4678	int i;
 4679
 4680	if (fw->size < sizeof(*fw_hdr)) {
 4681		dev_err(&tp->intf->dev, "file too small\n");
 4682		goto fail;
 4683	}
 4684
 4685	ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
 4686	if (ret)
 4687		goto fail;
 4688
 4689	ret = -EFAULT;
 4690
 4691	for (i = sizeof(*fw_hdr); i < fw->size;) {
 4692		struct fw_block *block = (struct fw_block *)&fw->data[i];
 4693		u32 type;
 4694
 4695		if ((i + sizeof(*block)) > fw->size)
 4696			goto fail;
 4697
 4698		type = __le32_to_cpu(block->type);
 4699		switch (type) {
 4700		case RTL_FW_END:
 4701			if (__le32_to_cpu(block->length) != sizeof(*block))
 4702				goto fail;
 4703			goto fw_end;
 4704		case RTL_FW_PLA:
 4705			if (test_bit(FW_FLAGS_PLA, &fw_flags)) {
 4706				dev_err(&tp->intf->dev,
 4707					"multiple PLA firmware encountered");
 4708				goto fail;
 4709			}
 4710
 4711			if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
 4712				dev_err(&tp->intf->dev,
 4713					"check PLA firmware failed\n");
 4714				goto fail;
 4715			}
 4716			__set_bit(FW_FLAGS_PLA, &fw_flags);
 4717			break;
 4718		case RTL_FW_USB:
 4719			if (test_bit(FW_FLAGS_USB, &fw_flags)) {
 4720				dev_err(&tp->intf->dev,
 4721					"multiple USB firmware encountered");
 4722				goto fail;
 4723			}
 4724
 4725			if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
 4726				dev_err(&tp->intf->dev,
 4727					"check USB firmware failed\n");
 4728				goto fail;
 4729			}
 4730			__set_bit(FW_FLAGS_USB, &fw_flags);
 4731			break;
 4732		case RTL_FW_PHY_START:
 4733			if (test_bit(FW_FLAGS_START, &fw_flags) ||
 4734			    test_bit(FW_FLAGS_NC, &fw_flags) ||
 4735			    test_bit(FW_FLAGS_NC1, &fw_flags) ||
 4736			    test_bit(FW_FLAGS_NC2, &fw_flags) ||
 4737			    test_bit(FW_FLAGS_UC2, &fw_flags) ||
 4738			    test_bit(FW_FLAGS_UC, &fw_flags) ||
 4739			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
 4740				dev_err(&tp->intf->dev,
 4741					"check PHY_START fail\n");
 4742				goto fail;
 4743			}
 4744
 4745			if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) {
 4746				dev_err(&tp->intf->dev,
 4747					"Invalid length for PHY_START\n");
 4748				goto fail;
 4749			}
 4750			__set_bit(FW_FLAGS_START, &fw_flags);
 4751			break;
 4752		case RTL_FW_PHY_STOP:
 4753			if (test_bit(FW_FLAGS_STOP, &fw_flags) ||
 4754			    !test_bit(FW_FLAGS_START, &fw_flags)) {
 4755				dev_err(&tp->intf->dev,
 4756					"Check PHY_STOP fail\n");
 4757				goto fail;
 4758			}
 4759
 4760			if (__le32_to_cpu(block->length) != sizeof(*block)) {
 4761				dev_err(&tp->intf->dev,
 4762					"Invalid length for PHY_STOP\n");
 4763				goto fail;
 4764			}
 4765			__set_bit(FW_FLAGS_STOP, &fw_flags);
 4766			break;
 4767		case RTL_FW_PHY_NC:
 4768			if (!test_bit(FW_FLAGS_START, &fw_flags) ||
 4769			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
 4770				dev_err(&tp->intf->dev,
 4771					"check PHY_NC fail\n");
 4772				goto fail;
 4773			}
 4774
 4775			if (test_bit(FW_FLAGS_NC, &fw_flags)) {
 4776				dev_err(&tp->intf->dev,
 4777					"multiple PHY NC encountered\n");
 4778				goto fail;
 4779			}
 4780
 4781			if (!rtl8152_is_fw_phy_nc_ok(tp, (struct fw_phy_nc *)block)) {
 4782				dev_err(&tp->intf->dev,
 4783					"check PHY NC firmware failed\n");
 4784				goto fail;
 4785			}
 4786			__set_bit(FW_FLAGS_NC, &fw_flags);
 4787			break;
 4788		case RTL_FW_PHY_UNION_NC:
 4789			if (!test_bit(FW_FLAGS_START, &fw_flags) ||
 4790			    test_bit(FW_FLAGS_NC1, &fw_flags) ||
 4791			    test_bit(FW_FLAGS_NC2, &fw_flags) ||
 4792			    test_bit(FW_FLAGS_UC2, &fw_flags) ||
 4793			    test_bit(FW_FLAGS_UC, &fw_flags) ||
 4794			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
 4795				dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n");
 4796				goto fail;
 4797			}
 4798
 4799			if (test_bit(FW_FLAGS_NC, &fw_flags)) {
 4800				dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n");
 4801				goto fail;
 4802			}
 4803
 4804			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
 4805				dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n");
 4806				goto fail;
 4807			}
 4808			__set_bit(FW_FLAGS_NC, &fw_flags);
 4809			break;
 4810		case RTL_FW_PHY_UNION_NC1:
 4811			if (!test_bit(FW_FLAGS_START, &fw_flags) ||
 4812			    test_bit(FW_FLAGS_NC2, &fw_flags) ||
 4813			    test_bit(FW_FLAGS_UC2, &fw_flags) ||
 4814			    test_bit(FW_FLAGS_UC, &fw_flags) ||
 4815			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
 4816				dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n");
 4817				goto fail;
 4818			}
 4819
 4820			if (test_bit(FW_FLAGS_NC1, &fw_flags)) {
 4821				dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n");
 4822				goto fail;
 4823			}
 4824
 4825			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
 4826				dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n");
 4827				goto fail;
 4828			}
 4829			__set_bit(FW_FLAGS_NC1, &fw_flags);
 4830			break;
 4831		case RTL_FW_PHY_UNION_NC2:
 4832			if (!test_bit(FW_FLAGS_START, &fw_flags) ||
 4833			    test_bit(FW_FLAGS_UC2, &fw_flags) ||
 4834			    test_bit(FW_FLAGS_UC, &fw_flags) ||
 4835			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
 4836				dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n");
 4837				goto fail;
 4838			}
 4839
 4840			if (test_bit(FW_FLAGS_NC2, &fw_flags)) {
 4841				dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n");
 4842				goto fail;
 4843			}
 4844
 4845			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
 4846				dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n");
 4847				goto fail;
 4848			}
 4849			__set_bit(FW_FLAGS_NC2, &fw_flags);
 4850			break;
 4851		case RTL_FW_PHY_UNION_UC2:
 4852			if (!test_bit(FW_FLAGS_START, &fw_flags) ||
 4853			    test_bit(FW_FLAGS_UC, &fw_flags) ||
 4854			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
 4855				dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n");
 4856				goto fail;
 4857			}
 4858
 4859			if (test_bit(FW_FLAGS_UC2, &fw_flags)) {
 4860				dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n");
 4861				goto fail;
 4862			}
 4863
 4864			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
 4865				dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n");
 4866				goto fail;
 4867			}
 4868			__set_bit(FW_FLAGS_UC2, &fw_flags);
 4869			break;
 4870		case RTL_FW_PHY_UNION_UC:
 4871			if (!test_bit(FW_FLAGS_START, &fw_flags) ||
 4872			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
 4873				dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n");
 4874				goto fail;
 4875			}
 4876
 4877			if (test_bit(FW_FLAGS_UC, &fw_flags)) {
 4878				dev_err(&tp->intf->dev, "multiple PHY UC encountered\n");
 4879				goto fail;
 4880			}
 4881
 4882			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
 4883				dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n");
 4884				goto fail;
 4885			}
 4886			__set_bit(FW_FLAGS_UC, &fw_flags);
 4887			break;
 4888		case RTL_FW_PHY_UNION_MISC:
 4889			if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
 4890				dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n");
 4891				goto fail;
 4892			}
 4893			break;
 4894		case RTL_FW_PHY_FIXUP:
 4895			if (!rtl8152_is_fw_phy_fixup_ok(tp, (struct fw_phy_fixup *)block)) {
 4896				dev_err(&tp->intf->dev, "check PHY fixup failed\n");
 4897				goto fail;
 4898			}
 4899			break;
 4900		case RTL_FW_PHY_SPEED_UP:
 4901			if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) {
 4902				dev_err(&tp->intf->dev, "multiple PHY firmware encountered");
 4903				goto fail;
 4904			}
 4905
 4906			if (!rtl8152_is_fw_phy_speed_up_ok(tp, (struct fw_phy_speed_up *)block)) {
 4907				dev_err(&tp->intf->dev, "check PHY speed up failed\n");
 4908				goto fail;
 4909			}
 4910			__set_bit(FW_FLAGS_SPEED_UP, &fw_flags);
 4911			break;
 4912		case RTL_FW_PHY_VER:
 4913			if (test_bit(FW_FLAGS_START, &fw_flags) ||
 4914			    test_bit(FW_FLAGS_NC, &fw_flags) ||
 4915			    test_bit(FW_FLAGS_NC1, &fw_flags) ||
 4916			    test_bit(FW_FLAGS_NC2, &fw_flags) ||
 4917			    test_bit(FW_FLAGS_UC2, &fw_flags) ||
 4918			    test_bit(FW_FLAGS_UC, &fw_flags) ||
 4919			    test_bit(FW_FLAGS_STOP, &fw_flags)) {
 4920				dev_err(&tp->intf->dev, "Invalid order to set PHY version\n");
 4921				goto fail;
 4922			}
 4923
 4924			if (test_bit(FW_FLAGS_VER, &fw_flags)) {
 4925				dev_err(&tp->intf->dev, "multiple PHY version encountered");
 4926				goto fail;
 4927			}
 4928
 4929			if (!rtl8152_is_fw_phy_ver_ok(tp, (struct fw_phy_ver *)block)) {
 4930				dev_err(&tp->intf->dev, "check PHY version failed\n");
 4931				goto fail;
 4932			}
 4933			__set_bit(FW_FLAGS_VER, &fw_flags);
 4934			break;
 4935		default:
 4936			dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
 4937				 type);
 4938			break;
 4939		}
 4940
 4941		/* next block */
 4942		i += ALIGN(__le32_to_cpu(block->length), 8);
 4943	}
 4944
 4945fw_end:
 4946	if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) {
 4947		dev_err(&tp->intf->dev, "without PHY_STOP\n");
 4948		goto fail;
 4949	}
 4950
 4951	return 0;
 4952fail:
 4953	return ret;
 4954}
 4955
 4956static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait)
 4957{
 4958	u32 len;
 4959	u8 *data;
 4960
 4961	rtl_reset_ocp_base(tp);
 4962
 4963	if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) {
 4964		dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
 4965		return;
 4966	}
 4967
 4968	len = __le32_to_cpu(phy->blk_hdr.length);
 4969	len -= __le16_to_cpu(phy->fw_offset);
 4970	data = (u8 *)phy + __le16_to_cpu(phy->fw_offset);
 4971
 4972	if (rtl_phy_patch_request(tp, true, wait))
 4973		return;
 4974
 4975	while (len) {
 4976		u32 ocp_data, size;
 4977		int i;
 4978
 4979		if (len < 2048)
 4980			size = len;
 4981		else
 4982			size = 2048;
 4983
 4984		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL);
 4985		ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE;
 4986		ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data);
 4987
 4988		generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB);
 4989
 4990		data += size;
 4991		len -= size;
 4992
 4993		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL);
 4994		ocp_data |= POL_GPHY_PATCH;
 4995		ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data);
 4996
 4997		for (i = 0; i < 1000; i++) {
 4998			if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH))
 4999				break;
 5000		}
 5001
 5002		if (i == 1000) {
 5003			dev_err(&tp->intf->dev, "ram code speedup mode timeout\n");
 5004			break;
 5005		}
 5006	}
 5007
 5008	rtl_reset_ocp_base(tp);
 5009
 5010	rtl_phy_patch_request(tp, false, wait);
 5011
 5012	if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version))
 5013		dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
 5014	else
 5015		dev_err(&tp->intf->dev, "ram code speedup mode fail\n");
 5016}
 5017
 5018static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver)
 5019{
 5020	u16 ver_addr, ver;
 5021
 5022	ver_addr = __le16_to_cpu(phy_ver->ver.addr);
 5023	ver = __le16_to_cpu(phy_ver->ver.data);
 5024
 5025	rtl_reset_ocp_base(tp);
 5026
 5027	if (sram_read(tp, ver_addr) >= ver) {
 5028		dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
 5029		return 0;
 5030	}
 5031
 5032	sram_write(tp, ver_addr, ver);
 5033
 5034	dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver);
 5035
 5036	return ver;
 5037}
 5038
 5039static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix)
 5040{
 5041	u16 addr, data;
 5042
 5043	rtl_reset_ocp_base(tp);
 5044
 5045	addr = __le16_to_cpu(fix->setting.addr);
 5046	data = ocp_reg_read(tp, addr);
 5047
 5048	switch (__le16_to_cpu(fix->bit_cmd)) {
 5049	case FW_FIXUP_AND:
 5050		data &= __le16_to_cpu(fix->setting.data);
 5051		break;
 5052	case FW_FIXUP_OR:
 5053		data |= __le16_to_cpu(fix->setting.data);
 5054		break;
 5055	case FW_FIXUP_NOT:
 5056		data &= ~__le16_to_cpu(fix->setting.data);
 5057		break;
 5058	case FW_FIXUP_XOR:
 5059		data ^= __le16_to_cpu(fix->setting.data);
 5060		break;
 5061	default:
 5062		return;
 5063	}
 5064
 5065	ocp_reg_write(tp, addr, data);
 5066
 5067	dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data);
 5068}
 5069
 5070static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy)
 5071{
 5072	__le16 *data;
 5073	u32 length;
 5074	int i, num;
 5075
 5076	rtl_reset_ocp_base(tp);
 5077
 5078	num = phy->pre_num;
 5079	for (i = 0; i < num; i++)
 5080		sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr),
 5081			   __le16_to_cpu(phy->pre_set[i].data));
 5082
 5083	length = __le32_to_cpu(phy->blk_hdr.length);
 5084	length -= __le16_to_cpu(phy->fw_offset);
 5085	num = length / 2;
 5086	data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
 5087
 5088	ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
 5089	for (i = 0; i < num; i++)
 5090		ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
 5091
 5092	num = phy->bp_num;
 5093	for (i = 0; i < num; i++)
 5094		sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data));
 5095
 5096	if (phy->bp_num && phy->bp_en.addr)
 5097		sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data));
 5098
 5099	dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
 5100}
 5101
 5102static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
 5103{
 5104	u16 mode_reg, bp_index;
 5105	u32 length, i, num;
 5106	__le16 *data;
 5107
 5108	rtl_reset_ocp_base(tp);
 5109
 5110	mode_reg = __le16_to_cpu(phy->mode_reg);
 5111	sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
 5112	sram_write(tp, __le16_to_cpu(phy->ba_reg),
 5113		   __le16_to_cpu(phy->ba_data));
 5114
 5115	length = __le32_to_cpu(phy->blk_hdr.length);
 5116	length -= __le16_to_cpu(phy->fw_offset);
 5117	num = length / 2;
 5118	data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
 5119
 5120	ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
 5121	for (i = 0; i < num; i++)
 5122		ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
 5123
 5124	sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
 5125		   __le16_to_cpu(phy->patch_en_value));
 5126
 5127	bp_index = __le16_to_cpu(phy->bp_start);
 5128	num = __le16_to_cpu(phy->bp_num);
 5129	for (i = 0; i < num; i++) {
 5130		sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
 5131		bp_index += 2;
 5132	}
 5133
 5134	sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
 5135
 5136	dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
 5137}
 5138
 5139static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
 5140{
 5141	u16 bp_en_addr, type, fw_ver_reg;
 5142	u32 length;
 5143	u8 *data;
 5144
 5145	switch (__le32_to_cpu(mac->blk_hdr.type)) {
 5146	case RTL_FW_PLA:
 5147		type = MCU_TYPE_PLA;
 5148		break;
 5149	case RTL_FW_USB:
 5150		type = MCU_TYPE_USB;
 5151		break;
 5152	default:
 5153		return;
 5154	}
 5155
 5156	fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
 5157	if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, fw_ver_reg) >= mac->fw_ver_data) {
 5158		dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB");
 5159		return;
 5160	}
 5161
 5162	rtl_clear_bp(tp, type);
 5163
 5164	/* Enable backup/restore of MACDBG. This is required after clearing PLA
 5165	 * break points and before applying the PLA firmware.
 5166	 */
 5167	if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
 5168	    !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
 5169		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
 5170		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
 5171	}
 5172
 5173	length = __le32_to_cpu(mac->blk_hdr.length);
 5174	length -= __le16_to_cpu(mac->fw_offset);
 5175
 5176	data = (u8 *)mac;
 5177	data += __le16_to_cpu(mac->fw_offset);
 5178
 5179	generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
 5180			  type);
 5181
 5182	ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
 5183		       __le16_to_cpu(mac->bp_ba_value));
 5184
 5185	generic_ocp_write(tp, __le16_to_cpu(mac->bp_start), BYTE_EN_DWORD,
 5186			  __le16_to_cpu(mac->bp_num) << 1, mac->bp, type);
 5187
 5188	bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
 5189	if (bp_en_addr)
 5190		ocp_write_word(tp, type, bp_en_addr,
 5191			       __le16_to_cpu(mac->bp_en_value));
 5192
 5193	if (fw_ver_reg)
 5194		ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
 5195			       mac->fw_ver_data);
 5196
 5197	dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
 5198}
 5199
 5200static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut)
 5201{
 5202	struct rtl_fw *rtl_fw = &tp->rtl_fw;
 5203	const struct firmware *fw;
 5204	struct fw_header *fw_hdr;
 5205	struct fw_phy_patch_key *key;
 5206	u16 key_addr = 0;
 5207	int i, patch_phy = 1;
 5208
 5209	if (IS_ERR_OR_NULL(rtl_fw->fw))
 5210		return;
 5211
 5212	fw = rtl_fw->fw;
 5213	fw_hdr = (struct fw_header *)fw->data;
 5214
 5215	if (rtl_fw->pre_fw)
 5216		rtl_fw->pre_fw(tp);
 5217
 5218	for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
 5219		struct fw_block *block = (struct fw_block *)&fw->data[i];
 5220
 5221		switch (__le32_to_cpu(block->type)) {
 5222		case RTL_FW_END:
 5223			goto post_fw;
 5224		case RTL_FW_PLA:
 5225		case RTL_FW_USB:
 5226			rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
 5227			break;
 5228		case RTL_FW_PHY_START:
 5229			if (!patch_phy)
 5230				break;
 5231			key = (struct fw_phy_patch_key *)block;
 5232			key_addr = __le16_to_cpu(key->key_reg);
 5233			rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut);
 5234			break;
 5235		case RTL_FW_PHY_STOP:
 5236			if (!patch_phy)
 5237				break;
 5238			WARN_ON(!key_addr);
 5239			rtl_post_ram_code(tp, key_addr, !power_cut);
 5240			break;
 5241		case RTL_FW_PHY_NC:
 5242			rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
 5243			break;
 5244		case RTL_FW_PHY_VER:
 5245			patch_phy = rtl8152_fw_phy_ver(tp, (struct fw_phy_ver *)block);
 5246			break;
 5247		case RTL_FW_PHY_UNION_NC:
 5248		case RTL_FW_PHY_UNION_NC1:
 5249		case RTL_FW_PHY_UNION_NC2:
 5250		case RTL_FW_PHY_UNION_UC2:
 5251		case RTL_FW_PHY_UNION_UC:
 5252		case RTL_FW_PHY_UNION_MISC:
 5253			if (patch_phy)
 5254				rtl8152_fw_phy_union_apply(tp, (struct fw_phy_union *)block);
 5255			break;
 5256		case RTL_FW_PHY_FIXUP:
 5257			if (patch_phy)
 5258				rtl8152_fw_phy_fixup(tp, (struct fw_phy_fixup *)block);
 5259			break;
 5260		case RTL_FW_PHY_SPEED_UP:
 5261			rtl_ram_code_speed_up(tp, (struct fw_phy_speed_up *)block, !power_cut);
 5262			break;
 5263		default:
 5264			break;
 5265		}
 5266
 5267		i += ALIGN(__le32_to_cpu(block->length), 8);
 5268	}
 5269
 5270post_fw:
 5271	if (rtl_fw->post_fw)
 5272		rtl_fw->post_fw(tp);
 5273
 5274	rtl_reset_ocp_base(tp);
 5275	strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
 5276	dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
 5277}
 5278
 5279static void rtl8152_release_firmware(struct r8152 *tp)
 5280{
 5281	struct rtl_fw *rtl_fw = &tp->rtl_fw;
 5282
 5283	if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
 5284		release_firmware(rtl_fw->fw);
 5285		rtl_fw->fw = NULL;
 5286	}
 5287}
 5288
 5289static int rtl8152_request_firmware(struct r8152 *tp)
 5290{
 5291	struct rtl_fw *rtl_fw = &tp->rtl_fw;
 5292	long rc;
 5293
 5294	if (rtl_fw->fw || !rtl_fw->fw_name) {
 5295		dev_info(&tp->intf->dev, "skip request firmware\n");
 5296		rc = 0;
 5297		goto result;
 5298	}
 5299
 5300	rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
 5301	if (rc < 0)
 5302		goto result;
 5303
 5304	rc = rtl8152_check_firmware(tp, rtl_fw);
 5305	if (rc < 0)
 5306		release_firmware(rtl_fw->fw);
 5307
 5308result:
 5309	if (rc) {
 5310		rtl_fw->fw = ERR_PTR(rc);
 5311
 5312		dev_warn(&tp->intf->dev,
 5313			 "unable to load firmware patch %s (%ld)\n",
 5314			 rtl_fw->fw_name, rc);
 5315	}
 5316
 5317	return rc;
 5318}
 5319
 5320static void r8152_aldps_en(struct r8152 *tp, bool enable)
 5321{
 5322	if (enable) {
 5323		ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
 5324						    LINKENA | DIS_SDSAVE);
 5325	} else {
 5326		ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
 5327						    DIS_SDSAVE);
 5328		msleep(20);
 5329	}
 5330}
 5331
 5332static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
 5333{
 5334	ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
 5335	ocp_reg_write(tp, OCP_EEE_DATA, reg);
 5336	ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
 5337}
 5338
 5339static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
 5340{
 5341	u16 data;
 5342
 5343	r8152_mmd_indirect(tp, dev, reg);
 5344	data = ocp_reg_read(tp, OCP_EEE_DATA);
 5345	ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
 5346
 5347	return data;
 5348}
 5349
 5350static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
 5351{
 5352	r8152_mmd_indirect(tp, dev, reg);
 5353	ocp_reg_write(tp, OCP_EEE_DATA, data);
 5354	ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
 5355}
 5356
 5357static void r8152_eee_en(struct r8152 *tp, bool enable)
 5358{
 5359	u16 config1, config2, config3;
 5360	u32 ocp_data;
 5361
 5362	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
 5363	config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
 5364	config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
 5365	config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
 5366
 5367	if (enable) {
 5368		ocp_data |= EEE_RX_EN | EEE_TX_EN;
 5369		config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
 5370		config1 |= sd_rise_time(1);
 5371		config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
 5372		config3 |= fast_snr(42);
 5373	} else {
 5374		ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
 5375		config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
 5376			     RX_QUIET_EN);
 5377		config1 |= sd_rise_time(7);
 5378		config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
 5379		config3 |= fast_snr(511);
 5380	}
 5381
 5382	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
 5383	ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
 5384	ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
 5385	ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
 5386}
 5387
 5388static void r8153_eee_en(struct r8152 *tp, bool enable)
 5389{
 5390	u32 ocp_data;
 5391	u16 config;
 5392
 5393	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
 5394	config = ocp_reg_read(tp, OCP_EEE_CFG);
 5395
 5396	if (enable) {
 5397		ocp_data |= EEE_RX_EN | EEE_TX_EN;
 5398		config |= EEE10_EN;
 5399	} else {
 5400		ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
 5401		config &= ~EEE10_EN;
 5402	}
 5403
 5404	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
 5405	ocp_reg_write(tp, OCP_EEE_CFG, config);
 5406
 5407	tp->ups_info.eee = enable;
 5408}
 5409
 5410static void r8156_eee_en(struct r8152 *tp, bool enable)
 5411{
 5412	u16 config;
 5413
 5414	r8153_eee_en(tp, enable);
 5415
 5416	config = ocp_reg_read(tp, OCP_EEE_ADV2);
 5417
 5418	if (enable)
 5419		config |= MDIO_EEE_2_5GT;
 5420	else
 5421		config &= ~MDIO_EEE_2_5GT;
 5422
 5423	ocp_reg_write(tp, OCP_EEE_ADV2, config);
 5424}
 5425
 5426static void rtl_eee_enable(struct r8152 *tp, bool enable)
 5427{
 5428	switch (tp->version) {
 5429	case RTL_VER_01:
 5430	case RTL_VER_02:
 5431	case RTL_VER_07:
 5432		if (enable) {
 5433			r8152_eee_en(tp, true);
 5434			r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
 5435					tp->eee_adv);
 5436		} else {
 5437			r8152_eee_en(tp, false);
 5438			r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
 5439		}
 5440		break;
 5441	case RTL_VER_03:
 5442	case RTL_VER_04:
 5443	case RTL_VER_05:
 5444	case RTL_VER_06:
 5445	case RTL_VER_08:
 5446	case RTL_VER_09:
 5447	case RTL_VER_14:
 5448		if (enable) {
 5449			r8153_eee_en(tp, true);
 5450			ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
 5451		} else {
 5452			r8153_eee_en(tp, false);
 5453			ocp_reg_write(tp, OCP_EEE_ADV, 0);
 5454		}
 5455		break;
 5456	case RTL_VER_10:
 5457	case RTL_VER_11:
 5458	case RTL_VER_12:
 5459	case RTL_VER_13:
 5460	case RTL_VER_15:
 5461		if (enable) {
 5462			r8156_eee_en(tp, true);
 5463			ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
 5464		} else {
 5465			r8156_eee_en(tp, false);
 5466			ocp_reg_write(tp, OCP_EEE_ADV, 0);
 5467		}
 5468		break;
 5469	default:
 5470		break;
 5471	}
 5472}
 5473
 5474static void r8152b_enable_fc(struct r8152 *tp)
 5475{
 5476	u16 anar;
 5477
 5478	anar = r8152_mdio_read(tp, MII_ADVERTISE);
 5479	anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 5480	r8152_mdio_write(tp, MII_ADVERTISE, anar);
 5481
 5482	tp->ups_info.flow_control = true;
 5483}
 5484
 5485static void rtl8152_disable(struct r8152 *tp)
 5486{
 5487	r8152_aldps_en(tp, false);
 5488	rtl_disable(tp);
 5489	r8152_aldps_en(tp, true);
 5490}
 5491
 5492static void r8152b_hw_phy_cfg(struct r8152 *tp)
 5493{
 5494	rtl8152_apply_firmware(tp, false);
 5495	rtl_eee_enable(tp, tp->eee_en);
 5496	r8152_aldps_en(tp, true);
 5497	r8152b_enable_fc(tp);
 5498
 5499	set_bit(PHY_RESET, &tp->flags);
 5500}
 5501
 5502static void wait_oob_link_list_ready(struct r8152 *tp)
 5503{
 5504	u32 ocp_data;
 5505	int i;
 5506
 5507	for (i = 0; i < 1000; i++) {
 5508		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 5509			break;
 5510		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
 5511		if (ocp_data & LINK_LIST_READY)
 5512			break;
 5513		usleep_range(1000, 2000);
 5514	}
 5515}
 5516
 5517static void r8156b_wait_loading_flash(struct r8152 *tp)
 5518{
 5519	if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) &&
 5520	    !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) {
 5521		int i;
 5522
 5523		for (i = 0; i < 100; i++) {
 5524			if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 5525				break;
 5526			if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE)
 5527				break;
 5528			usleep_range(1000, 2000);
 5529		}
 5530	}
 5531}
 5532
 5533static void r8152b_exit_oob(struct r8152 *tp)
 5534{
 5535	u32 ocp_data;
 
 5536
 5537	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
 5538	ocp_data &= ~RCR_ACPT_ALL;
 5539	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
 5540
 5541	rxdy_gated_en(tp, true);
 5542	r8153_teredo_off(tp);
 5543	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
 5544	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
 5545
 5546	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
 5547	ocp_data &= ~NOW_IS_OOB;
 5548	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
 5549
 5550	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
 5551	ocp_data &= ~MCU_BORW_EN;
 5552	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
 5553
 5554	wait_oob_link_list_ready(tp);
 
 
 
 
 
 5555
 5556	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
 5557	ocp_data |= RE_INIT_LL;
 5558	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
 5559
 5560	wait_oob_link_list_ready(tp);
 
 
 
 
 
 5561
 5562	rtl8152_nic_reset(tp);
 5563
 5564	/* rx share fifo credit full threshold */
 5565	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
 5566
 5567	if (tp->udev->speed == USB_SPEED_FULL ||
 5568	    tp->udev->speed == USB_SPEED_LOW) {
 5569		/* rx share fifo credit near full threshold */
 5570		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
 5571				RXFIFO_THR2_FULL);
 5572		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
 5573				RXFIFO_THR3_FULL);
 5574	} else {
 5575		/* rx share fifo credit near full threshold */
 5576		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
 5577				RXFIFO_THR2_HIGH);
 5578		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
 5579				RXFIFO_THR3_HIGH);
 5580	}
 5581
 5582	/* TX share fifo free credit full threshold */
 5583	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
 5584
 5585	ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
 5586	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
 5587	ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
 5588			TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
 5589
 5590	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
 5591
 5592	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
 5593
 5594	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
 5595	ocp_data |= TCR0_AUTO_FIFO;
 5596	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
 5597}
 5598
 5599static void r8152b_enter_oob(struct r8152 *tp)
 5600{
 5601	u32 ocp_data;
 
 5602
 5603	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
 5604	ocp_data &= ~NOW_IS_OOB;
 5605	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
 5606
 5607	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
 5608	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
 5609	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
 5610
 5611	rtl_disable(tp);
 5612
 5613	wait_oob_link_list_ready(tp);
 
 
 
 
 
 5614
 5615	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
 5616	ocp_data |= RE_INIT_LL;
 5617	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
 5618
 5619	wait_oob_link_list_ready(tp);
 
 
 
 
 
 5620
 5621	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
 5622
 5623	rtl_rx_vlan_en(tp, true);
 5624
 5625	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
 5626	ocp_data |= ALDPS_PROXY_MODE;
 5627	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
 5628
 5629	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
 5630	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
 5631	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
 5632
 5633	rxdy_gated_en(tp, false);
 5634
 5635	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
 5636	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
 5637	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
 5638}
 5639
 5640static int r8153_pre_firmware_1(struct r8152 *tp)
 5641{
 
 5642	int i;
 5643
 5644	/* Wait till the WTD timer is ready. It would take at most 104 ms. */
 5645	for (i = 0; i < 104; i++) {
 5646		u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
 
 
 
 5647
 5648		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 5649			return -ENODEV;
 5650		if (!(ocp_data & WTD1_EN))
 5651			break;
 5652		usleep_range(1000, 2000);
 
 
 5653	}
 5654
 5655	return 0;
 5656}
 5657
 5658static int r8153_post_firmware_1(struct r8152 *tp)
 5659{
 5660	/* set USB_BP_4 to support USB_SPEED_SUPER only */
 5661	if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
 5662		ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
 5663
 5664	/* reset UPHY timer to 36 ms */
 5665	ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
 5666
 5667	return 0;
 5668}
 5669
 5670static int r8153_pre_firmware_2(struct r8152 *tp)
 5671{
 5672	u32 ocp_data;
 5673
 5674	r8153_pre_firmware_1(tp);
 5675
 5676	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
 5677	ocp_data &= ~FW_FIX_SUSPEND;
 5678	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
 5679
 5680	return 0;
 5681}
 5682
 5683static int r8153_post_firmware_2(struct r8152 *tp)
 5684{
 5685	u32 ocp_data;
 5686
 5687	/* enable bp0 if support USB_SPEED_SUPER only */
 5688	if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
 5689		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
 5690		ocp_data |= BIT(0);
 5691		ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
 5692	}
 5693
 5694	/* reset UPHY timer to 36 ms */
 5695	ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
 5696
 5697	/* enable U3P3 check, set the counter to 4 */
 5698	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
 5699
 5700	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
 5701	ocp_data |= FW_FIX_SUSPEND;
 5702	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
 5703
 5704	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
 5705	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
 5706	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
 5707
 5708	return 0;
 5709}
 5710
 5711static int r8153_post_firmware_3(struct r8152 *tp)
 5712{
 5713	u32 ocp_data;
 5714
 5715	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
 5716	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
 5717	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
 5718
 5719	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
 5720	ocp_data |= FW_IP_RESET_EN;
 5721	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
 5722
 5723	return 0;
 5724}
 5725
 5726static int r8153b_pre_firmware_1(struct r8152 *tp)
 5727{
 5728	/* enable fc timer and set timer to 1 second. */
 5729	ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
 5730		       CTRL_TIMER_EN | (1000 / 8));
 5731
 5732	return 0;
 5733}
 5734
 5735static int r8153b_post_firmware_1(struct r8152 *tp)
 5736{
 5737	u32 ocp_data;
 5738
 5739	/* enable bp0 for RTL8153-BND */
 5740	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
 5741	if (ocp_data & BND_MASK) {
 5742		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
 5743		ocp_data |= BIT(0);
 5744		ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
 5745	}
 5746
 5747	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
 5748	ocp_data |= FLOW_CTRL_PATCH_OPT;
 5749	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
 5750
 5751	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
 5752	ocp_data |= FC_PATCH_TASK;
 5753	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
 5754
 5755	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
 5756	ocp_data |= FW_IP_RESET_EN;
 5757	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
 5758
 5759	return 0;
 5760}
 5761
 5762static int r8153c_post_firmware_1(struct r8152 *tp)
 5763{
 5764	u32 ocp_data;
 5765
 5766	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
 5767	ocp_data |= FLOW_CTRL_PATCH_2;
 5768	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
 5769
 5770	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
 5771	ocp_data |= FC_PATCH_TASK;
 5772	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
 5773
 5774	return 0;
 5775}
 5776
 5777static int r8156a_post_firmware_1(struct r8152 *tp)
 5778{
 5779	u32 ocp_data;
 5780
 5781	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
 5782	ocp_data |= FW_IP_RESET_EN;
 5783	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
 5784
 5785	/* Modify U3PHY parameter for compatibility issue */
 5786	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e);
 5787	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9);
 5788
 5789	return 0;
 5790}
 5791
 5792static void r8153_aldps_en(struct r8152 *tp, bool enable)
 5793{
 5794	u16 data;
 5795
 5796	data = ocp_reg_read(tp, OCP_POWER_CFG);
 5797	if (enable) {
 5798		data |= EN_ALDPS;
 5799		ocp_reg_write(tp, OCP_POWER_CFG, data);
 5800	} else {
 5801		int i;
 5802
 5803		data &= ~EN_ALDPS;
 5804		ocp_reg_write(tp, OCP_POWER_CFG, data);
 5805		for (i = 0; i < 20; i++) {
 5806			if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 5807				return;
 5808			usleep_range(1000, 2000);
 5809			if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
 5810				break;
 5811		}
 5812	}
 5813
 5814	tp->ups_info.aldps = enable;
 5815}
 5816
 5817static void r8153_hw_phy_cfg(struct r8152 *tp)
 5818{
 5819	u32 ocp_data;
 5820	u16 data;
 5821
 5822	/* disable ALDPS before updating the PHY parameters */
 5823	r8153_aldps_en(tp, false);
 5824
 5825	/* disable EEE before updating the PHY parameters */
 5826	rtl_eee_enable(tp, false);
 5827
 5828	rtl8152_apply_firmware(tp, false);
 5829
 5830	if (tp->version == RTL_VER_03) {
 5831		data = ocp_reg_read(tp, OCP_EEE_CFG);
 5832		data &= ~CTAP_SHORT_EN;
 5833		ocp_reg_write(tp, OCP_EEE_CFG, data);
 5834	}
 5835
 5836	data = ocp_reg_read(tp, OCP_POWER_CFG);
 5837	data |= EEE_CLKDIV_EN;
 5838	ocp_reg_write(tp, OCP_POWER_CFG, data);
 5839
 5840	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
 5841	data |= EN_10M_BGOFF;
 5842	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
 5843	data = ocp_reg_read(tp, OCP_POWER_CFG);
 5844	data |= EN_10M_PLLOFF;
 5845	ocp_reg_write(tp, OCP_POWER_CFG, data);
 5846	sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
 5847
 5848	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
 5849	ocp_data |= PFM_PWM_SWITCH;
 5850	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
 5851
 5852	/* Enable LPF corner auto tune */
 5853	sram_write(tp, SRAM_LPF_CFG, 0xf70f);
 5854
 5855	/* Adjust 10M Amplitude */
 5856	sram_write(tp, SRAM_10M_AMP1, 0x00af);
 5857	sram_write(tp, SRAM_10M_AMP2, 0x0208);
 5858
 5859	if (tp->eee_en)
 5860		rtl_eee_enable(tp, true);
 5861
 5862	r8153_aldps_en(tp, true);
 5863	r8152b_enable_fc(tp);
 5864
 5865	switch (tp->version) {
 5866	case RTL_VER_03:
 5867	case RTL_VER_04:
 5868		break;
 5869	case RTL_VER_05:
 5870	case RTL_VER_06:
 5871	default:
 5872		r8153_u2p3en(tp, true);
 5873		break;
 5874	}
 5875
 5876	set_bit(PHY_RESET, &tp->flags);
 5877}
 5878
 5879static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
 5880{
 5881	u32 ocp_data;
 5882
 5883	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
 5884	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
 5885	ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9;	/* data of bit16 */
 5886	ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
 5887
 5888	return ocp_data;
 5889}
 5890
 5891static void r8153b_hw_phy_cfg(struct r8152 *tp)
 5892{
 5893	u32 ocp_data;
 5894	u16 data;
 5895
 5896	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
 5897	if (ocp_data & PCUT_STATUS) {
 5898		ocp_data &= ~PCUT_STATUS;
 5899		ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
 5900	}
 5901
 5902	/* disable ALDPS before updating the PHY parameters */
 5903	r8153_aldps_en(tp, false);
 5904
 5905	/* disable EEE before updating the PHY parameters */
 5906	rtl_eee_enable(tp, false);
 5907
 5908	/* U1/U2/L1 idle timer. 500 us */
 5909	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
 5910
 5911	data = r8153_phy_status(tp, 0);
 5912
 5913	switch (data) {
 5914	case PHY_STAT_PWRDN:
 5915	case PHY_STAT_EXT_INIT:
 5916		rtl8152_apply_firmware(tp, true);
 5917
 5918		data = r8152_mdio_read(tp, MII_BMCR);
 5919		data &= ~BMCR_PDOWN;
 5920		r8152_mdio_write(tp, MII_BMCR, data);
 5921		break;
 5922	case PHY_STAT_LAN_ON:
 5923	default:
 5924		rtl8152_apply_firmware(tp, false);
 5925		break;
 5926	}
 5927
 5928	r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
 5929
 5930	data = sram_read(tp, SRAM_GREEN_CFG);
 5931	data |= R_TUNE_EN;
 5932	sram_write(tp, SRAM_GREEN_CFG, data);
 5933	data = ocp_reg_read(tp, OCP_NCTL_CFG);
 5934	data |= PGA_RETURN_EN;
 5935	ocp_reg_write(tp, OCP_NCTL_CFG, data);
 5936
 5937	/* ADC Bias Calibration:
 5938	 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
 5939	 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
 5940	 * ADC ioffset.
 5941	 */
 5942	ocp_data = r8152_efuse_read(tp, 0x7d);
 5943	data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
 5944	if (data != 0xffff)
 5945		ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
 5946
 5947	/* ups mode tx-link-pulse timing adjustment:
 5948	 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
 5949	 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
 5950	 */
 5951	ocp_data = ocp_reg_read(tp, 0xc426);
 5952	ocp_data &= 0x3fff;
 5953	if (ocp_data) {
 5954		u32 swr_cnt_1ms_ini;
 5955
 5956		swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
 5957		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
 5958		ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
 5959		ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
 5960	}
 5961
 5962	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
 5963	ocp_data |= PFM_PWM_SWITCH;
 5964	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
 5965
 5966	/* Advnace EEE */
 5967	if (!rtl_phy_patch_request(tp, true, true)) {
 5968		data = ocp_reg_read(tp, OCP_POWER_CFG);
 5969		data |= EEE_CLKDIV_EN;
 5970		ocp_reg_write(tp, OCP_POWER_CFG, data);
 5971		tp->ups_info.eee_ckdiv = true;
 5972
 5973		data = ocp_reg_read(tp, OCP_DOWN_SPEED);
 5974		data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
 5975		ocp_reg_write(tp, OCP_DOWN_SPEED, data);
 5976		tp->ups_info.eee_cmod_lv = true;
 5977		tp->ups_info._10m_ckdiv = true;
 5978		tp->ups_info.eee_plloff_giga = true;
 5979
 5980		ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
 5981		ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
 5982		tp->ups_info._250m_ckdiv = true;
 5983
 5984		rtl_phy_patch_request(tp, false, true);
 5985	}
 5986
 5987	if (tp->eee_en)
 5988		rtl_eee_enable(tp, true);
 5989
 5990	r8153_aldps_en(tp, true);
 5991	r8152b_enable_fc(tp);
 
 5992
 5993	set_bit(PHY_RESET, &tp->flags);
 5994}
 5995
 5996static void r8153c_hw_phy_cfg(struct r8152 *tp)
 5997{
 5998	r8153b_hw_phy_cfg(tp);
 5999
 6000	tp->ups_info.r_tune = true;
 6001}
 6002
 6003static void rtl8153_change_mtu(struct r8152 *tp)
 6004{
 6005	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
 6006	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
 6007}
 6008
 6009static void r8153_first_init(struct r8152 *tp)
 6010{
 6011	u32 ocp_data;
 
 6012
 
 6013	rxdy_gated_en(tp, true);
 6014	r8153_teredo_off(tp);
 6015
 6016	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
 6017	ocp_data &= ~RCR_ACPT_ALL;
 6018	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
 6019
 6020	rtl8152_nic_reset(tp);
 6021	rtl_reset_bmu(tp);
 6022
 6023	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
 6024	ocp_data &= ~NOW_IS_OOB;
 6025	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
 6026
 6027	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
 6028	ocp_data &= ~MCU_BORW_EN;
 6029	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
 6030
 6031	wait_oob_link_list_ready(tp);
 
 
 
 
 
 6032
 6033	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
 6034	ocp_data |= RE_INIT_LL;
 6035	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
 6036
 6037	wait_oob_link_list_ready(tp);
 
 
 
 
 
 6038
 6039	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
 6040
 6041	rtl8153_change_mtu(tp);
 
 
 6042
 6043	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
 6044	ocp_data |= TCR0_AUTO_FIFO;
 6045	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
 6046
 6047	rtl8152_nic_reset(tp);
 6048
 6049	/* rx share fifo credit full threshold */
 6050	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
 6051	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
 6052	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
 6053	/* TX share fifo free credit full threshold */
 6054	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
 6055}
 6056
 6057static void r8153_enter_oob(struct r8152 *tp)
 6058{
 6059	u32 ocp_data;
 
 
 
 6060
 6061	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
 6062	ocp_data &= ~NOW_IS_OOB;
 6063	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
 6064
 6065	/* RX FIFO settings for OOB */
 6066	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
 6067	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
 6068	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
 6069
 6070	rtl_disable(tp);
 6071	rtl_reset_bmu(tp);
 6072
 6073	wait_oob_link_list_ready(tp);
 
 
 
 
 
 6074
 6075	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
 6076	ocp_data |= RE_INIT_LL;
 6077	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
 6078
 6079	wait_oob_link_list_ready(tp);
 
 
 
 
 
 6080
 6081	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522);
 6082	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);
 6083
 6084	switch (tp->version) {
 6085	case RTL_VER_03:
 6086	case RTL_VER_04:
 6087	case RTL_VER_05:
 6088	case RTL_VER_06:
 6089		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
 6090		ocp_data &= ~TEREDO_WAKE_MASK;
 6091		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
 6092		break;
 6093
 6094	case RTL_VER_08:
 6095	case RTL_VER_09:
 6096	case RTL_VER_14:
 6097		/* Clear teredo wake event. bit[15:8] is the teredo wakeup
 6098		 * type. Set it to zero. bits[7:0] are the W1C bits about
 6099		 * the events. Set them to all 1 to clear them.
 6100		 */
 6101		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
 6102		break;
 6103
 6104	default:
 6105		break;
 6106	}
 6107
 6108	rtl_rx_vlan_en(tp, true);
 6109
 6110	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
 6111	ocp_data |= ALDPS_PROXY_MODE;
 6112	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
 6113
 6114	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
 6115	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
 6116	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
 6117
 6118	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
 6119	ocp_data |= MCU_BORW_EN;
 6120	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
 6121
 6122	rxdy_gated_en(tp, false);
 6123
 6124	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
 6125	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
 6126	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
 6127}
 6128
 6129static void rtl8153_disable(struct r8152 *tp)
 6130{
 6131	r8153_aldps_en(tp, false);
 6132	rtl_disable(tp);
 6133	rtl_reset_bmu(tp);
 6134	r8153_aldps_en(tp, true);
 6135}
 6136
 6137static u32 fc_pause_on_auto(struct r8152 *tp)
 6138{
 6139	return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024);
 6140}
 6141
 6142static u32 fc_pause_off_auto(struct r8152 *tp)
 6143{
 6144	return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024);
 6145}
 6146
 6147static void r8156_fc_parameter(struct r8152 *tp)
 6148{
 6149	u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp);
 6150	u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp);
 6151
 6152	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16);
 6153	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16);
 6154}
 6155
 6156static int rtl8156_enable(struct r8152 *tp)
 6157{
 6158	u32 ocp_data;
 6159	u16 speed;
 6160
 6161	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 6162		return -ENODEV;
 6163
 6164	r8156_fc_parameter(tp);
 6165	set_tx_qlen(tp);
 6166	rtl_set_eee_plus(tp);
 6167	r8153_set_rx_early_timeout(tp);
 6168	r8153_set_rx_early_size(tp);
 6169
 6170	speed = rtl8152_get_speed(tp);
 6171	rtl_set_ifg(tp, speed);
 6172
 6173	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
 6174	if (speed & _2500bps)
 6175		ocp_data &= ~IDLE_SPDWN_EN;
 6176	else
 6177		ocp_data |= IDLE_SPDWN_EN;
 6178	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
 6179
 6180	if (speed & _1000bps)
 6181		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11);
 6182	else if (speed & _500bps)
 6183		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d);
 6184
 6185	if (tp->udev->speed == USB_SPEED_HIGH) {
 6186		/* USB 0xb45e[3:0] l1_nyet_hird */
 6187		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
 6188		ocp_data &= ~0xf;
 6189		if (is_flow_control(speed))
 6190			ocp_data |= 0xf;
 6191		else
 6192			ocp_data |= 0x1;
 6193		ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
 6194	}
 6195
 6196	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
 6197	ocp_data &= ~FC_PATCH_TASK;
 6198	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
 6199	usleep_range(1000, 2000);
 6200	ocp_data |= FC_PATCH_TASK;
 6201	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
 6202
 6203	return rtl_enable(tp);
 6204}
 6205
 6206static void rtl8156_disable(struct r8152 *tp)
 6207{
 6208	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 0);
 6209	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 0);
 6210
 6211	rtl8153_disable(tp);
 6212}
 6213
 6214static int rtl8156b_enable(struct r8152 *tp)
 6215{
 6216	u32 ocp_data;
 6217	u16 speed;
 6218
 6219	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 6220		return -ENODEV;
 6221
 6222	set_tx_qlen(tp);
 6223	rtl_set_eee_plus(tp);
 6224
 6225	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM);
 6226	ocp_data &= ~RX_AGGR_NUM_MASK;
 6227	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data);
 6228
 6229	r8153_set_rx_early_timeout(tp);
 6230	r8153_set_rx_early_size(tp);
 6231
 6232	speed = rtl8152_get_speed(tp);
 6233	rtl_set_ifg(tp, speed);
 6234
 6235	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
 6236	if (speed & _2500bps)
 6237		ocp_data &= ~IDLE_SPDWN_EN;
 6238	else
 6239		ocp_data |= IDLE_SPDWN_EN;
 6240	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
 6241
 6242	if (tp->udev->speed == USB_SPEED_HIGH) {
 6243		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
 6244		ocp_data &= ~0xf;
 6245		if (is_flow_control(speed))
 6246			ocp_data |= 0xf;
 6247		else
 6248			ocp_data |= 0x1;
 6249		ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
 6250	}
 6251
 6252	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
 6253	ocp_data &= ~FC_PATCH_TASK;
 6254	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
 6255	usleep_range(1000, 2000);
 6256	ocp_data |= FC_PATCH_TASK;
 6257	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
 6258
 6259	return rtl_enable(tp);
 6260}
 6261
 6262static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
 6263			     u32 advertising)
 6264{
 6265	u16 bmcr;
 6266	int ret = 0;
 6267
 6268	if (autoneg == AUTONEG_DISABLE) {
 6269		if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
 6270			return -EINVAL;
 6271
 6272		switch (speed) {
 6273		case SPEED_10:
 6274			bmcr = BMCR_SPEED10;
 6275			if (duplex == DUPLEX_FULL) {
 6276				bmcr |= BMCR_FULLDPLX;
 6277				tp->ups_info.speed_duplex = FORCE_10M_FULL;
 6278			} else {
 6279				tp->ups_info.speed_duplex = FORCE_10M_HALF;
 6280			}
 6281			break;
 6282		case SPEED_100:
 6283			bmcr = BMCR_SPEED100;
 6284			if (duplex == DUPLEX_FULL) {
 6285				bmcr |= BMCR_FULLDPLX;
 6286				tp->ups_info.speed_duplex = FORCE_100M_FULL;
 6287			} else {
 6288				tp->ups_info.speed_duplex = FORCE_100M_HALF;
 6289			}
 6290			break;
 6291		case SPEED_1000:
 6292			if (tp->mii.supports_gmii) {
 6293				bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
 6294				tp->ups_info.speed_duplex = NWAY_1000M_FULL;
 6295				break;
 6296			}
 6297			fallthrough;
 6298		default:
 6299			ret = -EINVAL;
 6300			goto out;
 6301		}
 6302
 6303		if (duplex == DUPLEX_FULL)
 6304			tp->mii.full_duplex = 1;
 6305		else
 6306			tp->mii.full_duplex = 0;
 6307
 6308		tp->mii.force_media = 1;
 6309	} else {
 6310		u16 orig, new1;
 6311		u32 support;
 6312
 6313		support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
 6314			  RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
 6315
 6316		if (tp->mii.supports_gmii) {
 6317			support |= RTL_ADVERTISED_1000_FULL;
 6318
 6319			if (tp->support_2500full)
 6320				support |= RTL_ADVERTISED_2500_FULL;
 6321		}
 6322
 6323		if (!(advertising & support))
 6324			return -EINVAL;
 6325
 6326		orig = r8152_mdio_read(tp, MII_ADVERTISE);
 6327		new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
 6328				ADVERTISE_100HALF | ADVERTISE_100FULL);
 6329		if (advertising & RTL_ADVERTISED_10_HALF) {
 6330			new1 |= ADVERTISE_10HALF;
 6331			tp->ups_info.speed_duplex = NWAY_10M_HALF;
 6332		}
 6333		if (advertising & RTL_ADVERTISED_10_FULL) {
 6334			new1 |= ADVERTISE_10FULL;
 6335			tp->ups_info.speed_duplex = NWAY_10M_FULL;
 6336		}
 6337
 6338		if (advertising & RTL_ADVERTISED_100_HALF) {
 6339			new1 |= ADVERTISE_100HALF;
 6340			tp->ups_info.speed_duplex = NWAY_100M_HALF;
 6341		}
 6342		if (advertising & RTL_ADVERTISED_100_FULL) {
 6343			new1 |= ADVERTISE_100FULL;
 6344			tp->ups_info.speed_duplex = NWAY_100M_FULL;
 6345		}
 6346
 6347		if (orig != new1) {
 6348			r8152_mdio_write(tp, MII_ADVERTISE, new1);
 6349			tp->mii.advertising = new1;
 6350		}
 6351
 6352		if (tp->mii.supports_gmii) {
 6353			orig = r8152_mdio_read(tp, MII_CTRL1000);
 6354			new1 = orig & ~(ADVERTISE_1000FULL |
 
 
 6355					ADVERTISE_1000HALF);
 6356
 6357			if (advertising & RTL_ADVERTISED_1000_FULL) {
 6358				new1 |= ADVERTISE_1000FULL;
 6359				tp->ups_info.speed_duplex = NWAY_1000M_FULL;
 6360			}
 6361
 6362			if (orig != new1)
 6363				r8152_mdio_write(tp, MII_CTRL1000, new1);
 6364		}
 6365
 6366		if (tp->support_2500full) {
 6367			orig = ocp_reg_read(tp, OCP_10GBT_CTRL);
 6368			new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G;
 6369
 6370			if (advertising & RTL_ADVERTISED_2500_FULL) {
 6371				new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G;
 6372				tp->ups_info.speed_duplex = NWAY_2500M_FULL;
 6373			}
 6374
 6375			if (orig != new1)
 6376				ocp_reg_write(tp, OCP_10GBT_CTRL, new1);
 6377		}
 6378
 6379		bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
 6380
 6381		tp->mii.force_media = 0;
 6382	}
 6383
 6384	if (test_and_clear_bit(PHY_RESET, &tp->flags))
 6385		bmcr |= BMCR_RESET;
 6386
 6387	r8152_mdio_write(tp, MII_BMCR, bmcr);
 6388
 6389	if (bmcr & BMCR_RESET) {
 6390		int i;
 6391
 6392		for (i = 0; i < 50; i++) {
 6393			msleep(20);
 6394			if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
 6395				break;
 6396		}
 6397	}
 6398
 6399out:
 6400	return ret;
 6401}
 6402
 6403static void rtl8152_up(struct r8152 *tp)
 6404{
 6405	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 6406		return;
 6407
 6408	r8152_aldps_en(tp, false);
 6409	r8152b_exit_oob(tp);
 6410	r8152_aldps_en(tp, true);
 6411}
 6412
 6413static void rtl8152_down(struct r8152 *tp)
 6414{
 6415	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
 6416		rtl_drop_queued_tx(tp);
 6417		return;
 6418	}
 6419
 6420	r8152_power_cut_en(tp, false);
 6421	r8152_aldps_en(tp, false);
 6422	r8152b_enter_oob(tp);
 6423	r8152_aldps_en(tp, true);
 6424}
 6425
 6426static void rtl8153_up(struct r8152 *tp)
 6427{
 6428	u32 ocp_data;
 6429
 6430	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 6431		return;
 6432
 6433	r8153_u1u2en(tp, false);
 6434	r8153_u2p3en(tp, false);
 6435	r8153_aldps_en(tp, false);
 6436	r8153_first_init(tp);
 6437
 6438	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
 6439	ocp_data |= LANWAKE_CLR_EN;
 6440	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
 6441
 6442	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
 6443	ocp_data &= ~LANWAKE_PIN;
 6444	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
 6445
 6446	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
 6447	ocp_data &= ~DELAY_PHY_PWR_CHG;
 6448	ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
 6449
 6450	r8153_aldps_en(tp, true);
 6451
 6452	switch (tp->version) {
 6453	case RTL_VER_03:
 6454	case RTL_VER_04:
 6455		break;
 6456	case RTL_VER_05:
 6457	case RTL_VER_06:
 6458	default:
 6459		r8153_u2p3en(tp, true);
 6460		break;
 6461	}
 6462
 6463	r8153_u1u2en(tp, true);
 6464}
 6465
 6466static void rtl8153_down(struct r8152 *tp)
 6467{
 6468	u32 ocp_data;
 6469
 6470	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
 6471		rtl_drop_queued_tx(tp);
 6472		return;
 6473	}
 6474
 6475	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
 6476	ocp_data &= ~LANWAKE_CLR_EN;
 6477	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
 6478
 6479	r8153_u1u2en(tp, false);
 6480	r8153_u2p3en(tp, false);
 6481	r8153_power_cut_en(tp, false);
 6482	r8153_aldps_en(tp, false);
 6483	r8153_enter_oob(tp);
 6484	r8153_aldps_en(tp, true);
 6485}
 6486
 6487static void rtl8153b_up(struct r8152 *tp)
 6488{
 6489	u32 ocp_data;
 6490
 6491	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 6492		return;
 6493
 6494	r8153b_u1u2en(tp, false);
 6495	r8153_u2p3en(tp, false);
 6496	r8153_aldps_en(tp, false);
 6497
 6498	r8153_first_init(tp);
 6499	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
 6500
 6501	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
 6502	ocp_data &= ~PLA_MCU_SPDWN_EN;
 6503	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
 6504
 6505	r8153_aldps_en(tp, true);
 6506
 6507	if (tp->udev->speed >= USB_SPEED_SUPER)
 6508		r8153b_u1u2en(tp, true);
 6509}
 6510
 6511static void rtl8153b_down(struct r8152 *tp)
 6512{
 6513	u32 ocp_data;
 6514
 6515	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
 6516		rtl_drop_queued_tx(tp);
 6517		return;
 6518	}
 6519
 6520	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
 6521	ocp_data |= PLA_MCU_SPDWN_EN;
 6522	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
 6523
 6524	r8153b_u1u2en(tp, false);
 6525	r8153_u2p3en(tp, false);
 6526	r8153b_power_cut_en(tp, false);
 6527	r8153_aldps_en(tp, false);
 6528	r8153_enter_oob(tp);
 6529	r8153_aldps_en(tp, true);
 6530}
 6531
 6532static void rtl8153c_change_mtu(struct r8152 *tp)
 6533{
 6534	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
 6535	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64);
 6536
 6537	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
 6538
 6539	/* Adjust the tx fifo free credit full threshold, otherwise
 6540	 * the fifo would be too small to send a jumbo frame packet.
 6541	 */
 6542	if (tp->netdev->mtu < 8000)
 6543		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8);
 6544	else
 6545		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8);
 6546}
 6547
 6548static void rtl8153c_up(struct r8152 *tp)
 6549{
 6550	u32 ocp_data;
 6551
 6552	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 6553		return;
 6554
 6555	r8153b_u1u2en(tp, false);
 6556	r8153_u2p3en(tp, false);
 6557	r8153_aldps_en(tp, false);
 6558
 6559	rxdy_gated_en(tp, true);
 6560	r8153_teredo_off(tp);
 6561
 6562	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
 6563	ocp_data &= ~RCR_ACPT_ALL;
 6564	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
 6565
 6566	rtl8152_nic_reset(tp);
 6567	rtl_reset_bmu(tp);
 6568
 6569	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
 6570	ocp_data &= ~NOW_IS_OOB;
 6571	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
 6572
 6573	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
 6574	ocp_data &= ~MCU_BORW_EN;
 6575	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
 6576
 6577	wait_oob_link_list_ready(tp);
 6578
 6579	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
 6580	ocp_data |= RE_INIT_LL;
 6581	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
 6582
 6583	wait_oob_link_list_ready(tp);
 6584
 6585	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
 6586
 6587	rtl8153c_change_mtu(tp);
 6588
 6589	rtl8152_nic_reset(tp);
 6590
 6591	/* rx share fifo credit full threshold */
 6592	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02);
 6593	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08);
 6594	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
 6595	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
 6596
 6597	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
 6598
 6599	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
 6600
 6601	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
 6602	ocp_data |= BIT(8);
 6603	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
 6604
 6605	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
 6606
 6607	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
 6608	ocp_data &= ~PLA_MCU_SPDWN_EN;
 6609	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
 6610
 6611	r8153_aldps_en(tp, true);
 6612	r8153b_u1u2en(tp, true);
 6613}
 6614
 6615static void rtl8156_change_mtu(struct r8152 *tp)
 6616{
 6617	u32 rx_max_size = mtu_to_size(tp->netdev->mtu);
 6618
 6619	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size);
 6620	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
 6621	r8156_fc_parameter(tp);
 6622
 6623	/* TX share fifo free credit full threshold */
 6624	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
 6625	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL,
 6626		       ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16);
 6627}
 6628
 6629static void rtl8156_up(struct r8152 *tp)
 6630{
 6631	u32 ocp_data;
 6632
 6633	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 6634		return;
 6635
 6636	r8153b_u1u2en(tp, false);
 6637	r8153_u2p3en(tp, false);
 6638	r8153_aldps_en(tp, false);
 6639
 6640	rxdy_gated_en(tp, true);
 6641	r8153_teredo_off(tp);
 6642
 6643	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
 6644	ocp_data &= ~RCR_ACPT_ALL;
 6645	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
 6646
 6647	rtl8152_nic_reset(tp);
 6648	rtl_reset_bmu(tp);
 6649
 6650	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
 6651	ocp_data &= ~NOW_IS_OOB;
 6652	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
 6653
 6654	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
 6655	ocp_data &= ~MCU_BORW_EN;
 6656	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
 6657
 6658	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
 6659
 6660	rtl8156_change_mtu(tp);
 6661
 6662	switch (tp->version) {
 6663	case RTL_TEST_01:
 6664	case RTL_VER_10:
 6665	case RTL_VER_11:
 6666		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
 6667		ocp_data |= ACT_ODMA;
 6668		ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
 6669		break;
 6670	default:
 6671		break;
 6672	}
 6673
 6674	/* share FIFO settings */
 6675	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL);
 6676	ocp_data &= ~RXFIFO_FULL_MASK;
 6677	ocp_data |= 0x08;
 6678	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data);
 6679
 6680	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
 6681	ocp_data &= ~PLA_MCU_SPDWN_EN;
 6682	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
 6683
 6684	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION);
 6685	ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF);
 6686	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data);
 6687
 6688	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400);
 6689
 6690	if (tp->saved_wolopts != __rtl_get_wol(tp)) {
 6691		netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n");
 6692		__rtl_set_wol(tp, tp->saved_wolopts);
 6693	}
 6694
 6695	r8153_aldps_en(tp, true);
 6696	r8153_u2p3en(tp, true);
 6697
 6698	if (tp->udev->speed >= USB_SPEED_SUPER)
 6699		r8153b_u1u2en(tp, true);
 6700}
 6701
 6702static void rtl8156_down(struct r8152 *tp)
 6703{
 6704	u32 ocp_data;
 6705
 6706	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
 6707		rtl_drop_queued_tx(tp);
 6708		return;
 6709	}
 6710
 6711	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
 6712	ocp_data |= PLA_MCU_SPDWN_EN;
 6713	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
 6714
 6715	r8153b_u1u2en(tp, false);
 6716	r8153_u2p3en(tp, false);
 6717	r8153b_power_cut_en(tp, false);
 6718	r8153_aldps_en(tp, false);
 6719
 6720	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
 6721	ocp_data &= ~NOW_IS_OOB;
 6722	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
 6723
 6724	/* RX FIFO settings for OOB */
 6725	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 64 / 16);
 6726	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 1024 / 16);
 6727	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 4096 / 16);
 6728
 6729	rtl_disable(tp);
 6730	rtl_reset_bmu(tp);
 6731
 6732	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522);
 6733	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);
 6734
 6735	/* Clear teredo wake event. bit[15:8] is the teredo wakeup
 6736	 * type. Set it to zero. bits[7:0] are the W1C bits about
 6737	 * the events. Set them to all 1 to clear them.
 6738	 */
 6739	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
 6740
 6741	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
 6742	ocp_data |= NOW_IS_OOB;
 6743	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
 6744
 6745	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
 6746	ocp_data |= MCU_BORW_EN;
 6747	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
 6748
 6749	rtl_rx_vlan_en(tp, true);
 6750	rxdy_gated_en(tp, false);
 6751
 6752	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
 6753	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
 6754	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
 6755
 6756	r8153_aldps_en(tp, true);
 6757}
 6758
 6759static bool rtl8152_in_nway(struct r8152 *tp)
 6760{
 6761	u16 nway_state;
 6762
 6763	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
 6764	tp->ocp_base = 0x2000;
 6765	ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c);		/* phy state */
 6766	nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
 6767
 6768	/* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
 6769	if (nway_state & 0xc000)
 6770		return false;
 6771	else
 6772		return true;
 6773}
 6774
 6775static bool rtl8153_in_nway(struct r8152 *tp)
 6776{
 6777	u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
 6778
 6779	if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
 6780		return false;
 6781	else
 6782		return true;
 6783}
 6784
 6785static void r8156_mdio_force_mode(struct r8152 *tp)
 6786{
 6787	u16 data;
 6788
 6789	/* Select force mode through 0xa5b4 bit 15
 6790	 * 0: MDIO force mode
 6791	 * 1: MMD force mode
 6792	 */
 6793	data = ocp_reg_read(tp, 0xa5b4);
 6794	if (data & BIT(15)) {
 6795		data &= ~BIT(15);
 6796		ocp_reg_write(tp, 0xa5b4, data);
 6797	}
 6798}
 6799
 6800static void set_carrier(struct r8152 *tp)
 6801{
 6802	struct net_device *netdev = tp->netdev;
 6803	struct napi_struct *napi = &tp->napi;
 6804	u16 speed;
 6805
 6806	speed = rtl8152_get_speed(tp);
 6807
 6808	if (speed & LINK_STATUS) {
 6809		if (!netif_carrier_ok(netdev)) {
 6810			tp->rtl_ops.enable(tp);
 6811			netif_stop_queue(netdev);
 6812			napi_disable(napi);
 6813			netif_carrier_on(netdev);
 6814			rtl_start_rx(tp);
 6815			clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
 6816			_rtl8152_set_rx_mode(netdev);
 6817			napi_enable(napi);
 6818			netif_wake_queue(netdev);
 6819			netif_info(tp, link, netdev, "carrier on\n");
 6820		} else if (netif_queue_stopped(netdev) &&
 6821			   skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
 6822			netif_wake_queue(netdev);
 6823		}
 6824	} else {
 6825		if (netif_carrier_ok(netdev)) {
 6826			netif_carrier_off(netdev);
 6827			tasklet_disable(&tp->tx_tl);
 6828			napi_disable(napi);
 6829			tp->rtl_ops.disable(tp);
 6830			napi_enable(napi);
 6831			tasklet_enable(&tp->tx_tl);
 6832			netif_info(tp, link, netdev, "carrier off\n");
 6833		}
 6834	}
 6835}
 6836
 6837static void rtl_work_func_t(struct work_struct *work)
 6838{
 6839	struct r8152 *tp = container_of(work, struct r8152, schedule.work);
 6840
 6841	/* If the device is unplugged or !netif_running(), the workqueue
 6842	 * doesn't need to wake the device, and could return directly.
 6843	 */
 6844	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) || !netif_running(tp->netdev))
 6845		return;
 6846
 6847	if (usb_autopm_get_interface(tp->intf) < 0)
 6848		return;
 6849
 6850	if (!test_bit(WORK_ENABLE, &tp->flags))
 6851		goto out1;
 6852
 6853	if (!mutex_trylock(&tp->control)) {
 6854		schedule_delayed_work(&tp->schedule, 0);
 6855		goto out1;
 6856	}
 6857
 6858	if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
 6859		set_carrier(tp);
 6860
 6861	if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
 6862		_rtl8152_set_rx_mode(tp->netdev);
 6863
 6864	/* don't schedule tasket before linking */
 6865	if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
 6866	    netif_carrier_ok(tp->netdev))
 6867		tasklet_schedule(&tp->tx_tl);
 6868
 6869	if (test_and_clear_bit(RX_EPROTO, &tp->flags) &&
 6870	    !list_empty(&tp->rx_done))
 6871		napi_schedule(&tp->napi);
 6872
 6873	mutex_unlock(&tp->control);
 6874
 6875out1:
 6876	usb_autopm_put_interface(tp->intf);
 6877}
 6878
 6879static void rtl_hw_phy_work_func_t(struct work_struct *work)
 6880{
 6881	struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
 6882
 6883	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 6884		return;
 6885
 6886	if (usb_autopm_get_interface(tp->intf) < 0)
 6887		return;
 6888
 6889	mutex_lock(&tp->control);
 6890
 6891	if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
 6892		tp->rtl_fw.retry = false;
 6893		tp->rtl_fw.fw = NULL;
 6894
 6895		/* Delay execution in case request_firmware() is not ready yet.
 6896		 */
 6897		queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
 6898		goto ignore_once;
 6899	}
 6900
 6901	tp->rtl_ops.hw_phy_cfg(tp);
 6902
 6903	rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
 6904			  tp->advertising);
 6905
 6906ignore_once:
 6907	mutex_unlock(&tp->control);
 6908
 6909	usb_autopm_put_interface(tp->intf);
 6910}
 6911
 6912#ifdef CONFIG_PM_SLEEP
 6913static int rtl_notifier(struct notifier_block *nb, unsigned long action,
 6914			void *data)
 6915{
 6916	struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
 6917
 6918	switch (action) {
 6919	case PM_HIBERNATION_PREPARE:
 6920	case PM_SUSPEND_PREPARE:
 6921		usb_autopm_get_interface(tp->intf);
 6922		break;
 6923
 6924	case PM_POST_HIBERNATION:
 6925	case PM_POST_SUSPEND:
 6926		usb_autopm_put_interface(tp->intf);
 6927		break;
 6928
 6929	case PM_POST_RESTORE:
 6930	case PM_RESTORE_PREPARE:
 6931	default:
 6932		break;
 6933	}
 6934
 6935	return NOTIFY_DONE;
 6936}
 6937#endif
 6938
 6939static int rtl8152_open(struct net_device *netdev)
 6940{
 6941	struct r8152 *tp = netdev_priv(netdev);
 6942	int res = 0;
 6943
 6944	if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
 6945		cancel_delayed_work_sync(&tp->hw_phy_work);
 6946		rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
 6947	}
 6948
 6949	res = alloc_all_mem(tp);
 6950	if (res)
 6951		goto out;
 6952
 6953	res = usb_autopm_get_interface(tp->intf);
 6954	if (res < 0)
 6955		goto out_free;
 6956
 6957	mutex_lock(&tp->control);
 6958
 6959	tp->rtl_ops.up(tp);
 6960
 6961	netif_carrier_off(netdev);
 6962	netif_start_queue(netdev);
 6963	set_bit(WORK_ENABLE, &tp->flags);
 6964
 6965	res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
 6966	if (res) {
 6967		if (res == -ENODEV)
 6968			netif_device_detach(tp->netdev);
 6969		netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
 6970			   res);
 6971		goto out_unlock;
 6972	}
 6973	napi_enable(&tp->napi);
 6974	tasklet_enable(&tp->tx_tl);
 6975
 6976	mutex_unlock(&tp->control);
 6977
 6978	usb_autopm_put_interface(tp->intf);
 6979#ifdef CONFIG_PM_SLEEP
 6980	tp->pm_notifier.notifier_call = rtl_notifier;
 6981	register_pm_notifier(&tp->pm_notifier);
 6982#endif
 6983	return 0;
 6984
 6985out_unlock:
 6986	mutex_unlock(&tp->control);
 6987	usb_autopm_put_interface(tp->intf);
 6988out_free:
 6989	free_all_mem(tp);
 6990out:
 6991	return res;
 6992}
 6993
 6994static int rtl8152_close(struct net_device *netdev)
 6995{
 6996	struct r8152 *tp = netdev_priv(netdev);
 6997	int res = 0;
 6998
 6999#ifdef CONFIG_PM_SLEEP
 7000	unregister_pm_notifier(&tp->pm_notifier);
 7001#endif
 7002	tasklet_disable(&tp->tx_tl);
 7003	clear_bit(WORK_ENABLE, &tp->flags);
 7004	usb_kill_urb(tp->intr_urb);
 7005	cancel_delayed_work_sync(&tp->schedule);
 7006	napi_disable(&tp->napi);
 7007	netif_stop_queue(netdev);
 7008
 7009	res = usb_autopm_get_interface(tp->intf);
 7010	if (res < 0 || test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
 7011		rtl_drop_queued_tx(tp);
 7012		rtl_stop_rx(tp);
 7013	} else {
 7014		mutex_lock(&tp->control);
 7015
 7016		tp->rtl_ops.down(tp);
 7017
 7018		mutex_unlock(&tp->control);
 7019	}
 7020
 7021	if (!res)
 7022		usb_autopm_put_interface(tp->intf);
 
 7023
 7024	free_all_mem(tp);
 7025
 7026	return res;
 7027}
 7028
 7029static void rtl_tally_reset(struct r8152 *tp)
 7030{
 7031	u32 ocp_data;
 7032
 7033	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
 7034	ocp_data |= TALLY_RESET;
 7035	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
 7036}
 7037
 7038static void r8152b_init(struct r8152 *tp)
 7039{
 7040	u32 ocp_data;
 7041	u16 data;
 7042
 7043	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 7044		return;
 7045
 7046	data = r8152_mdio_read(tp, MII_BMCR);
 7047	if (data & BMCR_PDOWN) {
 7048		data &= ~BMCR_PDOWN;
 7049		r8152_mdio_write(tp, MII_BMCR, data);
 7050	}
 7051
 7052	r8152_aldps_en(tp, false);
 7053
 7054	if (tp->version == RTL_VER_01) {
 7055		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
 7056		ocp_data &= ~LED_MODE_MASK;
 7057		ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
 7058	}
 7059
 7060	r8152_power_cut_en(tp, false);
 7061
 7062	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
 7063	ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
 7064	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
 7065	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
 7066	ocp_data &= ~MCU_CLK_RATIO_MASK;
 7067	ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
 7068	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
 7069	ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
 7070		   SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
 7071	ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
 7072
 7073	rtl_tally_reset(tp);
 7074
 7075	/* enable rx aggregation */
 7076	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
 7077	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
 7078	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
 7079}
 7080
 7081static void r8153_init(struct r8152 *tp)
 7082{
 7083	u32 ocp_data;
 7084	u16 data;
 7085	int i;
 7086
 7087	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 7088		return;
 7089
 7090	r8153_u1u2en(tp, false);
 7091
 7092	for (i = 0; i < 500; i++) {
 7093		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
 7094		    AUTOLOAD_DONE)
 7095			break;
 7096
 7097		msleep(20);
 7098		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 7099			break;
 7100	}
 7101
 7102	data = r8153_phy_status(tp, 0);
 7103
 7104	if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
 7105	    tp->version == RTL_VER_05)
 7106		ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
 7107
 7108	data = r8152_mdio_read(tp, MII_BMCR);
 7109	if (data & BMCR_PDOWN) {
 7110		data &= ~BMCR_PDOWN;
 7111		r8152_mdio_write(tp, MII_BMCR, data);
 7112	}
 7113
 7114	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
 7115
 7116	r8153_u2p3en(tp, false);
 7117
 7118	if (tp->version == RTL_VER_04) {
 7119		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
 7120		ocp_data &= ~pwd_dn_scale_mask;
 7121		ocp_data |= pwd_dn_scale(96);
 7122		ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
 7123
 7124		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
 7125		ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
 7126		ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
 7127	} else if (tp->version == RTL_VER_05) {
 7128		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
 7129		ocp_data &= ~ECM_ALDPS;
 7130		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
 7131
 7132		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
 7133		if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
 7134			ocp_data &= ~DYNAMIC_BURST;
 7135		else
 7136			ocp_data |= DYNAMIC_BURST;
 7137		ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
 7138	} else if (tp->version == RTL_VER_06) {
 7139		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
 7140		if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
 7141			ocp_data &= ~DYNAMIC_BURST;
 7142		else
 7143			ocp_data |= DYNAMIC_BURST;
 7144		ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
 7145
 7146		r8153_queue_wake(tp, false);
 7147
 7148		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
 7149		if (rtl8152_get_speed(tp) & LINK_STATUS)
 7150			ocp_data |= CUR_LINK_OK;
 7151		else
 7152			ocp_data &= ~CUR_LINK_OK;
 7153		ocp_data |= POLL_LINK_CHG;
 7154		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
 7155	}
 7156
 7157	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
 7158	ocp_data |= EP4_FULL_FC;
 7159	ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
 7160
 7161	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
 7162	ocp_data &= ~TIMER11_EN;
 7163	ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
 7164
 7165	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
 7166	ocp_data &= ~LED_MODE_MASK;
 7167	ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
 7168
 7169	ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
 7170	if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
 7171		ocp_data |= LPM_TIMER_500MS;
 7172	else
 7173		ocp_data |= LPM_TIMER_500US;
 7174	ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
 7175
 7176	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
 7177	ocp_data &= ~SEN_VAL_MASK;
 7178	ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
 7179	ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
 7180
 7181	ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
 7182
 7183	r8153_power_cut_en(tp, false);
 7184	rtl_runtime_suspend_enable(tp, false);
 7185	r8153_mac_clk_speed_down(tp, false);
 7186	r8153_u1u2en(tp, true);
 
 7187	usb_enable_lpm(tp->udev);
 7188
 7189	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
 7190	ocp_data |= LANWAKE_CLR_EN;
 7191	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
 7192
 7193	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
 7194	ocp_data &= ~LANWAKE_PIN;
 7195	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
 7196
 7197	/* rx aggregation */
 7198	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
 7199	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
 7200	if (tp->dell_tb_rx_agg_bug)
 7201		ocp_data |= RX_AGG_DISABLE;
 7202
 7203	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
 7204
 7205	rtl_tally_reset(tp);
 7206
 7207	switch (tp->udev->speed) {
 7208	case USB_SPEED_SUPER:
 7209	case USB_SPEED_SUPER_PLUS:
 7210		tp->coalesce = COALESCE_SUPER;
 7211		break;
 7212	case USB_SPEED_HIGH:
 7213		tp->coalesce = COALESCE_HIGH;
 7214		break;
 7215	default:
 7216		tp->coalesce = COALESCE_SLOW;
 7217		break;
 7218	}
 7219}
 7220
 7221static void r8153b_init(struct r8152 *tp)
 7222{
 7223	u32 ocp_data;
 7224	u16 data;
 7225	int i;
 7226
 7227	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 7228		return;
 7229
 7230	r8153b_u1u2en(tp, false);
 7231
 7232	for (i = 0; i < 500; i++) {
 7233		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
 7234		    AUTOLOAD_DONE)
 7235			break;
 7236
 7237		msleep(20);
 7238		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 7239			break;
 7240	}
 7241
 7242	data = r8153_phy_status(tp, 0);
 7243
 7244	data = r8152_mdio_read(tp, MII_BMCR);
 7245	if (data & BMCR_PDOWN) {
 7246		data &= ~BMCR_PDOWN;
 7247		r8152_mdio_write(tp, MII_BMCR, data);
 7248	}
 7249
 7250	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
 7251
 7252	r8153_u2p3en(tp, false);
 7253
 7254	/* MSC timer = 0xfff * 8ms = 32760 ms */
 7255	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
 7256
 7257	r8153b_power_cut_en(tp, false);
 7258	r8153b_ups_en(tp, false);
 7259	r8153_queue_wake(tp, false);
 7260	rtl_runtime_suspend_enable(tp, false);
 7261
 7262	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
 7263	if (rtl8152_get_speed(tp) & LINK_STATUS)
 7264		ocp_data |= CUR_LINK_OK;
 7265	else
 7266		ocp_data &= ~CUR_LINK_OK;
 7267	ocp_data |= POLL_LINK_CHG;
 7268	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
 7269
 7270	if (tp->udev->speed >= USB_SPEED_SUPER)
 7271		r8153b_u1u2en(tp, true);
 7272
 7273	usb_enable_lpm(tp->udev);
 7274
 7275	/* MAC clock speed down */
 7276	r8153_mac_clk_speed_down(tp, true);
 7277
 7278	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
 7279	ocp_data &= ~PLA_MCU_SPDWN_EN;
 7280	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
 7281
 7282	if (tp->version == RTL_VER_09) {
 7283		/* Disable Test IO for 32QFN */
 7284		if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
 7285			ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
 7286			ocp_data |= TEST_IO_OFF;
 7287			ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
 7288		}
 7289	}
 7290
 7291	set_bit(GREEN_ETHERNET, &tp->flags);
 7292
 7293	/* rx aggregation */
 7294	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
 7295	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
 7296	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
 7297
 7298	rtl_tally_reset(tp);
 7299
 7300	tp->coalesce = 15000;	/* 15 us */
 7301}
 7302
 7303static void r8153c_init(struct r8152 *tp)
 7304{
 7305	u32 ocp_data;
 7306	u16 data;
 7307	int i;
 7308
 7309	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 7310		return;
 7311
 7312	r8153b_u1u2en(tp, false);
 7313
 7314	/* Disable spi_en */
 7315	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
 7316	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
 7317	ocp_data &= ~BIT(3);
 7318	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
 7319	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0);
 7320	ocp_data |= BIT(1);
 7321	ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data);
 7322
 7323	for (i = 0; i < 500; i++) {
 7324		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
 7325		    AUTOLOAD_DONE)
 7326			break;
 7327
 7328		msleep(20);
 7329		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 7330			return;
 7331	}
 7332
 7333	data = r8153_phy_status(tp, 0);
 7334
 7335	data = r8152_mdio_read(tp, MII_BMCR);
 7336	if (data & BMCR_PDOWN) {
 7337		data &= ~BMCR_PDOWN;
 7338		r8152_mdio_write(tp, MII_BMCR, data);
 7339	}
 7340
 7341	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
 7342
 7343	r8153_u2p3en(tp, false);
 7344
 7345	/* MSC timer = 0xfff * 8ms = 32760 ms */
 7346	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
 7347
 7348	r8153b_power_cut_en(tp, false);
 7349	r8153c_ups_en(tp, false);
 7350	r8153_queue_wake(tp, false);
 7351	rtl_runtime_suspend_enable(tp, false);
 7352
 7353	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
 7354	if (rtl8152_get_speed(tp) & LINK_STATUS)
 7355		ocp_data |= CUR_LINK_OK;
 7356	else
 7357		ocp_data &= ~CUR_LINK_OK;
 7358
 7359	ocp_data |= POLL_LINK_CHG;
 7360	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
 7361
 7362	r8153b_u1u2en(tp, true);
 7363
 7364	usb_enable_lpm(tp->udev);
 7365
 7366	/* MAC clock speed down */
 7367	r8153_mac_clk_speed_down(tp, true);
 7368
 7369	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
 7370	ocp_data &= ~BIT(7);
 7371	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
 7372
 7373	set_bit(GREEN_ETHERNET, &tp->flags);
 7374
 7375	/* rx aggregation */
 7376	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
 7377	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
 7378	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
 7379
 7380	rtl_tally_reset(tp);
 7381
 7382	tp->coalesce = 15000;	/* 15 us */
 7383}
 7384
 7385static void r8156_hw_phy_cfg(struct r8152 *tp)
 7386{
 7387	u32 ocp_data;
 7388	u16 data;
 7389
 7390	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
 7391	if (ocp_data & PCUT_STATUS) {
 7392		ocp_data &= ~PCUT_STATUS;
 7393		ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
 7394	}
 7395
 7396	data = r8153_phy_status(tp, 0);
 7397	switch (data) {
 7398	case PHY_STAT_EXT_INIT:
 7399		rtl8152_apply_firmware(tp, true);
 7400
 7401		data = ocp_reg_read(tp, 0xa468);
 7402		data &= ~(BIT(3) | BIT(1));
 7403		ocp_reg_write(tp, 0xa468, data);
 7404		break;
 7405	case PHY_STAT_LAN_ON:
 7406	case PHY_STAT_PWRDN:
 7407	default:
 7408		rtl8152_apply_firmware(tp, false);
 7409		break;
 7410	}
 7411
 7412	/* disable ALDPS before updating the PHY parameters */
 7413	r8153_aldps_en(tp, false);
 7414
 7415	/* disable EEE before updating the PHY parameters */
 7416	rtl_eee_enable(tp, false);
 7417
 7418	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
 7419	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
 7420
 7421	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
 7422	ocp_data |= PFM_PWM_SWITCH;
 7423	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
 7424
 7425	switch (tp->version) {
 7426	case RTL_VER_10:
 7427		data = ocp_reg_read(tp, 0xad40);
 7428		data &= ~0x3ff;
 7429		data |= BIT(7) | BIT(2);
 7430		ocp_reg_write(tp, 0xad40, data);
 7431
 7432		data = ocp_reg_read(tp, 0xad4e);
 7433		data |= BIT(4);
 7434		ocp_reg_write(tp, 0xad4e, data);
 7435		data = ocp_reg_read(tp, 0xad16);
 7436		data &= ~0x3ff;
 7437		data |= 0x6;
 7438		ocp_reg_write(tp, 0xad16, data);
 7439		data = ocp_reg_read(tp, 0xad32);
 7440		data &= ~0x3f;
 7441		data |= 6;
 7442		ocp_reg_write(tp, 0xad32, data);
 7443		data = ocp_reg_read(tp, 0xac08);
 7444		data &= ~(BIT(12) | BIT(8));
 7445		ocp_reg_write(tp, 0xac08, data);
 7446		data = ocp_reg_read(tp, 0xac8a);
 7447		data |= BIT(12) | BIT(13) | BIT(14);
 7448		data &= ~BIT(15);
 7449		ocp_reg_write(tp, 0xac8a, data);
 7450		data = ocp_reg_read(tp, 0xad18);
 7451		data |= BIT(10);
 7452		ocp_reg_write(tp, 0xad18, data);
 7453		data = ocp_reg_read(tp, 0xad1a);
 7454		data |= 0x3ff;
 7455		ocp_reg_write(tp, 0xad1a, data);
 7456		data = ocp_reg_read(tp, 0xad1c);
 7457		data |= 0x3ff;
 7458		ocp_reg_write(tp, 0xad1c, data);
 7459
 7460		data = sram_read(tp, 0x80ea);
 7461		data &= ~0xff00;
 7462		data |= 0xc400;
 7463		sram_write(tp, 0x80ea, data);
 7464		data = sram_read(tp, 0x80eb);
 7465		data &= ~0x0700;
 7466		data |= 0x0300;
 7467		sram_write(tp, 0x80eb, data);
 7468		data = sram_read(tp, 0x80f8);
 7469		data &= ~0xff00;
 7470		data |= 0x1c00;
 7471		sram_write(tp, 0x80f8, data);
 7472		data = sram_read(tp, 0x80f1);
 7473		data &= ~0xff00;
 7474		data |= 0x3000;
 7475		sram_write(tp, 0x80f1, data);
 7476
 7477		data = sram_read(tp, 0x80fe);
 7478		data &= ~0xff00;
 7479		data |= 0xa500;
 7480		sram_write(tp, 0x80fe, data);
 7481		data = sram_read(tp, 0x8102);
 7482		data &= ~0xff00;
 7483		data |= 0x5000;
 7484		sram_write(tp, 0x8102, data);
 7485		data = sram_read(tp, 0x8015);
 7486		data &= ~0xff00;
 7487		data |= 0x3300;
 7488		sram_write(tp, 0x8015, data);
 7489		data = sram_read(tp, 0x8100);
 7490		data &= ~0xff00;
 7491		data |= 0x7000;
 7492		sram_write(tp, 0x8100, data);
 7493		data = sram_read(tp, 0x8014);
 7494		data &= ~0xff00;
 7495		data |= 0xf000;
 7496		sram_write(tp, 0x8014, data);
 7497		data = sram_read(tp, 0x8016);
 7498		data &= ~0xff00;
 7499		data |= 0x6500;
 7500		sram_write(tp, 0x8016, data);
 7501		data = sram_read(tp, 0x80dc);
 7502		data &= ~0xff00;
 7503		data |= 0xed00;
 7504		sram_write(tp, 0x80dc, data);
 7505		data = sram_read(tp, 0x80df);
 7506		data |= BIT(8);
 7507		sram_write(tp, 0x80df, data);
 7508		data = sram_read(tp, 0x80e1);
 7509		data &= ~BIT(8);
 7510		sram_write(tp, 0x80e1, data);
 7511
 7512		data = ocp_reg_read(tp, 0xbf06);
 7513		data &= ~0x003f;
 7514		data |= 0x0038;
 7515		ocp_reg_write(tp, 0xbf06, data);
 7516
 7517		sram_write(tp, 0x819f, 0xddb6);
 7518
 7519		ocp_reg_write(tp, 0xbc34, 0x5555);
 7520		data = ocp_reg_read(tp, 0xbf0a);
 7521		data &= ~0x0e00;
 7522		data |= 0x0a00;
 7523		ocp_reg_write(tp, 0xbf0a, data);
 7524
 7525		data = ocp_reg_read(tp, 0xbd2c);
 7526		data &= ~BIT(13);
 7527		ocp_reg_write(tp, 0xbd2c, data);
 7528		break;
 7529	case RTL_VER_11:
 7530		data = ocp_reg_read(tp, 0xad16);
 7531		data |= 0x3ff;
 7532		ocp_reg_write(tp, 0xad16, data);
 7533		data = ocp_reg_read(tp, 0xad32);
 7534		data &= ~0x3f;
 7535		data |= 6;
 7536		ocp_reg_write(tp, 0xad32, data);
 7537		data = ocp_reg_read(tp, 0xac08);
 7538		data &= ~(BIT(12) | BIT(8));
 7539		ocp_reg_write(tp, 0xac08, data);
 7540		data = ocp_reg_read(tp, 0xacc0);
 7541		data &= ~0x3;
 7542		data |= BIT(1);
 7543		ocp_reg_write(tp, 0xacc0, data);
 7544		data = ocp_reg_read(tp, 0xad40);
 7545		data &= ~0xe7;
 7546		data |= BIT(6) | BIT(2);
 7547		ocp_reg_write(tp, 0xad40, data);
 7548		data = ocp_reg_read(tp, 0xac14);
 7549		data &= ~BIT(7);
 7550		ocp_reg_write(tp, 0xac14, data);
 7551		data = ocp_reg_read(tp, 0xac80);
 7552		data &= ~(BIT(8) | BIT(9));
 7553		ocp_reg_write(tp, 0xac80, data);
 7554		data = ocp_reg_read(tp, 0xac5e);
 7555		data &= ~0x7;
 7556		data |= BIT(1);
 7557		ocp_reg_write(tp, 0xac5e, data);
 7558		ocp_reg_write(tp, 0xad4c, 0x00a8);
 7559		ocp_reg_write(tp, 0xac5c, 0x01ff);
 7560		data = ocp_reg_read(tp, 0xac8a);
 7561		data &= ~0xf0;
 7562		data |= BIT(4) | BIT(5);
 7563		ocp_reg_write(tp, 0xac8a, data);
 7564		ocp_reg_write(tp, 0xb87c, 0x8157);
 7565		data = ocp_reg_read(tp, 0xb87e);
 7566		data &= ~0xff00;
 7567		data |= 0x0500;
 7568		ocp_reg_write(tp, 0xb87e, data);
 7569		ocp_reg_write(tp, 0xb87c, 0x8159);
 7570		data = ocp_reg_read(tp, 0xb87e);
 7571		data &= ~0xff00;
 7572		data |= 0x0700;
 7573		ocp_reg_write(tp, 0xb87e, data);
 7574
 7575		/* AAGC */
 7576		ocp_reg_write(tp, 0xb87c, 0x80a2);
 7577		ocp_reg_write(tp, 0xb87e, 0x0153);
 7578		ocp_reg_write(tp, 0xb87c, 0x809c);
 7579		ocp_reg_write(tp, 0xb87e, 0x0153);
 7580
 7581		/* EEE parameter */
 7582		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056);
 7583
 7584		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG);
 7585		ocp_data |= EN_XG_LIP | EN_G_LIP;
 7586		ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
 7587
 7588		sram_write(tp, 0x8257, 0x020f); /*  XG PLL */
 7589		sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */
 7590
 7591		if (rtl_phy_patch_request(tp, true, true))
 7592			return;
 7593
 7594		/* Advance EEE */
 7595		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
 7596		ocp_data |= EEE_SPDWN_EN;
 7597		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
 7598
 7599		data = ocp_reg_read(tp, OCP_DOWN_SPEED);
 7600		data &= ~(EN_EEE_100 | EN_EEE_1000);
 7601		data |= EN_10M_CLKDIV;
 7602		ocp_reg_write(tp, OCP_DOWN_SPEED, data);
 7603		tp->ups_info._10m_ckdiv = true;
 7604		tp->ups_info.eee_plloff_100 = false;
 7605		tp->ups_info.eee_plloff_giga = false;
 7606
 7607		data = ocp_reg_read(tp, OCP_POWER_CFG);
 7608		data &= ~EEE_CLKDIV_EN;
 7609		ocp_reg_write(tp, OCP_POWER_CFG, data);
 7610		tp->ups_info.eee_ckdiv = false;
 7611
 7612		ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
 7613		ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5));
 7614		tp->ups_info._250m_ckdiv = false;
 7615
 7616		rtl_phy_patch_request(tp, false, true);
 7617
 7618		/* enable ADC Ibias Cal */
 7619		data = ocp_reg_read(tp, 0xd068);
 7620		data |= BIT(13);
 7621		ocp_reg_write(tp, 0xd068, data);
 7622
 7623		/* enable Thermal Sensor */
 7624		data = sram_read(tp, 0x81a2);
 7625		data &= ~BIT(8);
 7626		sram_write(tp, 0x81a2, data);
 7627		data = ocp_reg_read(tp, 0xb54c);
 7628		data &= ~0xff00;
 7629		data |= 0xdb00;
 7630		ocp_reg_write(tp, 0xb54c, data);
 7631
 7632		/* Nway 2.5G Lite */
 7633		data = ocp_reg_read(tp, 0xa454);
 7634		data &= ~BIT(0);
 7635		ocp_reg_write(tp, 0xa454, data);
 7636
 7637		/* CS DSP solution */
 7638		data = ocp_reg_read(tp, OCP_10GBT_CTRL);
 7639		data |= RTL_ADV2_5G_F_R;
 7640		ocp_reg_write(tp, OCP_10GBT_CTRL, data);
 7641		data = ocp_reg_read(tp, 0xad4e);
 7642		data &= ~BIT(4);
 7643		ocp_reg_write(tp, 0xad4e, data);
 7644		data = ocp_reg_read(tp, 0xa86a);
 7645		data &= ~BIT(0);
 7646		ocp_reg_write(tp, 0xa86a, data);
 7647
 7648		/* MDI SWAP */
 7649		if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) &&
 7650		    (ocp_reg_read(tp, 0xd068) & BIT(1))) {
 7651			u16 swap_a, swap_b;
 7652
 7653			data = ocp_reg_read(tp, 0xd068);
 7654			data &= ~0x1f;
 7655			data |= 0x1; /* p0 */
 7656			ocp_reg_write(tp, 0xd068, data);
 7657			swap_a = ocp_reg_read(tp, 0xd06a);
 7658			data &= ~0x18;
 7659			data |= 0x18; /* p3 */
 7660			ocp_reg_write(tp, 0xd068, data);
 7661			swap_b = ocp_reg_read(tp, 0xd06a);
 7662			data &= ~0x18; /* p0 */
 7663			ocp_reg_write(tp, 0xd068, data);
 7664			ocp_reg_write(tp, 0xd06a,
 7665				      (swap_a & ~0x7ff) | (swap_b & 0x7ff));
 7666			data |= 0x18; /* p3 */
 7667			ocp_reg_write(tp, 0xd068, data);
 7668			ocp_reg_write(tp, 0xd06a,
 7669				      (swap_b & ~0x7ff) | (swap_a & 0x7ff));
 7670			data &= ~0x18;
 7671			data |= 0x08; /* p1 */
 7672			ocp_reg_write(tp, 0xd068, data);
 7673			swap_a = ocp_reg_read(tp, 0xd06a);
 7674			data &= ~0x18;
 7675			data |= 0x10; /* p2 */
 7676			ocp_reg_write(tp, 0xd068, data);
 7677			swap_b = ocp_reg_read(tp, 0xd06a);
 7678			data &= ~0x18;
 7679			data |= 0x08; /* p1 */
 7680			ocp_reg_write(tp, 0xd068, data);
 7681			ocp_reg_write(tp, 0xd06a,
 7682				      (swap_a & ~0x7ff) | (swap_b & 0x7ff));
 7683			data &= ~0x18;
 7684			data |= 0x10; /* p2 */
 7685			ocp_reg_write(tp, 0xd068, data);
 7686			ocp_reg_write(tp, 0xd06a,
 7687				      (swap_b & ~0x7ff) | (swap_a & 0x7ff));
 7688			swap_a = ocp_reg_read(tp, 0xbd5a);
 7689			swap_b = ocp_reg_read(tp, 0xbd5c);
 7690			ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) |
 7691				      ((swap_b & 0x1f) << 8) |
 7692				      ((swap_b >> 8) & 0x1f));
 7693			ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) |
 7694				      ((swap_a & 0x1f) << 8) |
 7695				      ((swap_a >> 8) & 0x1f));
 7696			swap_a = ocp_reg_read(tp, 0xbc18);
 7697			swap_b = ocp_reg_read(tp, 0xbc1a);
 7698			ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) |
 7699				      ((swap_b & 0x1f) << 8) |
 7700				      ((swap_b >> 8) & 0x1f));
 7701			ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) |
 7702				      ((swap_a & 0x1f) << 8) |
 7703				      ((swap_a >> 8) & 0x1f));
 7704		}
 7705
 7706		/* Notify the MAC when the speed is changed to force mode. */
 7707		data = ocp_reg_read(tp, OCP_INTR_EN);
 7708		data |= INTR_SPEED_FORCE;
 7709		ocp_reg_write(tp, OCP_INTR_EN, data);
 7710		break;
 7711	default:
 7712		break;
 7713	}
 7714
 7715	rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
 7716
 7717	data = ocp_reg_read(tp, 0xa428);
 7718	data &= ~BIT(9);
 7719	ocp_reg_write(tp, 0xa428, data);
 7720	data = ocp_reg_read(tp, 0xa5ea);
 7721	data &= ~BIT(0);
 7722	ocp_reg_write(tp, 0xa5ea, data);
 7723	tp->ups_info.lite_mode = 0;
 7724
 7725	if (tp->eee_en)
 7726		rtl_eee_enable(tp, true);
 7727
 7728	r8153_aldps_en(tp, true);
 7729	r8152b_enable_fc(tp);
 7730	r8153_u2p3en(tp, true);
 7731
 7732	set_bit(PHY_RESET, &tp->flags);
 7733}
 7734
 7735static void r8156b_hw_phy_cfg(struct r8152 *tp)
 7736{
 7737	u32 ocp_data;
 7738	u16 data;
 7739
 7740	switch (tp->version) {
 7741	case RTL_VER_12:
 7742		ocp_reg_write(tp, 0xbf86, 0x9000);
 7743		data = ocp_reg_read(tp, 0xc402);
 7744		data |= BIT(10);
 7745		ocp_reg_write(tp, 0xc402, data);
 7746		data &= ~BIT(10);
 7747		ocp_reg_write(tp, 0xc402, data);
 7748		ocp_reg_write(tp, 0xbd86, 0x1010);
 7749		ocp_reg_write(tp, 0xbd88, 0x1010);
 7750		data = ocp_reg_read(tp, 0xbd4e);
 7751		data &= ~(BIT(10) | BIT(11));
 7752		data |= BIT(11);
 7753		ocp_reg_write(tp, 0xbd4e, data);
 7754		data = ocp_reg_read(tp, 0xbf46);
 7755		data &= ~0xf00;
 7756		data |= 0x700;
 7757		ocp_reg_write(tp, 0xbf46, data);
 7758		break;
 7759	case RTL_VER_13:
 7760	case RTL_VER_15:
 7761		r8156b_wait_loading_flash(tp);
 7762		break;
 7763	default:
 7764		break;
 7765	}
 7766
 7767	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
 7768	if (ocp_data & PCUT_STATUS) {
 7769		ocp_data &= ~PCUT_STATUS;
 7770		ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
 7771	}
 7772
 7773	data = r8153_phy_status(tp, 0);
 7774	switch (data) {
 7775	case PHY_STAT_EXT_INIT:
 7776		rtl8152_apply_firmware(tp, true);
 7777
 7778		data = ocp_reg_read(tp, 0xa466);
 7779		data &= ~BIT(0);
 7780		ocp_reg_write(tp, 0xa466, data);
 7781
 7782		data = ocp_reg_read(tp, 0xa468);
 7783		data &= ~(BIT(3) | BIT(1));
 7784		ocp_reg_write(tp, 0xa468, data);
 7785		break;
 7786	case PHY_STAT_LAN_ON:
 7787	case PHY_STAT_PWRDN:
 7788	default:
 7789		rtl8152_apply_firmware(tp, false);
 7790		break;
 7791	}
 7792
 7793	data = r8152_mdio_read(tp, MII_BMCR);
 7794	if (data & BMCR_PDOWN) {
 7795		data &= ~BMCR_PDOWN;
 7796		r8152_mdio_write(tp, MII_BMCR, data);
 7797	}
 7798
 7799	/* disable ALDPS before updating the PHY parameters */
 7800	r8153_aldps_en(tp, false);
 7801
 7802	/* disable EEE before updating the PHY parameters */
 7803	rtl_eee_enable(tp, false);
 7804
 7805	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
 7806	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
 7807
 7808	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
 7809	ocp_data |= PFM_PWM_SWITCH;
 7810	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
 7811
 7812	switch (tp->version) {
 7813	case RTL_VER_12:
 7814		data = ocp_reg_read(tp, 0xbc08);
 7815		data |= BIT(3) | BIT(2);
 7816		ocp_reg_write(tp, 0xbc08, data);
 7817
 7818		data = sram_read(tp, 0x8fff);
 7819		data &= ~0xff00;
 7820		data |= 0x0400;
 7821		sram_write(tp, 0x8fff, data);
 7822
 7823		data = ocp_reg_read(tp, 0xacda);
 7824		data |= 0xff00;
 7825		ocp_reg_write(tp, 0xacda, data);
 7826		data = ocp_reg_read(tp, 0xacde);
 7827		data |= 0xf000;
 7828		ocp_reg_write(tp, 0xacde, data);
 7829		ocp_reg_write(tp, 0xac8c, 0x0ffc);
 7830		ocp_reg_write(tp, 0xac46, 0xb7b4);
 7831		ocp_reg_write(tp, 0xac50, 0x0fbc);
 7832		ocp_reg_write(tp, 0xac3c, 0x9240);
 7833		ocp_reg_write(tp, 0xac4e, 0x0db4);
 7834		ocp_reg_write(tp, 0xacc6, 0x0707);
 7835		ocp_reg_write(tp, 0xacc8, 0xa0d3);
 7836		ocp_reg_write(tp, 0xad08, 0x0007);
 7837
 7838		ocp_reg_write(tp, 0xb87c, 0x8560);
 7839		ocp_reg_write(tp, 0xb87e, 0x19cc);
 7840		ocp_reg_write(tp, 0xb87c, 0x8562);
 7841		ocp_reg_write(tp, 0xb87e, 0x19cc);
 7842		ocp_reg_write(tp, 0xb87c, 0x8564);
 7843		ocp_reg_write(tp, 0xb87e, 0x19cc);
 7844		ocp_reg_write(tp, 0xb87c, 0x8566);
 7845		ocp_reg_write(tp, 0xb87e, 0x147d);
 7846		ocp_reg_write(tp, 0xb87c, 0x8568);
 7847		ocp_reg_write(tp, 0xb87e, 0x147d);
 7848		ocp_reg_write(tp, 0xb87c, 0x856a);
 7849		ocp_reg_write(tp, 0xb87e, 0x147d);
 7850		ocp_reg_write(tp, 0xb87c, 0x8ffe);
 7851		ocp_reg_write(tp, 0xb87e, 0x0907);
 7852		ocp_reg_write(tp, 0xb87c, 0x80d6);
 7853		ocp_reg_write(tp, 0xb87e, 0x2801);
 7854		ocp_reg_write(tp, 0xb87c, 0x80f2);
 7855		ocp_reg_write(tp, 0xb87e, 0x2801);
 7856		ocp_reg_write(tp, 0xb87c, 0x80f4);
 7857		ocp_reg_write(tp, 0xb87e, 0x6077);
 7858		ocp_reg_write(tp, 0xb506, 0x01e7);
 7859
 7860		ocp_reg_write(tp, 0xb87c, 0x8013);
 7861		ocp_reg_write(tp, 0xb87e, 0x0700);
 7862		ocp_reg_write(tp, 0xb87c, 0x8fb9);
 7863		ocp_reg_write(tp, 0xb87e, 0x2801);
 7864		ocp_reg_write(tp, 0xb87c, 0x8fba);
 7865		ocp_reg_write(tp, 0xb87e, 0x0100);
 7866		ocp_reg_write(tp, 0xb87c, 0x8fbc);
 7867		ocp_reg_write(tp, 0xb87e, 0x1900);
 7868		ocp_reg_write(tp, 0xb87c, 0x8fbe);
 7869		ocp_reg_write(tp, 0xb87e, 0xe100);
 7870		ocp_reg_write(tp, 0xb87c, 0x8fc0);
 7871		ocp_reg_write(tp, 0xb87e, 0x0800);
 7872		ocp_reg_write(tp, 0xb87c, 0x8fc2);
 7873		ocp_reg_write(tp, 0xb87e, 0xe500);
 7874		ocp_reg_write(tp, 0xb87c, 0x8fc4);
 7875		ocp_reg_write(tp, 0xb87e, 0x0f00);
 7876		ocp_reg_write(tp, 0xb87c, 0x8fc6);
 7877		ocp_reg_write(tp, 0xb87e, 0xf100);
 7878		ocp_reg_write(tp, 0xb87c, 0x8fc8);
 7879		ocp_reg_write(tp, 0xb87e, 0x0400);
 7880		ocp_reg_write(tp, 0xb87c, 0x8fca);
 7881		ocp_reg_write(tp, 0xb87e, 0xf300);
 7882		ocp_reg_write(tp, 0xb87c, 0x8fcc);
 7883		ocp_reg_write(tp, 0xb87e, 0xfd00);
 7884		ocp_reg_write(tp, 0xb87c, 0x8fce);
 7885		ocp_reg_write(tp, 0xb87e, 0xff00);
 7886		ocp_reg_write(tp, 0xb87c, 0x8fd0);
 7887		ocp_reg_write(tp, 0xb87e, 0xfb00);
 7888		ocp_reg_write(tp, 0xb87c, 0x8fd2);
 7889		ocp_reg_write(tp, 0xb87e, 0x0100);
 7890		ocp_reg_write(tp, 0xb87c, 0x8fd4);
 7891		ocp_reg_write(tp, 0xb87e, 0xf400);
 7892		ocp_reg_write(tp, 0xb87c, 0x8fd6);
 7893		ocp_reg_write(tp, 0xb87e, 0xff00);
 7894		ocp_reg_write(tp, 0xb87c, 0x8fd8);
 7895		ocp_reg_write(tp, 0xb87e, 0xf600);
 7896
 7897		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG);
 7898		ocp_data |= EN_XG_LIP | EN_G_LIP;
 7899		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
 7900		ocp_reg_write(tp, 0xb87c, 0x813d);
 7901		ocp_reg_write(tp, 0xb87e, 0x390e);
 7902		ocp_reg_write(tp, 0xb87c, 0x814f);
 7903		ocp_reg_write(tp, 0xb87e, 0x790e);
 7904		ocp_reg_write(tp, 0xb87c, 0x80b0);
 7905		ocp_reg_write(tp, 0xb87e, 0x0f31);
 7906		data = ocp_reg_read(tp, 0xbf4c);
 7907		data |= BIT(1);
 7908		ocp_reg_write(tp, 0xbf4c, data);
 7909		data = ocp_reg_read(tp, 0xbcca);
 7910		data |= BIT(9) | BIT(8);
 7911		ocp_reg_write(tp, 0xbcca, data);
 7912		ocp_reg_write(tp, 0xb87c, 0x8141);
 7913		ocp_reg_write(tp, 0xb87e, 0x320e);
 7914		ocp_reg_write(tp, 0xb87c, 0x8153);
 7915		ocp_reg_write(tp, 0xb87e, 0x720e);
 7916		ocp_reg_write(tp, 0xb87c, 0x8529);
 7917		ocp_reg_write(tp, 0xb87e, 0x050e);
 7918		data = ocp_reg_read(tp, OCP_EEE_CFG);
 7919		data &= ~CTAP_SHORT_EN;
 7920		ocp_reg_write(tp, OCP_EEE_CFG, data);
 7921
 7922		sram_write(tp, 0x816c, 0xc4a0);
 7923		sram_write(tp, 0x8170, 0xc4a0);
 7924		sram_write(tp, 0x8174, 0x04a0);
 7925		sram_write(tp, 0x8178, 0x04a0);
 7926		sram_write(tp, 0x817c, 0x0719);
 7927		sram_write(tp, 0x8ff4, 0x0400);
 7928		sram_write(tp, 0x8ff1, 0x0404);
 7929
 7930		ocp_reg_write(tp, 0xbf4a, 0x001b);
 7931		ocp_reg_write(tp, 0xb87c, 0x8033);
 7932		ocp_reg_write(tp, 0xb87e, 0x7c13);
 7933		ocp_reg_write(tp, 0xb87c, 0x8037);
 7934		ocp_reg_write(tp, 0xb87e, 0x7c13);
 7935		ocp_reg_write(tp, 0xb87c, 0x803b);
 7936		ocp_reg_write(tp, 0xb87e, 0xfc32);
 7937		ocp_reg_write(tp, 0xb87c, 0x803f);
 7938		ocp_reg_write(tp, 0xb87e, 0x7c13);
 7939		ocp_reg_write(tp, 0xb87c, 0x8043);
 7940		ocp_reg_write(tp, 0xb87e, 0x7c13);
 7941		ocp_reg_write(tp, 0xb87c, 0x8047);
 7942		ocp_reg_write(tp, 0xb87e, 0x7c13);
 7943
 7944		ocp_reg_write(tp, 0xb87c, 0x8145);
 7945		ocp_reg_write(tp, 0xb87e, 0x370e);
 7946		ocp_reg_write(tp, 0xb87c, 0x8157);
 7947		ocp_reg_write(tp, 0xb87e, 0x770e);
 7948		ocp_reg_write(tp, 0xb87c, 0x8169);
 7949		ocp_reg_write(tp, 0xb87e, 0x0d0a);
 7950		ocp_reg_write(tp, 0xb87c, 0x817b);
 7951		ocp_reg_write(tp, 0xb87e, 0x1d0a);
 7952
 7953		data = sram_read(tp, 0x8217);
 7954		data &= ~0xff00;
 7955		data |= 0x5000;
 7956		sram_write(tp, 0x8217, data);
 7957		data = sram_read(tp, 0x821a);
 7958		data &= ~0xff00;
 7959		data |= 0x5000;
 7960		sram_write(tp, 0x821a, data);
 7961		sram_write(tp, 0x80da, 0x0403);
 7962		data = sram_read(tp, 0x80dc);
 7963		data &= ~0xff00;
 7964		data |= 0x1000;
 7965		sram_write(tp, 0x80dc, data);
 7966		sram_write(tp, 0x80b3, 0x0384);
 7967		sram_write(tp, 0x80b7, 0x2007);
 7968		data = sram_read(tp, 0x80ba);
 7969		data &= ~0xff00;
 7970		data |= 0x6c00;
 7971		sram_write(tp, 0x80ba, data);
 7972		sram_write(tp, 0x80b5, 0xf009);
 7973		data = sram_read(tp, 0x80bd);
 7974		data &= ~0xff00;
 7975		data |= 0x9f00;
 7976		sram_write(tp, 0x80bd, data);
 7977		sram_write(tp, 0x80c7, 0xf083);
 7978		sram_write(tp, 0x80dd, 0x03f0);
 7979		data = sram_read(tp, 0x80df);
 7980		data &= ~0xff00;
 7981		data |= 0x1000;
 7982		sram_write(tp, 0x80df, data);
 7983		sram_write(tp, 0x80cb, 0x2007);
 7984		data = sram_read(tp, 0x80ce);
 7985		data &= ~0xff00;
 7986		data |= 0x6c00;
 7987		sram_write(tp, 0x80ce, data);
 7988		sram_write(tp, 0x80c9, 0x8009);
 7989		data = sram_read(tp, 0x80d1);
 7990		data &= ~0xff00;
 7991		data |= 0x8000;
 7992		sram_write(tp, 0x80d1, data);
 7993		sram_write(tp, 0x80a3, 0x200a);
 7994		sram_write(tp, 0x80a5, 0xf0ad);
 7995		sram_write(tp, 0x809f, 0x6073);
 7996		sram_write(tp, 0x80a1, 0x000b);
 7997		data = sram_read(tp, 0x80a9);
 7998		data &= ~0xff00;
 7999		data |= 0xc000;
 8000		sram_write(tp, 0x80a9, data);
 8001
 8002		if (rtl_phy_patch_request(tp, true, true))
 8003			return;
 8004
 8005		data = ocp_reg_read(tp, 0xb896);
 8006		data &= ~BIT(0);
 8007		ocp_reg_write(tp, 0xb896, data);
 8008		data = ocp_reg_read(tp, 0xb892);
 8009		data &= ~0xff00;
 8010		ocp_reg_write(tp, 0xb892, data);
 8011		ocp_reg_write(tp, 0xb88e, 0xc23e);
 8012		ocp_reg_write(tp, 0xb890, 0x0000);
 8013		ocp_reg_write(tp, 0xb88e, 0xc240);
 8014		ocp_reg_write(tp, 0xb890, 0x0103);
 8015		ocp_reg_write(tp, 0xb88e, 0xc242);
 8016		ocp_reg_write(tp, 0xb890, 0x0507);
 8017		ocp_reg_write(tp, 0xb88e, 0xc244);
 8018		ocp_reg_write(tp, 0xb890, 0x090b);
 8019		ocp_reg_write(tp, 0xb88e, 0xc246);
 8020		ocp_reg_write(tp, 0xb890, 0x0c0e);
 8021		ocp_reg_write(tp, 0xb88e, 0xc248);
 8022		ocp_reg_write(tp, 0xb890, 0x1012);
 8023		ocp_reg_write(tp, 0xb88e, 0xc24a);
 8024		ocp_reg_write(tp, 0xb890, 0x1416);
 8025		data = ocp_reg_read(tp, 0xb896);
 8026		data |= BIT(0);
 8027		ocp_reg_write(tp, 0xb896, data);
 8028
 8029		rtl_phy_patch_request(tp, false, true);
 8030
 8031		data = ocp_reg_read(tp, 0xa86a);
 8032		data |= BIT(0);
 8033		ocp_reg_write(tp, 0xa86a, data);
 8034		data = ocp_reg_read(tp, 0xa6f0);
 8035		data |= BIT(0);
 8036		ocp_reg_write(tp, 0xa6f0, data);
 8037
 8038		ocp_reg_write(tp, 0xbfa0, 0xd70d);
 8039		ocp_reg_write(tp, 0xbfa2, 0x4100);
 8040		ocp_reg_write(tp, 0xbfa4, 0xe868);
 8041		ocp_reg_write(tp, 0xbfa6, 0xdc59);
 8042		ocp_reg_write(tp, 0xb54c, 0x3c18);
 8043		data = ocp_reg_read(tp, 0xbfa4);
 8044		data &= ~BIT(5);
 8045		ocp_reg_write(tp, 0xbfa4, data);
 8046		data = sram_read(tp, 0x817d);
 8047		data |= BIT(12);
 8048		sram_write(tp, 0x817d, data);
 8049		break;
 8050	case RTL_VER_13:
 8051		/* 2.5G INRX */
 8052		data = ocp_reg_read(tp, 0xac46);
 8053		data &= ~0x00f0;
 8054		data |= 0x0090;
 8055		ocp_reg_write(tp, 0xac46, data);
 8056		data = ocp_reg_read(tp, 0xad30);
 8057		data &= ~0x0003;
 8058		data |= 0x0001;
 8059		ocp_reg_write(tp, 0xad30, data);
 8060		fallthrough;
 8061	case RTL_VER_15:
 8062		/* EEE parameter */
 8063		ocp_reg_write(tp, 0xb87c, 0x80f5);
 8064		ocp_reg_write(tp, 0xb87e, 0x760e);
 8065		ocp_reg_write(tp, 0xb87c, 0x8107);
 8066		ocp_reg_write(tp, 0xb87e, 0x360e);
 8067		ocp_reg_write(tp, 0xb87c, 0x8551);
 8068		data = ocp_reg_read(tp, 0xb87e);
 8069		data &= ~0xff00;
 8070		data |= 0x0800;
 8071		ocp_reg_write(tp, 0xb87e, data);
 8072
 8073		/* ADC_PGA parameter */
 8074		data = ocp_reg_read(tp, 0xbf00);
 8075		data &= ~0xe000;
 8076		data |= 0xa000;
 8077		ocp_reg_write(tp, 0xbf00, data);
 8078		data = ocp_reg_read(tp, 0xbf46);
 8079		data &= ~0x0f00;
 8080		data |= 0x0300;
 8081		ocp_reg_write(tp, 0xbf46, data);
 8082
 8083		/* Green Table-PGA, 1G full viterbi */
 8084		sram_write(tp, 0x8044, 0x2417);
 8085		sram_write(tp, 0x804a, 0x2417);
 8086		sram_write(tp, 0x8050, 0x2417);
 8087		sram_write(tp, 0x8056, 0x2417);
 8088		sram_write(tp, 0x805c, 0x2417);
 8089		sram_write(tp, 0x8062, 0x2417);
 8090		sram_write(tp, 0x8068, 0x2417);
 8091		sram_write(tp, 0x806e, 0x2417);
 8092		sram_write(tp, 0x8074, 0x2417);
 8093		sram_write(tp, 0x807a, 0x2417);
 8094
 8095		/* XG PLL */
 8096		data = ocp_reg_read(tp, 0xbf84);
 8097		data &= ~0xe000;
 8098		data |= 0xa000;
 8099		ocp_reg_write(tp, 0xbf84, data);
 8100		break;
 8101	default:
 8102		break;
 8103	}
 8104
 8105	/* Notify the MAC when the speed is changed to force mode. */
 8106	data = ocp_reg_read(tp, OCP_INTR_EN);
 8107	data |= INTR_SPEED_FORCE;
 8108	ocp_reg_write(tp, OCP_INTR_EN, data);
 8109
 8110	if (rtl_phy_patch_request(tp, true, true))
 8111		return;
 8112
 8113	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
 8114	ocp_data |= EEE_SPDWN_EN;
 8115	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
 8116
 8117	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
 8118	data &= ~(EN_EEE_100 | EN_EEE_1000);
 8119	data |= EN_10M_CLKDIV;
 8120	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
 8121	tp->ups_info._10m_ckdiv = true;
 8122	tp->ups_info.eee_plloff_100 = false;
 8123	tp->ups_info.eee_plloff_giga = false;
 8124
 8125	data = ocp_reg_read(tp, OCP_POWER_CFG);
 8126	data &= ~EEE_CLKDIV_EN;
 8127	ocp_reg_write(tp, OCP_POWER_CFG, data);
 8128	tp->ups_info.eee_ckdiv = false;
 8129
 8130	rtl_phy_patch_request(tp, false, true);
 8131
 8132	rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
 8133
 8134	data = ocp_reg_read(tp, 0xa428);
 8135	data &= ~BIT(9);
 8136	ocp_reg_write(tp, 0xa428, data);
 8137	data = ocp_reg_read(tp, 0xa5ea);
 8138	data &= ~BIT(0);
 8139	ocp_reg_write(tp, 0xa5ea, data);
 8140	tp->ups_info.lite_mode = 0;
 8141
 8142	if (tp->eee_en)
 8143		rtl_eee_enable(tp, true);
 8144
 8145	r8153_aldps_en(tp, true);
 8146	r8152b_enable_fc(tp);
 8147	r8153_u2p3en(tp, true);
 8148
 8149	set_bit(PHY_RESET, &tp->flags);
 8150}
 8151
 8152static void r8156_init(struct r8152 *tp)
 8153{
 8154	u32 ocp_data;
 8155	u16 data;
 8156	int i;
 8157
 8158	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 8159		return;
 8160
 8161	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
 8162	ocp_data &= ~EN_ALL_SPEED;
 8163	ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
 8164
 8165	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
 8166
 8167	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
 8168	ocp_data |= BYPASS_MAC_RESET;
 8169	ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
 8170
 8171	r8153b_u1u2en(tp, false);
 8172
 8173	for (i = 0; i < 500; i++) {
 8174		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
 8175		    AUTOLOAD_DONE)
 8176			break;
 8177
 8178		msleep(20);
 8179		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 8180			return;
 8181	}
 8182
 8183	data = r8153_phy_status(tp, 0);
 8184	if (data == PHY_STAT_EXT_INIT) {
 8185		data = ocp_reg_read(tp, 0xa468);
 8186		data &= ~(BIT(3) | BIT(1));
 8187		ocp_reg_write(tp, 0xa468, data);
 8188	}
 8189
 8190	data = r8152_mdio_read(tp, MII_BMCR);
 8191	if (data & BMCR_PDOWN) {
 8192		data &= ~BMCR_PDOWN;
 8193		r8152_mdio_write(tp, MII_BMCR, data);
 8194	}
 8195
 8196	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
 8197	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
 8198
 8199	r8153_u2p3en(tp, false);
 8200
 8201	/* MSC timer = 0xfff * 8ms = 32760 ms */
 8202	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
 8203
 8204	/* U1/U2/L1 idle timer. 500 us */
 8205	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
 8206
 8207	r8153b_power_cut_en(tp, false);
 8208	r8156_ups_en(tp, false);
 8209	r8153_queue_wake(tp, false);
 8210	rtl_runtime_suspend_enable(tp, false);
 8211
 8212	if (tp->udev->speed >= USB_SPEED_SUPER)
 8213		r8153b_u1u2en(tp, true);
 8214
 8215	usb_enable_lpm(tp->udev);
 8216
 8217	r8156_mac_clk_spd(tp, true);
 8218
 8219	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
 8220	ocp_data &= ~PLA_MCU_SPDWN_EN;
 8221	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
 8222
 8223	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
 8224	if (rtl8152_get_speed(tp) & LINK_STATUS)
 8225		ocp_data |= CUR_LINK_OK;
 8226	else
 8227		ocp_data &= ~CUR_LINK_OK;
 8228	ocp_data |= POLL_LINK_CHG;
 8229	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
 8230
 8231	set_bit(GREEN_ETHERNET, &tp->flags);
 8232
 8233	/* rx aggregation */
 8234	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
 8235	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
 8236	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
 8237
 8238	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
 8239	ocp_data |= ACT_ODMA;
 8240	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
 8241
 8242	r8156_mdio_force_mode(tp);
 8243	rtl_tally_reset(tp);
 8244
 8245	tp->coalesce = 15000;	/* 15 us */
 8246}
 8247
 8248static void r8156b_init(struct r8152 *tp)
 8249{
 8250	u32 ocp_data;
 8251	u16 data;
 8252	int i;
 8253
 8254	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 8255		return;
 8256
 8257	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
 8258	ocp_data &= ~EN_ALL_SPEED;
 8259	ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
 8260
 8261	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
 8262
 8263	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
 8264	ocp_data |= BYPASS_MAC_RESET;
 8265	ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
 8266
 8267	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
 8268	ocp_data |= RX_DETECT8;
 8269	ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
 8270
 8271	r8153b_u1u2en(tp, false);
 8272
 8273	switch (tp->version) {
 8274	case RTL_VER_13:
 8275	case RTL_VER_15:
 8276		r8156b_wait_loading_flash(tp);
 8277		break;
 8278	default:
 8279		break;
 8280	}
 8281
 8282	for (i = 0; i < 500; i++) {
 8283		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
 8284		    AUTOLOAD_DONE)
 8285			break;
 8286
 8287		msleep(20);
 8288		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 8289			return;
 8290	}
 8291
 8292	data = r8153_phy_status(tp, 0);
 8293	if (data == PHY_STAT_EXT_INIT) {
 8294		data = ocp_reg_read(tp, 0xa468);
 8295		data &= ~(BIT(3) | BIT(1));
 8296		ocp_reg_write(tp, 0xa468, data);
 8297
 8298		data = ocp_reg_read(tp, 0xa466);
 8299		data &= ~BIT(0);
 8300		ocp_reg_write(tp, 0xa466, data);
 8301	}
 8302
 8303	data = r8152_mdio_read(tp, MII_BMCR);
 8304	if (data & BMCR_PDOWN) {
 8305		data &= ~BMCR_PDOWN;
 8306		r8152_mdio_write(tp, MII_BMCR, data);
 8307	}
 8308
 8309	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
 8310
 8311	r8153_u2p3en(tp, false);
 8312
 8313	/* MSC timer = 0xfff * 8ms = 32760 ms */
 8314	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
 8315
 8316	/* U1/U2/L1 idle timer. 500 us */
 8317	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
 8318
 8319	r8153b_power_cut_en(tp, false);
 8320	r8156_ups_en(tp, false);
 8321	r8153_queue_wake(tp, false);
 8322	rtl_runtime_suspend_enable(tp, false);
 8323
 8324	if (tp->udev->speed >= USB_SPEED_SUPER)
 8325		r8153b_u1u2en(tp, true);
 8326
 8327	usb_enable_lpm(tp->udev);
 8328
 8329	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR);
 8330	ocp_data &= ~SLOT_EN;
 8331	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
 8332
 8333	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
 8334	ocp_data |= FLOW_CTRL_EN;
 8335	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
 8336
 8337	/* enable fc timer and set timer to 600 ms. */
 8338	ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
 8339		       CTRL_TIMER_EN | (600 / 8));
 8340
 8341	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
 8342	if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN))
 8343		ocp_data |= FLOW_CTRL_PATCH_2;
 8344	ocp_data &= ~AUTO_SPEEDUP;
 8345	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
 8346
 8347	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
 8348	ocp_data |= FC_PATCH_TASK;
 8349	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
 8350
 8351	r8156_mac_clk_spd(tp, true);
 8352
 8353	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
 8354	ocp_data &= ~PLA_MCU_SPDWN_EN;
 8355	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
 8356
 8357	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
 8358	if (rtl8152_get_speed(tp) & LINK_STATUS)
 8359		ocp_data |= CUR_LINK_OK;
 8360	else
 8361		ocp_data &= ~CUR_LINK_OK;
 8362	ocp_data |= POLL_LINK_CHG;
 8363	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
 8364
 8365	set_bit(GREEN_ETHERNET, &tp->flags);
 8366
 8367	/* rx aggregation */
 8368	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
 8369	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
 8370	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
 8371
 8372	r8156_mdio_force_mode(tp);
 8373	rtl_tally_reset(tp);
 8374
 8375	tp->coalesce = 15000;	/* 15 us */
 8376}
 8377
 8378static bool rtl_check_vendor_ok(struct usb_interface *intf)
 8379{
 8380	struct usb_host_interface *alt = intf->cur_altsetting;
 8381	struct usb_endpoint_descriptor *in, *out, *intr;
 8382
 8383	if (usb_find_common_endpoints(alt, &in, &out, &intr, NULL) < 0) {
 8384		dev_err(&intf->dev, "Expected endpoints are not found\n");
 8385		return false;
 8386	}
 8387
 8388	/* Check Rx endpoint address */
 8389	if (usb_endpoint_num(in) != 1) {
 8390		dev_err(&intf->dev, "Invalid Rx endpoint address\n");
 8391		return false;
 8392	}
 8393
 8394	/* Check Tx endpoint address */
 8395	if (usb_endpoint_num(out) != 2) {
 8396		dev_err(&intf->dev, "Invalid Tx endpoint address\n");
 8397		return false;
 8398	}
 8399
 8400	/* Check interrupt endpoint address */
 8401	if (usb_endpoint_num(intr) != 3) {
 8402		dev_err(&intf->dev, "Invalid interrupt endpoint address\n");
 8403		return false;
 8404	}
 8405
 8406	return true;
 8407}
 8408
 8409static int rtl8152_pre_reset(struct usb_interface *intf)
 8410{
 8411	struct r8152 *tp = usb_get_intfdata(intf);
 8412	struct net_device *netdev;
 8413
 8414	rtnl_lock();
 8415
 8416	if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &tp->flags))
 8417		return 0;
 8418
 8419	netdev = tp->netdev;
 8420	if (!netif_running(netdev))
 8421		return 0;
 8422
 8423	netif_stop_queue(netdev);
 8424	tasklet_disable(&tp->tx_tl);
 8425	clear_bit(WORK_ENABLE, &tp->flags);
 8426	usb_kill_urb(tp->intr_urb);
 8427	cancel_delayed_work_sync(&tp->schedule);
 8428	napi_disable(&tp->napi);
 8429	if (netif_carrier_ok(netdev)) {
 8430		mutex_lock(&tp->control);
 8431		set_bit(IN_PRE_RESET, &tp->flags);
 8432		tp->rtl_ops.disable(tp);
 8433		clear_bit(IN_PRE_RESET, &tp->flags);
 8434		mutex_unlock(&tp->control);
 8435	}
 8436
 8437	return 0;
 8438}
 8439
 8440static int rtl8152_post_reset(struct usb_interface *intf)
 8441{
 8442	struct r8152 *tp = usb_get_intfdata(intf);
 8443	struct net_device *netdev;
 8444	struct sockaddr sa;
 8445
 8446	if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &tp->flags))
 8447		goto exit;
 8448
 8449	rtl_set_accessible(tp);
 8450
 8451	/* reset the MAC address in case of policy change */
 8452	if (determine_ethernet_addr(tp, &sa) >= 0)
 
 8453		dev_set_mac_address (tp->netdev, &sa, NULL);
 
 
 8454
 8455	netdev = tp->netdev;
 8456	if (!netif_running(netdev))
 8457		goto exit;
 8458
 8459	set_bit(WORK_ENABLE, &tp->flags);
 8460	if (netif_carrier_ok(netdev)) {
 8461		mutex_lock(&tp->control);
 8462		tp->rtl_ops.enable(tp);
 8463		rtl_start_rx(tp);
 8464		_rtl8152_set_rx_mode(netdev);
 8465		mutex_unlock(&tp->control);
 8466	}
 8467
 8468	napi_enable(&tp->napi);
 8469	tasklet_enable(&tp->tx_tl);
 8470	netif_wake_queue(netdev);
 8471	usb_submit_urb(tp->intr_urb, GFP_KERNEL);
 8472
 8473	if (!list_empty(&tp->rx_done))
 8474		napi_schedule(&tp->napi);
 8475
 8476exit:
 8477	rtnl_unlock();
 8478	return 0;
 8479}
 8480
 8481static bool delay_autosuspend(struct r8152 *tp)
 8482{
 8483	bool sw_linking = !!netif_carrier_ok(tp->netdev);
 8484	bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
 8485
 8486	/* This means a linking change occurs and the driver doesn't detect it,
 8487	 * yet. If the driver has disabled tx/rx and hw is linking on, the
 8488	 * device wouldn't wake up by receiving any packet.
 8489	 */
 8490	if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
 8491		return true;
 8492
 8493	/* If the linking down is occurred by nway, the device may miss the
 8494	 * linking change event. And it wouldn't wake when linking on.
 8495	 */
 8496	if (!sw_linking && tp->rtl_ops.in_nway(tp))
 8497		return true;
 8498	else if (!skb_queue_empty(&tp->tx_queue))
 8499		return true;
 8500	else
 8501		return false;
 8502}
 8503
 8504static int rtl8152_runtime_resume(struct r8152 *tp)
 8505{
 8506	struct net_device *netdev = tp->netdev;
 8507
 8508	if (netif_running(netdev) && netdev->flags & IFF_UP) {
 8509		struct napi_struct *napi = &tp->napi;
 8510
 8511		tp->rtl_ops.autosuspend_en(tp, false);
 8512		napi_disable(napi);
 8513		set_bit(WORK_ENABLE, &tp->flags);
 8514
 8515		if (netif_carrier_ok(netdev)) {
 8516			if (rtl8152_get_speed(tp) & LINK_STATUS) {
 8517				rtl_start_rx(tp);
 8518			} else {
 8519				netif_carrier_off(netdev);
 8520				tp->rtl_ops.disable(tp);
 8521				netif_info(tp, link, netdev, "linking down\n");
 8522			}
 8523		}
 8524
 8525		napi_enable(napi);
 8526		clear_bit(SELECTIVE_SUSPEND, &tp->flags);
 8527		smp_mb__after_atomic();
 8528
 8529		if (!list_empty(&tp->rx_done))
 8530			napi_schedule(&tp->napi);
 8531
 8532		usb_submit_urb(tp->intr_urb, GFP_NOIO);
 8533	} else {
 8534		if (netdev->flags & IFF_UP)
 8535			tp->rtl_ops.autosuspend_en(tp, false);
 8536
 8537		clear_bit(SELECTIVE_SUSPEND, &tp->flags);
 8538	}
 8539
 8540	return 0;
 8541}
 8542
 8543static int rtl8152_system_resume(struct r8152 *tp)
 8544{
 8545	struct net_device *netdev = tp->netdev;
 8546
 8547	netif_device_attach(netdev);
 8548
 8549	if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
 8550		tp->rtl_ops.up(tp);
 8551		netif_carrier_off(netdev);
 8552		set_bit(WORK_ENABLE, &tp->flags);
 8553		usb_submit_urb(tp->intr_urb, GFP_NOIO);
 8554	}
 8555
 8556	return 0;
 8557}
 8558
 8559static int rtl8152_runtime_suspend(struct r8152 *tp)
 8560{
 8561	struct net_device *netdev = tp->netdev;
 8562	int ret = 0;
 8563
 8564	if (!tp->rtl_ops.autosuspend_en)
 8565		return -EBUSY;
 8566
 8567	set_bit(SELECTIVE_SUSPEND, &tp->flags);
 8568	smp_mb__after_atomic();
 8569
 8570	if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
 8571		u32 rcr = 0;
 8572
 8573		if (netif_carrier_ok(netdev)) {
 8574			u32 ocp_data;
 8575
 8576			rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
 8577			ocp_data = rcr & ~RCR_ACPT_ALL;
 8578			ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
 8579			rxdy_gated_en(tp, true);
 8580			ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
 8581						 PLA_OOB_CTRL);
 8582			if (!(ocp_data & RXFIFO_EMPTY)) {
 8583				rxdy_gated_en(tp, false);
 8584				ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
 8585				clear_bit(SELECTIVE_SUSPEND, &tp->flags);
 8586				smp_mb__after_atomic();
 8587				ret = -EBUSY;
 8588				goto out1;
 8589			}
 8590		}
 8591
 8592		clear_bit(WORK_ENABLE, &tp->flags);
 8593		usb_kill_urb(tp->intr_urb);
 8594
 8595		tp->rtl_ops.autosuspend_en(tp, true);
 8596
 8597		if (netif_carrier_ok(netdev)) {
 8598			struct napi_struct *napi = &tp->napi;
 8599
 8600			napi_disable(napi);
 8601			rtl_stop_rx(tp);
 8602			rxdy_gated_en(tp, false);
 8603			ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
 8604			napi_enable(napi);
 8605		}
 8606
 8607		if (delay_autosuspend(tp)) {
 8608			rtl8152_runtime_resume(tp);
 8609			ret = -EBUSY;
 8610		}
 8611	}
 8612
 8613out1:
 8614	return ret;
 8615}
 8616
 8617static int rtl8152_system_suspend(struct r8152 *tp)
 8618{
 8619	struct net_device *netdev = tp->netdev;
 8620
 8621	netif_device_detach(netdev);
 8622
 8623	if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
 8624		struct napi_struct *napi = &tp->napi;
 8625
 8626		clear_bit(WORK_ENABLE, &tp->flags);
 8627		usb_kill_urb(tp->intr_urb);
 8628		tasklet_disable(&tp->tx_tl);
 8629		napi_disable(napi);
 8630		cancel_delayed_work_sync(&tp->schedule);
 8631		tp->rtl_ops.down(tp);
 8632		napi_enable(napi);
 8633		tasklet_enable(&tp->tx_tl);
 8634	}
 8635
 8636	return 0;
 8637}
 8638
 8639static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
 8640{
 8641	struct r8152 *tp = usb_get_intfdata(intf);
 8642	int ret;
 8643
 8644	mutex_lock(&tp->control);
 8645
 8646	if (PMSG_IS_AUTO(message))
 8647		ret = rtl8152_runtime_suspend(tp);
 8648	else
 8649		ret = rtl8152_system_suspend(tp);
 8650
 8651	mutex_unlock(&tp->control);
 8652
 8653	return ret;
 8654}
 8655
 8656static int rtl8152_resume(struct usb_interface *intf)
 8657{
 8658	struct r8152 *tp = usb_get_intfdata(intf);
 8659	int ret;
 8660
 8661	mutex_lock(&tp->control);
 8662
 8663	rtl_reset_ocp_base(tp);
 8664
 8665	if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
 8666		ret = rtl8152_runtime_resume(tp);
 8667	else
 8668		ret = rtl8152_system_resume(tp);
 8669
 8670	mutex_unlock(&tp->control);
 8671
 8672	return ret;
 8673}
 8674
 8675static int rtl8152_reset_resume(struct usb_interface *intf)
 8676{
 8677	struct r8152 *tp = usb_get_intfdata(intf);
 8678
 8679	clear_bit(SELECTIVE_SUSPEND, &tp->flags);
 8680	rtl_reset_ocp_base(tp);
 8681	tp->rtl_ops.init(tp);
 8682	queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
 8683	set_ethernet_addr(tp, true);
 8684	return rtl8152_resume(intf);
 8685}
 8686
 8687static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 8688{
 8689	struct r8152 *tp = netdev_priv(dev);
 8690
 8691	if (usb_autopm_get_interface(tp->intf) < 0)
 8692		return;
 8693
 8694	if (!rtl_can_wakeup(tp)) {
 8695		wol->supported = 0;
 8696		wol->wolopts = 0;
 8697	} else {
 8698		mutex_lock(&tp->control);
 8699		wol->supported = WAKE_ANY;
 8700		wol->wolopts = __rtl_get_wol(tp);
 8701		mutex_unlock(&tp->control);
 8702	}
 8703
 8704	usb_autopm_put_interface(tp->intf);
 8705}
 8706
 8707static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 8708{
 8709	struct r8152 *tp = netdev_priv(dev);
 8710	int ret;
 8711
 8712	if (!rtl_can_wakeup(tp))
 8713		return -EOPNOTSUPP;
 8714
 8715	if (wol->wolopts & ~WAKE_ANY)
 8716		return -EINVAL;
 8717
 8718	ret = usb_autopm_get_interface(tp->intf);
 8719	if (ret < 0)
 8720		goto out_set_wol;
 8721
 8722	mutex_lock(&tp->control);
 8723
 8724	__rtl_set_wol(tp, wol->wolopts);
 8725	tp->saved_wolopts = wol->wolopts & WAKE_ANY;
 8726
 8727	mutex_unlock(&tp->control);
 8728
 8729	usb_autopm_put_interface(tp->intf);
 8730
 8731out_set_wol:
 8732	return ret;
 8733}
 8734
 8735static u32 rtl8152_get_msglevel(struct net_device *dev)
 8736{
 8737	struct r8152 *tp = netdev_priv(dev);
 8738
 8739	return tp->msg_enable;
 8740}
 8741
 8742static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
 8743{
 8744	struct r8152 *tp = netdev_priv(dev);
 8745
 8746	tp->msg_enable = value;
 8747}
 8748
 8749static void rtl8152_get_drvinfo(struct net_device *netdev,
 8750				struct ethtool_drvinfo *info)
 8751{
 8752	struct r8152 *tp = netdev_priv(netdev);
 8753
 8754	strscpy(info->driver, MODULENAME, sizeof(info->driver));
 8755	strscpy(info->version, DRIVER_VERSION, sizeof(info->version));
 8756	usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
 8757	if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
 8758		strscpy(info->fw_version, tp->rtl_fw.version,
 8759			sizeof(info->fw_version));
 8760}
 8761
 8762static
 8763int rtl8152_get_link_ksettings(struct net_device *netdev,
 8764			       struct ethtool_link_ksettings *cmd)
 8765{
 8766	struct r8152 *tp = netdev_priv(netdev);
 8767	int ret;
 8768
 8769	if (!tp->mii.mdio_read)
 8770		return -EOPNOTSUPP;
 8771
 8772	ret = usb_autopm_get_interface(tp->intf);
 8773	if (ret < 0)
 8774		goto out;
 8775
 8776	mutex_lock(&tp->control);
 8777
 8778	mii_ethtool_get_link_ksettings(&tp->mii, cmd);
 8779
 8780	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 8781			 cmd->link_modes.supported, tp->support_2500full);
 8782
 8783	if (tp->support_2500full) {
 8784		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 8785				 cmd->link_modes.advertising,
 8786				 ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G);
 8787
 8788		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 8789				 cmd->link_modes.lp_advertising,
 8790				 ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G);
 8791
 8792		if (is_speed_2500(rtl8152_get_speed(tp)))
 8793			cmd->base.speed = SPEED_2500;
 8794	}
 8795
 8796	mutex_unlock(&tp->control);
 8797
 8798	usb_autopm_put_interface(tp->intf);
 8799
 8800out:
 8801	return ret;
 8802}
 8803
 8804static int rtl8152_set_link_ksettings(struct net_device *dev,
 8805				      const struct ethtool_link_ksettings *cmd)
 8806{
 8807	struct r8152 *tp = netdev_priv(dev);
 8808	u32 advertising = 0;
 8809	int ret;
 8810
 8811	ret = usb_autopm_get_interface(tp->intf);
 8812	if (ret < 0)
 8813		goto out;
 8814
 8815	if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
 8816		     cmd->link_modes.advertising))
 8817		advertising |= RTL_ADVERTISED_10_HALF;
 8818
 8819	if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
 8820		     cmd->link_modes.advertising))
 8821		advertising |= RTL_ADVERTISED_10_FULL;
 8822
 8823	if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
 8824		     cmd->link_modes.advertising))
 8825		advertising |= RTL_ADVERTISED_100_HALF;
 8826
 8827	if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
 8828		     cmd->link_modes.advertising))
 8829		advertising |= RTL_ADVERTISED_100_FULL;
 8830
 8831	if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
 8832		     cmd->link_modes.advertising))
 8833		advertising |= RTL_ADVERTISED_1000_HALF;
 8834
 8835	if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
 8836		     cmd->link_modes.advertising))
 8837		advertising |= RTL_ADVERTISED_1000_FULL;
 8838
 8839	if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 8840		     cmd->link_modes.advertising))
 8841		advertising |= RTL_ADVERTISED_2500_FULL;
 8842
 8843	mutex_lock(&tp->control);
 8844
 8845	ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
 8846				cmd->base.duplex, advertising);
 8847	if (!ret) {
 8848		tp->autoneg = cmd->base.autoneg;
 8849		tp->speed = cmd->base.speed;
 8850		tp->duplex = cmd->base.duplex;
 8851		tp->advertising = advertising;
 8852	}
 8853
 8854	mutex_unlock(&tp->control);
 8855
 8856	usb_autopm_put_interface(tp->intf);
 8857
 8858out:
 8859	return ret;
 8860}
 8861
 8862static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
 8863	"tx_packets",
 8864	"rx_packets",
 8865	"tx_errors",
 8866	"rx_errors",
 8867	"rx_missed",
 8868	"align_errors",
 8869	"tx_single_collisions",
 8870	"tx_multi_collisions",
 8871	"rx_unicast",
 8872	"rx_broadcast",
 8873	"rx_multicast",
 8874	"tx_aborted",
 8875	"tx_underrun",
 8876};
 8877
 8878static int rtl8152_get_sset_count(struct net_device *dev, int sset)
 8879{
 8880	switch (sset) {
 8881	case ETH_SS_STATS:
 8882		return ARRAY_SIZE(rtl8152_gstrings);
 8883	default:
 8884		return -EOPNOTSUPP;
 8885	}
 8886}
 8887
 8888static void rtl8152_get_ethtool_stats(struct net_device *dev,
 8889				      struct ethtool_stats *stats, u64 *data)
 8890{
 8891	struct r8152 *tp = netdev_priv(dev);
 8892	struct tally_counter tally;
 8893
 8894	if (usb_autopm_get_interface(tp->intf) < 0)
 8895		return;
 8896
 8897	generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
 8898
 8899	usb_autopm_put_interface(tp->intf);
 8900
 8901	data[0] = le64_to_cpu(tally.tx_packets);
 8902	data[1] = le64_to_cpu(tally.rx_packets);
 8903	data[2] = le64_to_cpu(tally.tx_errors);
 8904	data[3] = le32_to_cpu(tally.rx_errors);
 8905	data[4] = le16_to_cpu(tally.rx_missed);
 8906	data[5] = le16_to_cpu(tally.align_errors);
 8907	data[6] = le32_to_cpu(tally.tx_one_collision);
 8908	data[7] = le32_to_cpu(tally.tx_multi_collision);
 8909	data[8] = le64_to_cpu(tally.rx_unicast);
 8910	data[9] = le64_to_cpu(tally.rx_broadcast);
 8911	data[10] = le32_to_cpu(tally.rx_multicast);
 8912	data[11] = le16_to_cpu(tally.tx_aborted);
 8913	data[12] = le16_to_cpu(tally.tx_underrun);
 8914}
 8915
 8916static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
 8917{
 8918	switch (stringset) {
 8919	case ETH_SS_STATS:
 8920		memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
 8921		break;
 8922	}
 8923}
 8924
 8925static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
 8926{
 8927	u32 lp, adv, supported = 0;
 8928	u16 val;
 8929
 8930	val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
 8931	supported = mmd_eee_cap_to_ethtool_sup_t(val);
 8932
 8933	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
 8934	adv = mmd_eee_adv_to_ethtool_adv_t(val);
 8935
 8936	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
 8937	lp = mmd_eee_adv_to_ethtool_adv_t(val);
 8938
 8939	eee->eee_enabled = tp->eee_en;
 8940	eee->eee_active = !!(supported & adv & lp);
 8941	eee->supported = supported;
 8942	eee->advertised = tp->eee_adv;
 8943	eee->lp_advertised = lp;
 8944
 8945	return 0;
 8946}
 8947
 8948static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
 8949{
 8950	u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
 8951
 8952	tp->eee_en = eee->eee_enabled;
 8953	tp->eee_adv = val;
 8954
 8955	rtl_eee_enable(tp, tp->eee_en);
 8956
 8957	return 0;
 8958}
 8959
 8960static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
 8961{
 8962	u32 lp, adv, supported = 0;
 8963	u16 val;
 8964
 8965	val = ocp_reg_read(tp, OCP_EEE_ABLE);
 8966	supported = mmd_eee_cap_to_ethtool_sup_t(val);
 8967
 8968	val = ocp_reg_read(tp, OCP_EEE_ADV);
 8969	adv = mmd_eee_adv_to_ethtool_adv_t(val);
 8970
 8971	val = ocp_reg_read(tp, OCP_EEE_LPABLE);
 8972	lp = mmd_eee_adv_to_ethtool_adv_t(val);
 8973
 8974	eee->eee_enabled = tp->eee_en;
 8975	eee->eee_active = !!(supported & adv & lp);
 8976	eee->supported = supported;
 8977	eee->advertised = tp->eee_adv;
 8978	eee->lp_advertised = lp;
 8979
 8980	return 0;
 8981}
 8982
 8983static int
 8984rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
 8985{
 8986	struct r8152 *tp = netdev_priv(net);
 8987	int ret;
 8988
 8989	if (!tp->rtl_ops.eee_get) {
 8990		ret = -EOPNOTSUPP;
 8991		goto out;
 8992	}
 8993
 8994	ret = usb_autopm_get_interface(tp->intf);
 8995	if (ret < 0)
 8996		goto out;
 8997
 8998	mutex_lock(&tp->control);
 8999
 9000	ret = tp->rtl_ops.eee_get(tp, edata);
 9001
 9002	mutex_unlock(&tp->control);
 9003
 9004	usb_autopm_put_interface(tp->intf);
 9005
 9006out:
 9007	return ret;
 9008}
 9009
 9010static int
 9011rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
 9012{
 9013	struct r8152 *tp = netdev_priv(net);
 9014	int ret;
 9015
 9016	if (!tp->rtl_ops.eee_set) {
 9017		ret = -EOPNOTSUPP;
 9018		goto out;
 9019	}
 9020
 9021	ret = usb_autopm_get_interface(tp->intf);
 9022	if (ret < 0)
 9023		goto out;
 9024
 9025	mutex_lock(&tp->control);
 9026
 9027	ret = tp->rtl_ops.eee_set(tp, edata);
 9028	if (!ret)
 9029		ret = mii_nway_restart(&tp->mii);
 9030
 9031	mutex_unlock(&tp->control);
 9032
 9033	usb_autopm_put_interface(tp->intf);
 9034
 9035out:
 9036	return ret;
 9037}
 9038
 9039static int rtl8152_nway_reset(struct net_device *dev)
 9040{
 9041	struct r8152 *tp = netdev_priv(dev);
 9042	int ret;
 9043
 9044	ret = usb_autopm_get_interface(tp->intf);
 9045	if (ret < 0)
 9046		goto out;
 9047
 9048	mutex_lock(&tp->control);
 9049
 9050	ret = mii_nway_restart(&tp->mii);
 9051
 9052	mutex_unlock(&tp->control);
 9053
 9054	usb_autopm_put_interface(tp->intf);
 9055
 9056out:
 9057	return ret;
 9058}
 9059
 9060static int rtl8152_get_coalesce(struct net_device *netdev,
 9061				struct ethtool_coalesce *coalesce,
 9062				struct kernel_ethtool_coalesce *kernel_coal,
 9063				struct netlink_ext_ack *extack)
 9064{
 9065	struct r8152 *tp = netdev_priv(netdev);
 9066
 9067	switch (tp->version) {
 9068	case RTL_VER_01:
 9069	case RTL_VER_02:
 9070	case RTL_VER_07:
 9071		return -EOPNOTSUPP;
 9072	default:
 9073		break;
 9074	}
 9075
 9076	coalesce->rx_coalesce_usecs = tp->coalesce;
 9077
 9078	return 0;
 9079}
 9080
 9081static int rtl8152_set_coalesce(struct net_device *netdev,
 9082				struct ethtool_coalesce *coalesce,
 9083				struct kernel_ethtool_coalesce *kernel_coal,
 9084				struct netlink_ext_ack *extack)
 9085{
 9086	struct r8152 *tp = netdev_priv(netdev);
 9087	int ret;
 9088
 9089	switch (tp->version) {
 9090	case RTL_VER_01:
 9091	case RTL_VER_02:
 9092	case RTL_VER_07:
 9093		return -EOPNOTSUPP;
 9094	default:
 9095		break;
 9096	}
 9097
 9098	if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
 9099		return -EINVAL;
 9100
 9101	ret = usb_autopm_get_interface(tp->intf);
 9102	if (ret < 0)
 9103		return ret;
 9104
 9105	mutex_lock(&tp->control);
 9106
 9107	if (tp->coalesce != coalesce->rx_coalesce_usecs) {
 9108		tp->coalesce = coalesce->rx_coalesce_usecs;
 9109
 9110		if (netif_running(netdev) && netif_carrier_ok(netdev)) {
 9111			netif_stop_queue(netdev);
 9112			napi_disable(&tp->napi);
 9113			tp->rtl_ops.disable(tp);
 9114			tp->rtl_ops.enable(tp);
 9115			rtl_start_rx(tp);
 9116			clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
 9117			_rtl8152_set_rx_mode(netdev);
 9118			napi_enable(&tp->napi);
 9119			netif_wake_queue(netdev);
 9120		}
 9121	}
 9122
 9123	mutex_unlock(&tp->control);
 9124
 9125	usb_autopm_put_interface(tp->intf);
 9126
 9127	return ret;
 9128}
 9129
 9130static int rtl8152_get_tunable(struct net_device *netdev,
 9131			       const struct ethtool_tunable *tunable, void *d)
 9132{
 9133	struct r8152 *tp = netdev_priv(netdev);
 9134
 9135	switch (tunable->id) {
 9136	case ETHTOOL_RX_COPYBREAK:
 9137		*(u32 *)d = tp->rx_copybreak;
 9138		break;
 9139	default:
 9140		return -EOPNOTSUPP;
 9141	}
 9142
 9143	return 0;
 9144}
 9145
 9146static int rtl8152_set_tunable(struct net_device *netdev,
 9147			       const struct ethtool_tunable *tunable,
 9148			       const void *d)
 9149{
 9150	struct r8152 *tp = netdev_priv(netdev);
 9151	u32 val;
 9152
 9153	switch (tunable->id) {
 9154	case ETHTOOL_RX_COPYBREAK:
 9155		val = *(u32 *)d;
 9156		if (val < ETH_ZLEN) {
 9157			netif_err(tp, rx_err, netdev,
 9158				  "Invalid rx copy break value\n");
 9159			return -EINVAL;
 9160		}
 9161
 9162		if (tp->rx_copybreak != val) {
 9163			if (netdev->flags & IFF_UP) {
 9164				mutex_lock(&tp->control);
 9165				napi_disable(&tp->napi);
 9166				tp->rx_copybreak = val;
 9167				napi_enable(&tp->napi);
 9168				mutex_unlock(&tp->control);
 9169			} else {
 9170				tp->rx_copybreak = val;
 9171			}
 9172		}
 9173		break;
 9174	default:
 9175		return -EOPNOTSUPP;
 9176	}
 9177
 9178	return 0;
 9179}
 9180
 9181static void rtl8152_get_ringparam(struct net_device *netdev,
 9182				  struct ethtool_ringparam *ring,
 9183				  struct kernel_ethtool_ringparam *kernel_ring,
 9184				  struct netlink_ext_ack *extack)
 9185{
 9186	struct r8152 *tp = netdev_priv(netdev);
 9187
 9188	ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
 9189	ring->rx_pending = tp->rx_pending;
 9190}
 9191
 9192static int rtl8152_set_ringparam(struct net_device *netdev,
 9193				 struct ethtool_ringparam *ring,
 9194				 struct kernel_ethtool_ringparam *kernel_ring,
 9195				 struct netlink_ext_ack *extack)
 9196{
 9197	struct r8152 *tp = netdev_priv(netdev);
 9198
 9199	if (ring->rx_pending < (RTL8152_MAX_RX * 2))
 9200		return -EINVAL;
 9201
 9202	if (tp->rx_pending != ring->rx_pending) {
 9203		if (netdev->flags & IFF_UP) {
 9204			mutex_lock(&tp->control);
 9205			napi_disable(&tp->napi);
 9206			tp->rx_pending = ring->rx_pending;
 9207			napi_enable(&tp->napi);
 9208			mutex_unlock(&tp->control);
 9209		} else {
 9210			tp->rx_pending = ring->rx_pending;
 9211		}
 9212	}
 9213
 9214	return 0;
 9215}
 9216
 9217static void rtl8152_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
 9218{
 9219	struct r8152 *tp = netdev_priv(netdev);
 9220	u16 bmcr, lcladv, rmtadv;
 9221	u8 cap;
 9222
 9223	if (usb_autopm_get_interface(tp->intf) < 0)
 9224		return;
 9225
 9226	mutex_lock(&tp->control);
 9227
 9228	bmcr = r8152_mdio_read(tp, MII_BMCR);
 9229	lcladv = r8152_mdio_read(tp, MII_ADVERTISE);
 9230	rmtadv = r8152_mdio_read(tp, MII_LPA);
 9231
 9232	mutex_unlock(&tp->control);
 9233
 9234	usb_autopm_put_interface(tp->intf);
 9235
 9236	if (!(bmcr & BMCR_ANENABLE)) {
 9237		pause->autoneg = 0;
 9238		pause->rx_pause = 0;
 9239		pause->tx_pause = 0;
 9240		return;
 9241	}
 9242
 9243	pause->autoneg = 1;
 9244
 9245	cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
 9246
 9247	if (cap & FLOW_CTRL_RX)
 9248		pause->rx_pause = 1;
 9249
 9250	if (cap & FLOW_CTRL_TX)
 9251		pause->tx_pause = 1;
 9252}
 9253
 9254static int rtl8152_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
 9255{
 9256	struct r8152 *tp = netdev_priv(netdev);
 9257	u16 old, new1;
 9258	u8 cap = 0;
 9259	int ret;
 9260
 9261	ret = usb_autopm_get_interface(tp->intf);
 9262	if (ret < 0)
 9263		return ret;
 9264
 9265	mutex_lock(&tp->control);
 9266
 9267	if (pause->autoneg && !(r8152_mdio_read(tp, MII_BMCR) & BMCR_ANENABLE)) {
 9268		ret = -EINVAL;
 9269		goto out;
 9270	}
 9271
 9272	if (pause->rx_pause)
 9273		cap |= FLOW_CTRL_RX;
 9274
 9275	if (pause->tx_pause)
 9276		cap |= FLOW_CTRL_TX;
 9277
 9278	old = r8152_mdio_read(tp, MII_ADVERTISE);
 9279	new1 = (old & ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) | mii_advertise_flowctrl(cap);
 9280	if (old != new1)
 9281		r8152_mdio_write(tp, MII_ADVERTISE, new1);
 9282
 9283out:
 9284	mutex_unlock(&tp->control);
 9285	usb_autopm_put_interface(tp->intf);
 9286
 9287	return ret;
 9288}
 9289
 9290static const struct ethtool_ops ops = {
 9291	.supported_coalesce_params = ETHTOOL_COALESCE_USECS,
 9292	.get_drvinfo = rtl8152_get_drvinfo,
 9293	.get_link = ethtool_op_get_link,
 9294	.nway_reset = rtl8152_nway_reset,
 9295	.get_msglevel = rtl8152_get_msglevel,
 9296	.set_msglevel = rtl8152_set_msglevel,
 9297	.get_wol = rtl8152_get_wol,
 9298	.set_wol = rtl8152_set_wol,
 9299	.get_strings = rtl8152_get_strings,
 9300	.get_sset_count = rtl8152_get_sset_count,
 9301	.get_ethtool_stats = rtl8152_get_ethtool_stats,
 9302	.get_coalesce = rtl8152_get_coalesce,
 9303	.set_coalesce = rtl8152_set_coalesce,
 9304	.get_eee = rtl_ethtool_get_eee,
 9305	.set_eee = rtl_ethtool_set_eee,
 9306	.get_link_ksettings = rtl8152_get_link_ksettings,
 9307	.set_link_ksettings = rtl8152_set_link_ksettings,
 9308	.get_tunable = rtl8152_get_tunable,
 9309	.set_tunable = rtl8152_set_tunable,
 9310	.get_ringparam = rtl8152_get_ringparam,
 9311	.set_ringparam = rtl8152_set_ringparam,
 9312	.get_pauseparam = rtl8152_get_pauseparam,
 9313	.set_pauseparam = rtl8152_set_pauseparam,
 9314};
 9315
 9316static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
 9317{
 9318	struct r8152 *tp = netdev_priv(netdev);
 9319	struct mii_ioctl_data *data = if_mii(rq);
 9320	int res;
 9321
 9322	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 9323		return -ENODEV;
 9324
 9325	res = usb_autopm_get_interface(tp->intf);
 9326	if (res < 0)
 9327		goto out;
 9328
 9329	switch (cmd) {
 9330	case SIOCGMIIPHY:
 9331		data->phy_id = R8152_PHY_ID; /* Internal PHY */
 9332		break;
 9333
 9334	case SIOCGMIIREG:
 9335		mutex_lock(&tp->control);
 9336		data->val_out = r8152_mdio_read(tp, data->reg_num);
 9337		mutex_unlock(&tp->control);
 9338		break;
 9339
 9340	case SIOCSMIIREG:
 9341		if (!capable(CAP_NET_ADMIN)) {
 9342			res = -EPERM;
 9343			break;
 9344		}
 9345		mutex_lock(&tp->control);
 9346		r8152_mdio_write(tp, data->reg_num, data->val_in);
 9347		mutex_unlock(&tp->control);
 9348		break;
 9349
 9350	default:
 9351		res = -EOPNOTSUPP;
 9352	}
 9353
 9354	usb_autopm_put_interface(tp->intf);
 9355
 9356out:
 9357	return res;
 9358}
 9359
 9360static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
 9361{
 9362	struct r8152 *tp = netdev_priv(dev);
 9363	int ret;
 9364
 9365	switch (tp->version) {
 9366	case RTL_VER_01:
 9367	case RTL_VER_02:
 9368	case RTL_VER_07:
 9369		dev->mtu = new_mtu;
 9370		return 0;
 9371	default:
 9372		break;
 9373	}
 9374
 9375	ret = usb_autopm_get_interface(tp->intf);
 9376	if (ret < 0)
 9377		return ret;
 9378
 9379	mutex_lock(&tp->control);
 9380
 9381	dev->mtu = new_mtu;
 9382
 9383	if (netif_running(dev)) {
 9384		if (tp->rtl_ops.change_mtu)
 9385			tp->rtl_ops.change_mtu(tp);
 9386
 9387		if (netif_carrier_ok(dev)) {
 9388			netif_stop_queue(dev);
 9389			napi_disable(&tp->napi);
 9390			tasklet_disable(&tp->tx_tl);
 9391			tp->rtl_ops.disable(tp);
 9392			tp->rtl_ops.enable(tp);
 9393			rtl_start_rx(tp);
 9394			tasklet_enable(&tp->tx_tl);
 9395			napi_enable(&tp->napi);
 9396			rtl8152_set_rx_mode(dev);
 9397			netif_wake_queue(dev);
 9398		}
 9399	}
 9400
 9401	mutex_unlock(&tp->control);
 9402
 9403	usb_autopm_put_interface(tp->intf);
 9404
 9405	return ret;
 9406}
 9407
 9408static const struct net_device_ops rtl8152_netdev_ops = {
 9409	.ndo_open		= rtl8152_open,
 9410	.ndo_stop		= rtl8152_close,
 9411	.ndo_eth_ioctl		= rtl8152_ioctl,
 9412	.ndo_start_xmit		= rtl8152_start_xmit,
 9413	.ndo_tx_timeout		= rtl8152_tx_timeout,
 9414	.ndo_set_features	= rtl8152_set_features,
 9415	.ndo_set_rx_mode	= rtl8152_set_rx_mode,
 9416	.ndo_set_mac_address	= rtl8152_set_mac_address,
 9417	.ndo_change_mtu		= rtl8152_change_mtu,
 9418	.ndo_validate_addr	= eth_validate_addr,
 9419	.ndo_features_check	= rtl8152_features_check,
 9420};
 9421
 9422static void rtl8152_unload(struct r8152 *tp)
 9423{
 9424	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 9425		return;
 9426
 9427	if (tp->version != RTL_VER_01)
 9428		r8152_power_cut_en(tp, true);
 9429}
 9430
 9431static void rtl8153_unload(struct r8152 *tp)
 9432{
 9433	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 9434		return;
 9435
 9436	r8153_power_cut_en(tp, false);
 9437}
 9438
 9439static void rtl8153b_unload(struct r8152 *tp)
 9440{
 9441	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
 9442		return;
 9443
 9444	r8153b_power_cut_en(tp, false);
 9445}
 9446
 9447static int rtl_ops_init(struct r8152 *tp)
 9448{
 9449	struct rtl_ops *ops = &tp->rtl_ops;
 9450	int ret = 0;
 9451
 9452	switch (tp->version) {
 9453	case RTL_VER_01:
 9454	case RTL_VER_02:
 9455	case RTL_VER_07:
 9456		ops->init		= r8152b_init;
 9457		ops->enable		= rtl8152_enable;
 9458		ops->disable		= rtl8152_disable;
 9459		ops->up			= rtl8152_up;
 9460		ops->down		= rtl8152_down;
 9461		ops->unload		= rtl8152_unload;
 9462		ops->eee_get		= r8152_get_eee;
 9463		ops->eee_set		= r8152_set_eee;
 9464		ops->in_nway		= rtl8152_in_nway;
 9465		ops->hw_phy_cfg		= r8152b_hw_phy_cfg;
 9466		ops->autosuspend_en	= rtl_runtime_suspend_enable;
 9467		tp->rx_buf_sz		= 16 * 1024;
 9468		tp->eee_en		= true;
 9469		tp->eee_adv		= MDIO_EEE_100TX;
 9470		break;
 9471
 9472	case RTL_VER_03:
 9473	case RTL_VER_04:
 9474	case RTL_VER_05:
 9475	case RTL_VER_06:
 9476		ops->init		= r8153_init;
 9477		ops->enable		= rtl8153_enable;
 9478		ops->disable		= rtl8153_disable;
 9479		ops->up			= rtl8153_up;
 9480		ops->down		= rtl8153_down;
 9481		ops->unload		= rtl8153_unload;
 9482		ops->eee_get		= r8153_get_eee;
 9483		ops->eee_set		= r8152_set_eee;
 9484		ops->in_nway		= rtl8153_in_nway;
 9485		ops->hw_phy_cfg		= r8153_hw_phy_cfg;
 9486		ops->autosuspend_en	= rtl8153_runtime_enable;
 9487		ops->change_mtu		= rtl8153_change_mtu;
 9488		if (tp->udev->speed < USB_SPEED_SUPER)
 9489			tp->rx_buf_sz	= 16 * 1024;
 9490		else
 9491			tp->rx_buf_sz	= 32 * 1024;
 9492		tp->eee_en		= true;
 9493		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;
 9494		break;
 9495
 9496	case RTL_VER_08:
 9497	case RTL_VER_09:
 9498		ops->init		= r8153b_init;
 9499		ops->enable		= rtl8153_enable;
 9500		ops->disable		= rtl8153_disable;
 9501		ops->up			= rtl8153b_up;
 9502		ops->down		= rtl8153b_down;
 9503		ops->unload		= rtl8153b_unload;
 9504		ops->eee_get		= r8153_get_eee;
 9505		ops->eee_set		= r8152_set_eee;
 9506		ops->in_nway		= rtl8153_in_nway;
 9507		ops->hw_phy_cfg		= r8153b_hw_phy_cfg;
 9508		ops->autosuspend_en	= rtl8153b_runtime_enable;
 9509		ops->change_mtu		= rtl8153_change_mtu;
 9510		tp->rx_buf_sz		= 32 * 1024;
 9511		tp->eee_en		= true;
 9512		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;
 9513		break;
 9514
 9515	case RTL_VER_11:
 9516		tp->eee_en		= true;
 9517		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;
 9518		fallthrough;
 9519	case RTL_VER_10:
 9520		ops->init		= r8156_init;
 9521		ops->enable		= rtl8156_enable;
 9522		ops->disable		= rtl8156_disable;
 9523		ops->up			= rtl8156_up;
 9524		ops->down		= rtl8156_down;
 9525		ops->unload		= rtl8153_unload;
 9526		ops->eee_get		= r8153_get_eee;
 9527		ops->eee_set		= r8152_set_eee;
 9528		ops->in_nway		= rtl8153_in_nway;
 9529		ops->hw_phy_cfg		= r8156_hw_phy_cfg;
 9530		ops->autosuspend_en	= rtl8156_runtime_enable;
 9531		ops->change_mtu		= rtl8156_change_mtu;
 9532		tp->rx_buf_sz		= 48 * 1024;
 9533		tp->support_2500full	= 1;
 9534		break;
 9535
 9536	case RTL_VER_12:
 9537	case RTL_VER_13:
 9538		tp->support_2500full	= 1;
 9539		fallthrough;
 9540	case RTL_VER_15:
 9541		tp->eee_en		= true;
 9542		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;
 9543		ops->init		= r8156b_init;
 9544		ops->enable		= rtl8156b_enable;
 9545		ops->disable		= rtl8153_disable;
 9546		ops->up			= rtl8156_up;
 9547		ops->down		= rtl8156_down;
 9548		ops->unload		= rtl8153_unload;
 9549		ops->eee_get		= r8153_get_eee;
 9550		ops->eee_set		= r8152_set_eee;
 9551		ops->in_nway		= rtl8153_in_nway;
 9552		ops->hw_phy_cfg		= r8156b_hw_phy_cfg;
 9553		ops->autosuspend_en	= rtl8156_runtime_enable;
 9554		ops->change_mtu		= rtl8156_change_mtu;
 9555		tp->rx_buf_sz		= 48 * 1024;
 9556		break;
 9557
 9558	case RTL_VER_14:
 9559		ops->init		= r8153c_init;
 9560		ops->enable		= rtl8153_enable;
 9561		ops->disable		= rtl8153_disable;
 9562		ops->up			= rtl8153c_up;
 9563		ops->down		= rtl8153b_down;
 9564		ops->unload		= rtl8153_unload;
 9565		ops->eee_get		= r8153_get_eee;
 9566		ops->eee_set		= r8152_set_eee;
 9567		ops->in_nway		= rtl8153_in_nway;
 9568		ops->hw_phy_cfg		= r8153c_hw_phy_cfg;
 9569		ops->autosuspend_en	= rtl8153c_runtime_enable;
 9570		ops->change_mtu		= rtl8153c_change_mtu;
 9571		tp->rx_buf_sz		= 32 * 1024;
 9572		tp->eee_en		= true;
 9573		tp->eee_adv		= MDIO_EEE_1000T | MDIO_EEE_100TX;
 9574		break;
 9575
 9576	default:
 9577		ret = -ENODEV;
 9578		dev_err(&tp->intf->dev, "Unknown Device\n");
 9579		break;
 9580	}
 9581
 9582	return ret;
 9583}
 9584
 9585#define FIRMWARE_8153A_2	"rtl_nic/rtl8153a-2.fw"
 9586#define FIRMWARE_8153A_3	"rtl_nic/rtl8153a-3.fw"
 9587#define FIRMWARE_8153A_4	"rtl_nic/rtl8153a-4.fw"
 9588#define FIRMWARE_8153B_2	"rtl_nic/rtl8153b-2.fw"
 9589#define FIRMWARE_8153C_1	"rtl_nic/rtl8153c-1.fw"
 9590#define FIRMWARE_8156A_2	"rtl_nic/rtl8156a-2.fw"
 9591#define FIRMWARE_8156B_2	"rtl_nic/rtl8156b-2.fw"
 9592
 9593MODULE_FIRMWARE(FIRMWARE_8153A_2);
 9594MODULE_FIRMWARE(FIRMWARE_8153A_3);
 9595MODULE_FIRMWARE(FIRMWARE_8153A_4);
 9596MODULE_FIRMWARE(FIRMWARE_8153B_2);
 9597MODULE_FIRMWARE(FIRMWARE_8153C_1);
 9598MODULE_FIRMWARE(FIRMWARE_8156A_2);
 9599MODULE_FIRMWARE(FIRMWARE_8156B_2);
 9600
 9601static int rtl_fw_init(struct r8152 *tp)
 9602{
 9603	struct rtl_fw *rtl_fw = &tp->rtl_fw;
 9604
 9605	switch (tp->version) {
 9606	case RTL_VER_04:
 9607		rtl_fw->fw_name		= FIRMWARE_8153A_2;
 9608		rtl_fw->pre_fw		= r8153_pre_firmware_1;
 9609		rtl_fw->post_fw		= r8153_post_firmware_1;
 9610		break;
 9611	case RTL_VER_05:
 9612		rtl_fw->fw_name		= FIRMWARE_8153A_3;
 9613		rtl_fw->pre_fw		= r8153_pre_firmware_2;
 9614		rtl_fw->post_fw		= r8153_post_firmware_2;
 9615		break;
 9616	case RTL_VER_06:
 9617		rtl_fw->fw_name		= FIRMWARE_8153A_4;
 9618		rtl_fw->post_fw		= r8153_post_firmware_3;
 9619		break;
 9620	case RTL_VER_09:
 9621		rtl_fw->fw_name		= FIRMWARE_8153B_2;
 9622		rtl_fw->pre_fw		= r8153b_pre_firmware_1;
 9623		rtl_fw->post_fw		= r8153b_post_firmware_1;
 9624		break;
 9625	case RTL_VER_11:
 9626		rtl_fw->fw_name		= FIRMWARE_8156A_2;
 9627		rtl_fw->post_fw		= r8156a_post_firmware_1;
 9628		break;
 9629	case RTL_VER_13:
 9630	case RTL_VER_15:
 9631		rtl_fw->fw_name		= FIRMWARE_8156B_2;
 9632		break;
 9633	case RTL_VER_14:
 9634		rtl_fw->fw_name		= FIRMWARE_8153C_1;
 9635		rtl_fw->pre_fw		= r8153b_pre_firmware_1;
 9636		rtl_fw->post_fw		= r8153c_post_firmware_1;
 9637		break;
 9638	default:
 9639		break;
 9640	}
 9641
 9642	return 0;
 9643}
 9644
 9645static u8 __rtl_get_hw_ver(struct usb_device *udev)
 9646{
 
 9647	u32 ocp_data = 0;
 9648	__le32 *tmp;
 9649	u8 version;
 9650	int ret;
 9651	int i;
 9652
 9653	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
 9654	if (!tmp)
 9655		return 0;
 9656
 9657	/* Retry up to 3 times in case there is a transitory error. We do this
 9658	 * since retrying a read of the version is always safe and this
 9659	 * function doesn't take advantage of r8152_control_msg().
 9660	 */
 9661	for (i = 0; i < 3; i++) {
 9662		ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
 9663				      RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
 9664				      PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp),
 9665				      USB_CTRL_GET_TIMEOUT);
 9666		if (ret > 0) {
 9667			ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
 9668			break;
 9669		}
 9670	}
 9671
 9672	if (i != 0 && ret > 0)
 9673		dev_warn(&udev->dev, "Needed %d retries to read version\n", i);
 9674
 9675	kfree(tmp);
 9676
 9677	switch (ocp_data) {
 9678	case 0x4c00:
 9679		version = RTL_VER_01;
 9680		break;
 9681	case 0x4c10:
 9682		version = RTL_VER_02;
 9683		break;
 9684	case 0x5c00:
 9685		version = RTL_VER_03;
 9686		break;
 9687	case 0x5c10:
 9688		version = RTL_VER_04;
 9689		break;
 9690	case 0x5c20:
 9691		version = RTL_VER_05;
 9692		break;
 9693	case 0x5c30:
 9694		version = RTL_VER_06;
 9695		break;
 9696	case 0x4800:
 9697		version = RTL_VER_07;
 9698		break;
 9699	case 0x6000:
 9700		version = RTL_VER_08;
 9701		break;
 9702	case 0x6010:
 9703		version = RTL_VER_09;
 9704		break;
 9705	case 0x7010:
 9706		version = RTL_TEST_01;
 9707		break;
 9708	case 0x7020:
 9709		version = RTL_VER_10;
 9710		break;
 9711	case 0x7030:
 9712		version = RTL_VER_11;
 9713		break;
 9714	case 0x7400:
 9715		version = RTL_VER_12;
 9716		break;
 9717	case 0x7410:
 9718		version = RTL_VER_13;
 9719		break;
 9720	case 0x6400:
 9721		version = RTL_VER_14;
 9722		break;
 9723	case 0x7420:
 9724		version = RTL_VER_15;
 9725		break;
 9726	default:
 9727		version = RTL_VER_UNKNOWN;
 9728		dev_info(&udev->dev, "Unknown version 0x%04x\n", ocp_data);
 9729		break;
 9730	}
 9731
 9732	return version;
 9733}
 9734
 9735u8 rtl8152_get_version(struct usb_interface *intf)
 9736{
 9737	u8 version;
 9738
 9739	version = __rtl_get_hw_ver(interface_to_usbdev(intf));
 9740
 9741	dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
 9742
 9743	return version;
 9744}
 9745EXPORT_SYMBOL_GPL(rtl8152_get_version);
 9746
 9747static bool rtl8152_supports_lenovo_macpassthru(struct usb_device *udev)
 9748{
 9749	int parent_vendor_id = le16_to_cpu(udev->parent->descriptor.idVendor);
 9750	int product_id = le16_to_cpu(udev->descriptor.idProduct);
 9751	int vendor_id = le16_to_cpu(udev->descriptor.idVendor);
 9752
 9753	if (vendor_id == VENDOR_ID_LENOVO) {
 9754		switch (product_id) {
 9755		case DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB:
 9756		case DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK:
 9757		case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
 9758		case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
 9759		case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3:
 9760		case DEVICE_ID_THINKPAD_USB_C_DONGLE:
 9761			return 1;
 9762		}
 9763	} else if (vendor_id == VENDOR_ID_REALTEK && parent_vendor_id == VENDOR_ID_LENOVO) {
 9764		switch (product_id) {
 9765		case 0x8153:
 9766			return 1;
 9767		}
 9768	}
 9769	return 0;
 9770}
 9771
 9772static int rtl8152_probe_once(struct usb_interface *intf,
 9773			      const struct usb_device_id *id, u8 version)
 9774{
 9775	struct usb_device *udev = interface_to_usbdev(intf);
 
 9776	struct r8152 *tp;
 9777	struct net_device *netdev;
 9778	int ret;
 9779
 
 
 
 
 
 
 
 
 9780	usb_reset_device(udev);
 9781	netdev = alloc_etherdev(sizeof(struct r8152));
 9782	if (!netdev) {
 9783		dev_err(&intf->dev, "Out of memory\n");
 9784		return -ENOMEM;
 9785	}
 9786
 9787	SET_NETDEV_DEV(netdev, &intf->dev);
 9788	tp = netdev_priv(netdev);
 9789	tp->msg_enable = 0x7FFF;
 9790
 9791	tp->udev = udev;
 9792	tp->netdev = netdev;
 9793	tp->intf = intf;
 9794	tp->version = version;
 9795
 9796	tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0);
 9797	tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0);
 9798	tp->pipe_in = usb_rcvbulkpipe(udev, 1);
 9799	tp->pipe_out = usb_sndbulkpipe(udev, 2);
 9800	tp->pipe_intr = usb_rcvintpipe(udev, 3);
 9801
 9802	switch (version) {
 9803	case RTL_VER_01:
 9804	case RTL_VER_02:
 9805	case RTL_VER_07:
 9806		tp->mii.supports_gmii = 0;
 9807		break;
 9808	default:
 9809		tp->mii.supports_gmii = 1;
 9810		break;
 9811	}
 9812
 9813	ret = rtl_ops_init(tp);
 9814	if (ret)
 9815		goto out;
 9816
 9817	rtl_fw_init(tp);
 9818
 9819	mutex_init(&tp->control);
 9820	INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
 9821	INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
 9822	tasklet_setup(&tp->tx_tl, bottom_half);
 9823	tasklet_disable(&tp->tx_tl);
 9824
 9825	netdev->netdev_ops = &rtl8152_netdev_ops;
 9826	netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
 9827
 9828	netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
 9829			    NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
 9830			    NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
 9831			    NETIF_F_HW_VLAN_CTAG_TX;
 9832	netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
 9833			      NETIF_F_TSO | NETIF_F_FRAGLIST |
 9834			      NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
 9835			      NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
 9836	netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
 9837				NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
 9838				NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
 9839
 9840	if (tp->version == RTL_VER_01) {
 9841		netdev->features &= ~NETIF_F_RXCSUM;
 9842		netdev->hw_features &= ~NETIF_F_RXCSUM;
 9843	}
 9844
 9845	tp->lenovo_macpassthru = rtl8152_supports_lenovo_macpassthru(udev);
 9846
 9847	if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
 9848	    (!strcmp(udev->serial, "000001000000") ||
 9849	     !strcmp(udev->serial, "000002000000"))) {
 9850		dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
 9851		tp->dell_tb_rx_agg_bug = 1;
 9852	}
 9853
 9854	netdev->ethtool_ops = &ops;
 9855	netif_set_tso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
 9856
 9857	/* MTU range: 68 - 1500 or 9194 */
 9858	netdev->min_mtu = ETH_MIN_MTU;
 9859	switch (tp->version) {
 9860	case RTL_VER_03:
 9861	case RTL_VER_04:
 9862	case RTL_VER_05:
 9863	case RTL_VER_06:
 9864	case RTL_VER_08:
 9865	case RTL_VER_09:
 9866	case RTL_VER_14:
 9867		netdev->max_mtu = size_to_mtu(9 * 1024);
 9868		break;
 9869	case RTL_VER_10:
 9870	case RTL_VER_11:
 9871		netdev->max_mtu = size_to_mtu(15 * 1024);
 9872		break;
 9873	case RTL_VER_12:
 9874	case RTL_VER_13:
 9875	case RTL_VER_15:
 9876		netdev->max_mtu = size_to_mtu(16 * 1024);
 9877		break;
 9878	case RTL_VER_01:
 9879	case RTL_VER_02:
 9880	case RTL_VER_07:
 9881	default:
 9882		netdev->max_mtu = ETH_DATA_LEN;
 9883		break;
 
 
 
 9884	}
 9885
 9886	tp->mii.dev = netdev;
 9887	tp->mii.mdio_read = read_mii_word;
 9888	tp->mii.mdio_write = write_mii_word;
 9889	tp->mii.phy_id_mask = 0x3f;
 9890	tp->mii.reg_num_mask = 0x1f;
 9891	tp->mii.phy_id = R8152_PHY_ID;
 9892
 9893	tp->autoneg = AUTONEG_ENABLE;
 9894	tp->speed = SPEED_100;
 9895	tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
 9896			  RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
 9897	if (tp->mii.supports_gmii) {
 9898		if (tp->support_2500full &&
 9899		    tp->udev->speed >= USB_SPEED_SUPER) {
 9900			tp->speed = SPEED_2500;
 9901			tp->advertising |= RTL_ADVERTISED_2500_FULL;
 9902		} else {
 9903			tp->speed = SPEED_1000;
 9904		}
 9905		tp->advertising |= RTL_ADVERTISED_1000_FULL;
 9906	}
 9907	tp->duplex = DUPLEX_FULL;
 9908
 9909	tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
 9910	tp->rx_pending = 10 * RTL8152_MAX_RX;
 9911
 9912	intf->needs_remote_wakeup = 1;
 9913
 9914	if (!rtl_can_wakeup(tp))
 9915		__rtl_set_wol(tp, 0);
 9916	else
 9917		tp->saved_wolopts = __rtl_get_wol(tp);
 9918
 9919	tp->rtl_ops.init(tp);
 9920#if IS_BUILTIN(CONFIG_USB_RTL8152)
 9921	/* Retry in case request_firmware() is not ready yet. */
 9922	tp->rtl_fw.retry = true;
 9923#endif
 9924	queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
 9925	set_ethernet_addr(tp, false);
 9926
 9927	usb_set_intfdata(intf, tp);
 9928
 9929	netif_napi_add(netdev, &tp->napi, r8152_poll);
 9930
 9931	ret = register_netdev(netdev);
 9932	if (ret != 0) {
 9933		dev_err(&intf->dev, "couldn't register the device\n");
 9934		goto out1;
 9935	}
 9936
 
 
 
 
 9937	if (tp->saved_wolopts)
 9938		device_set_wakeup_enable(&udev->dev, true);
 9939	else
 9940		device_set_wakeup_enable(&udev->dev, false);
 9941
 9942	/* If we saw a control transfer error while probing then we may
 9943	 * want to try probe() again. Consider this an error.
 9944	 */
 9945	if (test_bit(PROBE_SHOULD_RETRY, &tp->flags))
 9946		goto out2;
 9947
 9948	set_bit(PROBED_WITH_NO_ERRORS, &tp->flags);
 9949	netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
 9950
 9951	return 0;
 9952
 9953out2:
 9954	unregister_netdev(netdev);
 9955
 9956out1:
 9957	tasklet_kill(&tp->tx_tl);
 9958	cancel_delayed_work_sync(&tp->hw_phy_work);
 9959	if (tp->rtl_ops.unload)
 9960		tp->rtl_ops.unload(tp);
 9961	rtl8152_release_firmware(tp);
 9962	usb_set_intfdata(intf, NULL);
 9963out:
 9964	if (test_bit(PROBE_SHOULD_RETRY, &tp->flags))
 9965		ret = -EAGAIN;
 9966
 9967	free_netdev(netdev);
 9968	return ret;
 9969}
 9970
 9971#define RTL8152_PROBE_TRIES	3
 9972
 9973static int rtl8152_probe(struct usb_interface *intf,
 9974			 const struct usb_device_id *id)
 9975{
 9976	u8 version;
 9977	int ret;
 9978	int i;
 9979
 9980	if (intf->cur_altsetting->desc.bInterfaceClass != USB_CLASS_VENDOR_SPEC)
 9981		return -ENODEV;
 9982
 9983	if (!rtl_check_vendor_ok(intf))
 9984		return -ENODEV;
 9985
 9986	version = rtl8152_get_version(intf);
 9987	if (version == RTL_VER_UNKNOWN)
 9988		return -ENODEV;
 9989
 9990	for (i = 0; i < RTL8152_PROBE_TRIES; i++) {
 9991		ret = rtl8152_probe_once(intf, id, version);
 9992		if (ret != -EAGAIN)
 9993			break;
 9994	}
 9995	if (ret == -EAGAIN) {
 9996		dev_err(&intf->dev,
 9997			"r8152 failed probe after %d tries; giving up\n", i);
 9998		return -ENODEV;
 9999	}
10000
10001	return ret;
10002}
10003
10004static void rtl8152_disconnect(struct usb_interface *intf)
10005{
10006	struct r8152 *tp = usb_get_intfdata(intf);
10007
10008	usb_set_intfdata(intf, NULL);
10009	if (tp) {
10010		rtl_set_unplug(tp);
10011
10012		unregister_netdev(tp->netdev);
10013		tasklet_kill(&tp->tx_tl);
10014		cancel_delayed_work_sync(&tp->hw_phy_work);
10015		if (tp->rtl_ops.unload)
10016			tp->rtl_ops.unload(tp);
10017		rtl8152_release_firmware(tp);
10018		free_netdev(tp->netdev);
10019	}
10020}
10021
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
10022/* table of devices that work with this driver */
10023static const struct usb_device_id rtl8152_table[] = {
10024	/* Realtek */
10025	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8050) },
10026	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8053) },
10027	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8152) },
10028	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8153) },
10029	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8155) },
10030	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8156) },
10031
10032	/* Microsoft */
10033	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab) },
10034	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6) },
10035	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927) },
10036	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0c5e) },
10037	{ USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101) },
10038	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x304f) },
10039	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x3054) },
10040	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x3062) },
10041	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x3069) },
10042	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x3082) },
10043	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x7205) },
10044	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x720c) },
10045	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x7214) },
10046	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x721e) },
10047	{ USB_DEVICE(VENDOR_ID_LENOVO,  0xa387) },
10048	{ USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041) },
10049	{ USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff) },
10050	{ USB_DEVICE(VENDOR_ID_TPLINK,  0x0601) },
10051	{ USB_DEVICE(VENDOR_ID_DLINK,   0xb301) },
10052	{ USB_DEVICE(VENDOR_ID_ASUS,    0x1976) },
10053	{}
10054};
10055
10056MODULE_DEVICE_TABLE(usb, rtl8152_table);
10057
10058static struct usb_driver rtl8152_driver = {
10059	.name =		MODULENAME,
10060	.id_table =	rtl8152_table,
10061	.probe =	rtl8152_probe,
10062	.disconnect =	rtl8152_disconnect,
10063	.suspend =	rtl8152_suspend,
10064	.resume =	rtl8152_resume,
10065	.reset_resume =	rtl8152_reset_resume,
10066	.pre_reset =	rtl8152_pre_reset,
10067	.post_reset =	rtl8152_post_reset,
10068	.supports_autosuspend = 1,
10069	.disable_hub_initiated_lpm = 1,
10070};
10071
10072static int rtl8152_cfgselector_choose_configuration(struct usb_device *udev)
10073{
10074	struct usb_host_config *c;
10075	int i, num_configs;
10076
10077	/* Switch the device to vendor mode, if and only if the vendor mode
10078	 * driver supports it.
10079	 */
10080	if (__rtl_get_hw_ver(udev) == RTL_VER_UNKNOWN)
10081		return 0;
10082
10083	/* The vendor mode is not always config #1, so to find it out. */
10084	c = udev->config;
10085	num_configs = udev->descriptor.bNumConfigurations;
10086	for (i = 0; i < num_configs; (i++, c++)) {
10087		struct usb_interface_descriptor	*desc = NULL;
10088
10089		if (!c->desc.bNumInterfaces)
10090			continue;
10091		desc = &c->intf_cache[0]->altsetting->desc;
10092		if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC)
10093			break;
10094	}
10095
10096	if (i == num_configs)
10097		return -ENODEV;
10098
10099	return c->desc.bConfigurationValue;
10100}
10101
10102static struct usb_device_driver rtl8152_cfgselector_driver = {
10103	.name =	MODULENAME "-cfgselector",
10104	.choose_configuration = rtl8152_cfgselector_choose_configuration,
10105	.id_table = rtl8152_table,
10106	.generic_subclass = 1,
10107	.supports_autosuspend = 1,
10108};
10109
10110static int __init rtl8152_driver_init(void)
10111{
10112	int ret;
10113
10114	ret = usb_register_device_driver(&rtl8152_cfgselector_driver, THIS_MODULE);
10115	if (ret)
10116		return ret;
10117	return usb_register(&rtl8152_driver);
10118}
10119
10120static void __exit rtl8152_driver_exit(void)
10121{
10122	usb_deregister(&rtl8152_driver);
10123	usb_deregister_device_driver(&rtl8152_cfgselector_driver);
10124}
10125
10126module_init(rtl8152_driver_init);
10127module_exit(rtl8152_driver_exit);
10128
10129MODULE_AUTHOR(DRIVER_AUTHOR);
10130MODULE_DESCRIPTION(DRIVER_DESC);
10131MODULE_LICENSE("GPL");
10132MODULE_VERSION(DRIVER_VERSION);