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1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (C) 2023 Linaro Ltd. */
4
5#include <linux/types.h>
6
7#include "../ipa.h"
8#include "../ipa_reg.h"
9
10static const u32 reg_flavor_0_fmask[] = {
11 [MAX_PIPES] = GENMASK(7, 0),
12 [MAX_CONS_PIPES] = GENMASK(15, 8),
13 [MAX_PROD_PIPES] = GENMASK(23, 16),
14 [PROD_LOWEST] = GENMASK(31, 24),
15};
16
17REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000);
18
19static const u32 reg_comp_cfg_fmask[] = {
20 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
21 [GSI_SNOC_BYPASS_DIS] = BIT(1),
22 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
23 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
24 /* Bit 4 reserved */
25 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
26 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
27 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
28 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
29 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
30 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
31 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
32 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
33 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
34 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
35 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
36 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
37 [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(17),
38 /* Bit 18 reserved */
39 [QMB_RAM_RD_CACHE_DISABLE] = BIT(19),
40 [GENQMB_AOOOWR] = BIT(20),
41 [IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21),
42 [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(27, 22),
43 /* Bits 28-29 reserved */
44 [GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30),
45 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
46};
47
48REG_FIELDS(COMP_CFG, comp_cfg, 0x0000002c);
49
50static const u32 reg_clkon_cfg_fmask[] = {
51 [CLKON_RX] = BIT(0),
52 [CLKON_PROC] = BIT(1),
53 [TX_WRAPPER] = BIT(2),
54 [CLKON_MISC] = BIT(3),
55 [RAM_ARB] = BIT(4),
56 [FTCH_HPS] = BIT(5),
57 [FTCH_DPS] = BIT(6),
58 [CLKON_HPS] = BIT(7),
59 [CLKON_DPS] = BIT(8),
60 [RX_HPS_CMDQS] = BIT(9),
61 [HPS_DPS_CMDQS] = BIT(10),
62 [DPS_TX_CMDQS] = BIT(11),
63 [RSRC_MNGR] = BIT(12),
64 [CTX_HANDLER] = BIT(13),
65 [ACK_MNGR] = BIT(14),
66 [D_DCPH] = BIT(15),
67 [H_DCPH] = BIT(16),
68 /* Bit 17 reserved */
69 [NTF_TX_CMDQS] = BIT(18),
70 [CLKON_TX_0] = BIT(19),
71 [CLKON_TX_1] = BIT(20),
72 [CLKON_FNR] = BIT(21),
73 [QSB2AXI_CMDQ_L] = BIT(22),
74 [AGGR_WRAPPER] = BIT(23),
75 [RAM_SLAVEWAY] = BIT(24),
76 [CLKON_QMB] = BIT(25),
77 [WEIGHT_ARB] = BIT(26),
78 [GSI_IF] = BIT(27),
79 [CLKON_GLOBAL] = BIT(28),
80 [GLOBAL_2X_CLK] = BIT(29),
81 [DPL_FIFO] = BIT(30),
82 [DRBIP] = BIT(31),
83};
84
85REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000034);
86
87static const u32 reg_route_fmask[] = {
88 [ROUTE_DEF_PIPE] = GENMASK(7, 0),
89 [ROUTE_FRAG_DEF_PIPE] = GENMASK(15, 8),
90 [ROUTE_DEF_HDR_OFST] = GENMASK(25, 16),
91 [ROUTE_DEF_HDR_TABLE] = BIT(26),
92 [ROUTE_DEF_RETAIN_HDR] = BIT(27),
93 [ROUTE_DIS] = BIT(28),
94 /* Bits 29-31 reserved */
95};
96
97REG_FIELDS(ROUTE, route, 0x00000038);
98
99static const u32 reg_shared_mem_size_fmask[] = {
100 [MEM_SIZE] = GENMASK(15, 0),
101 [MEM_BADDR] = GENMASK(31, 16),
102};
103
104REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000040);
105
106static const u32 reg_qsb_max_writes_fmask[] = {
107 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
108 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
109 /* Bits 8-31 reserved */
110};
111
112REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000054);
113
114static const u32 reg_qsb_max_reads_fmask[] = {
115 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
116 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
117 /* Bits 8-15 reserved */
118 [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16),
119 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
120};
121
122REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000058);
123
124/* Valid bits defined by ipa->available */
125
126REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x00000100, 0x0004);
127
128static const u32 reg_filt_rout_cache_flush_fmask[] = {
129 [ROUTER_CACHE] = BIT(0),
130 /* Bits 1-3 reserved */
131 [FILTER_CACHE] = BIT(4),
132 /* Bits 5-31 reserved */
133};
134
135REG_FIELDS(FILT_ROUT_CACHE_FLUSH, filt_rout_cache_flush, 0x0000404);
136
137static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
138 [IPA_BASE_ADDR] = GENMASK(17, 0),
139 /* Bits 18-31 reserved */
140};
141
142/* Offset must be a multiple of 8 */
143REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x00000478);
144
145static const u32 reg_ipa_tx_cfg_fmask[] = {
146 /* Bits 0-1 reserved */
147 [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2),
148 [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6),
149 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
150 [DMAW_MAX_BEATS_256_DIS] = BIT(11),
151 [PA_MASK_EN] = BIT(12),
152 [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
153 [DUAL_TX_ENABLE] = BIT(17),
154 [SSPND_PA_NO_START_STATE] = BIT(18),
155 /* Bit 19 reserved */
156 [HOLB_STICKY_DROP_EN] = BIT(20),
157 /* Bits 21-31 reserved */
158};
159
160REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x00000488);
161
162static const u32 reg_idle_indication_cfg_fmask[] = {
163 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
164 [CONST_NON_IDLE_ENABLE] = BIT(16),
165 /* Bits 17-31 reserved */
166};
167
168REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x000004a8);
169
170static const u32 reg_qtime_timestamp_cfg_fmask[] = {
171 [DPL_TIMESTAMP_LSB] = GENMASK(4, 0),
172 /* Bits 5-6 reserved */
173 [DPL_TIMESTAMP_SEL] = BIT(7),
174 [TAG_TIMESTAMP_LSB] = GENMASK(12, 8),
175 /* Bits 13-15 reserved */
176 [NAT_TIMESTAMP_LSB] = GENMASK(20, 16),
177 /* Bits 21-31 reserved */
178};
179
180REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x000004ac);
181
182static const u32 reg_timers_xo_clk_div_cfg_fmask[] = {
183 [DIV_VALUE] = GENMASK(8, 0),
184 /* Bits 9-30 reserved */
185 [DIV_ENABLE] = BIT(31),
186};
187
188REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x000004b0);
189
190static const u32 reg_timers_pulse_gran_cfg_fmask[] = {
191 [PULSE_GRAN_0] = GENMASK(2, 0),
192 [PULSE_GRAN_1] = GENMASK(5, 3),
193 [PULSE_GRAN_2] = GENMASK(8, 6),
194 [PULSE_GRAN_3] = GENMASK(11, 9),
195 /* Bits 12-31 reserved */
196};
197
198REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x000004b4);
199
200static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
201 [X_MIN_LIM] = GENMASK(5, 0),
202 /* Bits 6-7 reserved */
203 [X_MAX_LIM] = GENMASK(13, 8),
204 /* Bits 14-15 reserved */
205 [Y_MIN_LIM] = GENMASK(21, 16),
206 /* Bits 22-23 reserved */
207 [Y_MAX_LIM] = GENMASK(29, 24),
208 /* Bits 30-31 reserved */
209};
210
211REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
212 0x00000500, 0x0020);
213
214static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
215 [X_MIN_LIM] = GENMASK(5, 0),
216 /* Bits 6-7 reserved */
217 [X_MAX_LIM] = GENMASK(13, 8),
218 /* Bits 14-15 reserved */
219 [Y_MIN_LIM] = GENMASK(21, 16),
220 /* Bits 22-23 reserved */
221 [Y_MAX_LIM] = GENMASK(29, 24),
222 /* Bits 30-31 reserved */
223};
224
225REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
226 0x00000504, 0x0020);
227
228static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = {
229 [X_MIN_LIM] = GENMASK(5, 0),
230 /* Bits 6-7 reserved */
231 [X_MAX_LIM] = GENMASK(13, 8),
232 /* Bits 14-15 reserved */
233 [Y_MIN_LIM] = GENMASK(21, 16),
234 /* Bits 22-23 reserved */
235 [Y_MAX_LIM] = GENMASK(29, 24),
236 /* Bits 30-31 reserved */
237};
238
239REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type,
240 0x00000508, 0x0020);
241
242static const u32 reg_src_rsrc_grp_67_rsrc_type_fmask[] = {
243 [X_MIN_LIM] = GENMASK(5, 0),
244 /* Bits 6-7 reserved */
245 [X_MAX_LIM] = GENMASK(13, 8),
246 /* Bits 14-15 reserved */
247 [Y_MIN_LIM] = GENMASK(21, 16),
248 /* Bits 22-23 reserved */
249 [Y_MAX_LIM] = GENMASK(29, 24),
250 /* Bits 30-31 reserved */
251};
252
253REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type,
254 0x0000050c, 0x0020);
255
256static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
257 [X_MIN_LIM] = GENMASK(5, 0),
258 /* Bits 6-7 reserved */
259 [X_MAX_LIM] = GENMASK(13, 8),
260 /* Bits 14-15 reserved */
261 [Y_MIN_LIM] = GENMASK(21, 16),
262 /* Bits 22-23 reserved */
263 [Y_MAX_LIM] = GENMASK(29, 24),
264 /* Bits 30-31 reserved */
265};
266
267REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
268 0x00000600, 0x0020);
269
270static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
271 [X_MIN_LIM] = GENMASK(5, 0),
272 /* Bits 6-7 reserved */
273 [X_MAX_LIM] = GENMASK(13, 8),
274 /* Bits 14-15 reserved */
275 [Y_MIN_LIM] = GENMASK(21, 16),
276 /* Bits 22-23 reserved */
277 [Y_MAX_LIM] = GENMASK(29, 24),
278 /* Bits 30-31 reserved */
279};
280
281REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
282 0x00000604, 0x0020);
283
284static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {
285 [X_MIN_LIM] = GENMASK(5, 0),
286 /* Bits 6-7 reserved */
287 [X_MAX_LIM] = GENMASK(13, 8),
288 /* Bits 14-15 reserved */
289 [Y_MIN_LIM] = GENMASK(21, 16),
290 /* Bits 22-23 reserved */
291 [Y_MAX_LIM] = GENMASK(29, 24),
292 /* Bits 30-31 reserved */
293};
294
295REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,
296 0x00000608, 0x0020);
297
298static const u32 reg_dst_rsrc_grp_67_rsrc_type_fmask[] = {
299 [X_MIN_LIM] = GENMASK(5, 0),
300 /* Bits 6-7 reserved */
301 [X_MAX_LIM] = GENMASK(13, 8),
302 /* Bits 14-15 reserved */
303 [Y_MIN_LIM] = GENMASK(21, 16),
304 /* Bits 22-23 reserved */
305 [Y_MAX_LIM] = GENMASK(29, 24),
306 /* Bits 30-31 reserved */
307};
308
309REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type,
310 0x0000060c, 0x0020);
311
312/* Valid bits defined by ipa->available */
313
314REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000006b0, 0x0004);
315
316static const u32 reg_endp_init_cfg_fmask[] = {
317 [FRAG_OFFLOAD_EN] = BIT(0),
318 [CS_OFFLOAD_EN] = GENMASK(2, 1),
319 [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3),
320 /* Bit 7 reserved */
321 [CS_GEN_QMB_MASTER_SEL] = BIT(8),
322 /* Bits 9-31 reserved */
323};
324
325REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00001008, 0x0080);
326
327static const u32 reg_endp_init_nat_fmask[] = {
328 [NAT_EN] = GENMASK(1, 0),
329 /* Bits 2-31 reserved */
330};
331
332REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000100c, 0x0080);
333
334static const u32 reg_endp_init_hdr_fmask[] = {
335 [HDR_LEN] = GENMASK(5, 0),
336 [HDR_OFST_METADATA_VALID] = BIT(6),
337 [HDR_OFST_METADATA] = GENMASK(12, 7),
338 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
339 [HDR_OFST_PKT_SIZE_VALID] = BIT(19),
340 [HDR_OFST_PKT_SIZE] = GENMASK(25, 20),
341 /* Bit 26 reserved */
342 [HDR_LEN_INC_DEAGG_HDR] = BIT(27),
343 [HDR_LEN_MSB] = GENMASK(29, 28),
344 [HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
345};
346
347REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00001010, 0x0080);
348
349static const u32 reg_endp_init_hdr_ext_fmask[] = {
350 [HDR_ENDIANNESS] = BIT(0),
351 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
352 [HDR_TOTAL_LEN_OR_PAD] = BIT(2),
353 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
354 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4),
355 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
356 /* Bits 14-15 reserved */
357 [HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16),
358 [HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18),
359 [HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20),
360 [HDR_BYTES_TO_REMOVE_VALID] = BIT(22),
361 /* Bit 23 reserved */
362 [HDR_BYTES_TO_REMOVE] = GENMASK(31, 24),
363};
364
365REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00001014, 0x0080);
366
367REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
368 0x00001018, 0x0080);
369
370static const u32 reg_endp_init_mode_fmask[] = {
371 [ENDP_MODE] = GENMASK(2, 0),
372 [DCPH_ENABLE] = BIT(3),
373 [DEST_PIPE_INDEX] = GENMASK(11, 4),
374 [BYTE_THRESHOLD] = GENMASK(27, 12),
375 [PIPE_REPLICATION_EN] = BIT(28),
376 [PAD_EN] = BIT(29),
377 [DRBIP_ACL_ENABLE] = BIT(30),
378 /* Bit 31 reserved */
379};
380
381REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00001020, 0x0080);
382
383static const u32 reg_endp_init_aggr_fmask[] = {
384 [AGGR_EN] = GENMASK(1, 0),
385 [AGGR_TYPE] = GENMASK(4, 2),
386 [BYTE_LIMIT] = GENMASK(10, 5),
387 /* Bit 11 reserved */
388 [TIME_LIMIT] = GENMASK(16, 12),
389 [PKT_LIMIT] = GENMASK(22, 17),
390 [SW_EOF_ACTIVE] = BIT(23),
391 [FORCE_CLOSE] = BIT(24),
392 /* Bit 25 reserved */
393 [HARD_BYTE_LIMIT_EN] = BIT(26),
394 [AGGR_GRAN_SEL] = BIT(27),
395 /* Bits 28-31 reserved */
396};
397
398REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00001024, 0x0080);
399
400static const u32 reg_endp_init_hol_block_en_fmask[] = {
401 [HOL_BLOCK_EN] = BIT(0),
402 /* Bits 1-31 reserved */
403};
404
405REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
406 0x0000102c, 0x0080);
407
408static const u32 reg_endp_init_hol_block_timer_fmask[] = {
409 [TIMER_LIMIT] = GENMASK(4, 0),
410 /* Bits 5-7 reserved */
411 [TIMER_GRAN_SEL] = GENMASK(9, 8),
412 /* Bits 10-31 reserved */
413};
414
415REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
416 0x00001030, 0x0080);
417
418static const u32 reg_endp_init_deaggr_fmask[] = {
419 [DEAGGR_HDR_LEN] = GENMASK(5, 0),
420 [SYSPIPE_ERR_DETECTION] = BIT(6),
421 [PACKET_OFFSET_VALID] = BIT(7),
422 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
423 [IGNORE_MIN_PKT_ERR] = BIT(14),
424 /* Bit 15 reserved */
425 [MAX_PACKET_LEN] = GENMASK(31, 16),
426};
427
428REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00001034, 0x0080);
429
430static const u32 reg_endp_init_rsrc_grp_fmask[] = {
431 [ENDP_RSRC_GRP] = GENMASK(2, 0),
432 /* Bits 3-31 reserved */
433};
434
435REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00001038, 0x0080);
436
437static const u32 reg_endp_init_seq_fmask[] = {
438 [SEQ_TYPE] = GENMASK(7, 0),
439 /* Bits 8-31 reserved */
440};
441
442REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000103c, 0x0080);
443
444static const u32 reg_endp_status_fmask[] = {
445 [STATUS_EN] = BIT(0),
446 [STATUS_ENDP] = GENMASK(8, 1),
447 [STATUS_PKT_SUPPRESS] = BIT(9),
448 /* Bits 10-31 reserved */
449};
450
451REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00001040, 0x0080);
452
453static const u32 reg_endp_filter_cache_cfg_fmask[] = {
454 [CACHE_MSK_SRC_ID] = BIT(0),
455 [CACHE_MSK_SRC_IP] = BIT(1),
456 [CACHE_MSK_DST_IP] = BIT(2),
457 [CACHE_MSK_SRC_PORT] = BIT(3),
458 [CACHE_MSK_DST_PORT] = BIT(4),
459 [CACHE_MSK_PROTOCOL] = BIT(5),
460 [CACHE_MSK_METADATA] = BIT(6),
461 /* Bits 7-31 reserved */
462};
463
464REG_STRIDE_FIELDS(ENDP_FILTER_CACHE_CFG, endp_filter_cache_cfg,
465 0x0000105c, 0x0080);
466
467static const u32 reg_endp_router_cache_cfg_fmask[] = {
468 [CACHE_MSK_SRC_ID] = BIT(0),
469 [CACHE_MSK_SRC_IP] = BIT(1),
470 [CACHE_MSK_DST_IP] = BIT(2),
471 [CACHE_MSK_SRC_PORT] = BIT(3),
472 [CACHE_MSK_DST_PORT] = BIT(4),
473 [CACHE_MSK_PROTOCOL] = BIT(5),
474 [CACHE_MSK_METADATA] = BIT(6),
475 /* Bits 7-31 reserved */
476};
477
478REG_STRIDE_FIELDS(ENDP_ROUTER_CACHE_CFG, endp_router_cache_cfg,
479 0x00001070, 0x0080);
480
481/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
482REG(IPA_IRQ_STTS, ipa_irq_stts, 0x0000c008 + 0x1000 * GSI_EE_AP);
483
484/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
485REG(IPA_IRQ_EN, ipa_irq_en, 0x0000c00c + 0x1000 * GSI_EE_AP);
486
487/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
488REG(IPA_IRQ_CLR, ipa_irq_clr, 0x0000c010 + 0x1000 * GSI_EE_AP);
489
490static const u32 reg_ipa_irq_uc_fmask[] = {
491 [UC_INTR] = BIT(0),
492 /* Bits 1-31 reserved */
493};
494
495REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000c01c + 0x1000 * GSI_EE_AP);
496
497/* Valid bits defined by ipa->available */
498
499REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
500 0x0000c030 + 0x1000 * GSI_EE_AP, 0x0004);
501
502/* Valid bits defined by ipa->available */
503
504REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
505 0x0000c050 + 0x1000 * GSI_EE_AP, 0x0004);
506
507/* Valid bits defined by ipa->available */
508
509REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
510 0x0000c070 + 0x1000 * GSI_EE_AP, 0x0004);
511
512static const struct reg *reg_array[] = {
513 [COMP_CFG] = ®_comp_cfg,
514 [CLKON_CFG] = ®_clkon_cfg,
515 [ROUTE] = ®_route,
516 [SHARED_MEM_SIZE] = ®_shared_mem_size,
517 [QSB_MAX_WRITES] = ®_qsb_max_writes,
518 [QSB_MAX_READS] = ®_qsb_max_reads,
519 [FILT_ROUT_CACHE_FLUSH] = ®_filt_rout_cache_flush,
520 [STATE_AGGR_ACTIVE] = ®_state_aggr_active,
521 [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt,
522 [AGGR_FORCE_CLOSE] = ®_aggr_force_close,
523 [IPA_TX_CFG] = ®_ipa_tx_cfg,
524 [FLAVOR_0] = ®_flavor_0,
525 [IDLE_INDICATION_CFG] = ®_idle_indication_cfg,
526 [QTIME_TIMESTAMP_CFG] = ®_qtime_timestamp_cfg,
527 [TIMERS_XO_CLK_DIV_CFG] = ®_timers_xo_clk_div_cfg,
528 [TIMERS_PULSE_GRAN_CFG] = ®_timers_pulse_gran_cfg,
529 [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type,
530 [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type,
531 [SRC_RSRC_GRP_45_RSRC_TYPE] = ®_src_rsrc_grp_45_rsrc_type,
532 [SRC_RSRC_GRP_67_RSRC_TYPE] = ®_src_rsrc_grp_67_rsrc_type,
533 [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type,
534 [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type,
535 [DST_RSRC_GRP_45_RSRC_TYPE] = ®_dst_rsrc_grp_45_rsrc_type,
536 [DST_RSRC_GRP_67_RSRC_TYPE] = ®_dst_rsrc_grp_67_rsrc_type,
537 [ENDP_INIT_CFG] = ®_endp_init_cfg,
538 [ENDP_INIT_NAT] = ®_endp_init_nat,
539 [ENDP_INIT_HDR] = ®_endp_init_hdr,
540 [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext,
541 [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask,
542 [ENDP_INIT_MODE] = ®_endp_init_mode,
543 [ENDP_INIT_AGGR] = ®_endp_init_aggr,
544 [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en,
545 [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer,
546 [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr,
547 [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp,
548 [ENDP_INIT_SEQ] = ®_endp_init_seq,
549 [ENDP_STATUS] = ®_endp_status,
550 [ENDP_FILTER_CACHE_CFG] = ®_endp_filter_cache_cfg,
551 [ENDP_ROUTER_CACHE_CFG] = ®_endp_router_cache_cfg,
552 [IPA_IRQ_STTS] = ®_ipa_irq_stts,
553 [IPA_IRQ_EN] = ®_ipa_irq_en,
554 [IPA_IRQ_CLR] = ®_ipa_irq_clr,
555 [IPA_IRQ_UC] = ®_ipa_irq_uc,
556 [IRQ_SUSPEND_INFO] = ®_irq_suspend_info,
557 [IRQ_SUSPEND_EN] = ®_irq_suspend_en,
558 [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr,
559};
560
561const struct regs ipa_regs_v5_0 = {
562 .reg_count = ARRAY_SIZE(reg_array),
563 .reg = reg_array,
564};