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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
4 * Ethernet adapters. Based on earlier sk98lin, e100 and
5 * FreeBSD if_sk drivers.
6 *
7 * This driver intentionally does not support all the features
8 * of the original driver such as link fail-over and link management because
9 * those should be done at higher levels.
10 *
11 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 */
13
14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16#include <linux/in.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/netdevice.h>
21#include <linux/etherdevice.h>
22#include <linux/ethtool.h>
23#include <linux/pci.h>
24#include <linux/if_vlan.h>
25#include <linux/ip.h>
26#include <linux/delay.h>
27#include <linux/crc32.h>
28#include <linux/dma-mapping.h>
29#include <linux/debugfs.h>
30#include <linux/sched.h>
31#include <linux/seq_file.h>
32#include <linux/mii.h>
33#include <linux/slab.h>
34#include <linux/dmi.h>
35#include <linux/prefetch.h>
36#include <asm/irq.h>
37
38#include "skge.h"
39
40#define DRV_NAME "skge"
41#define DRV_VERSION "1.14"
42
43#define DEFAULT_TX_RING_SIZE 128
44#define DEFAULT_RX_RING_SIZE 512
45#define MAX_TX_RING_SIZE 1024
46#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
47#define MAX_RX_RING_SIZE 4096
48#define RX_COPY_THRESHOLD 128
49#define RX_BUF_SIZE 1536
50#define PHY_RETRIES 1000
51#define ETH_JUMBO_MTU 9000
52#define TX_WATCHDOG (5 * HZ)
53#define BLINK_MS 250
54#define LINK_HZ HZ
55
56#define SKGE_EEPROM_MAGIC 0x9933aabb
57
58
59MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
60MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
61MODULE_LICENSE("GPL");
62MODULE_VERSION(DRV_VERSION);
63
64static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
65 NETIF_MSG_LINK | NETIF_MSG_IFUP |
66 NETIF_MSG_IFDOWN);
67
68static int debug = -1; /* defaults above */
69module_param(debug, int, 0);
70MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
71
72static const struct pci_device_id skge_id_table[] = {
73 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) }, /* 3Com 3C940 */
74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) }, /* 3Com 3C940B */
75#ifdef CONFIG_SKGE_GENESIS
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */
77#endif
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */
79 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* D-Link DGE-530T (rev.B) */
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) }, /* D-Link DGE-530T */
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302) }, /* D-Link DGE-530T Rev C1 */
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, /* Marvell Yukon 88E8001/8003/8010 */
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
84 { PCI_DEVICE(PCI_VENDOR_ID_CNET, 0x434E) }, /* CNet PowerG-2000 */
85 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, 0x1064) }, /* Linksys EG1064 v2 */
86 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, /* Linksys EG1032 v2 */
87 { 0 }
88};
89MODULE_DEVICE_TABLE(pci, skge_id_table);
90
91static int skge_up(struct net_device *dev);
92static int skge_down(struct net_device *dev);
93static void skge_phy_reset(struct skge_port *skge);
94static void skge_tx_clean(struct net_device *dev);
95static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97static void genesis_get_stats(struct skge_port *skge, u64 *data);
98static void yukon_get_stats(struct skge_port *skge, u64 *data);
99static void yukon_init(struct skge_hw *hw, int port);
100static void genesis_mac_init(struct skge_hw *hw, int port);
101static void genesis_link_up(struct skge_port *skge);
102static void skge_set_multicast(struct net_device *dev);
103static irqreturn_t skge_intr(int irq, void *dev_id);
104
105/* Avoid conditionals by using array */
106static const int txqaddr[] = { Q_XA1, Q_XA2 };
107static const int rxqaddr[] = { Q_R1, Q_R2 };
108static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
109static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
110static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
111static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
112
113static inline bool is_genesis(const struct skge_hw *hw)
114{
115#ifdef CONFIG_SKGE_GENESIS
116 return hw->chip_id == CHIP_ID_GENESIS;
117#else
118 return false;
119#endif
120}
121
122static int skge_get_regs_len(struct net_device *dev)
123{
124 return 0x4000;
125}
126
127/*
128 * Returns copy of whole control register region
129 * Note: skip RAM address register because accessing it will
130 * cause bus hangs!
131 */
132static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
133 void *p)
134{
135 const struct skge_port *skge = netdev_priv(dev);
136 const void __iomem *io = skge->hw->regs;
137
138 regs->version = 1;
139 memset(p, 0, regs->len);
140 memcpy_fromio(p, io, B3_RAM_ADDR);
141
142 if (regs->len > B3_RI_WTO_R1) {
143 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
144 regs->len - B3_RI_WTO_R1);
145 }
146}
147
148/* Wake on Lan only supported on Yukon chips with rev 1 or above */
149static u32 wol_supported(const struct skge_hw *hw)
150{
151 if (is_genesis(hw))
152 return 0;
153
154 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
155 return 0;
156
157 return WAKE_MAGIC | WAKE_PHY;
158}
159
160static void skge_wol_init(struct skge_port *skge)
161{
162 struct skge_hw *hw = skge->hw;
163 int port = skge->port;
164 u16 ctrl;
165
166 skge_write16(hw, B0_CTST, CS_RST_CLR);
167 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
168
169 /* Turn on Vaux */
170 skge_write8(hw, B0_POWER_CTRL,
171 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
172
173 /* WA code for COMA mode -- clear PHY reset */
174 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
175 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
176 u32 reg = skge_read32(hw, B2_GP_IO);
177 reg |= GP_DIR_9;
178 reg &= ~GP_IO_9;
179 skge_write32(hw, B2_GP_IO, reg);
180 }
181
182 skge_write32(hw, SK_REG(port, GPHY_CTRL),
183 GPC_DIS_SLEEP |
184 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
185 GPC_ANEG_1 | GPC_RST_SET);
186
187 skge_write32(hw, SK_REG(port, GPHY_CTRL),
188 GPC_DIS_SLEEP |
189 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
190 GPC_ANEG_1 | GPC_RST_CLR);
191
192 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
193
194 /* Force to 10/100 skge_reset will re-enable on resume */
195 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
196 (PHY_AN_100FULL | PHY_AN_100HALF |
197 PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA));
198 /* no 1000 HD/FD */
199 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
200 gm_phy_write(hw, port, PHY_MARV_CTRL,
201 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
202 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
203
204
205 /* Set GMAC to no flow control and auto update for speed/duplex */
206 gma_write16(hw, port, GM_GP_CTRL,
207 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
208 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
209
210 /* Set WOL address */
211 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
212 skge->netdev->dev_addr, ETH_ALEN);
213
214 /* Turn on appropriate WOL control bits */
215 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
216 ctrl = 0;
217 if (skge->wol & WAKE_PHY)
218 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
219 else
220 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
221
222 if (skge->wol & WAKE_MAGIC)
223 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
224 else
225 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
226
227 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
228 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
229
230 /* block receiver */
231 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
232}
233
234static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
235{
236 struct skge_port *skge = netdev_priv(dev);
237
238 wol->supported = wol_supported(skge->hw);
239 wol->wolopts = skge->wol;
240}
241
242static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
243{
244 struct skge_port *skge = netdev_priv(dev);
245 struct skge_hw *hw = skge->hw;
246
247 if ((wol->wolopts & ~wol_supported(hw)) ||
248 !device_can_wakeup(&hw->pdev->dev))
249 return -EOPNOTSUPP;
250
251 skge->wol = wol->wolopts;
252
253 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
254
255 return 0;
256}
257
258/* Determine supported/advertised modes based on hardware.
259 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
260 */
261static u32 skge_supported_modes(const struct skge_hw *hw)
262{
263 u32 supported;
264
265 if (hw->copper) {
266 supported = (SUPPORTED_10baseT_Half |
267 SUPPORTED_10baseT_Full |
268 SUPPORTED_100baseT_Half |
269 SUPPORTED_100baseT_Full |
270 SUPPORTED_1000baseT_Half |
271 SUPPORTED_1000baseT_Full |
272 SUPPORTED_Autoneg |
273 SUPPORTED_TP);
274
275 if (is_genesis(hw))
276 supported &= ~(SUPPORTED_10baseT_Half |
277 SUPPORTED_10baseT_Full |
278 SUPPORTED_100baseT_Half |
279 SUPPORTED_100baseT_Full);
280
281 else if (hw->chip_id == CHIP_ID_YUKON)
282 supported &= ~SUPPORTED_1000baseT_Half;
283 } else
284 supported = (SUPPORTED_1000baseT_Full |
285 SUPPORTED_1000baseT_Half |
286 SUPPORTED_FIBRE |
287 SUPPORTED_Autoneg);
288
289 return supported;
290}
291
292static int skge_get_link_ksettings(struct net_device *dev,
293 struct ethtool_link_ksettings *cmd)
294{
295 struct skge_port *skge = netdev_priv(dev);
296 struct skge_hw *hw = skge->hw;
297 u32 supported, advertising;
298
299 supported = skge_supported_modes(hw);
300
301 if (hw->copper) {
302 cmd->base.port = PORT_TP;
303 cmd->base.phy_address = hw->phy_addr;
304 } else
305 cmd->base.port = PORT_FIBRE;
306
307 advertising = skge->advertising;
308 cmd->base.autoneg = skge->autoneg;
309 cmd->base.speed = skge->speed;
310 cmd->base.duplex = skge->duplex;
311
312 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
313 supported);
314 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
315 advertising);
316
317 return 0;
318}
319
320static int skge_set_link_ksettings(struct net_device *dev,
321 const struct ethtool_link_ksettings *cmd)
322{
323 struct skge_port *skge = netdev_priv(dev);
324 const struct skge_hw *hw = skge->hw;
325 u32 supported = skge_supported_modes(hw);
326 int err = 0;
327 u32 advertising;
328
329 ethtool_convert_link_mode_to_legacy_u32(&advertising,
330 cmd->link_modes.advertising);
331
332 if (cmd->base.autoneg == AUTONEG_ENABLE) {
333 advertising = supported;
334 skge->duplex = -1;
335 skge->speed = -1;
336 } else {
337 u32 setting;
338 u32 speed = cmd->base.speed;
339
340 switch (speed) {
341 case SPEED_1000:
342 if (cmd->base.duplex == DUPLEX_FULL)
343 setting = SUPPORTED_1000baseT_Full;
344 else if (cmd->base.duplex == DUPLEX_HALF)
345 setting = SUPPORTED_1000baseT_Half;
346 else
347 return -EINVAL;
348 break;
349 case SPEED_100:
350 if (cmd->base.duplex == DUPLEX_FULL)
351 setting = SUPPORTED_100baseT_Full;
352 else if (cmd->base.duplex == DUPLEX_HALF)
353 setting = SUPPORTED_100baseT_Half;
354 else
355 return -EINVAL;
356 break;
357
358 case SPEED_10:
359 if (cmd->base.duplex == DUPLEX_FULL)
360 setting = SUPPORTED_10baseT_Full;
361 else if (cmd->base.duplex == DUPLEX_HALF)
362 setting = SUPPORTED_10baseT_Half;
363 else
364 return -EINVAL;
365 break;
366 default:
367 return -EINVAL;
368 }
369
370 if ((setting & supported) == 0)
371 return -EINVAL;
372
373 skge->speed = speed;
374 skge->duplex = cmd->base.duplex;
375 }
376
377 skge->autoneg = cmd->base.autoneg;
378 skge->advertising = advertising;
379
380 if (netif_running(dev)) {
381 skge_down(dev);
382 err = skge_up(dev);
383 if (err) {
384 dev_close(dev);
385 return err;
386 }
387 }
388
389 return 0;
390}
391
392static void skge_get_drvinfo(struct net_device *dev,
393 struct ethtool_drvinfo *info)
394{
395 struct skge_port *skge = netdev_priv(dev);
396
397 strscpy(info->driver, DRV_NAME, sizeof(info->driver));
398 strscpy(info->version, DRV_VERSION, sizeof(info->version));
399 strscpy(info->bus_info, pci_name(skge->hw->pdev),
400 sizeof(info->bus_info));
401}
402
403static const struct skge_stat {
404 char name[ETH_GSTRING_LEN];
405 u16 xmac_offset;
406 u16 gma_offset;
407} skge_stats[] = {
408 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
409 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
410
411 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
412 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
413 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
414 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
415 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
416 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
417 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
418 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
419
420 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
421 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
422 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
423 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
424 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
425 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
426
427 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
428 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
429 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
430 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
431 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
432};
433
434static int skge_get_sset_count(struct net_device *dev, int sset)
435{
436 switch (sset) {
437 case ETH_SS_STATS:
438 return ARRAY_SIZE(skge_stats);
439 default:
440 return -EOPNOTSUPP;
441 }
442}
443
444static void skge_get_ethtool_stats(struct net_device *dev,
445 struct ethtool_stats *stats, u64 *data)
446{
447 struct skge_port *skge = netdev_priv(dev);
448
449 if (is_genesis(skge->hw))
450 genesis_get_stats(skge, data);
451 else
452 yukon_get_stats(skge, data);
453}
454
455/* Use hardware MIB variables for critical path statistics and
456 * transmit feedback not reported at interrupt.
457 * Other errors are accounted for in interrupt handler.
458 */
459static struct net_device_stats *skge_get_stats(struct net_device *dev)
460{
461 struct skge_port *skge = netdev_priv(dev);
462 u64 data[ARRAY_SIZE(skge_stats)];
463
464 if (is_genesis(skge->hw))
465 genesis_get_stats(skge, data);
466 else
467 yukon_get_stats(skge, data);
468
469 dev->stats.tx_bytes = data[0];
470 dev->stats.rx_bytes = data[1];
471 dev->stats.tx_packets = data[2] + data[4] + data[6];
472 dev->stats.rx_packets = data[3] + data[5] + data[7];
473 dev->stats.multicast = data[3] + data[5];
474 dev->stats.collisions = data[10];
475 dev->stats.tx_aborted_errors = data[12];
476
477 return &dev->stats;
478}
479
480static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
481{
482 int i;
483
484 switch (stringset) {
485 case ETH_SS_STATS:
486 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
487 memcpy(data + i * ETH_GSTRING_LEN,
488 skge_stats[i].name, ETH_GSTRING_LEN);
489 break;
490 }
491}
492
493static void skge_get_ring_param(struct net_device *dev,
494 struct ethtool_ringparam *p,
495 struct kernel_ethtool_ringparam *kernel_p,
496 struct netlink_ext_ack *extack)
497{
498 struct skge_port *skge = netdev_priv(dev);
499
500 p->rx_max_pending = MAX_RX_RING_SIZE;
501 p->tx_max_pending = MAX_TX_RING_SIZE;
502
503 p->rx_pending = skge->rx_ring.count;
504 p->tx_pending = skge->tx_ring.count;
505}
506
507static int skge_set_ring_param(struct net_device *dev,
508 struct ethtool_ringparam *p,
509 struct kernel_ethtool_ringparam *kernel_p,
510 struct netlink_ext_ack *extack)
511{
512 struct skge_port *skge = netdev_priv(dev);
513 int err = 0;
514
515 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
516 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
517 return -EINVAL;
518
519 skge->rx_ring.count = p->rx_pending;
520 skge->tx_ring.count = p->tx_pending;
521
522 if (netif_running(dev)) {
523 skge_down(dev);
524 err = skge_up(dev);
525 if (err)
526 dev_close(dev);
527 }
528
529 return err;
530}
531
532static u32 skge_get_msglevel(struct net_device *netdev)
533{
534 struct skge_port *skge = netdev_priv(netdev);
535 return skge->msg_enable;
536}
537
538static void skge_set_msglevel(struct net_device *netdev, u32 value)
539{
540 struct skge_port *skge = netdev_priv(netdev);
541 skge->msg_enable = value;
542}
543
544static int skge_nway_reset(struct net_device *dev)
545{
546 struct skge_port *skge = netdev_priv(dev);
547
548 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
549 return -EINVAL;
550
551 skge_phy_reset(skge);
552 return 0;
553}
554
555static void skge_get_pauseparam(struct net_device *dev,
556 struct ethtool_pauseparam *ecmd)
557{
558 struct skge_port *skge = netdev_priv(dev);
559
560 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
561 (skge->flow_control == FLOW_MODE_SYM_OR_REM));
562 ecmd->tx_pause = (ecmd->rx_pause ||
563 (skge->flow_control == FLOW_MODE_LOC_SEND));
564
565 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
566}
567
568static int skge_set_pauseparam(struct net_device *dev,
569 struct ethtool_pauseparam *ecmd)
570{
571 struct skge_port *skge = netdev_priv(dev);
572 struct ethtool_pauseparam old;
573 int err = 0;
574
575 skge_get_pauseparam(dev, &old);
576
577 if (ecmd->autoneg != old.autoneg)
578 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
579 else {
580 if (ecmd->rx_pause && ecmd->tx_pause)
581 skge->flow_control = FLOW_MODE_SYMMETRIC;
582 else if (ecmd->rx_pause && !ecmd->tx_pause)
583 skge->flow_control = FLOW_MODE_SYM_OR_REM;
584 else if (!ecmd->rx_pause && ecmd->tx_pause)
585 skge->flow_control = FLOW_MODE_LOC_SEND;
586 else
587 skge->flow_control = FLOW_MODE_NONE;
588 }
589
590 if (netif_running(dev)) {
591 skge_down(dev);
592 err = skge_up(dev);
593 if (err) {
594 dev_close(dev);
595 return err;
596 }
597 }
598
599 return 0;
600}
601
602/* Chip internal frequency for clock calculations */
603static inline u32 hwkhz(const struct skge_hw *hw)
604{
605 return is_genesis(hw) ? 53125 : 78125;
606}
607
608/* Chip HZ to microseconds */
609static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
610{
611 return (ticks * 1000) / hwkhz(hw);
612}
613
614/* Microseconds to chip HZ */
615static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
616{
617 return hwkhz(hw) * usec / 1000;
618}
619
620static int skge_get_coalesce(struct net_device *dev,
621 struct ethtool_coalesce *ecmd,
622 struct kernel_ethtool_coalesce *kernel_coal,
623 struct netlink_ext_ack *extack)
624{
625 struct skge_port *skge = netdev_priv(dev);
626 struct skge_hw *hw = skge->hw;
627 int port = skge->port;
628
629 ecmd->rx_coalesce_usecs = 0;
630 ecmd->tx_coalesce_usecs = 0;
631
632 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
633 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
634 u32 msk = skge_read32(hw, B2_IRQM_MSK);
635
636 if (msk & rxirqmask[port])
637 ecmd->rx_coalesce_usecs = delay;
638 if (msk & txirqmask[port])
639 ecmd->tx_coalesce_usecs = delay;
640 }
641
642 return 0;
643}
644
645/* Note: interrupt timer is per board, but can turn on/off per port */
646static int skge_set_coalesce(struct net_device *dev,
647 struct ethtool_coalesce *ecmd,
648 struct kernel_ethtool_coalesce *kernel_coal,
649 struct netlink_ext_ack *extack)
650{
651 struct skge_port *skge = netdev_priv(dev);
652 struct skge_hw *hw = skge->hw;
653 int port = skge->port;
654 u32 msk = skge_read32(hw, B2_IRQM_MSK);
655 u32 delay = 25;
656
657 if (ecmd->rx_coalesce_usecs == 0)
658 msk &= ~rxirqmask[port];
659 else if (ecmd->rx_coalesce_usecs < 25 ||
660 ecmd->rx_coalesce_usecs > 33333)
661 return -EINVAL;
662 else {
663 msk |= rxirqmask[port];
664 delay = ecmd->rx_coalesce_usecs;
665 }
666
667 if (ecmd->tx_coalesce_usecs == 0)
668 msk &= ~txirqmask[port];
669 else if (ecmd->tx_coalesce_usecs < 25 ||
670 ecmd->tx_coalesce_usecs > 33333)
671 return -EINVAL;
672 else {
673 msk |= txirqmask[port];
674 delay = min(delay, ecmd->rx_coalesce_usecs);
675 }
676
677 skge_write32(hw, B2_IRQM_MSK, msk);
678 if (msk == 0)
679 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
680 else {
681 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
682 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
683 }
684 return 0;
685}
686
687enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
688static void skge_led(struct skge_port *skge, enum led_mode mode)
689{
690 struct skge_hw *hw = skge->hw;
691 int port = skge->port;
692
693 spin_lock_bh(&hw->phy_lock);
694 if (is_genesis(hw)) {
695 switch (mode) {
696 case LED_MODE_OFF:
697 if (hw->phy_type == SK_PHY_BCOM)
698 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
699 else {
700 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
701 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
702 }
703 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
704 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
705 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
706 break;
707
708 case LED_MODE_ON:
709 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
710 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
711
712 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
713 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
714
715 break;
716
717 case LED_MODE_TST:
718 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
719 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
720 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
721
722 if (hw->phy_type == SK_PHY_BCOM)
723 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
724 else {
725 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
726 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
727 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
728 }
729
730 }
731 } else {
732 switch (mode) {
733 case LED_MODE_OFF:
734 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
735 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
736 PHY_M_LED_MO_DUP(MO_LED_OFF) |
737 PHY_M_LED_MO_10(MO_LED_OFF) |
738 PHY_M_LED_MO_100(MO_LED_OFF) |
739 PHY_M_LED_MO_1000(MO_LED_OFF) |
740 PHY_M_LED_MO_RX(MO_LED_OFF));
741 break;
742 case LED_MODE_ON:
743 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
744 PHY_M_LED_PULS_DUR(PULS_170MS) |
745 PHY_M_LED_BLINK_RT(BLINK_84MS) |
746 PHY_M_LEDC_TX_CTRL |
747 PHY_M_LEDC_DP_CTRL);
748
749 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
750 PHY_M_LED_MO_RX(MO_LED_OFF) |
751 (skge->speed == SPEED_100 ?
752 PHY_M_LED_MO_100(MO_LED_ON) : 0));
753 break;
754 case LED_MODE_TST:
755 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
756 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
757 PHY_M_LED_MO_DUP(MO_LED_ON) |
758 PHY_M_LED_MO_10(MO_LED_ON) |
759 PHY_M_LED_MO_100(MO_LED_ON) |
760 PHY_M_LED_MO_1000(MO_LED_ON) |
761 PHY_M_LED_MO_RX(MO_LED_ON));
762 }
763 }
764 spin_unlock_bh(&hw->phy_lock);
765}
766
767/* blink LED's for finding board */
768static int skge_set_phys_id(struct net_device *dev,
769 enum ethtool_phys_id_state state)
770{
771 struct skge_port *skge = netdev_priv(dev);
772
773 switch (state) {
774 case ETHTOOL_ID_ACTIVE:
775 return 2; /* cycle on/off twice per second */
776
777 case ETHTOOL_ID_ON:
778 skge_led(skge, LED_MODE_TST);
779 break;
780
781 case ETHTOOL_ID_OFF:
782 skge_led(skge, LED_MODE_OFF);
783 break;
784
785 case ETHTOOL_ID_INACTIVE:
786 /* back to regular LED state */
787 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
788 }
789
790 return 0;
791}
792
793static int skge_get_eeprom_len(struct net_device *dev)
794{
795 struct skge_port *skge = netdev_priv(dev);
796 u32 reg2;
797
798 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2);
799 return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
800}
801
802static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
803{
804 u32 val;
805
806 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
807
808 do {
809 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
810 } while (!(offset & PCI_VPD_ADDR_F));
811
812 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
813 return val;
814}
815
816static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
817{
818 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
819 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
820 offset | PCI_VPD_ADDR_F);
821
822 do {
823 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
824 } while (offset & PCI_VPD_ADDR_F);
825}
826
827static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
828 u8 *data)
829{
830 struct skge_port *skge = netdev_priv(dev);
831 struct pci_dev *pdev = skge->hw->pdev;
832 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
833 int length = eeprom->len;
834 u16 offset = eeprom->offset;
835
836 if (!cap)
837 return -EINVAL;
838
839 eeprom->magic = SKGE_EEPROM_MAGIC;
840
841 while (length > 0) {
842 u32 val = skge_vpd_read(pdev, cap, offset);
843 int n = min_t(int, length, sizeof(val));
844
845 memcpy(data, &val, n);
846 length -= n;
847 data += n;
848 offset += n;
849 }
850 return 0;
851}
852
853static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
854 u8 *data)
855{
856 struct skge_port *skge = netdev_priv(dev);
857 struct pci_dev *pdev = skge->hw->pdev;
858 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
859 int length = eeprom->len;
860 u16 offset = eeprom->offset;
861
862 if (!cap)
863 return -EINVAL;
864
865 if (eeprom->magic != SKGE_EEPROM_MAGIC)
866 return -EINVAL;
867
868 while (length > 0) {
869 u32 val;
870 int n = min_t(int, length, sizeof(val));
871
872 if (n < sizeof(val))
873 val = skge_vpd_read(pdev, cap, offset);
874 memcpy(&val, data, n);
875
876 skge_vpd_write(pdev, cap, offset, val);
877
878 length -= n;
879 data += n;
880 offset += n;
881 }
882 return 0;
883}
884
885static const struct ethtool_ops skge_ethtool_ops = {
886 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
887 .get_drvinfo = skge_get_drvinfo,
888 .get_regs_len = skge_get_regs_len,
889 .get_regs = skge_get_regs,
890 .get_wol = skge_get_wol,
891 .set_wol = skge_set_wol,
892 .get_msglevel = skge_get_msglevel,
893 .set_msglevel = skge_set_msglevel,
894 .nway_reset = skge_nway_reset,
895 .get_link = ethtool_op_get_link,
896 .get_eeprom_len = skge_get_eeprom_len,
897 .get_eeprom = skge_get_eeprom,
898 .set_eeprom = skge_set_eeprom,
899 .get_ringparam = skge_get_ring_param,
900 .set_ringparam = skge_set_ring_param,
901 .get_pauseparam = skge_get_pauseparam,
902 .set_pauseparam = skge_set_pauseparam,
903 .get_coalesce = skge_get_coalesce,
904 .set_coalesce = skge_set_coalesce,
905 .get_strings = skge_get_strings,
906 .set_phys_id = skge_set_phys_id,
907 .get_sset_count = skge_get_sset_count,
908 .get_ethtool_stats = skge_get_ethtool_stats,
909 .get_link_ksettings = skge_get_link_ksettings,
910 .set_link_ksettings = skge_set_link_ksettings,
911};
912
913/*
914 * Allocate ring elements and chain them together
915 * One-to-one association of board descriptors with ring elements
916 */
917static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
918{
919 struct skge_tx_desc *d;
920 struct skge_element *e;
921 int i;
922
923 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
924 if (!ring->start)
925 return -ENOMEM;
926
927 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
928 e->desc = d;
929 if (i == ring->count - 1) {
930 e->next = ring->start;
931 d->next_offset = base;
932 } else {
933 e->next = e + 1;
934 d->next_offset = base + (i+1) * sizeof(*d);
935 }
936 }
937 ring->to_use = ring->to_clean = ring->start;
938
939 return 0;
940}
941
942/* Allocate and setup a new buffer for receiving */
943static int skge_rx_setup(struct skge_port *skge, struct skge_element *e,
944 struct sk_buff *skb, unsigned int bufsize)
945{
946 struct skge_rx_desc *rd = e->desc;
947 dma_addr_t map;
948
949 map = dma_map_single(&skge->hw->pdev->dev, skb->data, bufsize,
950 DMA_FROM_DEVICE);
951
952 if (dma_mapping_error(&skge->hw->pdev->dev, map))
953 return -1;
954
955 rd->dma_lo = lower_32_bits(map);
956 rd->dma_hi = upper_32_bits(map);
957 e->skb = skb;
958 rd->csum1_start = ETH_HLEN;
959 rd->csum2_start = ETH_HLEN;
960 rd->csum1 = 0;
961 rd->csum2 = 0;
962
963 wmb();
964
965 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
966 dma_unmap_addr_set(e, mapaddr, map);
967 dma_unmap_len_set(e, maplen, bufsize);
968 return 0;
969}
970
971/* Resume receiving using existing skb,
972 * Note: DMA address is not changed by chip.
973 * MTU not changed while receiver active.
974 */
975static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
976{
977 struct skge_rx_desc *rd = e->desc;
978
979 rd->csum2 = 0;
980 rd->csum2_start = ETH_HLEN;
981
982 wmb();
983
984 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
985}
986
987
988/* Free all buffers in receive ring, assumes receiver stopped */
989static void skge_rx_clean(struct skge_port *skge)
990{
991 struct skge_hw *hw = skge->hw;
992 struct skge_ring *ring = &skge->rx_ring;
993 struct skge_element *e;
994
995 e = ring->start;
996 do {
997 struct skge_rx_desc *rd = e->desc;
998 rd->control = 0;
999 if (e->skb) {
1000 dma_unmap_single(&hw->pdev->dev,
1001 dma_unmap_addr(e, mapaddr),
1002 dma_unmap_len(e, maplen),
1003 DMA_FROM_DEVICE);
1004 dev_kfree_skb(e->skb);
1005 e->skb = NULL;
1006 }
1007 } while ((e = e->next) != ring->start);
1008}
1009
1010
1011/* Allocate buffers for receive ring
1012 * For receive: to_clean is next received frame.
1013 */
1014static int skge_rx_fill(struct net_device *dev)
1015{
1016 struct skge_port *skge = netdev_priv(dev);
1017 struct skge_ring *ring = &skge->rx_ring;
1018 struct skge_element *e;
1019
1020 e = ring->start;
1021 do {
1022 struct sk_buff *skb;
1023
1024 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1025 GFP_KERNEL);
1026 if (!skb)
1027 return -ENOMEM;
1028
1029 skb_reserve(skb, NET_IP_ALIGN);
1030 if (skge_rx_setup(skge, e, skb, skge->rx_buf_size) < 0) {
1031 dev_kfree_skb(skb);
1032 return -EIO;
1033 }
1034 } while ((e = e->next) != ring->start);
1035
1036 ring->to_clean = ring->start;
1037 return 0;
1038}
1039
1040static const char *skge_pause(enum pause_status status)
1041{
1042 switch (status) {
1043 case FLOW_STAT_NONE:
1044 return "none";
1045 case FLOW_STAT_REM_SEND:
1046 return "rx only";
1047 case FLOW_STAT_LOC_SEND:
1048 return "tx_only";
1049 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1050 return "both";
1051 default:
1052 return "indeterminated";
1053 }
1054}
1055
1056
1057static void skge_link_up(struct skge_port *skge)
1058{
1059 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1060 LED_BLK_OFF|LED_SYNC_OFF|LED_REG_ON);
1061
1062 netif_carrier_on(skge->netdev);
1063 netif_wake_queue(skge->netdev);
1064
1065 netif_info(skge, link, skge->netdev,
1066 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1067 skge->speed,
1068 skge->duplex == DUPLEX_FULL ? "full" : "half",
1069 skge_pause(skge->flow_status));
1070}
1071
1072static void skge_link_down(struct skge_port *skge)
1073{
1074 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
1075 netif_carrier_off(skge->netdev);
1076 netif_stop_queue(skge->netdev);
1077
1078 netif_info(skge, link, skge->netdev, "Link is down\n");
1079}
1080
1081static void xm_link_down(struct skge_hw *hw, int port)
1082{
1083 struct net_device *dev = hw->dev[port];
1084 struct skge_port *skge = netdev_priv(dev);
1085
1086 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1087
1088 if (netif_carrier_ok(dev))
1089 skge_link_down(skge);
1090}
1091
1092static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1093{
1094 int i;
1095
1096 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1097 *val = xm_read16(hw, port, XM_PHY_DATA);
1098
1099 if (hw->phy_type == SK_PHY_XMAC)
1100 goto ready;
1101
1102 for (i = 0; i < PHY_RETRIES; i++) {
1103 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1104 goto ready;
1105 udelay(1);
1106 }
1107
1108 return -ETIMEDOUT;
1109 ready:
1110 *val = xm_read16(hw, port, XM_PHY_DATA);
1111
1112 return 0;
1113}
1114
1115static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1116{
1117 u16 v = 0;
1118 if (__xm_phy_read(hw, port, reg, &v))
1119 pr_warn("%s: phy read timed out\n", hw->dev[port]->name);
1120 return v;
1121}
1122
1123static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1124{
1125 int i;
1126
1127 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1128 for (i = 0; i < PHY_RETRIES; i++) {
1129 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1130 goto ready;
1131 udelay(1);
1132 }
1133 return -EIO;
1134
1135 ready:
1136 xm_write16(hw, port, XM_PHY_DATA, val);
1137 for (i = 0; i < PHY_RETRIES; i++) {
1138 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1139 return 0;
1140 udelay(1);
1141 }
1142 return -ETIMEDOUT;
1143}
1144
1145static void genesis_init(struct skge_hw *hw)
1146{
1147 /* set blink source counter */
1148 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1149 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1150
1151 /* configure mac arbiter */
1152 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1153
1154 /* configure mac arbiter timeout values */
1155 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1156 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1157 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1158 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1159
1160 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1161 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1162 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1163 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1164
1165 /* configure packet arbiter timeout */
1166 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1167 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1168 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1169 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1170 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1171}
1172
1173static void genesis_reset(struct skge_hw *hw, int port)
1174{
1175 static const u8 zero[8] = { 0 };
1176 u32 reg;
1177
1178 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1179
1180 /* reset the statistics module */
1181 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1182 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1183 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1184 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1185 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1186
1187 /* disable Broadcom PHY IRQ */
1188 if (hw->phy_type == SK_PHY_BCOM)
1189 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1190
1191 xm_outhash(hw, port, XM_HSM, zero);
1192
1193 /* Flush TX and RX fifo */
1194 reg = xm_read32(hw, port, XM_MODE);
1195 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1196 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1197}
1198
1199/* Convert mode to MII values */
1200static const u16 phy_pause_map[] = {
1201 [FLOW_MODE_NONE] = 0,
1202 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1203 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1204 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1205};
1206
1207/* special defines for FIBER (88E1011S only) */
1208static const u16 fiber_pause_map[] = {
1209 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1210 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1211 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1212 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1213};
1214
1215
1216/* Check status of Broadcom phy link */
1217static void bcom_check_link(struct skge_hw *hw, int port)
1218{
1219 struct net_device *dev = hw->dev[port];
1220 struct skge_port *skge = netdev_priv(dev);
1221 u16 status;
1222
1223 /* read twice because of latch */
1224 xm_phy_read(hw, port, PHY_BCOM_STAT);
1225 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1226
1227 if ((status & PHY_ST_LSYNC) == 0) {
1228 xm_link_down(hw, port);
1229 return;
1230 }
1231
1232 if (skge->autoneg == AUTONEG_ENABLE) {
1233 u16 lpa, aux;
1234
1235 if (!(status & PHY_ST_AN_OVER))
1236 return;
1237
1238 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1239 if (lpa & PHY_B_AN_RF) {
1240 netdev_notice(dev, "remote fault\n");
1241 return;
1242 }
1243
1244 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1245
1246 /* Check Duplex mismatch */
1247 switch (aux & PHY_B_AS_AN_RES_MSK) {
1248 case PHY_B_RES_1000FD:
1249 skge->duplex = DUPLEX_FULL;
1250 break;
1251 case PHY_B_RES_1000HD:
1252 skge->duplex = DUPLEX_HALF;
1253 break;
1254 default:
1255 netdev_notice(dev, "duplex mismatch\n");
1256 return;
1257 }
1258
1259 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1260 switch (aux & PHY_B_AS_PAUSE_MSK) {
1261 case PHY_B_AS_PAUSE_MSK:
1262 skge->flow_status = FLOW_STAT_SYMMETRIC;
1263 break;
1264 case PHY_B_AS_PRR:
1265 skge->flow_status = FLOW_STAT_REM_SEND;
1266 break;
1267 case PHY_B_AS_PRT:
1268 skge->flow_status = FLOW_STAT_LOC_SEND;
1269 break;
1270 default:
1271 skge->flow_status = FLOW_STAT_NONE;
1272 }
1273 skge->speed = SPEED_1000;
1274 }
1275
1276 if (!netif_carrier_ok(dev))
1277 genesis_link_up(skge);
1278}
1279
1280/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1281 * Phy on for 100 or 10Mbit operation
1282 */
1283static void bcom_phy_init(struct skge_port *skge)
1284{
1285 struct skge_hw *hw = skge->hw;
1286 int port = skge->port;
1287 int i;
1288 u16 id1, r, ext, ctl;
1289
1290 /* magic workaround patterns for Broadcom */
1291 static const struct {
1292 u16 reg;
1293 u16 val;
1294 } A1hack[] = {
1295 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1296 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1297 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1298 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1299 }, C0hack[] = {
1300 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1301 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1302 };
1303
1304 /* read Id from external PHY (all have the same address) */
1305 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1306
1307 /* Optimize MDIO transfer by suppressing preamble. */
1308 r = xm_read16(hw, port, XM_MMU_CMD);
1309 r |= XM_MMU_NO_PRE;
1310 xm_write16(hw, port, XM_MMU_CMD, r);
1311
1312 switch (id1) {
1313 case PHY_BCOM_ID1_C0:
1314 /*
1315 * Workaround BCOM Errata for the C0 type.
1316 * Write magic patterns to reserved registers.
1317 */
1318 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1319 xm_phy_write(hw, port,
1320 C0hack[i].reg, C0hack[i].val);
1321
1322 break;
1323 case PHY_BCOM_ID1_A1:
1324 /*
1325 * Workaround BCOM Errata for the A1 type.
1326 * Write magic patterns to reserved registers.
1327 */
1328 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1329 xm_phy_write(hw, port,
1330 A1hack[i].reg, A1hack[i].val);
1331 break;
1332 }
1333
1334 /*
1335 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1336 * Disable Power Management after reset.
1337 */
1338 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1339 r |= PHY_B_AC_DIS_PM;
1340 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1341
1342 /* Dummy read */
1343 xm_read16(hw, port, XM_ISRC);
1344
1345 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1346 ctl = PHY_CT_SP1000; /* always 1000mbit */
1347
1348 if (skge->autoneg == AUTONEG_ENABLE) {
1349 /*
1350 * Workaround BCOM Errata #1 for the C5 type.
1351 * 1000Base-T Link Acquisition Failure in Slave Mode
1352 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1353 */
1354 u16 adv = PHY_B_1000C_RD;
1355 if (skge->advertising & ADVERTISED_1000baseT_Half)
1356 adv |= PHY_B_1000C_AHD;
1357 if (skge->advertising & ADVERTISED_1000baseT_Full)
1358 adv |= PHY_B_1000C_AFD;
1359 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1360
1361 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1362 } else {
1363 if (skge->duplex == DUPLEX_FULL)
1364 ctl |= PHY_CT_DUP_MD;
1365 /* Force to slave */
1366 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1367 }
1368
1369 /* Set autonegotiation pause parameters */
1370 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1371 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1372
1373 /* Handle Jumbo frames */
1374 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1375 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1376 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1377
1378 ext |= PHY_B_PEC_HIGH_LA;
1379
1380 }
1381
1382 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1383 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1384
1385 /* Use link status change interrupt */
1386 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1387}
1388
1389static void xm_phy_init(struct skge_port *skge)
1390{
1391 struct skge_hw *hw = skge->hw;
1392 int port = skge->port;
1393 u16 ctrl = 0;
1394
1395 if (skge->autoneg == AUTONEG_ENABLE) {
1396 if (skge->advertising & ADVERTISED_1000baseT_Half)
1397 ctrl |= PHY_X_AN_HD;
1398 if (skge->advertising & ADVERTISED_1000baseT_Full)
1399 ctrl |= PHY_X_AN_FD;
1400
1401 ctrl |= fiber_pause_map[skge->flow_control];
1402
1403 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1404
1405 /* Restart Auto-negotiation */
1406 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1407 } else {
1408 /* Set DuplexMode in Config register */
1409 if (skge->duplex == DUPLEX_FULL)
1410 ctrl |= PHY_CT_DUP_MD;
1411 /*
1412 * Do NOT enable Auto-negotiation here. This would hold
1413 * the link down because no IDLEs are transmitted
1414 */
1415 }
1416
1417 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1418
1419 /* Poll PHY for status changes */
1420 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1421}
1422
1423static int xm_check_link(struct net_device *dev)
1424{
1425 struct skge_port *skge = netdev_priv(dev);
1426 struct skge_hw *hw = skge->hw;
1427 int port = skge->port;
1428 u16 status;
1429
1430 /* read twice because of latch */
1431 xm_phy_read(hw, port, PHY_XMAC_STAT);
1432 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1433
1434 if ((status & PHY_ST_LSYNC) == 0) {
1435 xm_link_down(hw, port);
1436 return 0;
1437 }
1438
1439 if (skge->autoneg == AUTONEG_ENABLE) {
1440 u16 lpa, res;
1441
1442 if (!(status & PHY_ST_AN_OVER))
1443 return 0;
1444
1445 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1446 if (lpa & PHY_B_AN_RF) {
1447 netdev_notice(dev, "remote fault\n");
1448 return 0;
1449 }
1450
1451 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1452
1453 /* Check Duplex mismatch */
1454 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1455 case PHY_X_RS_FD:
1456 skge->duplex = DUPLEX_FULL;
1457 break;
1458 case PHY_X_RS_HD:
1459 skge->duplex = DUPLEX_HALF;
1460 break;
1461 default:
1462 netdev_notice(dev, "duplex mismatch\n");
1463 return 0;
1464 }
1465
1466 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1467 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1468 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1469 (lpa & PHY_X_P_SYM_MD))
1470 skge->flow_status = FLOW_STAT_SYMMETRIC;
1471 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1472 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1473 /* Enable PAUSE receive, disable PAUSE transmit */
1474 skge->flow_status = FLOW_STAT_REM_SEND;
1475 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1476 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1477 /* Disable PAUSE receive, enable PAUSE transmit */
1478 skge->flow_status = FLOW_STAT_LOC_SEND;
1479 else
1480 skge->flow_status = FLOW_STAT_NONE;
1481
1482 skge->speed = SPEED_1000;
1483 }
1484
1485 if (!netif_carrier_ok(dev))
1486 genesis_link_up(skge);
1487 return 1;
1488}
1489
1490/* Poll to check for link coming up.
1491 *
1492 * Since internal PHY is wired to a level triggered pin, can't
1493 * get an interrupt when carrier is detected, need to poll for
1494 * link coming up.
1495 */
1496static void xm_link_timer(struct timer_list *t)
1497{
1498 struct skge_port *skge = from_timer(skge, t, link_timer);
1499 struct net_device *dev = skge->netdev;
1500 struct skge_hw *hw = skge->hw;
1501 int port = skge->port;
1502 int i;
1503 unsigned long flags;
1504
1505 if (!netif_running(dev))
1506 return;
1507
1508 spin_lock_irqsave(&hw->phy_lock, flags);
1509
1510 /*
1511 * Verify that the link by checking GPIO register three times.
1512 * This pin has the signal from the link_sync pin connected to it.
1513 */
1514 for (i = 0; i < 3; i++) {
1515 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1516 goto link_down;
1517 }
1518
1519 /* Re-enable interrupt to detect link down */
1520 if (xm_check_link(dev)) {
1521 u16 msk = xm_read16(hw, port, XM_IMSK);
1522 msk &= ~XM_IS_INP_ASS;
1523 xm_write16(hw, port, XM_IMSK, msk);
1524 xm_read16(hw, port, XM_ISRC);
1525 } else {
1526link_down:
1527 mod_timer(&skge->link_timer,
1528 round_jiffies(jiffies + LINK_HZ));
1529 }
1530 spin_unlock_irqrestore(&hw->phy_lock, flags);
1531}
1532
1533static void genesis_mac_init(struct skge_hw *hw, int port)
1534{
1535 struct net_device *dev = hw->dev[port];
1536 struct skge_port *skge = netdev_priv(dev);
1537 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1538 int i;
1539 u32 r;
1540 static const u8 zero[6] = { 0 };
1541
1542 for (i = 0; i < 10; i++) {
1543 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1544 MFF_SET_MAC_RST);
1545 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1546 goto reset_ok;
1547 udelay(1);
1548 }
1549
1550 netdev_warn(dev, "genesis reset failed\n");
1551
1552 reset_ok:
1553 /* Unreset the XMAC. */
1554 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1555
1556 /*
1557 * Perform additional initialization for external PHYs,
1558 * namely for the 1000baseTX cards that use the XMAC's
1559 * GMII mode.
1560 */
1561 if (hw->phy_type != SK_PHY_XMAC) {
1562 /* Take external Phy out of reset */
1563 r = skge_read32(hw, B2_GP_IO);
1564 if (port == 0)
1565 r |= GP_DIR_0|GP_IO_0;
1566 else
1567 r |= GP_DIR_2|GP_IO_2;
1568
1569 skge_write32(hw, B2_GP_IO, r);
1570
1571 /* Enable GMII interface */
1572 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1573 }
1574
1575
1576 switch (hw->phy_type) {
1577 case SK_PHY_XMAC:
1578 xm_phy_init(skge);
1579 break;
1580 case SK_PHY_BCOM:
1581 bcom_phy_init(skge);
1582 bcom_check_link(hw, port);
1583 }
1584
1585 /* Set Station Address */
1586 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1587
1588 /* We don't use match addresses so clear */
1589 for (i = 1; i < 16; i++)
1590 xm_outaddr(hw, port, XM_EXM(i), zero);
1591
1592 /* Clear MIB counters */
1593 xm_write16(hw, port, XM_STAT_CMD,
1594 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1595 /* Clear two times according to Errata #3 */
1596 xm_write16(hw, port, XM_STAT_CMD,
1597 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1598
1599 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1600 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1601
1602 /* We don't need the FCS appended to the packet. */
1603 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1604 if (jumbo)
1605 r |= XM_RX_BIG_PK_OK;
1606
1607 if (skge->duplex == DUPLEX_HALF) {
1608 /*
1609 * If in manual half duplex mode the other side might be in
1610 * full duplex mode, so ignore if a carrier extension is not seen
1611 * on frames received
1612 */
1613 r |= XM_RX_DIS_CEXT;
1614 }
1615 xm_write16(hw, port, XM_RX_CMD, r);
1616
1617 /* We want short frames padded to 60 bytes. */
1618 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1619
1620 /* Increase threshold for jumbo frames on dual port */
1621 if (hw->ports > 1 && jumbo)
1622 xm_write16(hw, port, XM_TX_THR, 1020);
1623 else
1624 xm_write16(hw, port, XM_TX_THR, 512);
1625
1626 /*
1627 * Enable the reception of all error frames. This is
1628 * a necessary evil due to the design of the XMAC. The
1629 * XMAC's receive FIFO is only 8K in size, however jumbo
1630 * frames can be up to 9000 bytes in length. When bad
1631 * frame filtering is enabled, the XMAC's RX FIFO operates
1632 * in 'store and forward' mode. For this to work, the
1633 * entire frame has to fit into the FIFO, but that means
1634 * that jumbo frames larger than 8192 bytes will be
1635 * truncated. Disabling all bad frame filtering causes
1636 * the RX FIFO to operate in streaming mode, in which
1637 * case the XMAC will start transferring frames out of the
1638 * RX FIFO as soon as the FIFO threshold is reached.
1639 */
1640 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1641
1642
1643 /*
1644 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1645 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1646 * and 'Octets Rx OK Hi Cnt Ov'.
1647 */
1648 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1649
1650 /*
1651 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1652 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1653 * and 'Octets Tx OK Hi Cnt Ov'.
1654 */
1655 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1656
1657 /* Configure MAC arbiter */
1658 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1659
1660 /* configure timeout values */
1661 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1662 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1663 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1664 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1665
1666 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1667 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1668 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1669 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1670
1671 /* Configure Rx MAC FIFO */
1672 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1673 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1674 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1675
1676 /* Configure Tx MAC FIFO */
1677 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1678 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1679 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1680
1681 if (jumbo) {
1682 /* Enable frame flushing if jumbo frames used */
1683 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
1684 } else {
1685 /* enable timeout timers if normal frames */
1686 skge_write16(hw, B3_PA_CTRL,
1687 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1688 }
1689}
1690
1691static void genesis_stop(struct skge_port *skge)
1692{
1693 struct skge_hw *hw = skge->hw;
1694 int port = skge->port;
1695 unsigned retries = 1000;
1696 u16 cmd;
1697
1698 /* Disable Tx and Rx */
1699 cmd = xm_read16(hw, port, XM_MMU_CMD);
1700 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1701 xm_write16(hw, port, XM_MMU_CMD, cmd);
1702
1703 genesis_reset(hw, port);
1704
1705 /* Clear Tx packet arbiter timeout IRQ */
1706 skge_write16(hw, B3_PA_CTRL,
1707 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1708
1709 /* Reset the MAC */
1710 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1711 do {
1712 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1713 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1714 break;
1715 } while (--retries > 0);
1716
1717 /* For external PHYs there must be special handling */
1718 if (hw->phy_type != SK_PHY_XMAC) {
1719 u32 reg = skge_read32(hw, B2_GP_IO);
1720 if (port == 0) {
1721 reg |= GP_DIR_0;
1722 reg &= ~GP_IO_0;
1723 } else {
1724 reg |= GP_DIR_2;
1725 reg &= ~GP_IO_2;
1726 }
1727 skge_write32(hw, B2_GP_IO, reg);
1728 skge_read32(hw, B2_GP_IO);
1729 }
1730
1731 xm_write16(hw, port, XM_MMU_CMD,
1732 xm_read16(hw, port, XM_MMU_CMD)
1733 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1734
1735 xm_read16(hw, port, XM_MMU_CMD);
1736}
1737
1738
1739static void genesis_get_stats(struct skge_port *skge, u64 *data)
1740{
1741 struct skge_hw *hw = skge->hw;
1742 int port = skge->port;
1743 int i;
1744 unsigned long timeout = jiffies + HZ;
1745
1746 xm_write16(hw, port,
1747 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1748
1749 /* wait for update to complete */
1750 while (xm_read16(hw, port, XM_STAT_CMD)
1751 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1752 if (time_after(jiffies, timeout))
1753 break;
1754 udelay(10);
1755 }
1756
1757 /* special case for 64 bit octet counter */
1758 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1759 | xm_read32(hw, port, XM_TXO_OK_LO);
1760 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1761 | xm_read32(hw, port, XM_RXO_OK_LO);
1762
1763 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1764 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1765}
1766
1767static void genesis_mac_intr(struct skge_hw *hw, int port)
1768{
1769 struct net_device *dev = hw->dev[port];
1770 struct skge_port *skge = netdev_priv(dev);
1771 u16 status = xm_read16(hw, port, XM_ISRC);
1772
1773 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1774 "mac interrupt status 0x%x\n", status);
1775
1776 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1777 xm_link_down(hw, port);
1778 mod_timer(&skge->link_timer, jiffies + 1);
1779 }
1780
1781 if (status & XM_IS_TXF_UR) {
1782 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1783 ++dev->stats.tx_fifo_errors;
1784 }
1785}
1786
1787static void genesis_link_up(struct skge_port *skge)
1788{
1789 struct skge_hw *hw = skge->hw;
1790 int port = skge->port;
1791 u16 cmd, msk;
1792 u32 mode;
1793
1794 cmd = xm_read16(hw, port, XM_MMU_CMD);
1795
1796 /*
1797 * enabling pause frame reception is required for 1000BT
1798 * because the XMAC is not reset if the link is going down
1799 */
1800 if (skge->flow_status == FLOW_STAT_NONE ||
1801 skge->flow_status == FLOW_STAT_LOC_SEND)
1802 /* Disable Pause Frame Reception */
1803 cmd |= XM_MMU_IGN_PF;
1804 else
1805 /* Enable Pause Frame Reception */
1806 cmd &= ~XM_MMU_IGN_PF;
1807
1808 xm_write16(hw, port, XM_MMU_CMD, cmd);
1809
1810 mode = xm_read32(hw, port, XM_MODE);
1811 if (skge->flow_status == FLOW_STAT_SYMMETRIC ||
1812 skge->flow_status == FLOW_STAT_LOC_SEND) {
1813 /*
1814 * Configure Pause Frame Generation
1815 * Use internal and external Pause Frame Generation.
1816 * Sending pause frames is edge triggered.
1817 * Send a Pause frame with the maximum pause time if
1818 * internal oder external FIFO full condition occurs.
1819 * Send a zero pause time frame to re-start transmission.
1820 */
1821 /* XM_PAUSE_DA = '010000C28001' (default) */
1822 /* XM_MAC_PTIME = 0xffff (maximum) */
1823 /* remember this value is defined in big endian (!) */
1824 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1825
1826 mode |= XM_PAUSE_MODE;
1827 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1828 } else {
1829 /*
1830 * disable pause frame generation is required for 1000BT
1831 * because the XMAC is not reset if the link is going down
1832 */
1833 /* Disable Pause Mode in Mode Register */
1834 mode &= ~XM_PAUSE_MODE;
1835
1836 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1837 }
1838
1839 xm_write32(hw, port, XM_MODE, mode);
1840
1841 /* Turn on detection of Tx underrun */
1842 msk = xm_read16(hw, port, XM_IMSK);
1843 msk &= ~XM_IS_TXF_UR;
1844 xm_write16(hw, port, XM_IMSK, msk);
1845
1846 xm_read16(hw, port, XM_ISRC);
1847
1848 /* get MMU Command Reg. */
1849 cmd = xm_read16(hw, port, XM_MMU_CMD);
1850 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1851 cmd |= XM_MMU_GMII_FD;
1852
1853 /*
1854 * Workaround BCOM Errata (#10523) for all BCom Phys
1855 * Enable Power Management after link up
1856 */
1857 if (hw->phy_type == SK_PHY_BCOM) {
1858 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1859 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1860 & ~PHY_B_AC_DIS_PM);
1861 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1862 }
1863
1864 /* enable Rx/Tx */
1865 xm_write16(hw, port, XM_MMU_CMD,
1866 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1867 skge_link_up(skge);
1868}
1869
1870
1871static inline void bcom_phy_intr(struct skge_port *skge)
1872{
1873 struct skge_hw *hw = skge->hw;
1874 int port = skge->port;
1875 u16 isrc;
1876
1877 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1878 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1879 "phy interrupt status 0x%x\n", isrc);
1880
1881 if (isrc & PHY_B_IS_PSE)
1882 pr_err("%s: uncorrectable pair swap error\n",
1883 hw->dev[port]->name);
1884
1885 /* Workaround BCom Errata:
1886 * enable and disable loopback mode if "NO HCD" occurs.
1887 */
1888 if (isrc & PHY_B_IS_NO_HDCL) {
1889 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1890 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1891 ctrl | PHY_CT_LOOP);
1892 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1893 ctrl & ~PHY_CT_LOOP);
1894 }
1895
1896 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1897 bcom_check_link(hw, port);
1898
1899}
1900
1901static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1902{
1903 int i;
1904
1905 gma_write16(hw, port, GM_SMI_DATA, val);
1906 gma_write16(hw, port, GM_SMI_CTRL,
1907 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1908 for (i = 0; i < PHY_RETRIES; i++) {
1909 udelay(1);
1910
1911 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1912 return 0;
1913 }
1914
1915 pr_warn("%s: phy write timeout\n", hw->dev[port]->name);
1916 return -EIO;
1917}
1918
1919static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1920{
1921 int i;
1922
1923 gma_write16(hw, port, GM_SMI_CTRL,
1924 GM_SMI_CT_PHY_AD(hw->phy_addr)
1925 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1926
1927 for (i = 0; i < PHY_RETRIES; i++) {
1928 udelay(1);
1929 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1930 goto ready;
1931 }
1932
1933 return -ETIMEDOUT;
1934 ready:
1935 *val = gma_read16(hw, port, GM_SMI_DATA);
1936 return 0;
1937}
1938
1939static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1940{
1941 u16 v = 0;
1942 if (__gm_phy_read(hw, port, reg, &v))
1943 pr_warn("%s: phy read timeout\n", hw->dev[port]->name);
1944 return v;
1945}
1946
1947/* Marvell Phy Initialization */
1948static void yukon_init(struct skge_hw *hw, int port)
1949{
1950 struct skge_port *skge = netdev_priv(hw->dev[port]);
1951 u16 ctrl, ct1000, adv;
1952
1953 if (skge->autoneg == AUTONEG_ENABLE) {
1954 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1955
1956 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1957 PHY_M_EC_MAC_S_MSK);
1958 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1959
1960 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1961
1962 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1963 }
1964
1965 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1966 if (skge->autoneg == AUTONEG_DISABLE)
1967 ctrl &= ~PHY_CT_ANE;
1968
1969 ctrl |= PHY_CT_RESET;
1970 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1971
1972 ctrl = 0;
1973 ct1000 = 0;
1974 adv = PHY_AN_CSMA;
1975
1976 if (skge->autoneg == AUTONEG_ENABLE) {
1977 if (hw->copper) {
1978 if (skge->advertising & ADVERTISED_1000baseT_Full)
1979 ct1000 |= PHY_M_1000C_AFD;
1980 if (skge->advertising & ADVERTISED_1000baseT_Half)
1981 ct1000 |= PHY_M_1000C_AHD;
1982 if (skge->advertising & ADVERTISED_100baseT_Full)
1983 adv |= PHY_M_AN_100_FD;
1984 if (skge->advertising & ADVERTISED_100baseT_Half)
1985 adv |= PHY_M_AN_100_HD;
1986 if (skge->advertising & ADVERTISED_10baseT_Full)
1987 adv |= PHY_M_AN_10_FD;
1988 if (skge->advertising & ADVERTISED_10baseT_Half)
1989 adv |= PHY_M_AN_10_HD;
1990
1991 /* Set Flow-control capabilities */
1992 adv |= phy_pause_map[skge->flow_control];
1993 } else {
1994 if (skge->advertising & ADVERTISED_1000baseT_Full)
1995 adv |= PHY_M_AN_1000X_AFD;
1996 if (skge->advertising & ADVERTISED_1000baseT_Half)
1997 adv |= PHY_M_AN_1000X_AHD;
1998
1999 adv |= fiber_pause_map[skge->flow_control];
2000 }
2001
2002 /* Restart Auto-negotiation */
2003 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
2004 } else {
2005 /* forced speed/duplex settings */
2006 ct1000 = PHY_M_1000C_MSE;
2007
2008 if (skge->duplex == DUPLEX_FULL)
2009 ctrl |= PHY_CT_DUP_MD;
2010
2011 switch (skge->speed) {
2012 case SPEED_1000:
2013 ctrl |= PHY_CT_SP1000;
2014 break;
2015 case SPEED_100:
2016 ctrl |= PHY_CT_SP100;
2017 break;
2018 }
2019
2020 ctrl |= PHY_CT_RESET;
2021 }
2022
2023 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2024
2025 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2026 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2027
2028 /* Enable phy interrupt on autonegotiation complete (or link up) */
2029 if (skge->autoneg == AUTONEG_ENABLE)
2030 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2031 else
2032 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2033}
2034
2035static void yukon_reset(struct skge_hw *hw, int port)
2036{
2037 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2038 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2039 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2040 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2041 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2042
2043 gma_write16(hw, port, GM_RX_CTRL,
2044 gma_read16(hw, port, GM_RX_CTRL)
2045 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2046}
2047
2048/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2049static int is_yukon_lite_a0(struct skge_hw *hw)
2050{
2051 u32 reg;
2052 int ret;
2053
2054 if (hw->chip_id != CHIP_ID_YUKON)
2055 return 0;
2056
2057 reg = skge_read32(hw, B2_FAR);
2058 skge_write8(hw, B2_FAR + 3, 0xff);
2059 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2060 skge_write32(hw, B2_FAR, reg);
2061 return ret;
2062}
2063
2064static void yukon_mac_init(struct skge_hw *hw, int port)
2065{
2066 struct skge_port *skge = netdev_priv(hw->dev[port]);
2067 int i;
2068 u32 reg;
2069 const u8 *addr = hw->dev[port]->dev_addr;
2070
2071 /* WA code for COMA mode -- set PHY reset */
2072 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2073 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2074 reg = skge_read32(hw, B2_GP_IO);
2075 reg |= GP_DIR_9 | GP_IO_9;
2076 skge_write32(hw, B2_GP_IO, reg);
2077 }
2078
2079 /* hard reset */
2080 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2081 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2082
2083 /* WA code for COMA mode -- clear PHY reset */
2084 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2085 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2086 reg = skge_read32(hw, B2_GP_IO);
2087 reg |= GP_DIR_9;
2088 reg &= ~GP_IO_9;
2089 skge_write32(hw, B2_GP_IO, reg);
2090 }
2091
2092 /* Set hardware config mode */
2093 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2094 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2095 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2096
2097 /* Clear GMC reset */
2098 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2099 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2100 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2101
2102 if (skge->autoneg == AUTONEG_DISABLE) {
2103 reg = GM_GPCR_AU_ALL_DIS;
2104 gma_write16(hw, port, GM_GP_CTRL,
2105 gma_read16(hw, port, GM_GP_CTRL) | reg);
2106
2107 switch (skge->speed) {
2108 case SPEED_1000:
2109 reg &= ~GM_GPCR_SPEED_100;
2110 reg |= GM_GPCR_SPEED_1000;
2111 break;
2112 case SPEED_100:
2113 reg &= ~GM_GPCR_SPEED_1000;
2114 reg |= GM_GPCR_SPEED_100;
2115 break;
2116 case SPEED_10:
2117 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2118 break;
2119 }
2120
2121 if (skge->duplex == DUPLEX_FULL)
2122 reg |= GM_GPCR_DUP_FULL;
2123 } else
2124 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2125
2126 switch (skge->flow_control) {
2127 case FLOW_MODE_NONE:
2128 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2129 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2130 break;
2131 case FLOW_MODE_LOC_SEND:
2132 /* disable Rx flow-control */
2133 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2134 break;
2135 case FLOW_MODE_SYMMETRIC:
2136 case FLOW_MODE_SYM_OR_REM:
2137 /* enable Tx & Rx flow-control */
2138 break;
2139 }
2140
2141 gma_write16(hw, port, GM_GP_CTRL, reg);
2142 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2143
2144 yukon_init(hw, port);
2145
2146 /* MIB clear */
2147 reg = gma_read16(hw, port, GM_PHY_ADDR);
2148 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2149
2150 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2151 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2152 gma_write16(hw, port, GM_PHY_ADDR, reg);
2153
2154 /* transmit control */
2155 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2156
2157 /* receive control reg: unicast + multicast + no FCS */
2158 gma_write16(hw, port, GM_RX_CTRL,
2159 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2160
2161 /* transmit flow control */
2162 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2163
2164 /* transmit parameter */
2165 gma_write16(hw, port, GM_TX_PARAM,
2166 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2167 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2168 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2169
2170 /* configure the Serial Mode Register */
2171 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2172 | GM_SMOD_VLAN_ENA
2173 | IPG_DATA_VAL(IPG_DATA_DEF);
2174
2175 if (hw->dev[port]->mtu > ETH_DATA_LEN)
2176 reg |= GM_SMOD_JUMBO_ENA;
2177
2178 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2179
2180 /* physical address: used for pause frames */
2181 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2182 /* virtual address for data */
2183 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2184
2185 /* enable interrupt mask for counter overflows */
2186 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2187 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2188 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2189
2190 /* Initialize Mac Fifo */
2191
2192 /* Configure Rx MAC FIFO */
2193 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2194 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2195
2196 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2197 if (is_yukon_lite_a0(hw))
2198 reg &= ~GMF_RX_F_FL_ON;
2199
2200 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2201 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2202 /*
2203 * because Pause Packet Truncation in GMAC is not working
2204 * we have to increase the Flush Threshold to 64 bytes
2205 * in order to flush pause packets in Rx FIFO on Yukon-1
2206 */
2207 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2208
2209 /* Configure Tx MAC FIFO */
2210 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2211 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2212}
2213
2214/* Go into power down mode */
2215static void yukon_suspend(struct skge_hw *hw, int port)
2216{
2217 u16 ctrl;
2218
2219 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2220 ctrl |= PHY_M_PC_POL_R_DIS;
2221 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2222
2223 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2224 ctrl |= PHY_CT_RESET;
2225 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2226
2227 /* switch IEEE compatible power down mode on */
2228 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2229 ctrl |= PHY_CT_PDOWN;
2230 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2231}
2232
2233static void yukon_stop(struct skge_port *skge)
2234{
2235 struct skge_hw *hw = skge->hw;
2236 int port = skge->port;
2237
2238 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2239 yukon_reset(hw, port);
2240
2241 gma_write16(hw, port, GM_GP_CTRL,
2242 gma_read16(hw, port, GM_GP_CTRL)
2243 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2244 gma_read16(hw, port, GM_GP_CTRL);
2245
2246 yukon_suspend(hw, port);
2247
2248 /* set GPHY Control reset */
2249 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2250 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2251}
2252
2253static void yukon_get_stats(struct skge_port *skge, u64 *data)
2254{
2255 struct skge_hw *hw = skge->hw;
2256 int port = skge->port;
2257 int i;
2258
2259 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2260 | gma_read32(hw, port, GM_TXO_OK_LO);
2261 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2262 | gma_read32(hw, port, GM_RXO_OK_LO);
2263
2264 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2265 data[i] = gma_read32(hw, port,
2266 skge_stats[i].gma_offset);
2267}
2268
2269static void yukon_mac_intr(struct skge_hw *hw, int port)
2270{
2271 struct net_device *dev = hw->dev[port];
2272 struct skge_port *skge = netdev_priv(dev);
2273 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2274
2275 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2276 "mac interrupt status 0x%x\n", status);
2277
2278 if (status & GM_IS_RX_FF_OR) {
2279 ++dev->stats.rx_fifo_errors;
2280 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2281 }
2282
2283 if (status & GM_IS_TX_FF_UR) {
2284 ++dev->stats.tx_fifo_errors;
2285 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2286 }
2287
2288}
2289
2290static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2291{
2292 switch (aux & PHY_M_PS_SPEED_MSK) {
2293 case PHY_M_PS_SPEED_1000:
2294 return SPEED_1000;
2295 case PHY_M_PS_SPEED_100:
2296 return SPEED_100;
2297 default:
2298 return SPEED_10;
2299 }
2300}
2301
2302static void yukon_link_up(struct skge_port *skge)
2303{
2304 struct skge_hw *hw = skge->hw;
2305 int port = skge->port;
2306 u16 reg;
2307
2308 /* Enable Transmit FIFO Underrun */
2309 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2310
2311 reg = gma_read16(hw, port, GM_GP_CTRL);
2312 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2313 reg |= GM_GPCR_DUP_FULL;
2314
2315 /* enable Rx/Tx */
2316 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2317 gma_write16(hw, port, GM_GP_CTRL, reg);
2318
2319 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2320 skge_link_up(skge);
2321}
2322
2323static void yukon_link_down(struct skge_port *skge)
2324{
2325 struct skge_hw *hw = skge->hw;
2326 int port = skge->port;
2327 u16 ctrl;
2328
2329 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2330 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2331 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2332
2333 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2334 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2335 ctrl |= PHY_M_AN_ASP;
2336 /* restore Asymmetric Pause bit */
2337 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2338 }
2339
2340 skge_link_down(skge);
2341
2342 yukon_init(hw, port);
2343}
2344
2345static void yukon_phy_intr(struct skge_port *skge)
2346{
2347 struct skge_hw *hw = skge->hw;
2348 int port = skge->port;
2349 const char *reason = NULL;
2350 u16 istatus, phystat;
2351
2352 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2353 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2354
2355 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2356 "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
2357
2358 if (istatus & PHY_M_IS_AN_COMPL) {
2359 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2360 & PHY_M_AN_RF) {
2361 reason = "remote fault";
2362 goto failed;
2363 }
2364
2365 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2366 reason = "master/slave fault";
2367 goto failed;
2368 }
2369
2370 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2371 reason = "speed/duplex";
2372 goto failed;
2373 }
2374
2375 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2376 ? DUPLEX_FULL : DUPLEX_HALF;
2377 skge->speed = yukon_speed(hw, phystat);
2378
2379 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2380 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2381 case PHY_M_PS_PAUSE_MSK:
2382 skge->flow_status = FLOW_STAT_SYMMETRIC;
2383 break;
2384 case PHY_M_PS_RX_P_EN:
2385 skge->flow_status = FLOW_STAT_REM_SEND;
2386 break;
2387 case PHY_M_PS_TX_P_EN:
2388 skge->flow_status = FLOW_STAT_LOC_SEND;
2389 break;
2390 default:
2391 skge->flow_status = FLOW_STAT_NONE;
2392 }
2393
2394 if (skge->flow_status == FLOW_STAT_NONE ||
2395 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2396 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2397 else
2398 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2399 yukon_link_up(skge);
2400 return;
2401 }
2402
2403 if (istatus & PHY_M_IS_LSP_CHANGE)
2404 skge->speed = yukon_speed(hw, phystat);
2405
2406 if (istatus & PHY_M_IS_DUP_CHANGE)
2407 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2408 if (istatus & PHY_M_IS_LST_CHANGE) {
2409 if (phystat & PHY_M_PS_LINK_UP)
2410 yukon_link_up(skge);
2411 else
2412 yukon_link_down(skge);
2413 }
2414 return;
2415 failed:
2416 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason);
2417
2418 /* XXX restart autonegotiation? */
2419}
2420
2421static void skge_phy_reset(struct skge_port *skge)
2422{
2423 struct skge_hw *hw = skge->hw;
2424 int port = skge->port;
2425 struct net_device *dev = hw->dev[port];
2426
2427 netif_stop_queue(skge->netdev);
2428 netif_carrier_off(skge->netdev);
2429
2430 spin_lock_bh(&hw->phy_lock);
2431 if (is_genesis(hw)) {
2432 genesis_reset(hw, port);
2433 genesis_mac_init(hw, port);
2434 } else {
2435 yukon_reset(hw, port);
2436 yukon_init(hw, port);
2437 }
2438 spin_unlock_bh(&hw->phy_lock);
2439
2440 skge_set_multicast(dev);
2441}
2442
2443/* Basic MII support */
2444static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2445{
2446 struct mii_ioctl_data *data = if_mii(ifr);
2447 struct skge_port *skge = netdev_priv(dev);
2448 struct skge_hw *hw = skge->hw;
2449 int err = -EOPNOTSUPP;
2450
2451 if (!netif_running(dev))
2452 return -ENODEV; /* Phy still in reset */
2453
2454 switch (cmd) {
2455 case SIOCGMIIPHY:
2456 data->phy_id = hw->phy_addr;
2457
2458 fallthrough;
2459 case SIOCGMIIREG: {
2460 u16 val = 0;
2461 spin_lock_bh(&hw->phy_lock);
2462
2463 if (is_genesis(hw))
2464 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2465 else
2466 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2467 spin_unlock_bh(&hw->phy_lock);
2468 data->val_out = val;
2469 break;
2470 }
2471
2472 case SIOCSMIIREG:
2473 spin_lock_bh(&hw->phy_lock);
2474 if (is_genesis(hw))
2475 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2476 data->val_in);
2477 else
2478 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2479 data->val_in);
2480 spin_unlock_bh(&hw->phy_lock);
2481 break;
2482 }
2483 return err;
2484}
2485
2486static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2487{
2488 u32 end;
2489
2490 start /= 8;
2491 len /= 8;
2492 end = start + len - 1;
2493
2494 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2495 skge_write32(hw, RB_ADDR(q, RB_START), start);
2496 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2497 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2498 skge_write32(hw, RB_ADDR(q, RB_END), end);
2499
2500 if (q == Q_R1 || q == Q_R2) {
2501 /* Set thresholds on receive queue's */
2502 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2503 start + (2*len)/3);
2504 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2505 start + (len/3));
2506 } else {
2507 /* Enable store & forward on Tx queue's because
2508 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2509 */
2510 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2511 }
2512
2513 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2514}
2515
2516/* Setup Bus Memory Interface */
2517static void skge_qset(struct skge_port *skge, u16 q,
2518 const struct skge_element *e)
2519{
2520 struct skge_hw *hw = skge->hw;
2521 u32 watermark = 0x600;
2522 u64 base = skge->dma + (e->desc - skge->mem);
2523
2524 /* optimization to reduce window on 32bit/33mhz */
2525 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2526 watermark /= 2;
2527
2528 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2529 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2530 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2531 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2532}
2533
2534static int skge_up(struct net_device *dev)
2535{
2536 struct skge_port *skge = netdev_priv(dev);
2537 struct skge_hw *hw = skge->hw;
2538 int port = skge->port;
2539 u32 chunk, ram_addr;
2540 size_t rx_size, tx_size;
2541 int err;
2542
2543 if (!is_valid_ether_addr(dev->dev_addr))
2544 return -EINVAL;
2545
2546 netif_info(skge, ifup, skge->netdev, "enabling interface\n");
2547
2548 if (dev->mtu > RX_BUF_SIZE)
2549 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2550 else
2551 skge->rx_buf_size = RX_BUF_SIZE;
2552
2553
2554 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2555 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2556 skge->mem_size = tx_size + rx_size;
2557 skge->mem = dma_alloc_coherent(&hw->pdev->dev, skge->mem_size,
2558 &skge->dma, GFP_KERNEL);
2559 if (!skge->mem)
2560 return -ENOMEM;
2561
2562 BUG_ON(skge->dma & 7);
2563
2564 if (upper_32_bits(skge->dma) != upper_32_bits(skge->dma + skge->mem_size)) {
2565 dev_err(&hw->pdev->dev, "dma_alloc_coherent region crosses 4G boundary\n");
2566 err = -EINVAL;
2567 goto free_pci_mem;
2568 }
2569
2570 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2571 if (err)
2572 goto free_pci_mem;
2573
2574 err = skge_rx_fill(dev);
2575 if (err)
2576 goto free_rx_ring;
2577
2578 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2579 skge->dma + rx_size);
2580 if (err)
2581 goto free_rx_ring;
2582
2583 if (hw->ports == 1) {
2584 err = request_irq(hw->pdev->irq, skge_intr, IRQF_SHARED,
2585 dev->name, hw);
2586 if (err) {
2587 netdev_err(dev, "Unable to allocate interrupt %d error: %d\n",
2588 hw->pdev->irq, err);
2589 goto free_tx_ring;
2590 }
2591 }
2592
2593 /* Initialize MAC */
2594 netif_carrier_off(dev);
2595 spin_lock_bh(&hw->phy_lock);
2596 if (is_genesis(hw))
2597 genesis_mac_init(hw, port);
2598 else
2599 yukon_mac_init(hw, port);
2600 spin_unlock_bh(&hw->phy_lock);
2601
2602 /* Configure RAMbuffers - equally between ports and tx/rx */
2603 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
2604 ram_addr = hw->ram_offset + 2 * chunk * port;
2605
2606 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2607 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2608
2609 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2610 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2611 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2612
2613 /* Start receiver BMU */
2614 wmb();
2615 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2616 skge_led(skge, LED_MODE_ON);
2617
2618 spin_lock_irq(&hw->hw_lock);
2619 hw->intr_mask |= portmask[port];
2620 skge_write32(hw, B0_IMSK, hw->intr_mask);
2621 skge_read32(hw, B0_IMSK);
2622 spin_unlock_irq(&hw->hw_lock);
2623
2624 napi_enable(&skge->napi);
2625
2626 skge_set_multicast(dev);
2627
2628 return 0;
2629
2630 free_tx_ring:
2631 kfree(skge->tx_ring.start);
2632 free_rx_ring:
2633 skge_rx_clean(skge);
2634 kfree(skge->rx_ring.start);
2635 free_pci_mem:
2636 dma_free_coherent(&hw->pdev->dev, skge->mem_size, skge->mem,
2637 skge->dma);
2638 skge->mem = NULL;
2639
2640 return err;
2641}
2642
2643/* stop receiver */
2644static void skge_rx_stop(struct skge_hw *hw, int port)
2645{
2646 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2647 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2648 RB_RST_SET|RB_DIS_OP_MD);
2649 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2650}
2651
2652static int skge_down(struct net_device *dev)
2653{
2654 struct skge_port *skge = netdev_priv(dev);
2655 struct skge_hw *hw = skge->hw;
2656 int port = skge->port;
2657
2658 if (!skge->mem)
2659 return 0;
2660
2661 netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
2662
2663 netif_tx_disable(dev);
2664
2665 if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)
2666 del_timer_sync(&skge->link_timer);
2667
2668 napi_disable(&skge->napi);
2669 netif_carrier_off(dev);
2670
2671 spin_lock_irq(&hw->hw_lock);
2672 hw->intr_mask &= ~portmask[port];
2673 skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask);
2674 skge_read32(hw, B0_IMSK);
2675 spin_unlock_irq(&hw->hw_lock);
2676
2677 if (hw->ports == 1)
2678 free_irq(hw->pdev->irq, hw);
2679
2680 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
2681 if (is_genesis(hw))
2682 genesis_stop(skge);
2683 else
2684 yukon_stop(skge);
2685
2686 /* Stop transmitter */
2687 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2688 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2689 RB_RST_SET|RB_DIS_OP_MD);
2690
2691
2692 /* Disable Force Sync bit and Enable Alloc bit */
2693 skge_write8(hw, SK_REG(port, TXA_CTRL),
2694 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2695
2696 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2697 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2698 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2699
2700 /* Reset PCI FIFO */
2701 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2702 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2703
2704 /* Reset the RAM Buffer async Tx queue */
2705 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2706
2707 skge_rx_stop(hw, port);
2708
2709 if (is_genesis(hw)) {
2710 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2711 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2712 } else {
2713 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2714 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2715 }
2716
2717 skge_led(skge, LED_MODE_OFF);
2718
2719 netif_tx_lock_bh(dev);
2720 skge_tx_clean(dev);
2721 netif_tx_unlock_bh(dev);
2722
2723 skge_rx_clean(skge);
2724
2725 kfree(skge->rx_ring.start);
2726 kfree(skge->tx_ring.start);
2727 dma_free_coherent(&hw->pdev->dev, skge->mem_size, skge->mem,
2728 skge->dma);
2729 skge->mem = NULL;
2730 return 0;
2731}
2732
2733static inline int skge_avail(const struct skge_ring *ring)
2734{
2735 smp_mb();
2736 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2737 + (ring->to_clean - ring->to_use) - 1;
2738}
2739
2740static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2741 struct net_device *dev)
2742{
2743 struct skge_port *skge = netdev_priv(dev);
2744 struct skge_hw *hw = skge->hw;
2745 struct skge_element *e;
2746 struct skge_tx_desc *td;
2747 int i;
2748 u32 control, len;
2749 dma_addr_t map;
2750
2751 if (skb_padto(skb, ETH_ZLEN))
2752 return NETDEV_TX_OK;
2753
2754 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2755 return NETDEV_TX_BUSY;
2756
2757 e = skge->tx_ring.to_use;
2758 td = e->desc;
2759 BUG_ON(td->control & BMU_OWN);
2760 e->skb = skb;
2761 len = skb_headlen(skb);
2762 map = dma_map_single(&hw->pdev->dev, skb->data, len, DMA_TO_DEVICE);
2763 if (dma_mapping_error(&hw->pdev->dev, map))
2764 goto mapping_error;
2765
2766 dma_unmap_addr_set(e, mapaddr, map);
2767 dma_unmap_len_set(e, maplen, len);
2768
2769 td->dma_lo = lower_32_bits(map);
2770 td->dma_hi = upper_32_bits(map);
2771
2772 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2773 const int offset = skb_checksum_start_offset(skb);
2774
2775 /* This seems backwards, but it is what the sk98lin
2776 * does. Looks like hardware is wrong?
2777 */
2778 if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
2779 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2780 control = BMU_TCP_CHECK;
2781 else
2782 control = BMU_UDP_CHECK;
2783
2784 td->csum_offs = 0;
2785 td->csum_start = offset;
2786 td->csum_write = offset + skb->csum_offset;
2787 } else
2788 control = BMU_CHECK;
2789
2790 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2791 control |= BMU_EOF | BMU_IRQ_EOF;
2792 else {
2793 struct skge_tx_desc *tf = td;
2794
2795 control |= BMU_STFWD;
2796 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2797 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2798
2799 map = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
2800 skb_frag_size(frag), DMA_TO_DEVICE);
2801 if (dma_mapping_error(&hw->pdev->dev, map))
2802 goto mapping_unwind;
2803
2804 e = e->next;
2805 e->skb = skb;
2806 tf = e->desc;
2807 BUG_ON(tf->control & BMU_OWN);
2808
2809 tf->dma_lo = lower_32_bits(map);
2810 tf->dma_hi = upper_32_bits(map);
2811 dma_unmap_addr_set(e, mapaddr, map);
2812 dma_unmap_len_set(e, maplen, skb_frag_size(frag));
2813
2814 tf->control = BMU_OWN | BMU_SW | control | skb_frag_size(frag);
2815 }
2816 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2817 }
2818 /* Make sure all the descriptors written */
2819 wmb();
2820 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2821 wmb();
2822
2823 netdev_sent_queue(dev, skb->len);
2824
2825 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2826
2827 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
2828 "tx queued, slot %td, len %d\n",
2829 e - skge->tx_ring.start, skb->len);
2830
2831 skge->tx_ring.to_use = e->next;
2832 smp_wmb();
2833
2834 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2835 netdev_dbg(dev, "transmit queue full\n");
2836 netif_stop_queue(dev);
2837 }
2838
2839 return NETDEV_TX_OK;
2840
2841mapping_unwind:
2842 e = skge->tx_ring.to_use;
2843 dma_unmap_single(&hw->pdev->dev, dma_unmap_addr(e, mapaddr),
2844 dma_unmap_len(e, maplen), DMA_TO_DEVICE);
2845 while (i-- > 0) {
2846 e = e->next;
2847 dma_unmap_page(&hw->pdev->dev, dma_unmap_addr(e, mapaddr),
2848 dma_unmap_len(e, maplen), DMA_TO_DEVICE);
2849 }
2850
2851mapping_error:
2852 if (net_ratelimit())
2853 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
2854 dev_kfree_skb_any(skb);
2855 return NETDEV_TX_OK;
2856}
2857
2858
2859/* Free resources associated with this reing element */
2860static inline void skge_tx_unmap(struct pci_dev *pdev, struct skge_element *e,
2861 u32 control)
2862{
2863 /* skb header vs. fragment */
2864 if (control & BMU_STF)
2865 dma_unmap_single(&pdev->dev, dma_unmap_addr(e, mapaddr),
2866 dma_unmap_len(e, maplen), DMA_TO_DEVICE);
2867 else
2868 dma_unmap_page(&pdev->dev, dma_unmap_addr(e, mapaddr),
2869 dma_unmap_len(e, maplen), DMA_TO_DEVICE);
2870}
2871
2872/* Free all buffers in transmit ring */
2873static void skge_tx_clean(struct net_device *dev)
2874{
2875 struct skge_port *skge = netdev_priv(dev);
2876 struct skge_element *e;
2877
2878 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2879 struct skge_tx_desc *td = e->desc;
2880
2881 skge_tx_unmap(skge->hw->pdev, e, td->control);
2882
2883 if (td->control & BMU_EOF)
2884 dev_kfree_skb(e->skb);
2885 td->control = 0;
2886 }
2887
2888 netdev_reset_queue(dev);
2889 skge->tx_ring.to_clean = e;
2890}
2891
2892static void skge_tx_timeout(struct net_device *dev, unsigned int txqueue)
2893{
2894 struct skge_port *skge = netdev_priv(dev);
2895
2896 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
2897
2898 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2899 skge_tx_clean(dev);
2900 netif_wake_queue(dev);
2901}
2902
2903static int skge_change_mtu(struct net_device *dev, int new_mtu)
2904{
2905 int err;
2906
2907 if (!netif_running(dev)) {
2908 dev->mtu = new_mtu;
2909 return 0;
2910 }
2911
2912 skge_down(dev);
2913
2914 dev->mtu = new_mtu;
2915
2916 err = skge_up(dev);
2917 if (err)
2918 dev_close(dev);
2919
2920 return err;
2921}
2922
2923static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2924
2925static void genesis_add_filter(u8 filter[8], const u8 *addr)
2926{
2927 u32 crc, bit;
2928
2929 crc = ether_crc_le(ETH_ALEN, addr);
2930 bit = ~crc & 0x3f;
2931 filter[bit/8] |= 1 << (bit%8);
2932}
2933
2934static void genesis_set_multicast(struct net_device *dev)
2935{
2936 struct skge_port *skge = netdev_priv(dev);
2937 struct skge_hw *hw = skge->hw;
2938 int port = skge->port;
2939 struct netdev_hw_addr *ha;
2940 u32 mode;
2941 u8 filter[8];
2942
2943 mode = xm_read32(hw, port, XM_MODE);
2944 mode |= XM_MD_ENA_HASH;
2945 if (dev->flags & IFF_PROMISC)
2946 mode |= XM_MD_ENA_PROM;
2947 else
2948 mode &= ~XM_MD_ENA_PROM;
2949
2950 if (dev->flags & IFF_ALLMULTI)
2951 memset(filter, 0xff, sizeof(filter));
2952 else {
2953 memset(filter, 0, sizeof(filter));
2954
2955 if (skge->flow_status == FLOW_STAT_REM_SEND ||
2956 skge->flow_status == FLOW_STAT_SYMMETRIC)
2957 genesis_add_filter(filter, pause_mc_addr);
2958
2959 netdev_for_each_mc_addr(ha, dev)
2960 genesis_add_filter(filter, ha->addr);
2961 }
2962
2963 xm_write32(hw, port, XM_MODE, mode);
2964 xm_outhash(hw, port, XM_HSM, filter);
2965}
2966
2967static void yukon_add_filter(u8 filter[8], const u8 *addr)
2968{
2969 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2970
2971 filter[bit / 8] |= 1 << (bit % 8);
2972}
2973
2974static void yukon_set_multicast(struct net_device *dev)
2975{
2976 struct skge_port *skge = netdev_priv(dev);
2977 struct skge_hw *hw = skge->hw;
2978 int port = skge->port;
2979 struct netdev_hw_addr *ha;
2980 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2981 skge->flow_status == FLOW_STAT_SYMMETRIC);
2982 u16 reg;
2983 u8 filter[8];
2984
2985 memset(filter, 0, sizeof(filter));
2986
2987 reg = gma_read16(hw, port, GM_RX_CTRL);
2988 reg |= GM_RXCR_UCF_ENA;
2989
2990 if (dev->flags & IFF_PROMISC) /* promiscuous */
2991 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2992 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2993 memset(filter, 0xff, sizeof(filter));
2994 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
2995 reg &= ~GM_RXCR_MCF_ENA;
2996 else {
2997 reg |= GM_RXCR_MCF_ENA;
2998
2999 if (rx_pause)
3000 yukon_add_filter(filter, pause_mc_addr);
3001
3002 netdev_for_each_mc_addr(ha, dev)
3003 yukon_add_filter(filter, ha->addr);
3004 }
3005
3006
3007 gma_write16(hw, port, GM_MC_ADDR_H1,
3008 (u16)filter[0] | ((u16)filter[1] << 8));
3009 gma_write16(hw, port, GM_MC_ADDR_H2,
3010 (u16)filter[2] | ((u16)filter[3] << 8));
3011 gma_write16(hw, port, GM_MC_ADDR_H3,
3012 (u16)filter[4] | ((u16)filter[5] << 8));
3013 gma_write16(hw, port, GM_MC_ADDR_H4,
3014 (u16)filter[6] | ((u16)filter[7] << 8));
3015
3016 gma_write16(hw, port, GM_RX_CTRL, reg);
3017}
3018
3019static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3020{
3021 if (is_genesis(hw))
3022 return status >> XMR_FS_LEN_SHIFT;
3023 else
3024 return status >> GMR_FS_LEN_SHIFT;
3025}
3026
3027static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3028{
3029 if (is_genesis(hw))
3030 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3031 else
3032 return (status & GMR_FS_ANY_ERR) ||
3033 (status & GMR_FS_RX_OK) == 0;
3034}
3035
3036static void skge_set_multicast(struct net_device *dev)
3037{
3038 struct skge_port *skge = netdev_priv(dev);
3039
3040 if (is_genesis(skge->hw))
3041 genesis_set_multicast(dev);
3042 else
3043 yukon_set_multicast(dev);
3044
3045}
3046
3047
3048/* Get receive buffer from descriptor.
3049 * Handles copy of small buffers and reallocation failures
3050 */
3051static struct sk_buff *skge_rx_get(struct net_device *dev,
3052 struct skge_element *e,
3053 u32 control, u32 status, u16 csum)
3054{
3055 struct skge_port *skge = netdev_priv(dev);
3056 struct sk_buff *skb;
3057 u16 len = control & BMU_BBC;
3058
3059 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
3060 "rx slot %td status 0x%x len %d\n",
3061 e - skge->rx_ring.start, status, len);
3062
3063 if (len > skge->rx_buf_size)
3064 goto error;
3065
3066 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3067 goto error;
3068
3069 if (bad_phy_status(skge->hw, status))
3070 goto error;
3071
3072 if (phy_length(skge->hw, status) != len)
3073 goto error;
3074
3075 if (len < RX_COPY_THRESHOLD) {
3076 skb = netdev_alloc_skb_ip_align(dev, len);
3077 if (!skb)
3078 goto resubmit;
3079
3080 dma_sync_single_for_cpu(&skge->hw->pdev->dev,
3081 dma_unmap_addr(e, mapaddr),
3082 dma_unmap_len(e, maplen),
3083 DMA_FROM_DEVICE);
3084 skb_copy_from_linear_data(e->skb, skb->data, len);
3085 dma_sync_single_for_device(&skge->hw->pdev->dev,
3086 dma_unmap_addr(e, mapaddr),
3087 dma_unmap_len(e, maplen),
3088 DMA_FROM_DEVICE);
3089 skge_rx_reuse(e, skge->rx_buf_size);
3090 } else {
3091 struct skge_element ee;
3092 struct sk_buff *nskb;
3093
3094 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
3095 if (!nskb)
3096 goto resubmit;
3097
3098 ee = *e;
3099
3100 skb = ee.skb;
3101 prefetch(skb->data);
3102
3103 if (skge_rx_setup(skge, e, nskb, skge->rx_buf_size) < 0) {
3104 dev_kfree_skb(nskb);
3105 goto resubmit;
3106 }
3107
3108 dma_unmap_single(&skge->hw->pdev->dev,
3109 dma_unmap_addr(&ee, mapaddr),
3110 dma_unmap_len(&ee, maplen), DMA_FROM_DEVICE);
3111 }
3112
3113 skb_put(skb, len);
3114
3115 if (dev->features & NETIF_F_RXCSUM) {
3116 skb->csum = le16_to_cpu(csum);
3117 skb->ip_summed = CHECKSUM_COMPLETE;
3118 }
3119
3120 skb->protocol = eth_type_trans(skb, dev);
3121
3122 return skb;
3123error:
3124
3125 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
3126 "rx err, slot %td control 0x%x status 0x%x\n",
3127 e - skge->rx_ring.start, control, status);
3128
3129 if (is_genesis(skge->hw)) {
3130 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3131 dev->stats.rx_length_errors++;
3132 if (status & XMR_FS_FRA_ERR)
3133 dev->stats.rx_frame_errors++;
3134 if (status & XMR_FS_FCS_ERR)
3135 dev->stats.rx_crc_errors++;
3136 } else {
3137 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3138 dev->stats.rx_length_errors++;
3139 if (status & GMR_FS_FRAGMENT)
3140 dev->stats.rx_frame_errors++;
3141 if (status & GMR_FS_CRC_ERR)
3142 dev->stats.rx_crc_errors++;
3143 }
3144
3145resubmit:
3146 skge_rx_reuse(e, skge->rx_buf_size);
3147 return NULL;
3148}
3149
3150/* Free all buffers in Tx ring which are no longer owned by device */
3151static void skge_tx_done(struct net_device *dev)
3152{
3153 struct skge_port *skge = netdev_priv(dev);
3154 struct skge_ring *ring = &skge->tx_ring;
3155 struct skge_element *e;
3156 unsigned int bytes_compl = 0, pkts_compl = 0;
3157
3158 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3159
3160 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3161 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3162
3163 if (control & BMU_OWN)
3164 break;
3165
3166 skge_tx_unmap(skge->hw->pdev, e, control);
3167
3168 if (control & BMU_EOF) {
3169 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
3170 "tx done slot %td\n",
3171 e - skge->tx_ring.start);
3172
3173 pkts_compl++;
3174 bytes_compl += e->skb->len;
3175
3176 dev_consume_skb_any(e->skb);
3177 }
3178 }
3179 netdev_completed_queue(dev, pkts_compl, bytes_compl);
3180 skge->tx_ring.to_clean = e;
3181
3182 /* Can run lockless until we need to synchronize to restart queue. */
3183 smp_mb();
3184
3185 if (unlikely(netif_queue_stopped(dev) &&
3186 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3187 netif_tx_lock(dev);
3188 if (unlikely(netif_queue_stopped(dev) &&
3189 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3190 netif_wake_queue(dev);
3191
3192 }
3193 netif_tx_unlock(dev);
3194 }
3195}
3196
3197static int skge_poll(struct napi_struct *napi, int budget)
3198{
3199 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3200 struct net_device *dev = skge->netdev;
3201 struct skge_hw *hw = skge->hw;
3202 struct skge_ring *ring = &skge->rx_ring;
3203 struct skge_element *e;
3204 int work_done = 0;
3205
3206 skge_tx_done(dev);
3207
3208 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3209
3210 for (e = ring->to_clean; prefetch(e->next), work_done < budget; e = e->next) {
3211 struct skge_rx_desc *rd = e->desc;
3212 struct sk_buff *skb;
3213 u32 control;
3214
3215 rmb();
3216 control = rd->control;
3217 if (control & BMU_OWN)
3218 break;
3219
3220 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3221 if (likely(skb)) {
3222 napi_gro_receive(napi, skb);
3223 ++work_done;
3224 }
3225 }
3226 ring->to_clean = e;
3227
3228 /* restart receiver */
3229 wmb();
3230 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3231
3232 if (work_done < budget && napi_complete_done(napi, work_done)) {
3233 unsigned long flags;
3234
3235 spin_lock_irqsave(&hw->hw_lock, flags);
3236 hw->intr_mask |= napimask[skge->port];
3237 skge_write32(hw, B0_IMSK, hw->intr_mask);
3238 skge_read32(hw, B0_IMSK);
3239 spin_unlock_irqrestore(&hw->hw_lock, flags);
3240 }
3241
3242 return work_done;
3243}
3244
3245/* Parity errors seem to happen when Genesis is connected to a switch
3246 * with no other ports present. Heartbeat error??
3247 */
3248static void skge_mac_parity(struct skge_hw *hw, int port)
3249{
3250 struct net_device *dev = hw->dev[port];
3251
3252 ++dev->stats.tx_heartbeat_errors;
3253
3254 if (is_genesis(hw))
3255 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3256 MFF_CLR_PERR);
3257 else
3258 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3259 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3260 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3261 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3262}
3263
3264static void skge_mac_intr(struct skge_hw *hw, int port)
3265{
3266 if (is_genesis(hw))
3267 genesis_mac_intr(hw, port);
3268 else
3269 yukon_mac_intr(hw, port);
3270}
3271
3272/* Handle device specific framing and timeout interrupts */
3273static void skge_error_irq(struct skge_hw *hw)
3274{
3275 struct pci_dev *pdev = hw->pdev;
3276 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3277
3278 if (is_genesis(hw)) {
3279 /* clear xmac errors */
3280 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3281 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3282 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3283 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3284 } else {
3285 /* Timestamp (unused) overflow */
3286 if (hwstatus & IS_IRQ_TIST_OV)
3287 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3288 }
3289
3290 if (hwstatus & IS_RAM_RD_PAR) {
3291 dev_err(&pdev->dev, "Ram read data parity error\n");
3292 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3293 }
3294
3295 if (hwstatus & IS_RAM_WR_PAR) {
3296 dev_err(&pdev->dev, "Ram write data parity error\n");
3297 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3298 }
3299
3300 if (hwstatus & IS_M1_PAR_ERR)
3301 skge_mac_parity(hw, 0);
3302
3303 if (hwstatus & IS_M2_PAR_ERR)
3304 skge_mac_parity(hw, 1);
3305
3306 if (hwstatus & IS_R1_PAR_ERR) {
3307 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3308 hw->dev[0]->name);
3309 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3310 }
3311
3312 if (hwstatus & IS_R2_PAR_ERR) {
3313 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3314 hw->dev[1]->name);
3315 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3316 }
3317
3318 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3319 u16 pci_status, pci_cmd;
3320
3321 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3322 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3323
3324 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3325 pci_cmd, pci_status);
3326
3327 /* Write the error bits back to clear them. */
3328 pci_status &= PCI_STATUS_ERROR_BITS;
3329 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3330 pci_write_config_word(pdev, PCI_COMMAND,
3331 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3332 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3333 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3334
3335 /* if error still set then just ignore it */
3336 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3337 if (hwstatus & IS_IRQ_STAT) {
3338 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3339 hw->intr_mask &= ~IS_HW_ERR;
3340 }
3341 }
3342}
3343
3344/*
3345 * Interrupt from PHY are handled in tasklet (softirq)
3346 * because accessing phy registers requires spin wait which might
3347 * cause excess interrupt latency.
3348 */
3349static void skge_extirq(struct tasklet_struct *t)
3350{
3351 struct skge_hw *hw = from_tasklet(hw, t, phy_task);
3352 int port;
3353
3354 for (port = 0; port < hw->ports; port++) {
3355 struct net_device *dev = hw->dev[port];
3356
3357 if (netif_running(dev)) {
3358 struct skge_port *skge = netdev_priv(dev);
3359
3360 spin_lock(&hw->phy_lock);
3361 if (!is_genesis(hw))
3362 yukon_phy_intr(skge);
3363 else if (hw->phy_type == SK_PHY_BCOM)
3364 bcom_phy_intr(skge);
3365 spin_unlock(&hw->phy_lock);
3366 }
3367 }
3368
3369 spin_lock_irq(&hw->hw_lock);
3370 hw->intr_mask |= IS_EXT_REG;
3371 skge_write32(hw, B0_IMSK, hw->intr_mask);
3372 skge_read32(hw, B0_IMSK);
3373 spin_unlock_irq(&hw->hw_lock);
3374}
3375
3376static irqreturn_t skge_intr(int irq, void *dev_id)
3377{
3378 struct skge_hw *hw = dev_id;
3379 u32 status;
3380 int handled = 0;
3381
3382 spin_lock(&hw->hw_lock);
3383 /* Reading this register masks IRQ */
3384 status = skge_read32(hw, B0_SP_ISRC);
3385 if (status == 0 || status == ~0)
3386 goto out;
3387
3388 handled = 1;
3389 status &= hw->intr_mask;
3390 if (status & IS_EXT_REG) {
3391 hw->intr_mask &= ~IS_EXT_REG;
3392 tasklet_schedule(&hw->phy_task);
3393 }
3394
3395 if (status & (IS_XA1_F|IS_R1_F)) {
3396 struct skge_port *skge = netdev_priv(hw->dev[0]);
3397 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3398 napi_schedule(&skge->napi);
3399 }
3400
3401 if (status & IS_PA_TO_TX1)
3402 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3403
3404 if (status & IS_PA_TO_RX1) {
3405 ++hw->dev[0]->stats.rx_over_errors;
3406 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3407 }
3408
3409
3410 if (status & IS_MAC1)
3411 skge_mac_intr(hw, 0);
3412
3413 if (hw->dev[1]) {
3414 struct skge_port *skge = netdev_priv(hw->dev[1]);
3415
3416 if (status & (IS_XA2_F|IS_R2_F)) {
3417 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3418 napi_schedule(&skge->napi);
3419 }
3420
3421 if (status & IS_PA_TO_RX2) {
3422 ++hw->dev[1]->stats.rx_over_errors;
3423 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3424 }
3425
3426 if (status & IS_PA_TO_TX2)
3427 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3428
3429 if (status & IS_MAC2)
3430 skge_mac_intr(hw, 1);
3431 }
3432
3433 if (status & IS_HW_ERR)
3434 skge_error_irq(hw);
3435out:
3436 skge_write32(hw, B0_IMSK, hw->intr_mask);
3437 skge_read32(hw, B0_IMSK);
3438 spin_unlock(&hw->hw_lock);
3439
3440 return IRQ_RETVAL(handled);
3441}
3442
3443#ifdef CONFIG_NET_POLL_CONTROLLER
3444static void skge_netpoll(struct net_device *dev)
3445{
3446 struct skge_port *skge = netdev_priv(dev);
3447
3448 disable_irq(dev->irq);
3449 skge_intr(dev->irq, skge->hw);
3450 enable_irq(dev->irq);
3451}
3452#endif
3453
3454static int skge_set_mac_address(struct net_device *dev, void *p)
3455{
3456 struct skge_port *skge = netdev_priv(dev);
3457 struct skge_hw *hw = skge->hw;
3458 unsigned port = skge->port;
3459 const struct sockaddr *addr = p;
3460 u16 ctrl;
3461
3462 if (!is_valid_ether_addr(addr->sa_data))
3463 return -EADDRNOTAVAIL;
3464
3465 eth_hw_addr_set(dev, addr->sa_data);
3466
3467 if (!netif_running(dev)) {
3468 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3469 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3470 } else {
3471 /* disable Rx */
3472 spin_lock_bh(&hw->phy_lock);
3473 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3474 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3475
3476 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3477 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3478
3479 if (is_genesis(hw))
3480 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3481 else {
3482 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3483 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3484 }
3485
3486 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3487 spin_unlock_bh(&hw->phy_lock);
3488 }
3489
3490 return 0;
3491}
3492
3493static const struct {
3494 u8 id;
3495 const char *name;
3496} skge_chips[] = {
3497 { CHIP_ID_GENESIS, "Genesis" },
3498 { CHIP_ID_YUKON, "Yukon" },
3499 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3500 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3501};
3502
3503static const char *skge_board_name(const struct skge_hw *hw)
3504{
3505 int i;
3506 static char buf[16];
3507
3508 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3509 if (skge_chips[i].id == hw->chip_id)
3510 return skge_chips[i].name;
3511
3512 snprintf(buf, sizeof(buf), "chipid 0x%x", hw->chip_id);
3513 return buf;
3514}
3515
3516
3517/*
3518 * Setup the board data structure, but don't bring up
3519 * the port(s)
3520 */
3521static int skge_reset(struct skge_hw *hw)
3522{
3523 u32 reg;
3524 u16 ctst, pci_status;
3525 u8 t8, mac_cfg, pmd_type;
3526 int i;
3527
3528 ctst = skge_read16(hw, B0_CTST);
3529
3530 /* do a SW reset */
3531 skge_write8(hw, B0_CTST, CS_RST_SET);
3532 skge_write8(hw, B0_CTST, CS_RST_CLR);
3533
3534 /* clear PCI errors, if any */
3535 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3536 skge_write8(hw, B2_TST_CTRL2, 0);
3537
3538 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3539 pci_write_config_word(hw->pdev, PCI_STATUS,
3540 pci_status | PCI_STATUS_ERROR_BITS);
3541 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3542 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3543
3544 /* restore CLK_RUN bits (for Yukon-Lite) */
3545 skge_write16(hw, B0_CTST,
3546 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3547
3548 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3549 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3550 pmd_type = skge_read8(hw, B2_PMD_TYP);
3551 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3552
3553 switch (hw->chip_id) {
3554 case CHIP_ID_GENESIS:
3555#ifdef CONFIG_SKGE_GENESIS
3556 switch (hw->phy_type) {
3557 case SK_PHY_XMAC:
3558 hw->phy_addr = PHY_ADDR_XMAC;
3559 break;
3560 case SK_PHY_BCOM:
3561 hw->phy_addr = PHY_ADDR_BCOM;
3562 break;
3563 default:
3564 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3565 hw->phy_type);
3566 return -EOPNOTSUPP;
3567 }
3568 break;
3569#else
3570 dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n");
3571 return -EOPNOTSUPP;
3572#endif
3573
3574 case CHIP_ID_YUKON:
3575 case CHIP_ID_YUKON_LITE:
3576 case CHIP_ID_YUKON_LP:
3577 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3578 hw->copper = 1;
3579
3580 hw->phy_addr = PHY_ADDR_MARV;
3581 break;
3582
3583 default:
3584 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3585 hw->chip_id);
3586 return -EOPNOTSUPP;
3587 }
3588
3589 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3590 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3591 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3592
3593 /* read the adapters RAM size */
3594 t8 = skge_read8(hw, B2_E_0);
3595 if (is_genesis(hw)) {
3596 if (t8 == 3) {
3597 /* special case: 4 x 64k x 36, offset = 0x80000 */
3598 hw->ram_size = 0x100000;
3599 hw->ram_offset = 0x80000;
3600 } else
3601 hw->ram_size = t8 * 512;
3602 } else if (t8 == 0)
3603 hw->ram_size = 0x20000;
3604 else
3605 hw->ram_size = t8 * 4096;
3606
3607 hw->intr_mask = IS_HW_ERR;
3608
3609 /* Use PHY IRQ for all but fiber based Genesis board */
3610 if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC))
3611 hw->intr_mask |= IS_EXT_REG;
3612
3613 if (is_genesis(hw))
3614 genesis_init(hw);
3615 else {
3616 /* switch power to VCC (WA for VAUX problem) */
3617 skge_write8(hw, B0_POWER_CTRL,
3618 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3619
3620 /* avoid boards with stuck Hardware error bits */
3621 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3622 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3623 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3624 hw->intr_mask &= ~IS_HW_ERR;
3625 }
3626
3627 /* Clear PHY COMA */
3628 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3629 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
3630 reg &= ~PCI_PHY_COMA;
3631 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3632 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3633
3634
3635 for (i = 0; i < hw->ports; i++) {
3636 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3637 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3638 }
3639 }
3640
3641 /* turn off hardware timer (unused) */
3642 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3643 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3644 skge_write8(hw, B0_LED, LED_STAT_ON);
3645
3646 /* enable the Tx Arbiters */
3647 for (i = 0; i < hw->ports; i++)
3648 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3649
3650 /* Initialize ram interface */
3651 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3652
3653 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3654 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3655 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3656 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3657 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3658 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3659 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3660 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3661 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3662 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3663 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3664 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3665
3666 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3667
3668 /* Set interrupt moderation for Transmit only
3669 * Receive interrupts avoided by NAPI
3670 */
3671 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3672 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3673 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3674
3675 /* Leave irq disabled until first port is brought up. */
3676 skge_write32(hw, B0_IMSK, 0);
3677
3678 for (i = 0; i < hw->ports; i++) {
3679 if (is_genesis(hw))
3680 genesis_reset(hw, i);
3681 else
3682 yukon_reset(hw, i);
3683 }
3684
3685 return 0;
3686}
3687
3688
3689#ifdef CONFIG_SKGE_DEBUG
3690
3691static struct dentry *skge_debug;
3692
3693static int skge_debug_show(struct seq_file *seq, void *v)
3694{
3695 struct net_device *dev = seq->private;
3696 const struct skge_port *skge = netdev_priv(dev);
3697 const struct skge_hw *hw = skge->hw;
3698 const struct skge_element *e;
3699
3700 if (!netif_running(dev))
3701 return -ENETDOWN;
3702
3703 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3704 skge_read32(hw, B0_IMSK));
3705
3706 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3707 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3708 const struct skge_tx_desc *t = e->desc;
3709 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3710 t->control, t->dma_hi, t->dma_lo, t->status,
3711 t->csum_offs, t->csum_write, t->csum_start);
3712 }
3713
3714 seq_puts(seq, "\nRx Ring:\n");
3715 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3716 const struct skge_rx_desc *r = e->desc;
3717
3718 if (r->control & BMU_OWN)
3719 break;
3720
3721 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3722 r->control, r->dma_hi, r->dma_lo, r->status,
3723 r->timestamp, r->csum1, r->csum1_start);
3724 }
3725
3726 return 0;
3727}
3728DEFINE_SHOW_ATTRIBUTE(skge_debug);
3729
3730/*
3731 * Use network device events to create/remove/rename
3732 * debugfs file entries
3733 */
3734static int skge_device_event(struct notifier_block *unused,
3735 unsigned long event, void *ptr)
3736{
3737 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
3738 struct skge_port *skge;
3739
3740 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
3741 goto done;
3742
3743 skge = netdev_priv(dev);
3744 switch (event) {
3745 case NETDEV_CHANGENAME:
3746 if (skge->debugfs)
3747 skge->debugfs = debugfs_rename(skge_debug,
3748 skge->debugfs,
3749 skge_debug, dev->name);
3750 break;
3751
3752 case NETDEV_GOING_DOWN:
3753 debugfs_remove(skge->debugfs);
3754 skge->debugfs = NULL;
3755 break;
3756
3757 case NETDEV_UP:
3758 skge->debugfs = debugfs_create_file(dev->name, 0444, skge_debug,
3759 dev, &skge_debug_fops);
3760 break;
3761 }
3762
3763done:
3764 return NOTIFY_DONE;
3765}
3766
3767static struct notifier_block skge_notifier = {
3768 .notifier_call = skge_device_event,
3769};
3770
3771
3772static __init void skge_debug_init(void)
3773{
3774 skge_debug = debugfs_create_dir("skge", NULL);
3775
3776 register_netdevice_notifier(&skge_notifier);
3777}
3778
3779static __exit void skge_debug_cleanup(void)
3780{
3781 if (skge_debug) {
3782 unregister_netdevice_notifier(&skge_notifier);
3783 debugfs_remove(skge_debug);
3784 skge_debug = NULL;
3785 }
3786}
3787
3788#else
3789#define skge_debug_init()
3790#define skge_debug_cleanup()
3791#endif
3792
3793static const struct net_device_ops skge_netdev_ops = {
3794 .ndo_open = skge_up,
3795 .ndo_stop = skge_down,
3796 .ndo_start_xmit = skge_xmit_frame,
3797 .ndo_eth_ioctl = skge_ioctl,
3798 .ndo_get_stats = skge_get_stats,
3799 .ndo_tx_timeout = skge_tx_timeout,
3800 .ndo_change_mtu = skge_change_mtu,
3801 .ndo_validate_addr = eth_validate_addr,
3802 .ndo_set_rx_mode = skge_set_multicast,
3803 .ndo_set_mac_address = skge_set_mac_address,
3804#ifdef CONFIG_NET_POLL_CONTROLLER
3805 .ndo_poll_controller = skge_netpoll,
3806#endif
3807};
3808
3809
3810/* Initialize network device */
3811static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3812 int highmem)
3813{
3814 struct skge_port *skge;
3815 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3816 u8 addr[ETH_ALEN];
3817
3818 if (!dev)
3819 return NULL;
3820
3821 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3822 dev->netdev_ops = &skge_netdev_ops;
3823 dev->ethtool_ops = &skge_ethtool_ops;
3824 dev->watchdog_timeo = TX_WATCHDOG;
3825 dev->irq = hw->pdev->irq;
3826
3827 /* MTU range: 60 - 9000 */
3828 dev->min_mtu = ETH_ZLEN;
3829 dev->max_mtu = ETH_JUMBO_MTU;
3830
3831 if (highmem)
3832 dev->features |= NETIF_F_HIGHDMA;
3833
3834 skge = netdev_priv(dev);
3835 netif_napi_add(dev, &skge->napi, skge_poll);
3836 skge->netdev = dev;
3837 skge->hw = hw;
3838 skge->msg_enable = netif_msg_init(debug, default_msg);
3839
3840 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3841 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3842
3843 /* Auto speed and flow control */
3844 skge->autoneg = AUTONEG_ENABLE;
3845 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3846 skge->duplex = -1;
3847 skge->speed = -1;
3848 skge->advertising = skge_supported_modes(hw);
3849
3850 if (device_can_wakeup(&hw->pdev->dev)) {
3851 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3852 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3853 }
3854
3855 hw->dev[port] = dev;
3856
3857 skge->port = port;
3858
3859 /* Only used for Genesis XMAC */
3860 if (is_genesis(hw))
3861 timer_setup(&skge->link_timer, xm_link_timer, 0);
3862 else {
3863 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3864 NETIF_F_RXCSUM;
3865 dev->features |= dev->hw_features;
3866 }
3867
3868 /* read the mac address */
3869 memcpy_fromio(addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3870 eth_hw_addr_set(dev, addr);
3871
3872 return dev;
3873}
3874
3875static void skge_show_addr(struct net_device *dev)
3876{
3877 const struct skge_port *skge = netdev_priv(dev);
3878
3879 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
3880}
3881
3882static int only_32bit_dma;
3883
3884static int skge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3885{
3886 struct net_device *dev, *dev1;
3887 struct skge_hw *hw;
3888 int err, using_dac = 0;
3889
3890 err = pci_enable_device(pdev);
3891 if (err) {
3892 dev_err(&pdev->dev, "cannot enable PCI device\n");
3893 goto err_out;
3894 }
3895
3896 err = pci_request_regions(pdev, DRV_NAME);
3897 if (err) {
3898 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3899 goto err_out_disable_pdev;
3900 }
3901
3902 pci_set_master(pdev);
3903
3904 if (!only_32bit_dma && !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
3905 using_dac = 1;
3906 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
3907 } else if (!(err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)))) {
3908 using_dac = 0;
3909 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
3910 }
3911
3912 if (err) {
3913 dev_err(&pdev->dev, "no usable DMA configuration\n");
3914 goto err_out_free_regions;
3915 }
3916
3917#ifdef __BIG_ENDIAN
3918 /* byte swap descriptors in hardware */
3919 {
3920 u32 reg;
3921
3922 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3923 reg |= PCI_REV_DESC;
3924 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3925 }
3926#endif
3927
3928 err = -ENOMEM;
3929 /* space for skge@pci:0000:04:00.0 */
3930 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
3931 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
3932 if (!hw)
3933 goto err_out_free_regions;
3934
3935 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
3936
3937 hw->pdev = pdev;
3938 spin_lock_init(&hw->hw_lock);
3939 spin_lock_init(&hw->phy_lock);
3940 tasklet_setup(&hw->phy_task, skge_extirq);
3941
3942 hw->regs = ioremap(pci_resource_start(pdev, 0), 0x4000);
3943 if (!hw->regs) {
3944 dev_err(&pdev->dev, "cannot map device registers\n");
3945 goto err_out_free_hw;
3946 }
3947
3948 err = skge_reset(hw);
3949 if (err)
3950 goto err_out_iounmap;
3951
3952 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
3953 DRV_VERSION,
3954 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3955 skge_board_name(hw), hw->chip_rev);
3956
3957 dev = skge_devinit(hw, 0, using_dac);
3958 if (!dev) {
3959 err = -ENOMEM;
3960 goto err_out_led_off;
3961 }
3962
3963 /* Some motherboards are broken and has zero in ROM. */
3964 if (!is_valid_ether_addr(dev->dev_addr))
3965 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3966
3967 err = register_netdev(dev);
3968 if (err) {
3969 dev_err(&pdev->dev, "cannot register net device\n");
3970 goto err_out_free_netdev;
3971 }
3972
3973 skge_show_addr(dev);
3974
3975 if (hw->ports > 1) {
3976 dev1 = skge_devinit(hw, 1, using_dac);
3977 if (!dev1) {
3978 err = -ENOMEM;
3979 goto err_out_unregister;
3980 }
3981
3982 err = register_netdev(dev1);
3983 if (err) {
3984 dev_err(&pdev->dev, "cannot register second net device\n");
3985 goto err_out_free_dev1;
3986 }
3987
3988 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED,
3989 hw->irq_name, hw);
3990 if (err) {
3991 dev_err(&pdev->dev, "cannot assign irq %d\n",
3992 pdev->irq);
3993 goto err_out_unregister_dev1;
3994 }
3995
3996 skge_show_addr(dev1);
3997 }
3998 pci_set_drvdata(pdev, hw);
3999
4000 return 0;
4001
4002err_out_unregister_dev1:
4003 unregister_netdev(dev1);
4004err_out_free_dev1:
4005 free_netdev(dev1);
4006err_out_unregister:
4007 unregister_netdev(dev);
4008err_out_free_netdev:
4009 free_netdev(dev);
4010err_out_led_off:
4011 skge_write16(hw, B0_LED, LED_STAT_OFF);
4012err_out_iounmap:
4013 iounmap(hw->regs);
4014err_out_free_hw:
4015 kfree(hw);
4016err_out_free_regions:
4017 pci_release_regions(pdev);
4018err_out_disable_pdev:
4019 pci_disable_device(pdev);
4020err_out:
4021 return err;
4022}
4023
4024static void skge_remove(struct pci_dev *pdev)
4025{
4026 struct skge_hw *hw = pci_get_drvdata(pdev);
4027 struct net_device *dev0, *dev1;
4028
4029 if (!hw)
4030 return;
4031
4032 dev1 = hw->dev[1];
4033 if (dev1)
4034 unregister_netdev(dev1);
4035 dev0 = hw->dev[0];
4036 unregister_netdev(dev0);
4037
4038 tasklet_kill(&hw->phy_task);
4039
4040 spin_lock_irq(&hw->hw_lock);
4041 hw->intr_mask = 0;
4042
4043 if (hw->ports > 1) {
4044 skge_write32(hw, B0_IMSK, 0);
4045 skge_read32(hw, B0_IMSK);
4046 }
4047 spin_unlock_irq(&hw->hw_lock);
4048
4049 skge_write16(hw, B0_LED, LED_STAT_OFF);
4050 skge_write8(hw, B0_CTST, CS_RST_SET);
4051
4052 if (hw->ports > 1)
4053 free_irq(pdev->irq, hw);
4054 pci_release_regions(pdev);
4055 pci_disable_device(pdev);
4056 if (dev1)
4057 free_netdev(dev1);
4058 free_netdev(dev0);
4059
4060 iounmap(hw->regs);
4061 kfree(hw);
4062}
4063
4064#ifdef CONFIG_PM_SLEEP
4065static int skge_suspend(struct device *dev)
4066{
4067 struct skge_hw *hw = dev_get_drvdata(dev);
4068 int i;
4069
4070 if (!hw)
4071 return 0;
4072
4073 for (i = 0; i < hw->ports; i++) {
4074 struct net_device *dev = hw->dev[i];
4075 struct skge_port *skge = netdev_priv(dev);
4076
4077 if (netif_running(dev))
4078 skge_down(dev);
4079
4080 if (skge->wol)
4081 skge_wol_init(skge);
4082 }
4083
4084 skge_write32(hw, B0_IMSK, 0);
4085
4086 return 0;
4087}
4088
4089static int skge_resume(struct device *dev)
4090{
4091 struct skge_hw *hw = dev_get_drvdata(dev);
4092 int i, err;
4093
4094 if (!hw)
4095 return 0;
4096
4097 err = skge_reset(hw);
4098 if (err)
4099 goto out;
4100
4101 for (i = 0; i < hw->ports; i++) {
4102 struct net_device *dev = hw->dev[i];
4103
4104 if (netif_running(dev)) {
4105 err = skge_up(dev);
4106
4107 if (err) {
4108 netdev_err(dev, "could not up: %d\n", err);
4109 dev_close(dev);
4110 goto out;
4111 }
4112 }
4113 }
4114out:
4115 return err;
4116}
4117
4118static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume);
4119#define SKGE_PM_OPS (&skge_pm_ops)
4120
4121#else
4122
4123#define SKGE_PM_OPS NULL
4124#endif /* CONFIG_PM_SLEEP */
4125
4126static void skge_shutdown(struct pci_dev *pdev)
4127{
4128 struct skge_hw *hw = pci_get_drvdata(pdev);
4129 int i;
4130
4131 if (!hw)
4132 return;
4133
4134 for (i = 0; i < hw->ports; i++) {
4135 struct net_device *dev = hw->dev[i];
4136 struct skge_port *skge = netdev_priv(dev);
4137
4138 if (skge->wol)
4139 skge_wol_init(skge);
4140 }
4141
4142 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
4143 pci_set_power_state(pdev, PCI_D3hot);
4144}
4145
4146static struct pci_driver skge_driver = {
4147 .name = DRV_NAME,
4148 .id_table = skge_id_table,
4149 .probe = skge_probe,
4150 .remove = skge_remove,
4151 .shutdown = skge_shutdown,
4152 .driver.pm = SKGE_PM_OPS,
4153};
4154
4155static const struct dmi_system_id skge_32bit_dma_boards[] = {
4156 {
4157 .ident = "Gigabyte nForce boards",
4158 .matches = {
4159 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"),
4160 DMI_MATCH(DMI_BOARD_NAME, "nForce"),
4161 },
4162 },
4163 {
4164 .ident = "ASUS P5NSLI",
4165 .matches = {
4166 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
4167 DMI_MATCH(DMI_BOARD_NAME, "P5NSLI")
4168 },
4169 },
4170 {
4171 .ident = "FUJITSU SIEMENS A8NE-FM",
4172 .matches = {
4173 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTek Computer INC."),
4174 DMI_MATCH(DMI_BOARD_NAME, "A8NE-FM")
4175 },
4176 },
4177 {}
4178};
4179
4180static int __init skge_init_module(void)
4181{
4182 if (dmi_check_system(skge_32bit_dma_boards))
4183 only_32bit_dma = 1;
4184 skge_debug_init();
4185 return pci_register_driver(&skge_driver);
4186}
4187
4188static void __exit skge_cleanup_module(void)
4189{
4190 pci_unregister_driver(&skge_driver);
4191 skge_debug_cleanup();
4192}
4193
4194module_init(skge_init_module);
4195module_exit(skge_cleanup_module);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
4 * Ethernet adapters. Based on earlier sk98lin, e100 and
5 * FreeBSD if_sk drivers.
6 *
7 * This driver intentionally does not support all the features
8 * of the original driver such as link fail-over and link management because
9 * those should be done at higher levels.
10 *
11 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 */
13
14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16#include <linux/in.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/netdevice.h>
21#include <linux/etherdevice.h>
22#include <linux/ethtool.h>
23#include <linux/pci.h>
24#include <linux/if_vlan.h>
25#include <linux/ip.h>
26#include <linux/delay.h>
27#include <linux/crc32.h>
28#include <linux/dma-mapping.h>
29#include <linux/debugfs.h>
30#include <linux/sched.h>
31#include <linux/seq_file.h>
32#include <linux/mii.h>
33#include <linux/slab.h>
34#include <linux/dmi.h>
35#include <linux/prefetch.h>
36#include <asm/irq.h>
37
38#include "skge.h"
39
40#define DRV_NAME "skge"
41#define DRV_VERSION "1.14"
42
43#define DEFAULT_TX_RING_SIZE 128
44#define DEFAULT_RX_RING_SIZE 512
45#define MAX_TX_RING_SIZE 1024
46#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
47#define MAX_RX_RING_SIZE 4096
48#define RX_COPY_THRESHOLD 128
49#define RX_BUF_SIZE 1536
50#define PHY_RETRIES 1000
51#define ETH_JUMBO_MTU 9000
52#define TX_WATCHDOG (5 * HZ)
53#define NAPI_WEIGHT 64
54#define BLINK_MS 250
55#define LINK_HZ HZ
56
57#define SKGE_EEPROM_MAGIC 0x9933aabb
58
59
60MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
61MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
62MODULE_LICENSE("GPL");
63MODULE_VERSION(DRV_VERSION);
64
65static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
66 NETIF_MSG_LINK | NETIF_MSG_IFUP |
67 NETIF_MSG_IFDOWN);
68
69static int debug = -1; /* defaults above */
70module_param(debug, int, 0);
71MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
72
73static const struct pci_device_id skge_id_table[] = {
74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) }, /* 3Com 3C940 */
75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) }, /* 3Com 3C940B */
76#ifdef CONFIG_SKGE_GENESIS
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */
78#endif
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* D-Link DGE-530T (rev.B) */
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) }, /* D-Link DGE-530T */
82 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302) }, /* D-Link DGE-530T Rev C1 */
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, /* Marvell Yukon 88E8001/8003/8010 */
84 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
85 { PCI_DEVICE(PCI_VENDOR_ID_CNET, 0x434E) }, /* CNet PowerG-2000 */
86 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, 0x1064) }, /* Linksys EG1064 v2 */
87 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, /* Linksys EG1032 v2 */
88 { 0 }
89};
90MODULE_DEVICE_TABLE(pci, skge_id_table);
91
92static int skge_up(struct net_device *dev);
93static int skge_down(struct net_device *dev);
94static void skge_phy_reset(struct skge_port *skge);
95static void skge_tx_clean(struct net_device *dev);
96static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
98static void genesis_get_stats(struct skge_port *skge, u64 *data);
99static void yukon_get_stats(struct skge_port *skge, u64 *data);
100static void yukon_init(struct skge_hw *hw, int port);
101static void genesis_mac_init(struct skge_hw *hw, int port);
102static void genesis_link_up(struct skge_port *skge);
103static void skge_set_multicast(struct net_device *dev);
104static irqreturn_t skge_intr(int irq, void *dev_id);
105
106/* Avoid conditionals by using array */
107static const int txqaddr[] = { Q_XA1, Q_XA2 };
108static const int rxqaddr[] = { Q_R1, Q_R2 };
109static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
110static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
111static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
112static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
113
114static inline bool is_genesis(const struct skge_hw *hw)
115{
116#ifdef CONFIG_SKGE_GENESIS
117 return hw->chip_id == CHIP_ID_GENESIS;
118#else
119 return false;
120#endif
121}
122
123static int skge_get_regs_len(struct net_device *dev)
124{
125 return 0x4000;
126}
127
128/*
129 * Returns copy of whole control register region
130 * Note: skip RAM address register because accessing it will
131 * cause bus hangs!
132 */
133static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
134 void *p)
135{
136 const struct skge_port *skge = netdev_priv(dev);
137 const void __iomem *io = skge->hw->regs;
138
139 regs->version = 1;
140 memset(p, 0, regs->len);
141 memcpy_fromio(p, io, B3_RAM_ADDR);
142
143 if (regs->len > B3_RI_WTO_R1) {
144 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
145 regs->len - B3_RI_WTO_R1);
146 }
147}
148
149/* Wake on Lan only supported on Yukon chips with rev 1 or above */
150static u32 wol_supported(const struct skge_hw *hw)
151{
152 if (is_genesis(hw))
153 return 0;
154
155 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
156 return 0;
157
158 return WAKE_MAGIC | WAKE_PHY;
159}
160
161static void skge_wol_init(struct skge_port *skge)
162{
163 struct skge_hw *hw = skge->hw;
164 int port = skge->port;
165 u16 ctrl;
166
167 skge_write16(hw, B0_CTST, CS_RST_CLR);
168 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
169
170 /* Turn on Vaux */
171 skge_write8(hw, B0_POWER_CTRL,
172 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
173
174 /* WA code for COMA mode -- clear PHY reset */
175 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
176 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
177 u32 reg = skge_read32(hw, B2_GP_IO);
178 reg |= GP_DIR_9;
179 reg &= ~GP_IO_9;
180 skge_write32(hw, B2_GP_IO, reg);
181 }
182
183 skge_write32(hw, SK_REG(port, GPHY_CTRL),
184 GPC_DIS_SLEEP |
185 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
186 GPC_ANEG_1 | GPC_RST_SET);
187
188 skge_write32(hw, SK_REG(port, GPHY_CTRL),
189 GPC_DIS_SLEEP |
190 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
191 GPC_ANEG_1 | GPC_RST_CLR);
192
193 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
194
195 /* Force to 10/100 skge_reset will re-enable on resume */
196 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
197 (PHY_AN_100FULL | PHY_AN_100HALF |
198 PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA));
199 /* no 1000 HD/FD */
200 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
201 gm_phy_write(hw, port, PHY_MARV_CTRL,
202 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
203 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
204
205
206 /* Set GMAC to no flow control and auto update for speed/duplex */
207 gma_write16(hw, port, GM_GP_CTRL,
208 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
209 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
210
211 /* Set WOL address */
212 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
213 skge->netdev->dev_addr, ETH_ALEN);
214
215 /* Turn on appropriate WOL control bits */
216 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
217 ctrl = 0;
218 if (skge->wol & WAKE_PHY)
219 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
220 else
221 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
222
223 if (skge->wol & WAKE_MAGIC)
224 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
225 else
226 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
227
228 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
229 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
230
231 /* block receiver */
232 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
233}
234
235static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
236{
237 struct skge_port *skge = netdev_priv(dev);
238
239 wol->supported = wol_supported(skge->hw);
240 wol->wolopts = skge->wol;
241}
242
243static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
244{
245 struct skge_port *skge = netdev_priv(dev);
246 struct skge_hw *hw = skge->hw;
247
248 if ((wol->wolopts & ~wol_supported(hw)) ||
249 !device_can_wakeup(&hw->pdev->dev))
250 return -EOPNOTSUPP;
251
252 skge->wol = wol->wolopts;
253
254 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
255
256 return 0;
257}
258
259/* Determine supported/advertised modes based on hardware.
260 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
261 */
262static u32 skge_supported_modes(const struct skge_hw *hw)
263{
264 u32 supported;
265
266 if (hw->copper) {
267 supported = (SUPPORTED_10baseT_Half |
268 SUPPORTED_10baseT_Full |
269 SUPPORTED_100baseT_Half |
270 SUPPORTED_100baseT_Full |
271 SUPPORTED_1000baseT_Half |
272 SUPPORTED_1000baseT_Full |
273 SUPPORTED_Autoneg |
274 SUPPORTED_TP);
275
276 if (is_genesis(hw))
277 supported &= ~(SUPPORTED_10baseT_Half |
278 SUPPORTED_10baseT_Full |
279 SUPPORTED_100baseT_Half |
280 SUPPORTED_100baseT_Full);
281
282 else if (hw->chip_id == CHIP_ID_YUKON)
283 supported &= ~SUPPORTED_1000baseT_Half;
284 } else
285 supported = (SUPPORTED_1000baseT_Full |
286 SUPPORTED_1000baseT_Half |
287 SUPPORTED_FIBRE |
288 SUPPORTED_Autoneg);
289
290 return supported;
291}
292
293static int skge_get_link_ksettings(struct net_device *dev,
294 struct ethtool_link_ksettings *cmd)
295{
296 struct skge_port *skge = netdev_priv(dev);
297 struct skge_hw *hw = skge->hw;
298 u32 supported, advertising;
299
300 supported = skge_supported_modes(hw);
301
302 if (hw->copper) {
303 cmd->base.port = PORT_TP;
304 cmd->base.phy_address = hw->phy_addr;
305 } else
306 cmd->base.port = PORT_FIBRE;
307
308 advertising = skge->advertising;
309 cmd->base.autoneg = skge->autoneg;
310 cmd->base.speed = skge->speed;
311 cmd->base.duplex = skge->duplex;
312
313 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
314 supported);
315 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
316 advertising);
317
318 return 0;
319}
320
321static int skge_set_link_ksettings(struct net_device *dev,
322 const struct ethtool_link_ksettings *cmd)
323{
324 struct skge_port *skge = netdev_priv(dev);
325 const struct skge_hw *hw = skge->hw;
326 u32 supported = skge_supported_modes(hw);
327 int err = 0;
328 u32 advertising;
329
330 ethtool_convert_link_mode_to_legacy_u32(&advertising,
331 cmd->link_modes.advertising);
332
333 if (cmd->base.autoneg == AUTONEG_ENABLE) {
334 advertising = supported;
335 skge->duplex = -1;
336 skge->speed = -1;
337 } else {
338 u32 setting;
339 u32 speed = cmd->base.speed;
340
341 switch (speed) {
342 case SPEED_1000:
343 if (cmd->base.duplex == DUPLEX_FULL)
344 setting = SUPPORTED_1000baseT_Full;
345 else if (cmd->base.duplex == DUPLEX_HALF)
346 setting = SUPPORTED_1000baseT_Half;
347 else
348 return -EINVAL;
349 break;
350 case SPEED_100:
351 if (cmd->base.duplex == DUPLEX_FULL)
352 setting = SUPPORTED_100baseT_Full;
353 else if (cmd->base.duplex == DUPLEX_HALF)
354 setting = SUPPORTED_100baseT_Half;
355 else
356 return -EINVAL;
357 break;
358
359 case SPEED_10:
360 if (cmd->base.duplex == DUPLEX_FULL)
361 setting = SUPPORTED_10baseT_Full;
362 else if (cmd->base.duplex == DUPLEX_HALF)
363 setting = SUPPORTED_10baseT_Half;
364 else
365 return -EINVAL;
366 break;
367 default:
368 return -EINVAL;
369 }
370
371 if ((setting & supported) == 0)
372 return -EINVAL;
373
374 skge->speed = speed;
375 skge->duplex = cmd->base.duplex;
376 }
377
378 skge->autoneg = cmd->base.autoneg;
379 skge->advertising = advertising;
380
381 if (netif_running(dev)) {
382 skge_down(dev);
383 err = skge_up(dev);
384 if (err) {
385 dev_close(dev);
386 return err;
387 }
388 }
389
390 return 0;
391}
392
393static void skge_get_drvinfo(struct net_device *dev,
394 struct ethtool_drvinfo *info)
395{
396 struct skge_port *skge = netdev_priv(dev);
397
398 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
399 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
400 strlcpy(info->bus_info, pci_name(skge->hw->pdev),
401 sizeof(info->bus_info));
402}
403
404static const struct skge_stat {
405 char name[ETH_GSTRING_LEN];
406 u16 xmac_offset;
407 u16 gma_offset;
408} skge_stats[] = {
409 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
410 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
411
412 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
413 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
414 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
415 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
416 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
417 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
418 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
419 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
420
421 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
422 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
423 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
424 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
425 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
426 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
427
428 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
429 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
430 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
431 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
432 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
433};
434
435static int skge_get_sset_count(struct net_device *dev, int sset)
436{
437 switch (sset) {
438 case ETH_SS_STATS:
439 return ARRAY_SIZE(skge_stats);
440 default:
441 return -EOPNOTSUPP;
442 }
443}
444
445static void skge_get_ethtool_stats(struct net_device *dev,
446 struct ethtool_stats *stats, u64 *data)
447{
448 struct skge_port *skge = netdev_priv(dev);
449
450 if (is_genesis(skge->hw))
451 genesis_get_stats(skge, data);
452 else
453 yukon_get_stats(skge, data);
454}
455
456/* Use hardware MIB variables for critical path statistics and
457 * transmit feedback not reported at interrupt.
458 * Other errors are accounted for in interrupt handler.
459 */
460static struct net_device_stats *skge_get_stats(struct net_device *dev)
461{
462 struct skge_port *skge = netdev_priv(dev);
463 u64 data[ARRAY_SIZE(skge_stats)];
464
465 if (is_genesis(skge->hw))
466 genesis_get_stats(skge, data);
467 else
468 yukon_get_stats(skge, data);
469
470 dev->stats.tx_bytes = data[0];
471 dev->stats.rx_bytes = data[1];
472 dev->stats.tx_packets = data[2] + data[4] + data[6];
473 dev->stats.rx_packets = data[3] + data[5] + data[7];
474 dev->stats.multicast = data[3] + data[5];
475 dev->stats.collisions = data[10];
476 dev->stats.tx_aborted_errors = data[12];
477
478 return &dev->stats;
479}
480
481static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
482{
483 int i;
484
485 switch (stringset) {
486 case ETH_SS_STATS:
487 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
488 memcpy(data + i * ETH_GSTRING_LEN,
489 skge_stats[i].name, ETH_GSTRING_LEN);
490 break;
491 }
492}
493
494static void skge_get_ring_param(struct net_device *dev,
495 struct ethtool_ringparam *p)
496{
497 struct skge_port *skge = netdev_priv(dev);
498
499 p->rx_max_pending = MAX_RX_RING_SIZE;
500 p->tx_max_pending = MAX_TX_RING_SIZE;
501
502 p->rx_pending = skge->rx_ring.count;
503 p->tx_pending = skge->tx_ring.count;
504}
505
506static int skge_set_ring_param(struct net_device *dev,
507 struct ethtool_ringparam *p)
508{
509 struct skge_port *skge = netdev_priv(dev);
510 int err = 0;
511
512 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
513 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
514 return -EINVAL;
515
516 skge->rx_ring.count = p->rx_pending;
517 skge->tx_ring.count = p->tx_pending;
518
519 if (netif_running(dev)) {
520 skge_down(dev);
521 err = skge_up(dev);
522 if (err)
523 dev_close(dev);
524 }
525
526 return err;
527}
528
529static u32 skge_get_msglevel(struct net_device *netdev)
530{
531 struct skge_port *skge = netdev_priv(netdev);
532 return skge->msg_enable;
533}
534
535static void skge_set_msglevel(struct net_device *netdev, u32 value)
536{
537 struct skge_port *skge = netdev_priv(netdev);
538 skge->msg_enable = value;
539}
540
541static int skge_nway_reset(struct net_device *dev)
542{
543 struct skge_port *skge = netdev_priv(dev);
544
545 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
546 return -EINVAL;
547
548 skge_phy_reset(skge);
549 return 0;
550}
551
552static void skge_get_pauseparam(struct net_device *dev,
553 struct ethtool_pauseparam *ecmd)
554{
555 struct skge_port *skge = netdev_priv(dev);
556
557 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
558 (skge->flow_control == FLOW_MODE_SYM_OR_REM));
559 ecmd->tx_pause = (ecmd->rx_pause ||
560 (skge->flow_control == FLOW_MODE_LOC_SEND));
561
562 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
563}
564
565static int skge_set_pauseparam(struct net_device *dev,
566 struct ethtool_pauseparam *ecmd)
567{
568 struct skge_port *skge = netdev_priv(dev);
569 struct ethtool_pauseparam old;
570 int err = 0;
571
572 skge_get_pauseparam(dev, &old);
573
574 if (ecmd->autoneg != old.autoneg)
575 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
576 else {
577 if (ecmd->rx_pause && ecmd->tx_pause)
578 skge->flow_control = FLOW_MODE_SYMMETRIC;
579 else if (ecmd->rx_pause && !ecmd->tx_pause)
580 skge->flow_control = FLOW_MODE_SYM_OR_REM;
581 else if (!ecmd->rx_pause && ecmd->tx_pause)
582 skge->flow_control = FLOW_MODE_LOC_SEND;
583 else
584 skge->flow_control = FLOW_MODE_NONE;
585 }
586
587 if (netif_running(dev)) {
588 skge_down(dev);
589 err = skge_up(dev);
590 if (err) {
591 dev_close(dev);
592 return err;
593 }
594 }
595
596 return 0;
597}
598
599/* Chip internal frequency for clock calculations */
600static inline u32 hwkhz(const struct skge_hw *hw)
601{
602 return is_genesis(hw) ? 53125 : 78125;
603}
604
605/* Chip HZ to microseconds */
606static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
607{
608 return (ticks * 1000) / hwkhz(hw);
609}
610
611/* Microseconds to chip HZ */
612static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
613{
614 return hwkhz(hw) * usec / 1000;
615}
616
617static int skge_get_coalesce(struct net_device *dev,
618 struct ethtool_coalesce *ecmd)
619{
620 struct skge_port *skge = netdev_priv(dev);
621 struct skge_hw *hw = skge->hw;
622 int port = skge->port;
623
624 ecmd->rx_coalesce_usecs = 0;
625 ecmd->tx_coalesce_usecs = 0;
626
627 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
628 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
629 u32 msk = skge_read32(hw, B2_IRQM_MSK);
630
631 if (msk & rxirqmask[port])
632 ecmd->rx_coalesce_usecs = delay;
633 if (msk & txirqmask[port])
634 ecmd->tx_coalesce_usecs = delay;
635 }
636
637 return 0;
638}
639
640/* Note: interrupt timer is per board, but can turn on/off per port */
641static int skge_set_coalesce(struct net_device *dev,
642 struct ethtool_coalesce *ecmd)
643{
644 struct skge_port *skge = netdev_priv(dev);
645 struct skge_hw *hw = skge->hw;
646 int port = skge->port;
647 u32 msk = skge_read32(hw, B2_IRQM_MSK);
648 u32 delay = 25;
649
650 if (ecmd->rx_coalesce_usecs == 0)
651 msk &= ~rxirqmask[port];
652 else if (ecmd->rx_coalesce_usecs < 25 ||
653 ecmd->rx_coalesce_usecs > 33333)
654 return -EINVAL;
655 else {
656 msk |= rxirqmask[port];
657 delay = ecmd->rx_coalesce_usecs;
658 }
659
660 if (ecmd->tx_coalesce_usecs == 0)
661 msk &= ~txirqmask[port];
662 else if (ecmd->tx_coalesce_usecs < 25 ||
663 ecmd->tx_coalesce_usecs > 33333)
664 return -EINVAL;
665 else {
666 msk |= txirqmask[port];
667 delay = min(delay, ecmd->rx_coalesce_usecs);
668 }
669
670 skge_write32(hw, B2_IRQM_MSK, msk);
671 if (msk == 0)
672 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
673 else {
674 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
675 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
676 }
677 return 0;
678}
679
680enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
681static void skge_led(struct skge_port *skge, enum led_mode mode)
682{
683 struct skge_hw *hw = skge->hw;
684 int port = skge->port;
685
686 spin_lock_bh(&hw->phy_lock);
687 if (is_genesis(hw)) {
688 switch (mode) {
689 case LED_MODE_OFF:
690 if (hw->phy_type == SK_PHY_BCOM)
691 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
692 else {
693 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
694 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
695 }
696 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
697 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
698 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
699 break;
700
701 case LED_MODE_ON:
702 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
703 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
704
705 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
706 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
707
708 break;
709
710 case LED_MODE_TST:
711 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
712 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
713 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
714
715 if (hw->phy_type == SK_PHY_BCOM)
716 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
717 else {
718 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
719 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
720 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
721 }
722
723 }
724 } else {
725 switch (mode) {
726 case LED_MODE_OFF:
727 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
728 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
729 PHY_M_LED_MO_DUP(MO_LED_OFF) |
730 PHY_M_LED_MO_10(MO_LED_OFF) |
731 PHY_M_LED_MO_100(MO_LED_OFF) |
732 PHY_M_LED_MO_1000(MO_LED_OFF) |
733 PHY_M_LED_MO_RX(MO_LED_OFF));
734 break;
735 case LED_MODE_ON:
736 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
737 PHY_M_LED_PULS_DUR(PULS_170MS) |
738 PHY_M_LED_BLINK_RT(BLINK_84MS) |
739 PHY_M_LEDC_TX_CTRL |
740 PHY_M_LEDC_DP_CTRL);
741
742 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
743 PHY_M_LED_MO_RX(MO_LED_OFF) |
744 (skge->speed == SPEED_100 ?
745 PHY_M_LED_MO_100(MO_LED_ON) : 0));
746 break;
747 case LED_MODE_TST:
748 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
749 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
750 PHY_M_LED_MO_DUP(MO_LED_ON) |
751 PHY_M_LED_MO_10(MO_LED_ON) |
752 PHY_M_LED_MO_100(MO_LED_ON) |
753 PHY_M_LED_MO_1000(MO_LED_ON) |
754 PHY_M_LED_MO_RX(MO_LED_ON));
755 }
756 }
757 spin_unlock_bh(&hw->phy_lock);
758}
759
760/* blink LED's for finding board */
761static int skge_set_phys_id(struct net_device *dev,
762 enum ethtool_phys_id_state state)
763{
764 struct skge_port *skge = netdev_priv(dev);
765
766 switch (state) {
767 case ETHTOOL_ID_ACTIVE:
768 return 2; /* cycle on/off twice per second */
769
770 case ETHTOOL_ID_ON:
771 skge_led(skge, LED_MODE_TST);
772 break;
773
774 case ETHTOOL_ID_OFF:
775 skge_led(skge, LED_MODE_OFF);
776 break;
777
778 case ETHTOOL_ID_INACTIVE:
779 /* back to regular LED state */
780 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
781 }
782
783 return 0;
784}
785
786static int skge_get_eeprom_len(struct net_device *dev)
787{
788 struct skge_port *skge = netdev_priv(dev);
789 u32 reg2;
790
791 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2);
792 return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
793}
794
795static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
796{
797 u32 val;
798
799 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
800
801 do {
802 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
803 } while (!(offset & PCI_VPD_ADDR_F));
804
805 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
806 return val;
807}
808
809static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
810{
811 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
812 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
813 offset | PCI_VPD_ADDR_F);
814
815 do {
816 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
817 } while (offset & PCI_VPD_ADDR_F);
818}
819
820static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
821 u8 *data)
822{
823 struct skge_port *skge = netdev_priv(dev);
824 struct pci_dev *pdev = skge->hw->pdev;
825 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
826 int length = eeprom->len;
827 u16 offset = eeprom->offset;
828
829 if (!cap)
830 return -EINVAL;
831
832 eeprom->magic = SKGE_EEPROM_MAGIC;
833
834 while (length > 0) {
835 u32 val = skge_vpd_read(pdev, cap, offset);
836 int n = min_t(int, length, sizeof(val));
837
838 memcpy(data, &val, n);
839 length -= n;
840 data += n;
841 offset += n;
842 }
843 return 0;
844}
845
846static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
847 u8 *data)
848{
849 struct skge_port *skge = netdev_priv(dev);
850 struct pci_dev *pdev = skge->hw->pdev;
851 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
852 int length = eeprom->len;
853 u16 offset = eeprom->offset;
854
855 if (!cap)
856 return -EINVAL;
857
858 if (eeprom->magic != SKGE_EEPROM_MAGIC)
859 return -EINVAL;
860
861 while (length > 0) {
862 u32 val;
863 int n = min_t(int, length, sizeof(val));
864
865 if (n < sizeof(val))
866 val = skge_vpd_read(pdev, cap, offset);
867 memcpy(&val, data, n);
868
869 skge_vpd_write(pdev, cap, offset, val);
870
871 length -= n;
872 data += n;
873 offset += n;
874 }
875 return 0;
876}
877
878static const struct ethtool_ops skge_ethtool_ops = {
879 .get_drvinfo = skge_get_drvinfo,
880 .get_regs_len = skge_get_regs_len,
881 .get_regs = skge_get_regs,
882 .get_wol = skge_get_wol,
883 .set_wol = skge_set_wol,
884 .get_msglevel = skge_get_msglevel,
885 .set_msglevel = skge_set_msglevel,
886 .nway_reset = skge_nway_reset,
887 .get_link = ethtool_op_get_link,
888 .get_eeprom_len = skge_get_eeprom_len,
889 .get_eeprom = skge_get_eeprom,
890 .set_eeprom = skge_set_eeprom,
891 .get_ringparam = skge_get_ring_param,
892 .set_ringparam = skge_set_ring_param,
893 .get_pauseparam = skge_get_pauseparam,
894 .set_pauseparam = skge_set_pauseparam,
895 .get_coalesce = skge_get_coalesce,
896 .set_coalesce = skge_set_coalesce,
897 .get_strings = skge_get_strings,
898 .set_phys_id = skge_set_phys_id,
899 .get_sset_count = skge_get_sset_count,
900 .get_ethtool_stats = skge_get_ethtool_stats,
901 .get_link_ksettings = skge_get_link_ksettings,
902 .set_link_ksettings = skge_set_link_ksettings,
903};
904
905/*
906 * Allocate ring elements and chain them together
907 * One-to-one association of board descriptors with ring elements
908 */
909static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
910{
911 struct skge_tx_desc *d;
912 struct skge_element *e;
913 int i;
914
915 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
916 if (!ring->start)
917 return -ENOMEM;
918
919 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
920 e->desc = d;
921 if (i == ring->count - 1) {
922 e->next = ring->start;
923 d->next_offset = base;
924 } else {
925 e->next = e + 1;
926 d->next_offset = base + (i+1) * sizeof(*d);
927 }
928 }
929 ring->to_use = ring->to_clean = ring->start;
930
931 return 0;
932}
933
934/* Allocate and setup a new buffer for receiving */
935static int skge_rx_setup(struct skge_port *skge, struct skge_element *e,
936 struct sk_buff *skb, unsigned int bufsize)
937{
938 struct skge_rx_desc *rd = e->desc;
939 dma_addr_t map;
940
941 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
942 PCI_DMA_FROMDEVICE);
943
944 if (pci_dma_mapping_error(skge->hw->pdev, map))
945 return -1;
946
947 rd->dma_lo = lower_32_bits(map);
948 rd->dma_hi = upper_32_bits(map);
949 e->skb = skb;
950 rd->csum1_start = ETH_HLEN;
951 rd->csum2_start = ETH_HLEN;
952 rd->csum1 = 0;
953 rd->csum2 = 0;
954
955 wmb();
956
957 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
958 dma_unmap_addr_set(e, mapaddr, map);
959 dma_unmap_len_set(e, maplen, bufsize);
960 return 0;
961}
962
963/* Resume receiving using existing skb,
964 * Note: DMA address is not changed by chip.
965 * MTU not changed while receiver active.
966 */
967static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
968{
969 struct skge_rx_desc *rd = e->desc;
970
971 rd->csum2 = 0;
972 rd->csum2_start = ETH_HLEN;
973
974 wmb();
975
976 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
977}
978
979
980/* Free all buffers in receive ring, assumes receiver stopped */
981static void skge_rx_clean(struct skge_port *skge)
982{
983 struct skge_hw *hw = skge->hw;
984 struct skge_ring *ring = &skge->rx_ring;
985 struct skge_element *e;
986
987 e = ring->start;
988 do {
989 struct skge_rx_desc *rd = e->desc;
990 rd->control = 0;
991 if (e->skb) {
992 pci_unmap_single(hw->pdev,
993 dma_unmap_addr(e, mapaddr),
994 dma_unmap_len(e, maplen),
995 PCI_DMA_FROMDEVICE);
996 dev_kfree_skb(e->skb);
997 e->skb = NULL;
998 }
999 } while ((e = e->next) != ring->start);
1000}
1001
1002
1003/* Allocate buffers for receive ring
1004 * For receive: to_clean is next received frame.
1005 */
1006static int skge_rx_fill(struct net_device *dev)
1007{
1008 struct skge_port *skge = netdev_priv(dev);
1009 struct skge_ring *ring = &skge->rx_ring;
1010 struct skge_element *e;
1011
1012 e = ring->start;
1013 do {
1014 struct sk_buff *skb;
1015
1016 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1017 GFP_KERNEL);
1018 if (!skb)
1019 return -ENOMEM;
1020
1021 skb_reserve(skb, NET_IP_ALIGN);
1022 if (skge_rx_setup(skge, e, skb, skge->rx_buf_size) < 0) {
1023 dev_kfree_skb(skb);
1024 return -EIO;
1025 }
1026 } while ((e = e->next) != ring->start);
1027
1028 ring->to_clean = ring->start;
1029 return 0;
1030}
1031
1032static const char *skge_pause(enum pause_status status)
1033{
1034 switch (status) {
1035 case FLOW_STAT_NONE:
1036 return "none";
1037 case FLOW_STAT_REM_SEND:
1038 return "rx only";
1039 case FLOW_STAT_LOC_SEND:
1040 return "tx_only";
1041 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1042 return "both";
1043 default:
1044 return "indeterminated";
1045 }
1046}
1047
1048
1049static void skge_link_up(struct skge_port *skge)
1050{
1051 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1052 LED_BLK_OFF|LED_SYNC_OFF|LED_REG_ON);
1053
1054 netif_carrier_on(skge->netdev);
1055 netif_wake_queue(skge->netdev);
1056
1057 netif_info(skge, link, skge->netdev,
1058 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1059 skge->speed,
1060 skge->duplex == DUPLEX_FULL ? "full" : "half",
1061 skge_pause(skge->flow_status));
1062}
1063
1064static void skge_link_down(struct skge_port *skge)
1065{
1066 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
1067 netif_carrier_off(skge->netdev);
1068 netif_stop_queue(skge->netdev);
1069
1070 netif_info(skge, link, skge->netdev, "Link is down\n");
1071}
1072
1073static void xm_link_down(struct skge_hw *hw, int port)
1074{
1075 struct net_device *dev = hw->dev[port];
1076 struct skge_port *skge = netdev_priv(dev);
1077
1078 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1079
1080 if (netif_carrier_ok(dev))
1081 skge_link_down(skge);
1082}
1083
1084static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1085{
1086 int i;
1087
1088 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1089 *val = xm_read16(hw, port, XM_PHY_DATA);
1090
1091 if (hw->phy_type == SK_PHY_XMAC)
1092 goto ready;
1093
1094 for (i = 0; i < PHY_RETRIES; i++) {
1095 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1096 goto ready;
1097 udelay(1);
1098 }
1099
1100 return -ETIMEDOUT;
1101 ready:
1102 *val = xm_read16(hw, port, XM_PHY_DATA);
1103
1104 return 0;
1105}
1106
1107static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1108{
1109 u16 v = 0;
1110 if (__xm_phy_read(hw, port, reg, &v))
1111 pr_warn("%s: phy read timed out\n", hw->dev[port]->name);
1112 return v;
1113}
1114
1115static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1116{
1117 int i;
1118
1119 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1120 for (i = 0; i < PHY_RETRIES; i++) {
1121 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1122 goto ready;
1123 udelay(1);
1124 }
1125 return -EIO;
1126
1127 ready:
1128 xm_write16(hw, port, XM_PHY_DATA, val);
1129 for (i = 0; i < PHY_RETRIES; i++) {
1130 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1131 return 0;
1132 udelay(1);
1133 }
1134 return -ETIMEDOUT;
1135}
1136
1137static void genesis_init(struct skge_hw *hw)
1138{
1139 /* set blink source counter */
1140 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1141 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1142
1143 /* configure mac arbiter */
1144 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1145
1146 /* configure mac arbiter timeout values */
1147 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1148 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1149 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1150 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1151
1152 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1153 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1154 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1155 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1156
1157 /* configure packet arbiter timeout */
1158 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1159 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1160 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1161 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1162 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1163}
1164
1165static void genesis_reset(struct skge_hw *hw, int port)
1166{
1167 static const u8 zero[8] = { 0 };
1168 u32 reg;
1169
1170 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1171
1172 /* reset the statistics module */
1173 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1174 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1175 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1176 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1177 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1178
1179 /* disable Broadcom PHY IRQ */
1180 if (hw->phy_type == SK_PHY_BCOM)
1181 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1182
1183 xm_outhash(hw, port, XM_HSM, zero);
1184
1185 /* Flush TX and RX fifo */
1186 reg = xm_read32(hw, port, XM_MODE);
1187 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1188 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1189}
1190
1191/* Convert mode to MII values */
1192static const u16 phy_pause_map[] = {
1193 [FLOW_MODE_NONE] = 0,
1194 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1195 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1196 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1197};
1198
1199/* special defines for FIBER (88E1011S only) */
1200static const u16 fiber_pause_map[] = {
1201 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1202 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1203 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1204 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1205};
1206
1207
1208/* Check status of Broadcom phy link */
1209static void bcom_check_link(struct skge_hw *hw, int port)
1210{
1211 struct net_device *dev = hw->dev[port];
1212 struct skge_port *skge = netdev_priv(dev);
1213 u16 status;
1214
1215 /* read twice because of latch */
1216 xm_phy_read(hw, port, PHY_BCOM_STAT);
1217 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1218
1219 if ((status & PHY_ST_LSYNC) == 0) {
1220 xm_link_down(hw, port);
1221 return;
1222 }
1223
1224 if (skge->autoneg == AUTONEG_ENABLE) {
1225 u16 lpa, aux;
1226
1227 if (!(status & PHY_ST_AN_OVER))
1228 return;
1229
1230 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1231 if (lpa & PHY_B_AN_RF) {
1232 netdev_notice(dev, "remote fault\n");
1233 return;
1234 }
1235
1236 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1237
1238 /* Check Duplex mismatch */
1239 switch (aux & PHY_B_AS_AN_RES_MSK) {
1240 case PHY_B_RES_1000FD:
1241 skge->duplex = DUPLEX_FULL;
1242 break;
1243 case PHY_B_RES_1000HD:
1244 skge->duplex = DUPLEX_HALF;
1245 break;
1246 default:
1247 netdev_notice(dev, "duplex mismatch\n");
1248 return;
1249 }
1250
1251 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1252 switch (aux & PHY_B_AS_PAUSE_MSK) {
1253 case PHY_B_AS_PAUSE_MSK:
1254 skge->flow_status = FLOW_STAT_SYMMETRIC;
1255 break;
1256 case PHY_B_AS_PRR:
1257 skge->flow_status = FLOW_STAT_REM_SEND;
1258 break;
1259 case PHY_B_AS_PRT:
1260 skge->flow_status = FLOW_STAT_LOC_SEND;
1261 break;
1262 default:
1263 skge->flow_status = FLOW_STAT_NONE;
1264 }
1265 skge->speed = SPEED_1000;
1266 }
1267
1268 if (!netif_carrier_ok(dev))
1269 genesis_link_up(skge);
1270}
1271
1272/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1273 * Phy on for 100 or 10Mbit operation
1274 */
1275static void bcom_phy_init(struct skge_port *skge)
1276{
1277 struct skge_hw *hw = skge->hw;
1278 int port = skge->port;
1279 int i;
1280 u16 id1, r, ext, ctl;
1281
1282 /* magic workaround patterns for Broadcom */
1283 static const struct {
1284 u16 reg;
1285 u16 val;
1286 } A1hack[] = {
1287 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1288 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1289 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1290 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1291 }, C0hack[] = {
1292 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1293 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1294 };
1295
1296 /* read Id from external PHY (all have the same address) */
1297 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1298
1299 /* Optimize MDIO transfer by suppressing preamble. */
1300 r = xm_read16(hw, port, XM_MMU_CMD);
1301 r |= XM_MMU_NO_PRE;
1302 xm_write16(hw, port, XM_MMU_CMD, r);
1303
1304 switch (id1) {
1305 case PHY_BCOM_ID1_C0:
1306 /*
1307 * Workaround BCOM Errata for the C0 type.
1308 * Write magic patterns to reserved registers.
1309 */
1310 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1311 xm_phy_write(hw, port,
1312 C0hack[i].reg, C0hack[i].val);
1313
1314 break;
1315 case PHY_BCOM_ID1_A1:
1316 /*
1317 * Workaround BCOM Errata for the A1 type.
1318 * Write magic patterns to reserved registers.
1319 */
1320 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1321 xm_phy_write(hw, port,
1322 A1hack[i].reg, A1hack[i].val);
1323 break;
1324 }
1325
1326 /*
1327 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1328 * Disable Power Management after reset.
1329 */
1330 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1331 r |= PHY_B_AC_DIS_PM;
1332 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1333
1334 /* Dummy read */
1335 xm_read16(hw, port, XM_ISRC);
1336
1337 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1338 ctl = PHY_CT_SP1000; /* always 1000mbit */
1339
1340 if (skge->autoneg == AUTONEG_ENABLE) {
1341 /*
1342 * Workaround BCOM Errata #1 for the C5 type.
1343 * 1000Base-T Link Acquisition Failure in Slave Mode
1344 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1345 */
1346 u16 adv = PHY_B_1000C_RD;
1347 if (skge->advertising & ADVERTISED_1000baseT_Half)
1348 adv |= PHY_B_1000C_AHD;
1349 if (skge->advertising & ADVERTISED_1000baseT_Full)
1350 adv |= PHY_B_1000C_AFD;
1351 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1352
1353 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1354 } else {
1355 if (skge->duplex == DUPLEX_FULL)
1356 ctl |= PHY_CT_DUP_MD;
1357 /* Force to slave */
1358 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1359 }
1360
1361 /* Set autonegotiation pause parameters */
1362 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1363 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1364
1365 /* Handle Jumbo frames */
1366 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1367 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1368 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1369
1370 ext |= PHY_B_PEC_HIGH_LA;
1371
1372 }
1373
1374 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1375 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1376
1377 /* Use link status change interrupt */
1378 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1379}
1380
1381static void xm_phy_init(struct skge_port *skge)
1382{
1383 struct skge_hw *hw = skge->hw;
1384 int port = skge->port;
1385 u16 ctrl = 0;
1386
1387 if (skge->autoneg == AUTONEG_ENABLE) {
1388 if (skge->advertising & ADVERTISED_1000baseT_Half)
1389 ctrl |= PHY_X_AN_HD;
1390 if (skge->advertising & ADVERTISED_1000baseT_Full)
1391 ctrl |= PHY_X_AN_FD;
1392
1393 ctrl |= fiber_pause_map[skge->flow_control];
1394
1395 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1396
1397 /* Restart Auto-negotiation */
1398 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1399 } else {
1400 /* Set DuplexMode in Config register */
1401 if (skge->duplex == DUPLEX_FULL)
1402 ctrl |= PHY_CT_DUP_MD;
1403 /*
1404 * Do NOT enable Auto-negotiation here. This would hold
1405 * the link down because no IDLEs are transmitted
1406 */
1407 }
1408
1409 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1410
1411 /* Poll PHY for status changes */
1412 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1413}
1414
1415static int xm_check_link(struct net_device *dev)
1416{
1417 struct skge_port *skge = netdev_priv(dev);
1418 struct skge_hw *hw = skge->hw;
1419 int port = skge->port;
1420 u16 status;
1421
1422 /* read twice because of latch */
1423 xm_phy_read(hw, port, PHY_XMAC_STAT);
1424 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1425
1426 if ((status & PHY_ST_LSYNC) == 0) {
1427 xm_link_down(hw, port);
1428 return 0;
1429 }
1430
1431 if (skge->autoneg == AUTONEG_ENABLE) {
1432 u16 lpa, res;
1433
1434 if (!(status & PHY_ST_AN_OVER))
1435 return 0;
1436
1437 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1438 if (lpa & PHY_B_AN_RF) {
1439 netdev_notice(dev, "remote fault\n");
1440 return 0;
1441 }
1442
1443 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1444
1445 /* Check Duplex mismatch */
1446 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1447 case PHY_X_RS_FD:
1448 skge->duplex = DUPLEX_FULL;
1449 break;
1450 case PHY_X_RS_HD:
1451 skge->duplex = DUPLEX_HALF;
1452 break;
1453 default:
1454 netdev_notice(dev, "duplex mismatch\n");
1455 return 0;
1456 }
1457
1458 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1459 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1460 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1461 (lpa & PHY_X_P_SYM_MD))
1462 skge->flow_status = FLOW_STAT_SYMMETRIC;
1463 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1464 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1465 /* Enable PAUSE receive, disable PAUSE transmit */
1466 skge->flow_status = FLOW_STAT_REM_SEND;
1467 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1468 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1469 /* Disable PAUSE receive, enable PAUSE transmit */
1470 skge->flow_status = FLOW_STAT_LOC_SEND;
1471 else
1472 skge->flow_status = FLOW_STAT_NONE;
1473
1474 skge->speed = SPEED_1000;
1475 }
1476
1477 if (!netif_carrier_ok(dev))
1478 genesis_link_up(skge);
1479 return 1;
1480}
1481
1482/* Poll to check for link coming up.
1483 *
1484 * Since internal PHY is wired to a level triggered pin, can't
1485 * get an interrupt when carrier is detected, need to poll for
1486 * link coming up.
1487 */
1488static void xm_link_timer(struct timer_list *t)
1489{
1490 struct skge_port *skge = from_timer(skge, t, link_timer);
1491 struct net_device *dev = skge->netdev;
1492 struct skge_hw *hw = skge->hw;
1493 int port = skge->port;
1494 int i;
1495 unsigned long flags;
1496
1497 if (!netif_running(dev))
1498 return;
1499
1500 spin_lock_irqsave(&hw->phy_lock, flags);
1501
1502 /*
1503 * Verify that the link by checking GPIO register three times.
1504 * This pin has the signal from the link_sync pin connected to it.
1505 */
1506 for (i = 0; i < 3; i++) {
1507 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1508 goto link_down;
1509 }
1510
1511 /* Re-enable interrupt to detect link down */
1512 if (xm_check_link(dev)) {
1513 u16 msk = xm_read16(hw, port, XM_IMSK);
1514 msk &= ~XM_IS_INP_ASS;
1515 xm_write16(hw, port, XM_IMSK, msk);
1516 xm_read16(hw, port, XM_ISRC);
1517 } else {
1518link_down:
1519 mod_timer(&skge->link_timer,
1520 round_jiffies(jiffies + LINK_HZ));
1521 }
1522 spin_unlock_irqrestore(&hw->phy_lock, flags);
1523}
1524
1525static void genesis_mac_init(struct skge_hw *hw, int port)
1526{
1527 struct net_device *dev = hw->dev[port];
1528 struct skge_port *skge = netdev_priv(dev);
1529 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1530 int i;
1531 u32 r;
1532 static const u8 zero[6] = { 0 };
1533
1534 for (i = 0; i < 10; i++) {
1535 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1536 MFF_SET_MAC_RST);
1537 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1538 goto reset_ok;
1539 udelay(1);
1540 }
1541
1542 netdev_warn(dev, "genesis reset failed\n");
1543
1544 reset_ok:
1545 /* Unreset the XMAC. */
1546 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1547
1548 /*
1549 * Perform additional initialization for external PHYs,
1550 * namely for the 1000baseTX cards that use the XMAC's
1551 * GMII mode.
1552 */
1553 if (hw->phy_type != SK_PHY_XMAC) {
1554 /* Take external Phy out of reset */
1555 r = skge_read32(hw, B2_GP_IO);
1556 if (port == 0)
1557 r |= GP_DIR_0|GP_IO_0;
1558 else
1559 r |= GP_DIR_2|GP_IO_2;
1560
1561 skge_write32(hw, B2_GP_IO, r);
1562
1563 /* Enable GMII interface */
1564 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1565 }
1566
1567
1568 switch (hw->phy_type) {
1569 case SK_PHY_XMAC:
1570 xm_phy_init(skge);
1571 break;
1572 case SK_PHY_BCOM:
1573 bcom_phy_init(skge);
1574 bcom_check_link(hw, port);
1575 }
1576
1577 /* Set Station Address */
1578 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1579
1580 /* We don't use match addresses so clear */
1581 for (i = 1; i < 16; i++)
1582 xm_outaddr(hw, port, XM_EXM(i), zero);
1583
1584 /* Clear MIB counters */
1585 xm_write16(hw, port, XM_STAT_CMD,
1586 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1587 /* Clear two times according to Errata #3 */
1588 xm_write16(hw, port, XM_STAT_CMD,
1589 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1590
1591 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1592 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1593
1594 /* We don't need the FCS appended to the packet. */
1595 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1596 if (jumbo)
1597 r |= XM_RX_BIG_PK_OK;
1598
1599 if (skge->duplex == DUPLEX_HALF) {
1600 /*
1601 * If in manual half duplex mode the other side might be in
1602 * full duplex mode, so ignore if a carrier extension is not seen
1603 * on frames received
1604 */
1605 r |= XM_RX_DIS_CEXT;
1606 }
1607 xm_write16(hw, port, XM_RX_CMD, r);
1608
1609 /* We want short frames padded to 60 bytes. */
1610 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1611
1612 /* Increase threshold for jumbo frames on dual port */
1613 if (hw->ports > 1 && jumbo)
1614 xm_write16(hw, port, XM_TX_THR, 1020);
1615 else
1616 xm_write16(hw, port, XM_TX_THR, 512);
1617
1618 /*
1619 * Enable the reception of all error frames. This is is
1620 * a necessary evil due to the design of the XMAC. The
1621 * XMAC's receive FIFO is only 8K in size, however jumbo
1622 * frames can be up to 9000 bytes in length. When bad
1623 * frame filtering is enabled, the XMAC's RX FIFO operates
1624 * in 'store and forward' mode. For this to work, the
1625 * entire frame has to fit into the FIFO, but that means
1626 * that jumbo frames larger than 8192 bytes will be
1627 * truncated. Disabling all bad frame filtering causes
1628 * the RX FIFO to operate in streaming mode, in which
1629 * case the XMAC will start transferring frames out of the
1630 * RX FIFO as soon as the FIFO threshold is reached.
1631 */
1632 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1633
1634
1635 /*
1636 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1637 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1638 * and 'Octets Rx OK Hi Cnt Ov'.
1639 */
1640 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1641
1642 /*
1643 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1644 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1645 * and 'Octets Tx OK Hi Cnt Ov'.
1646 */
1647 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1648
1649 /* Configure MAC arbiter */
1650 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1651
1652 /* configure timeout values */
1653 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1654 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1655 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1656 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1657
1658 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1659 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1660 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1661 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1662
1663 /* Configure Rx MAC FIFO */
1664 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1665 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1666 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1667
1668 /* Configure Tx MAC FIFO */
1669 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1670 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1671 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1672
1673 if (jumbo) {
1674 /* Enable frame flushing if jumbo frames used */
1675 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
1676 } else {
1677 /* enable timeout timers if normal frames */
1678 skge_write16(hw, B3_PA_CTRL,
1679 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1680 }
1681}
1682
1683static void genesis_stop(struct skge_port *skge)
1684{
1685 struct skge_hw *hw = skge->hw;
1686 int port = skge->port;
1687 unsigned retries = 1000;
1688 u16 cmd;
1689
1690 /* Disable Tx and Rx */
1691 cmd = xm_read16(hw, port, XM_MMU_CMD);
1692 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1693 xm_write16(hw, port, XM_MMU_CMD, cmd);
1694
1695 genesis_reset(hw, port);
1696
1697 /* Clear Tx packet arbiter timeout IRQ */
1698 skge_write16(hw, B3_PA_CTRL,
1699 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1700
1701 /* Reset the MAC */
1702 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1703 do {
1704 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1705 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1706 break;
1707 } while (--retries > 0);
1708
1709 /* For external PHYs there must be special handling */
1710 if (hw->phy_type != SK_PHY_XMAC) {
1711 u32 reg = skge_read32(hw, B2_GP_IO);
1712 if (port == 0) {
1713 reg |= GP_DIR_0;
1714 reg &= ~GP_IO_0;
1715 } else {
1716 reg |= GP_DIR_2;
1717 reg &= ~GP_IO_2;
1718 }
1719 skge_write32(hw, B2_GP_IO, reg);
1720 skge_read32(hw, B2_GP_IO);
1721 }
1722
1723 xm_write16(hw, port, XM_MMU_CMD,
1724 xm_read16(hw, port, XM_MMU_CMD)
1725 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1726
1727 xm_read16(hw, port, XM_MMU_CMD);
1728}
1729
1730
1731static void genesis_get_stats(struct skge_port *skge, u64 *data)
1732{
1733 struct skge_hw *hw = skge->hw;
1734 int port = skge->port;
1735 int i;
1736 unsigned long timeout = jiffies + HZ;
1737
1738 xm_write16(hw, port,
1739 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1740
1741 /* wait for update to complete */
1742 while (xm_read16(hw, port, XM_STAT_CMD)
1743 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1744 if (time_after(jiffies, timeout))
1745 break;
1746 udelay(10);
1747 }
1748
1749 /* special case for 64 bit octet counter */
1750 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1751 | xm_read32(hw, port, XM_TXO_OK_LO);
1752 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1753 | xm_read32(hw, port, XM_RXO_OK_LO);
1754
1755 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1756 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1757}
1758
1759static void genesis_mac_intr(struct skge_hw *hw, int port)
1760{
1761 struct net_device *dev = hw->dev[port];
1762 struct skge_port *skge = netdev_priv(dev);
1763 u16 status = xm_read16(hw, port, XM_ISRC);
1764
1765 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1766 "mac interrupt status 0x%x\n", status);
1767
1768 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1769 xm_link_down(hw, port);
1770 mod_timer(&skge->link_timer, jiffies + 1);
1771 }
1772
1773 if (status & XM_IS_TXF_UR) {
1774 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1775 ++dev->stats.tx_fifo_errors;
1776 }
1777}
1778
1779static void genesis_link_up(struct skge_port *skge)
1780{
1781 struct skge_hw *hw = skge->hw;
1782 int port = skge->port;
1783 u16 cmd, msk;
1784 u32 mode;
1785
1786 cmd = xm_read16(hw, port, XM_MMU_CMD);
1787
1788 /*
1789 * enabling pause frame reception is required for 1000BT
1790 * because the XMAC is not reset if the link is going down
1791 */
1792 if (skge->flow_status == FLOW_STAT_NONE ||
1793 skge->flow_status == FLOW_STAT_LOC_SEND)
1794 /* Disable Pause Frame Reception */
1795 cmd |= XM_MMU_IGN_PF;
1796 else
1797 /* Enable Pause Frame Reception */
1798 cmd &= ~XM_MMU_IGN_PF;
1799
1800 xm_write16(hw, port, XM_MMU_CMD, cmd);
1801
1802 mode = xm_read32(hw, port, XM_MODE);
1803 if (skge->flow_status == FLOW_STAT_SYMMETRIC ||
1804 skge->flow_status == FLOW_STAT_LOC_SEND) {
1805 /*
1806 * Configure Pause Frame Generation
1807 * Use internal and external Pause Frame Generation.
1808 * Sending pause frames is edge triggered.
1809 * Send a Pause frame with the maximum pause time if
1810 * internal oder external FIFO full condition occurs.
1811 * Send a zero pause time frame to re-start transmission.
1812 */
1813 /* XM_PAUSE_DA = '010000C28001' (default) */
1814 /* XM_MAC_PTIME = 0xffff (maximum) */
1815 /* remember this value is defined in big endian (!) */
1816 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1817
1818 mode |= XM_PAUSE_MODE;
1819 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1820 } else {
1821 /*
1822 * disable pause frame generation is required for 1000BT
1823 * because the XMAC is not reset if the link is going down
1824 */
1825 /* Disable Pause Mode in Mode Register */
1826 mode &= ~XM_PAUSE_MODE;
1827
1828 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1829 }
1830
1831 xm_write32(hw, port, XM_MODE, mode);
1832
1833 /* Turn on detection of Tx underrun */
1834 msk = xm_read16(hw, port, XM_IMSK);
1835 msk &= ~XM_IS_TXF_UR;
1836 xm_write16(hw, port, XM_IMSK, msk);
1837
1838 xm_read16(hw, port, XM_ISRC);
1839
1840 /* get MMU Command Reg. */
1841 cmd = xm_read16(hw, port, XM_MMU_CMD);
1842 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1843 cmd |= XM_MMU_GMII_FD;
1844
1845 /*
1846 * Workaround BCOM Errata (#10523) for all BCom Phys
1847 * Enable Power Management after link up
1848 */
1849 if (hw->phy_type == SK_PHY_BCOM) {
1850 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1851 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1852 & ~PHY_B_AC_DIS_PM);
1853 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1854 }
1855
1856 /* enable Rx/Tx */
1857 xm_write16(hw, port, XM_MMU_CMD,
1858 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1859 skge_link_up(skge);
1860}
1861
1862
1863static inline void bcom_phy_intr(struct skge_port *skge)
1864{
1865 struct skge_hw *hw = skge->hw;
1866 int port = skge->port;
1867 u16 isrc;
1868
1869 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1870 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1871 "phy interrupt status 0x%x\n", isrc);
1872
1873 if (isrc & PHY_B_IS_PSE)
1874 pr_err("%s: uncorrectable pair swap error\n",
1875 hw->dev[port]->name);
1876
1877 /* Workaround BCom Errata:
1878 * enable and disable loopback mode if "NO HCD" occurs.
1879 */
1880 if (isrc & PHY_B_IS_NO_HDCL) {
1881 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1882 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1883 ctrl | PHY_CT_LOOP);
1884 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1885 ctrl & ~PHY_CT_LOOP);
1886 }
1887
1888 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1889 bcom_check_link(hw, port);
1890
1891}
1892
1893static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1894{
1895 int i;
1896
1897 gma_write16(hw, port, GM_SMI_DATA, val);
1898 gma_write16(hw, port, GM_SMI_CTRL,
1899 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1900 for (i = 0; i < PHY_RETRIES; i++) {
1901 udelay(1);
1902
1903 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1904 return 0;
1905 }
1906
1907 pr_warn("%s: phy write timeout\n", hw->dev[port]->name);
1908 return -EIO;
1909}
1910
1911static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1912{
1913 int i;
1914
1915 gma_write16(hw, port, GM_SMI_CTRL,
1916 GM_SMI_CT_PHY_AD(hw->phy_addr)
1917 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1918
1919 for (i = 0; i < PHY_RETRIES; i++) {
1920 udelay(1);
1921 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1922 goto ready;
1923 }
1924
1925 return -ETIMEDOUT;
1926 ready:
1927 *val = gma_read16(hw, port, GM_SMI_DATA);
1928 return 0;
1929}
1930
1931static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1932{
1933 u16 v = 0;
1934 if (__gm_phy_read(hw, port, reg, &v))
1935 pr_warn("%s: phy read timeout\n", hw->dev[port]->name);
1936 return v;
1937}
1938
1939/* Marvell Phy Initialization */
1940static void yukon_init(struct skge_hw *hw, int port)
1941{
1942 struct skge_port *skge = netdev_priv(hw->dev[port]);
1943 u16 ctrl, ct1000, adv;
1944
1945 if (skge->autoneg == AUTONEG_ENABLE) {
1946 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1947
1948 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1949 PHY_M_EC_MAC_S_MSK);
1950 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1951
1952 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1953
1954 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1955 }
1956
1957 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1958 if (skge->autoneg == AUTONEG_DISABLE)
1959 ctrl &= ~PHY_CT_ANE;
1960
1961 ctrl |= PHY_CT_RESET;
1962 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1963
1964 ctrl = 0;
1965 ct1000 = 0;
1966 adv = PHY_AN_CSMA;
1967
1968 if (skge->autoneg == AUTONEG_ENABLE) {
1969 if (hw->copper) {
1970 if (skge->advertising & ADVERTISED_1000baseT_Full)
1971 ct1000 |= PHY_M_1000C_AFD;
1972 if (skge->advertising & ADVERTISED_1000baseT_Half)
1973 ct1000 |= PHY_M_1000C_AHD;
1974 if (skge->advertising & ADVERTISED_100baseT_Full)
1975 adv |= PHY_M_AN_100_FD;
1976 if (skge->advertising & ADVERTISED_100baseT_Half)
1977 adv |= PHY_M_AN_100_HD;
1978 if (skge->advertising & ADVERTISED_10baseT_Full)
1979 adv |= PHY_M_AN_10_FD;
1980 if (skge->advertising & ADVERTISED_10baseT_Half)
1981 adv |= PHY_M_AN_10_HD;
1982
1983 /* Set Flow-control capabilities */
1984 adv |= phy_pause_map[skge->flow_control];
1985 } else {
1986 if (skge->advertising & ADVERTISED_1000baseT_Full)
1987 adv |= PHY_M_AN_1000X_AFD;
1988 if (skge->advertising & ADVERTISED_1000baseT_Half)
1989 adv |= PHY_M_AN_1000X_AHD;
1990
1991 adv |= fiber_pause_map[skge->flow_control];
1992 }
1993
1994 /* Restart Auto-negotiation */
1995 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1996 } else {
1997 /* forced speed/duplex settings */
1998 ct1000 = PHY_M_1000C_MSE;
1999
2000 if (skge->duplex == DUPLEX_FULL)
2001 ctrl |= PHY_CT_DUP_MD;
2002
2003 switch (skge->speed) {
2004 case SPEED_1000:
2005 ctrl |= PHY_CT_SP1000;
2006 break;
2007 case SPEED_100:
2008 ctrl |= PHY_CT_SP100;
2009 break;
2010 }
2011
2012 ctrl |= PHY_CT_RESET;
2013 }
2014
2015 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2016
2017 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2018 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2019
2020 /* Enable phy interrupt on autonegotiation complete (or link up) */
2021 if (skge->autoneg == AUTONEG_ENABLE)
2022 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2023 else
2024 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2025}
2026
2027static void yukon_reset(struct skge_hw *hw, int port)
2028{
2029 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2030 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2031 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2032 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2033 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2034
2035 gma_write16(hw, port, GM_RX_CTRL,
2036 gma_read16(hw, port, GM_RX_CTRL)
2037 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2038}
2039
2040/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2041static int is_yukon_lite_a0(struct skge_hw *hw)
2042{
2043 u32 reg;
2044 int ret;
2045
2046 if (hw->chip_id != CHIP_ID_YUKON)
2047 return 0;
2048
2049 reg = skge_read32(hw, B2_FAR);
2050 skge_write8(hw, B2_FAR + 3, 0xff);
2051 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2052 skge_write32(hw, B2_FAR, reg);
2053 return ret;
2054}
2055
2056static void yukon_mac_init(struct skge_hw *hw, int port)
2057{
2058 struct skge_port *skge = netdev_priv(hw->dev[port]);
2059 int i;
2060 u32 reg;
2061 const u8 *addr = hw->dev[port]->dev_addr;
2062
2063 /* WA code for COMA mode -- set PHY reset */
2064 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2065 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2066 reg = skge_read32(hw, B2_GP_IO);
2067 reg |= GP_DIR_9 | GP_IO_9;
2068 skge_write32(hw, B2_GP_IO, reg);
2069 }
2070
2071 /* hard reset */
2072 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2073 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2074
2075 /* WA code for COMA mode -- clear PHY reset */
2076 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2077 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2078 reg = skge_read32(hw, B2_GP_IO);
2079 reg |= GP_DIR_9;
2080 reg &= ~GP_IO_9;
2081 skge_write32(hw, B2_GP_IO, reg);
2082 }
2083
2084 /* Set hardware config mode */
2085 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2086 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2087 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2088
2089 /* Clear GMC reset */
2090 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2091 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2092 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2093
2094 if (skge->autoneg == AUTONEG_DISABLE) {
2095 reg = GM_GPCR_AU_ALL_DIS;
2096 gma_write16(hw, port, GM_GP_CTRL,
2097 gma_read16(hw, port, GM_GP_CTRL) | reg);
2098
2099 switch (skge->speed) {
2100 case SPEED_1000:
2101 reg &= ~GM_GPCR_SPEED_100;
2102 reg |= GM_GPCR_SPEED_1000;
2103 break;
2104 case SPEED_100:
2105 reg &= ~GM_GPCR_SPEED_1000;
2106 reg |= GM_GPCR_SPEED_100;
2107 break;
2108 case SPEED_10:
2109 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2110 break;
2111 }
2112
2113 if (skge->duplex == DUPLEX_FULL)
2114 reg |= GM_GPCR_DUP_FULL;
2115 } else
2116 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2117
2118 switch (skge->flow_control) {
2119 case FLOW_MODE_NONE:
2120 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2121 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2122 break;
2123 case FLOW_MODE_LOC_SEND:
2124 /* disable Rx flow-control */
2125 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2126 break;
2127 case FLOW_MODE_SYMMETRIC:
2128 case FLOW_MODE_SYM_OR_REM:
2129 /* enable Tx & Rx flow-control */
2130 break;
2131 }
2132
2133 gma_write16(hw, port, GM_GP_CTRL, reg);
2134 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2135
2136 yukon_init(hw, port);
2137
2138 /* MIB clear */
2139 reg = gma_read16(hw, port, GM_PHY_ADDR);
2140 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2141
2142 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2143 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2144 gma_write16(hw, port, GM_PHY_ADDR, reg);
2145
2146 /* transmit control */
2147 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2148
2149 /* receive control reg: unicast + multicast + no FCS */
2150 gma_write16(hw, port, GM_RX_CTRL,
2151 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2152
2153 /* transmit flow control */
2154 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2155
2156 /* transmit parameter */
2157 gma_write16(hw, port, GM_TX_PARAM,
2158 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2159 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2160 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2161
2162 /* configure the Serial Mode Register */
2163 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2164 | GM_SMOD_VLAN_ENA
2165 | IPG_DATA_VAL(IPG_DATA_DEF);
2166
2167 if (hw->dev[port]->mtu > ETH_DATA_LEN)
2168 reg |= GM_SMOD_JUMBO_ENA;
2169
2170 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2171
2172 /* physical address: used for pause frames */
2173 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2174 /* virtual address for data */
2175 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2176
2177 /* enable interrupt mask for counter overflows */
2178 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2179 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2180 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2181
2182 /* Initialize Mac Fifo */
2183
2184 /* Configure Rx MAC FIFO */
2185 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2186 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2187
2188 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2189 if (is_yukon_lite_a0(hw))
2190 reg &= ~GMF_RX_F_FL_ON;
2191
2192 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2193 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2194 /*
2195 * because Pause Packet Truncation in GMAC is not working
2196 * we have to increase the Flush Threshold to 64 bytes
2197 * in order to flush pause packets in Rx FIFO on Yukon-1
2198 */
2199 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2200
2201 /* Configure Tx MAC FIFO */
2202 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2203 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2204}
2205
2206/* Go into power down mode */
2207static void yukon_suspend(struct skge_hw *hw, int port)
2208{
2209 u16 ctrl;
2210
2211 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2212 ctrl |= PHY_M_PC_POL_R_DIS;
2213 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2214
2215 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2216 ctrl |= PHY_CT_RESET;
2217 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2218
2219 /* switch IEEE compatible power down mode on */
2220 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2221 ctrl |= PHY_CT_PDOWN;
2222 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2223}
2224
2225static void yukon_stop(struct skge_port *skge)
2226{
2227 struct skge_hw *hw = skge->hw;
2228 int port = skge->port;
2229
2230 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2231 yukon_reset(hw, port);
2232
2233 gma_write16(hw, port, GM_GP_CTRL,
2234 gma_read16(hw, port, GM_GP_CTRL)
2235 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2236 gma_read16(hw, port, GM_GP_CTRL);
2237
2238 yukon_suspend(hw, port);
2239
2240 /* set GPHY Control reset */
2241 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2242 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2243}
2244
2245static void yukon_get_stats(struct skge_port *skge, u64 *data)
2246{
2247 struct skge_hw *hw = skge->hw;
2248 int port = skge->port;
2249 int i;
2250
2251 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2252 | gma_read32(hw, port, GM_TXO_OK_LO);
2253 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2254 | gma_read32(hw, port, GM_RXO_OK_LO);
2255
2256 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2257 data[i] = gma_read32(hw, port,
2258 skge_stats[i].gma_offset);
2259}
2260
2261static void yukon_mac_intr(struct skge_hw *hw, int port)
2262{
2263 struct net_device *dev = hw->dev[port];
2264 struct skge_port *skge = netdev_priv(dev);
2265 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2266
2267 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2268 "mac interrupt status 0x%x\n", status);
2269
2270 if (status & GM_IS_RX_FF_OR) {
2271 ++dev->stats.rx_fifo_errors;
2272 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2273 }
2274
2275 if (status & GM_IS_TX_FF_UR) {
2276 ++dev->stats.tx_fifo_errors;
2277 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2278 }
2279
2280}
2281
2282static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2283{
2284 switch (aux & PHY_M_PS_SPEED_MSK) {
2285 case PHY_M_PS_SPEED_1000:
2286 return SPEED_1000;
2287 case PHY_M_PS_SPEED_100:
2288 return SPEED_100;
2289 default:
2290 return SPEED_10;
2291 }
2292}
2293
2294static void yukon_link_up(struct skge_port *skge)
2295{
2296 struct skge_hw *hw = skge->hw;
2297 int port = skge->port;
2298 u16 reg;
2299
2300 /* Enable Transmit FIFO Underrun */
2301 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2302
2303 reg = gma_read16(hw, port, GM_GP_CTRL);
2304 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2305 reg |= GM_GPCR_DUP_FULL;
2306
2307 /* enable Rx/Tx */
2308 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2309 gma_write16(hw, port, GM_GP_CTRL, reg);
2310
2311 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2312 skge_link_up(skge);
2313}
2314
2315static void yukon_link_down(struct skge_port *skge)
2316{
2317 struct skge_hw *hw = skge->hw;
2318 int port = skge->port;
2319 u16 ctrl;
2320
2321 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2322 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2323 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2324
2325 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2326 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2327 ctrl |= PHY_M_AN_ASP;
2328 /* restore Asymmetric Pause bit */
2329 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2330 }
2331
2332 skge_link_down(skge);
2333
2334 yukon_init(hw, port);
2335}
2336
2337static void yukon_phy_intr(struct skge_port *skge)
2338{
2339 struct skge_hw *hw = skge->hw;
2340 int port = skge->port;
2341 const char *reason = NULL;
2342 u16 istatus, phystat;
2343
2344 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2345 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2346
2347 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2348 "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
2349
2350 if (istatus & PHY_M_IS_AN_COMPL) {
2351 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2352 & PHY_M_AN_RF) {
2353 reason = "remote fault";
2354 goto failed;
2355 }
2356
2357 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2358 reason = "master/slave fault";
2359 goto failed;
2360 }
2361
2362 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2363 reason = "speed/duplex";
2364 goto failed;
2365 }
2366
2367 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2368 ? DUPLEX_FULL : DUPLEX_HALF;
2369 skge->speed = yukon_speed(hw, phystat);
2370
2371 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2372 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2373 case PHY_M_PS_PAUSE_MSK:
2374 skge->flow_status = FLOW_STAT_SYMMETRIC;
2375 break;
2376 case PHY_M_PS_RX_P_EN:
2377 skge->flow_status = FLOW_STAT_REM_SEND;
2378 break;
2379 case PHY_M_PS_TX_P_EN:
2380 skge->flow_status = FLOW_STAT_LOC_SEND;
2381 break;
2382 default:
2383 skge->flow_status = FLOW_STAT_NONE;
2384 }
2385
2386 if (skge->flow_status == FLOW_STAT_NONE ||
2387 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2388 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2389 else
2390 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2391 yukon_link_up(skge);
2392 return;
2393 }
2394
2395 if (istatus & PHY_M_IS_LSP_CHANGE)
2396 skge->speed = yukon_speed(hw, phystat);
2397
2398 if (istatus & PHY_M_IS_DUP_CHANGE)
2399 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2400 if (istatus & PHY_M_IS_LST_CHANGE) {
2401 if (phystat & PHY_M_PS_LINK_UP)
2402 yukon_link_up(skge);
2403 else
2404 yukon_link_down(skge);
2405 }
2406 return;
2407 failed:
2408 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason);
2409
2410 /* XXX restart autonegotiation? */
2411}
2412
2413static void skge_phy_reset(struct skge_port *skge)
2414{
2415 struct skge_hw *hw = skge->hw;
2416 int port = skge->port;
2417 struct net_device *dev = hw->dev[port];
2418
2419 netif_stop_queue(skge->netdev);
2420 netif_carrier_off(skge->netdev);
2421
2422 spin_lock_bh(&hw->phy_lock);
2423 if (is_genesis(hw)) {
2424 genesis_reset(hw, port);
2425 genesis_mac_init(hw, port);
2426 } else {
2427 yukon_reset(hw, port);
2428 yukon_init(hw, port);
2429 }
2430 spin_unlock_bh(&hw->phy_lock);
2431
2432 skge_set_multicast(dev);
2433}
2434
2435/* Basic MII support */
2436static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2437{
2438 struct mii_ioctl_data *data = if_mii(ifr);
2439 struct skge_port *skge = netdev_priv(dev);
2440 struct skge_hw *hw = skge->hw;
2441 int err = -EOPNOTSUPP;
2442
2443 if (!netif_running(dev))
2444 return -ENODEV; /* Phy still in reset */
2445
2446 switch (cmd) {
2447 case SIOCGMIIPHY:
2448 data->phy_id = hw->phy_addr;
2449
2450 /* fallthru */
2451 case SIOCGMIIREG: {
2452 u16 val = 0;
2453 spin_lock_bh(&hw->phy_lock);
2454
2455 if (is_genesis(hw))
2456 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2457 else
2458 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2459 spin_unlock_bh(&hw->phy_lock);
2460 data->val_out = val;
2461 break;
2462 }
2463
2464 case SIOCSMIIREG:
2465 spin_lock_bh(&hw->phy_lock);
2466 if (is_genesis(hw))
2467 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2468 data->val_in);
2469 else
2470 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2471 data->val_in);
2472 spin_unlock_bh(&hw->phy_lock);
2473 break;
2474 }
2475 return err;
2476}
2477
2478static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2479{
2480 u32 end;
2481
2482 start /= 8;
2483 len /= 8;
2484 end = start + len - 1;
2485
2486 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2487 skge_write32(hw, RB_ADDR(q, RB_START), start);
2488 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2489 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2490 skge_write32(hw, RB_ADDR(q, RB_END), end);
2491
2492 if (q == Q_R1 || q == Q_R2) {
2493 /* Set thresholds on receive queue's */
2494 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2495 start + (2*len)/3);
2496 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2497 start + (len/3));
2498 } else {
2499 /* Enable store & forward on Tx queue's because
2500 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2501 */
2502 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2503 }
2504
2505 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2506}
2507
2508/* Setup Bus Memory Interface */
2509static void skge_qset(struct skge_port *skge, u16 q,
2510 const struct skge_element *e)
2511{
2512 struct skge_hw *hw = skge->hw;
2513 u32 watermark = 0x600;
2514 u64 base = skge->dma + (e->desc - skge->mem);
2515
2516 /* optimization to reduce window on 32bit/33mhz */
2517 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2518 watermark /= 2;
2519
2520 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2521 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2522 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2523 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2524}
2525
2526static int skge_up(struct net_device *dev)
2527{
2528 struct skge_port *skge = netdev_priv(dev);
2529 struct skge_hw *hw = skge->hw;
2530 int port = skge->port;
2531 u32 chunk, ram_addr;
2532 size_t rx_size, tx_size;
2533 int err;
2534
2535 if (!is_valid_ether_addr(dev->dev_addr))
2536 return -EINVAL;
2537
2538 netif_info(skge, ifup, skge->netdev, "enabling interface\n");
2539
2540 if (dev->mtu > RX_BUF_SIZE)
2541 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2542 else
2543 skge->rx_buf_size = RX_BUF_SIZE;
2544
2545
2546 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2547 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2548 skge->mem_size = tx_size + rx_size;
2549 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2550 if (!skge->mem)
2551 return -ENOMEM;
2552
2553 BUG_ON(skge->dma & 7);
2554
2555 if (upper_32_bits(skge->dma) != upper_32_bits(skge->dma + skge->mem_size)) {
2556 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2557 err = -EINVAL;
2558 goto free_pci_mem;
2559 }
2560
2561 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2562 if (err)
2563 goto free_pci_mem;
2564
2565 err = skge_rx_fill(dev);
2566 if (err)
2567 goto free_rx_ring;
2568
2569 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2570 skge->dma + rx_size);
2571 if (err)
2572 goto free_rx_ring;
2573
2574 if (hw->ports == 1) {
2575 err = request_irq(hw->pdev->irq, skge_intr, IRQF_SHARED,
2576 dev->name, hw);
2577 if (err) {
2578 netdev_err(dev, "Unable to allocate interrupt %d error: %d\n",
2579 hw->pdev->irq, err);
2580 goto free_tx_ring;
2581 }
2582 }
2583
2584 /* Initialize MAC */
2585 netif_carrier_off(dev);
2586 spin_lock_bh(&hw->phy_lock);
2587 if (is_genesis(hw))
2588 genesis_mac_init(hw, port);
2589 else
2590 yukon_mac_init(hw, port);
2591 spin_unlock_bh(&hw->phy_lock);
2592
2593 /* Configure RAMbuffers - equally between ports and tx/rx */
2594 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
2595 ram_addr = hw->ram_offset + 2 * chunk * port;
2596
2597 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2598 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2599
2600 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2601 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2602 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2603
2604 /* Start receiver BMU */
2605 wmb();
2606 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2607 skge_led(skge, LED_MODE_ON);
2608
2609 spin_lock_irq(&hw->hw_lock);
2610 hw->intr_mask |= portmask[port];
2611 skge_write32(hw, B0_IMSK, hw->intr_mask);
2612 skge_read32(hw, B0_IMSK);
2613 spin_unlock_irq(&hw->hw_lock);
2614
2615 napi_enable(&skge->napi);
2616
2617 skge_set_multicast(dev);
2618
2619 return 0;
2620
2621 free_tx_ring:
2622 kfree(skge->tx_ring.start);
2623 free_rx_ring:
2624 skge_rx_clean(skge);
2625 kfree(skge->rx_ring.start);
2626 free_pci_mem:
2627 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2628 skge->mem = NULL;
2629
2630 return err;
2631}
2632
2633/* stop receiver */
2634static void skge_rx_stop(struct skge_hw *hw, int port)
2635{
2636 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2637 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2638 RB_RST_SET|RB_DIS_OP_MD);
2639 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2640}
2641
2642static int skge_down(struct net_device *dev)
2643{
2644 struct skge_port *skge = netdev_priv(dev);
2645 struct skge_hw *hw = skge->hw;
2646 int port = skge->port;
2647
2648 if (!skge->mem)
2649 return 0;
2650
2651 netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
2652
2653 netif_tx_disable(dev);
2654
2655 if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)
2656 del_timer_sync(&skge->link_timer);
2657
2658 napi_disable(&skge->napi);
2659 netif_carrier_off(dev);
2660
2661 spin_lock_irq(&hw->hw_lock);
2662 hw->intr_mask &= ~portmask[port];
2663 skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask);
2664 skge_read32(hw, B0_IMSK);
2665 spin_unlock_irq(&hw->hw_lock);
2666
2667 if (hw->ports == 1)
2668 free_irq(hw->pdev->irq, hw);
2669
2670 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
2671 if (is_genesis(hw))
2672 genesis_stop(skge);
2673 else
2674 yukon_stop(skge);
2675
2676 /* Stop transmitter */
2677 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2678 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2679 RB_RST_SET|RB_DIS_OP_MD);
2680
2681
2682 /* Disable Force Sync bit and Enable Alloc bit */
2683 skge_write8(hw, SK_REG(port, TXA_CTRL),
2684 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2685
2686 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2687 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2688 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2689
2690 /* Reset PCI FIFO */
2691 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2692 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2693
2694 /* Reset the RAM Buffer async Tx queue */
2695 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2696
2697 skge_rx_stop(hw, port);
2698
2699 if (is_genesis(hw)) {
2700 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2701 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2702 } else {
2703 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2704 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2705 }
2706
2707 skge_led(skge, LED_MODE_OFF);
2708
2709 netif_tx_lock_bh(dev);
2710 skge_tx_clean(dev);
2711 netif_tx_unlock_bh(dev);
2712
2713 skge_rx_clean(skge);
2714
2715 kfree(skge->rx_ring.start);
2716 kfree(skge->tx_ring.start);
2717 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2718 skge->mem = NULL;
2719 return 0;
2720}
2721
2722static inline int skge_avail(const struct skge_ring *ring)
2723{
2724 smp_mb();
2725 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2726 + (ring->to_clean - ring->to_use) - 1;
2727}
2728
2729static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2730 struct net_device *dev)
2731{
2732 struct skge_port *skge = netdev_priv(dev);
2733 struct skge_hw *hw = skge->hw;
2734 struct skge_element *e;
2735 struct skge_tx_desc *td;
2736 int i;
2737 u32 control, len;
2738 dma_addr_t map;
2739
2740 if (skb_padto(skb, ETH_ZLEN))
2741 return NETDEV_TX_OK;
2742
2743 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2744 return NETDEV_TX_BUSY;
2745
2746 e = skge->tx_ring.to_use;
2747 td = e->desc;
2748 BUG_ON(td->control & BMU_OWN);
2749 e->skb = skb;
2750 len = skb_headlen(skb);
2751 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2752 if (pci_dma_mapping_error(hw->pdev, map))
2753 goto mapping_error;
2754
2755 dma_unmap_addr_set(e, mapaddr, map);
2756 dma_unmap_len_set(e, maplen, len);
2757
2758 td->dma_lo = lower_32_bits(map);
2759 td->dma_hi = upper_32_bits(map);
2760
2761 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2762 const int offset = skb_checksum_start_offset(skb);
2763
2764 /* This seems backwards, but it is what the sk98lin
2765 * does. Looks like hardware is wrong?
2766 */
2767 if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
2768 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2769 control = BMU_TCP_CHECK;
2770 else
2771 control = BMU_UDP_CHECK;
2772
2773 td->csum_offs = 0;
2774 td->csum_start = offset;
2775 td->csum_write = offset + skb->csum_offset;
2776 } else
2777 control = BMU_CHECK;
2778
2779 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2780 control |= BMU_EOF | BMU_IRQ_EOF;
2781 else {
2782 struct skge_tx_desc *tf = td;
2783
2784 control |= BMU_STFWD;
2785 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2786 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2787
2788 map = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
2789 skb_frag_size(frag), DMA_TO_DEVICE);
2790 if (dma_mapping_error(&hw->pdev->dev, map))
2791 goto mapping_unwind;
2792
2793 e = e->next;
2794 e->skb = skb;
2795 tf = e->desc;
2796 BUG_ON(tf->control & BMU_OWN);
2797
2798 tf->dma_lo = lower_32_bits(map);
2799 tf->dma_hi = upper_32_bits(map);
2800 dma_unmap_addr_set(e, mapaddr, map);
2801 dma_unmap_len_set(e, maplen, skb_frag_size(frag));
2802
2803 tf->control = BMU_OWN | BMU_SW | control | skb_frag_size(frag);
2804 }
2805 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2806 }
2807 /* Make sure all the descriptors written */
2808 wmb();
2809 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2810 wmb();
2811
2812 netdev_sent_queue(dev, skb->len);
2813
2814 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2815
2816 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
2817 "tx queued, slot %td, len %d\n",
2818 e - skge->tx_ring.start, skb->len);
2819
2820 skge->tx_ring.to_use = e->next;
2821 smp_wmb();
2822
2823 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2824 netdev_dbg(dev, "transmit queue full\n");
2825 netif_stop_queue(dev);
2826 }
2827
2828 return NETDEV_TX_OK;
2829
2830mapping_unwind:
2831 e = skge->tx_ring.to_use;
2832 pci_unmap_single(hw->pdev,
2833 dma_unmap_addr(e, mapaddr),
2834 dma_unmap_len(e, maplen),
2835 PCI_DMA_TODEVICE);
2836 while (i-- > 0) {
2837 e = e->next;
2838 pci_unmap_page(hw->pdev,
2839 dma_unmap_addr(e, mapaddr),
2840 dma_unmap_len(e, maplen),
2841 PCI_DMA_TODEVICE);
2842 }
2843
2844mapping_error:
2845 if (net_ratelimit())
2846 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
2847 dev_kfree_skb_any(skb);
2848 return NETDEV_TX_OK;
2849}
2850
2851
2852/* Free resources associated with this reing element */
2853static inline void skge_tx_unmap(struct pci_dev *pdev, struct skge_element *e,
2854 u32 control)
2855{
2856 /* skb header vs. fragment */
2857 if (control & BMU_STF)
2858 pci_unmap_single(pdev, dma_unmap_addr(e, mapaddr),
2859 dma_unmap_len(e, maplen),
2860 PCI_DMA_TODEVICE);
2861 else
2862 pci_unmap_page(pdev, dma_unmap_addr(e, mapaddr),
2863 dma_unmap_len(e, maplen),
2864 PCI_DMA_TODEVICE);
2865}
2866
2867/* Free all buffers in transmit ring */
2868static void skge_tx_clean(struct net_device *dev)
2869{
2870 struct skge_port *skge = netdev_priv(dev);
2871 struct skge_element *e;
2872
2873 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2874 struct skge_tx_desc *td = e->desc;
2875
2876 skge_tx_unmap(skge->hw->pdev, e, td->control);
2877
2878 if (td->control & BMU_EOF)
2879 dev_kfree_skb(e->skb);
2880 td->control = 0;
2881 }
2882
2883 netdev_reset_queue(dev);
2884 skge->tx_ring.to_clean = e;
2885}
2886
2887static void skge_tx_timeout(struct net_device *dev)
2888{
2889 struct skge_port *skge = netdev_priv(dev);
2890
2891 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
2892
2893 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2894 skge_tx_clean(dev);
2895 netif_wake_queue(dev);
2896}
2897
2898static int skge_change_mtu(struct net_device *dev, int new_mtu)
2899{
2900 int err;
2901
2902 if (!netif_running(dev)) {
2903 dev->mtu = new_mtu;
2904 return 0;
2905 }
2906
2907 skge_down(dev);
2908
2909 dev->mtu = new_mtu;
2910
2911 err = skge_up(dev);
2912 if (err)
2913 dev_close(dev);
2914
2915 return err;
2916}
2917
2918static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2919
2920static void genesis_add_filter(u8 filter[8], const u8 *addr)
2921{
2922 u32 crc, bit;
2923
2924 crc = ether_crc_le(ETH_ALEN, addr);
2925 bit = ~crc & 0x3f;
2926 filter[bit/8] |= 1 << (bit%8);
2927}
2928
2929static void genesis_set_multicast(struct net_device *dev)
2930{
2931 struct skge_port *skge = netdev_priv(dev);
2932 struct skge_hw *hw = skge->hw;
2933 int port = skge->port;
2934 struct netdev_hw_addr *ha;
2935 u32 mode;
2936 u8 filter[8];
2937
2938 mode = xm_read32(hw, port, XM_MODE);
2939 mode |= XM_MD_ENA_HASH;
2940 if (dev->flags & IFF_PROMISC)
2941 mode |= XM_MD_ENA_PROM;
2942 else
2943 mode &= ~XM_MD_ENA_PROM;
2944
2945 if (dev->flags & IFF_ALLMULTI)
2946 memset(filter, 0xff, sizeof(filter));
2947 else {
2948 memset(filter, 0, sizeof(filter));
2949
2950 if (skge->flow_status == FLOW_STAT_REM_SEND ||
2951 skge->flow_status == FLOW_STAT_SYMMETRIC)
2952 genesis_add_filter(filter, pause_mc_addr);
2953
2954 netdev_for_each_mc_addr(ha, dev)
2955 genesis_add_filter(filter, ha->addr);
2956 }
2957
2958 xm_write32(hw, port, XM_MODE, mode);
2959 xm_outhash(hw, port, XM_HSM, filter);
2960}
2961
2962static void yukon_add_filter(u8 filter[8], const u8 *addr)
2963{
2964 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2965 filter[bit/8] |= 1 << (bit%8);
2966}
2967
2968static void yukon_set_multicast(struct net_device *dev)
2969{
2970 struct skge_port *skge = netdev_priv(dev);
2971 struct skge_hw *hw = skge->hw;
2972 int port = skge->port;
2973 struct netdev_hw_addr *ha;
2974 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2975 skge->flow_status == FLOW_STAT_SYMMETRIC);
2976 u16 reg;
2977 u8 filter[8];
2978
2979 memset(filter, 0, sizeof(filter));
2980
2981 reg = gma_read16(hw, port, GM_RX_CTRL);
2982 reg |= GM_RXCR_UCF_ENA;
2983
2984 if (dev->flags & IFF_PROMISC) /* promiscuous */
2985 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2986 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2987 memset(filter, 0xff, sizeof(filter));
2988 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
2989 reg &= ~GM_RXCR_MCF_ENA;
2990 else {
2991 reg |= GM_RXCR_MCF_ENA;
2992
2993 if (rx_pause)
2994 yukon_add_filter(filter, pause_mc_addr);
2995
2996 netdev_for_each_mc_addr(ha, dev)
2997 yukon_add_filter(filter, ha->addr);
2998 }
2999
3000
3001 gma_write16(hw, port, GM_MC_ADDR_H1,
3002 (u16)filter[0] | ((u16)filter[1] << 8));
3003 gma_write16(hw, port, GM_MC_ADDR_H2,
3004 (u16)filter[2] | ((u16)filter[3] << 8));
3005 gma_write16(hw, port, GM_MC_ADDR_H3,
3006 (u16)filter[4] | ((u16)filter[5] << 8));
3007 gma_write16(hw, port, GM_MC_ADDR_H4,
3008 (u16)filter[6] | ((u16)filter[7] << 8));
3009
3010 gma_write16(hw, port, GM_RX_CTRL, reg);
3011}
3012
3013static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3014{
3015 if (is_genesis(hw))
3016 return status >> XMR_FS_LEN_SHIFT;
3017 else
3018 return status >> GMR_FS_LEN_SHIFT;
3019}
3020
3021static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3022{
3023 if (is_genesis(hw))
3024 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3025 else
3026 return (status & GMR_FS_ANY_ERR) ||
3027 (status & GMR_FS_RX_OK) == 0;
3028}
3029
3030static void skge_set_multicast(struct net_device *dev)
3031{
3032 struct skge_port *skge = netdev_priv(dev);
3033
3034 if (is_genesis(skge->hw))
3035 genesis_set_multicast(dev);
3036 else
3037 yukon_set_multicast(dev);
3038
3039}
3040
3041
3042/* Get receive buffer from descriptor.
3043 * Handles copy of small buffers and reallocation failures
3044 */
3045static struct sk_buff *skge_rx_get(struct net_device *dev,
3046 struct skge_element *e,
3047 u32 control, u32 status, u16 csum)
3048{
3049 struct skge_port *skge = netdev_priv(dev);
3050 struct sk_buff *skb;
3051 u16 len = control & BMU_BBC;
3052
3053 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
3054 "rx slot %td status 0x%x len %d\n",
3055 e - skge->rx_ring.start, status, len);
3056
3057 if (len > skge->rx_buf_size)
3058 goto error;
3059
3060 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3061 goto error;
3062
3063 if (bad_phy_status(skge->hw, status))
3064 goto error;
3065
3066 if (phy_length(skge->hw, status) != len)
3067 goto error;
3068
3069 if (len < RX_COPY_THRESHOLD) {
3070 skb = netdev_alloc_skb_ip_align(dev, len);
3071 if (!skb)
3072 goto resubmit;
3073
3074 pci_dma_sync_single_for_cpu(skge->hw->pdev,
3075 dma_unmap_addr(e, mapaddr),
3076 dma_unmap_len(e, maplen),
3077 PCI_DMA_FROMDEVICE);
3078 skb_copy_from_linear_data(e->skb, skb->data, len);
3079 pci_dma_sync_single_for_device(skge->hw->pdev,
3080 dma_unmap_addr(e, mapaddr),
3081 dma_unmap_len(e, maplen),
3082 PCI_DMA_FROMDEVICE);
3083 skge_rx_reuse(e, skge->rx_buf_size);
3084 } else {
3085 struct skge_element ee;
3086 struct sk_buff *nskb;
3087
3088 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
3089 if (!nskb)
3090 goto resubmit;
3091
3092 ee = *e;
3093
3094 skb = ee.skb;
3095 prefetch(skb->data);
3096
3097 if (skge_rx_setup(skge, e, nskb, skge->rx_buf_size) < 0) {
3098 dev_kfree_skb(nskb);
3099 goto resubmit;
3100 }
3101
3102 pci_unmap_single(skge->hw->pdev,
3103 dma_unmap_addr(&ee, mapaddr),
3104 dma_unmap_len(&ee, maplen),
3105 PCI_DMA_FROMDEVICE);
3106 }
3107
3108 skb_put(skb, len);
3109
3110 if (dev->features & NETIF_F_RXCSUM) {
3111 skb->csum = le16_to_cpu(csum);
3112 skb->ip_summed = CHECKSUM_COMPLETE;
3113 }
3114
3115 skb->protocol = eth_type_trans(skb, dev);
3116
3117 return skb;
3118error:
3119
3120 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
3121 "rx err, slot %td control 0x%x status 0x%x\n",
3122 e - skge->rx_ring.start, control, status);
3123
3124 if (is_genesis(skge->hw)) {
3125 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3126 dev->stats.rx_length_errors++;
3127 if (status & XMR_FS_FRA_ERR)
3128 dev->stats.rx_frame_errors++;
3129 if (status & XMR_FS_FCS_ERR)
3130 dev->stats.rx_crc_errors++;
3131 } else {
3132 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3133 dev->stats.rx_length_errors++;
3134 if (status & GMR_FS_FRAGMENT)
3135 dev->stats.rx_frame_errors++;
3136 if (status & GMR_FS_CRC_ERR)
3137 dev->stats.rx_crc_errors++;
3138 }
3139
3140resubmit:
3141 skge_rx_reuse(e, skge->rx_buf_size);
3142 return NULL;
3143}
3144
3145/* Free all buffers in Tx ring which are no longer owned by device */
3146static void skge_tx_done(struct net_device *dev)
3147{
3148 struct skge_port *skge = netdev_priv(dev);
3149 struct skge_ring *ring = &skge->tx_ring;
3150 struct skge_element *e;
3151 unsigned int bytes_compl = 0, pkts_compl = 0;
3152
3153 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3154
3155 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3156 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3157
3158 if (control & BMU_OWN)
3159 break;
3160
3161 skge_tx_unmap(skge->hw->pdev, e, control);
3162
3163 if (control & BMU_EOF) {
3164 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
3165 "tx done slot %td\n",
3166 e - skge->tx_ring.start);
3167
3168 pkts_compl++;
3169 bytes_compl += e->skb->len;
3170
3171 dev_consume_skb_any(e->skb);
3172 }
3173 }
3174 netdev_completed_queue(dev, pkts_compl, bytes_compl);
3175 skge->tx_ring.to_clean = e;
3176
3177 /* Can run lockless until we need to synchronize to restart queue. */
3178 smp_mb();
3179
3180 if (unlikely(netif_queue_stopped(dev) &&
3181 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3182 netif_tx_lock(dev);
3183 if (unlikely(netif_queue_stopped(dev) &&
3184 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3185 netif_wake_queue(dev);
3186
3187 }
3188 netif_tx_unlock(dev);
3189 }
3190}
3191
3192static int skge_poll(struct napi_struct *napi, int budget)
3193{
3194 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3195 struct net_device *dev = skge->netdev;
3196 struct skge_hw *hw = skge->hw;
3197 struct skge_ring *ring = &skge->rx_ring;
3198 struct skge_element *e;
3199 int work_done = 0;
3200
3201 skge_tx_done(dev);
3202
3203 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3204
3205 for (e = ring->to_clean; prefetch(e->next), work_done < budget; e = e->next) {
3206 struct skge_rx_desc *rd = e->desc;
3207 struct sk_buff *skb;
3208 u32 control;
3209
3210 rmb();
3211 control = rd->control;
3212 if (control & BMU_OWN)
3213 break;
3214
3215 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3216 if (likely(skb)) {
3217 napi_gro_receive(napi, skb);
3218 ++work_done;
3219 }
3220 }
3221 ring->to_clean = e;
3222
3223 /* restart receiver */
3224 wmb();
3225 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3226
3227 if (work_done < budget && napi_complete_done(napi, work_done)) {
3228 unsigned long flags;
3229
3230 spin_lock_irqsave(&hw->hw_lock, flags);
3231 hw->intr_mask |= napimask[skge->port];
3232 skge_write32(hw, B0_IMSK, hw->intr_mask);
3233 skge_read32(hw, B0_IMSK);
3234 spin_unlock_irqrestore(&hw->hw_lock, flags);
3235 }
3236
3237 return work_done;
3238}
3239
3240/* Parity errors seem to happen when Genesis is connected to a switch
3241 * with no other ports present. Heartbeat error??
3242 */
3243static void skge_mac_parity(struct skge_hw *hw, int port)
3244{
3245 struct net_device *dev = hw->dev[port];
3246
3247 ++dev->stats.tx_heartbeat_errors;
3248
3249 if (is_genesis(hw))
3250 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3251 MFF_CLR_PERR);
3252 else
3253 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3254 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3255 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3256 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3257}
3258
3259static void skge_mac_intr(struct skge_hw *hw, int port)
3260{
3261 if (is_genesis(hw))
3262 genesis_mac_intr(hw, port);
3263 else
3264 yukon_mac_intr(hw, port);
3265}
3266
3267/* Handle device specific framing and timeout interrupts */
3268static void skge_error_irq(struct skge_hw *hw)
3269{
3270 struct pci_dev *pdev = hw->pdev;
3271 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3272
3273 if (is_genesis(hw)) {
3274 /* clear xmac errors */
3275 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3276 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3277 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3278 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3279 } else {
3280 /* Timestamp (unused) overflow */
3281 if (hwstatus & IS_IRQ_TIST_OV)
3282 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3283 }
3284
3285 if (hwstatus & IS_RAM_RD_PAR) {
3286 dev_err(&pdev->dev, "Ram read data parity error\n");
3287 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3288 }
3289
3290 if (hwstatus & IS_RAM_WR_PAR) {
3291 dev_err(&pdev->dev, "Ram write data parity error\n");
3292 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3293 }
3294
3295 if (hwstatus & IS_M1_PAR_ERR)
3296 skge_mac_parity(hw, 0);
3297
3298 if (hwstatus & IS_M2_PAR_ERR)
3299 skge_mac_parity(hw, 1);
3300
3301 if (hwstatus & IS_R1_PAR_ERR) {
3302 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3303 hw->dev[0]->name);
3304 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3305 }
3306
3307 if (hwstatus & IS_R2_PAR_ERR) {
3308 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3309 hw->dev[1]->name);
3310 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3311 }
3312
3313 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3314 u16 pci_status, pci_cmd;
3315
3316 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3317 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3318
3319 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3320 pci_cmd, pci_status);
3321
3322 /* Write the error bits back to clear them. */
3323 pci_status &= PCI_STATUS_ERROR_BITS;
3324 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3325 pci_write_config_word(pdev, PCI_COMMAND,
3326 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3327 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3328 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3329
3330 /* if error still set then just ignore it */
3331 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3332 if (hwstatus & IS_IRQ_STAT) {
3333 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3334 hw->intr_mask &= ~IS_HW_ERR;
3335 }
3336 }
3337}
3338
3339/*
3340 * Interrupt from PHY are handled in tasklet (softirq)
3341 * because accessing phy registers requires spin wait which might
3342 * cause excess interrupt latency.
3343 */
3344static void skge_extirq(unsigned long arg)
3345{
3346 struct skge_hw *hw = (struct skge_hw *) arg;
3347 int port;
3348
3349 for (port = 0; port < hw->ports; port++) {
3350 struct net_device *dev = hw->dev[port];
3351
3352 if (netif_running(dev)) {
3353 struct skge_port *skge = netdev_priv(dev);
3354
3355 spin_lock(&hw->phy_lock);
3356 if (!is_genesis(hw))
3357 yukon_phy_intr(skge);
3358 else if (hw->phy_type == SK_PHY_BCOM)
3359 bcom_phy_intr(skge);
3360 spin_unlock(&hw->phy_lock);
3361 }
3362 }
3363
3364 spin_lock_irq(&hw->hw_lock);
3365 hw->intr_mask |= IS_EXT_REG;
3366 skge_write32(hw, B0_IMSK, hw->intr_mask);
3367 skge_read32(hw, B0_IMSK);
3368 spin_unlock_irq(&hw->hw_lock);
3369}
3370
3371static irqreturn_t skge_intr(int irq, void *dev_id)
3372{
3373 struct skge_hw *hw = dev_id;
3374 u32 status;
3375 int handled = 0;
3376
3377 spin_lock(&hw->hw_lock);
3378 /* Reading this register masks IRQ */
3379 status = skge_read32(hw, B0_SP_ISRC);
3380 if (status == 0 || status == ~0)
3381 goto out;
3382
3383 handled = 1;
3384 status &= hw->intr_mask;
3385 if (status & IS_EXT_REG) {
3386 hw->intr_mask &= ~IS_EXT_REG;
3387 tasklet_schedule(&hw->phy_task);
3388 }
3389
3390 if (status & (IS_XA1_F|IS_R1_F)) {
3391 struct skge_port *skge = netdev_priv(hw->dev[0]);
3392 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3393 napi_schedule(&skge->napi);
3394 }
3395
3396 if (status & IS_PA_TO_TX1)
3397 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3398
3399 if (status & IS_PA_TO_RX1) {
3400 ++hw->dev[0]->stats.rx_over_errors;
3401 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3402 }
3403
3404
3405 if (status & IS_MAC1)
3406 skge_mac_intr(hw, 0);
3407
3408 if (hw->dev[1]) {
3409 struct skge_port *skge = netdev_priv(hw->dev[1]);
3410
3411 if (status & (IS_XA2_F|IS_R2_F)) {
3412 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3413 napi_schedule(&skge->napi);
3414 }
3415
3416 if (status & IS_PA_TO_RX2) {
3417 ++hw->dev[1]->stats.rx_over_errors;
3418 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3419 }
3420
3421 if (status & IS_PA_TO_TX2)
3422 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3423
3424 if (status & IS_MAC2)
3425 skge_mac_intr(hw, 1);
3426 }
3427
3428 if (status & IS_HW_ERR)
3429 skge_error_irq(hw);
3430out:
3431 skge_write32(hw, B0_IMSK, hw->intr_mask);
3432 skge_read32(hw, B0_IMSK);
3433 spin_unlock(&hw->hw_lock);
3434
3435 return IRQ_RETVAL(handled);
3436}
3437
3438#ifdef CONFIG_NET_POLL_CONTROLLER
3439static void skge_netpoll(struct net_device *dev)
3440{
3441 struct skge_port *skge = netdev_priv(dev);
3442
3443 disable_irq(dev->irq);
3444 skge_intr(dev->irq, skge->hw);
3445 enable_irq(dev->irq);
3446}
3447#endif
3448
3449static int skge_set_mac_address(struct net_device *dev, void *p)
3450{
3451 struct skge_port *skge = netdev_priv(dev);
3452 struct skge_hw *hw = skge->hw;
3453 unsigned port = skge->port;
3454 const struct sockaddr *addr = p;
3455 u16 ctrl;
3456
3457 if (!is_valid_ether_addr(addr->sa_data))
3458 return -EADDRNOTAVAIL;
3459
3460 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3461
3462 if (!netif_running(dev)) {
3463 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3464 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3465 } else {
3466 /* disable Rx */
3467 spin_lock_bh(&hw->phy_lock);
3468 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3469 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3470
3471 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3472 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3473
3474 if (is_genesis(hw))
3475 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3476 else {
3477 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3478 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3479 }
3480
3481 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3482 spin_unlock_bh(&hw->phy_lock);
3483 }
3484
3485 return 0;
3486}
3487
3488static const struct {
3489 u8 id;
3490 const char *name;
3491} skge_chips[] = {
3492 { CHIP_ID_GENESIS, "Genesis" },
3493 { CHIP_ID_YUKON, "Yukon" },
3494 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3495 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3496};
3497
3498static const char *skge_board_name(const struct skge_hw *hw)
3499{
3500 int i;
3501 static char buf[16];
3502
3503 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3504 if (skge_chips[i].id == hw->chip_id)
3505 return skge_chips[i].name;
3506
3507 snprintf(buf, sizeof(buf), "chipid 0x%x", hw->chip_id);
3508 return buf;
3509}
3510
3511
3512/*
3513 * Setup the board data structure, but don't bring up
3514 * the port(s)
3515 */
3516static int skge_reset(struct skge_hw *hw)
3517{
3518 u32 reg;
3519 u16 ctst, pci_status;
3520 u8 t8, mac_cfg, pmd_type;
3521 int i;
3522
3523 ctst = skge_read16(hw, B0_CTST);
3524
3525 /* do a SW reset */
3526 skge_write8(hw, B0_CTST, CS_RST_SET);
3527 skge_write8(hw, B0_CTST, CS_RST_CLR);
3528
3529 /* clear PCI errors, if any */
3530 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3531 skge_write8(hw, B2_TST_CTRL2, 0);
3532
3533 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3534 pci_write_config_word(hw->pdev, PCI_STATUS,
3535 pci_status | PCI_STATUS_ERROR_BITS);
3536 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3537 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3538
3539 /* restore CLK_RUN bits (for Yukon-Lite) */
3540 skge_write16(hw, B0_CTST,
3541 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3542
3543 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3544 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3545 pmd_type = skge_read8(hw, B2_PMD_TYP);
3546 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3547
3548 switch (hw->chip_id) {
3549 case CHIP_ID_GENESIS:
3550#ifdef CONFIG_SKGE_GENESIS
3551 switch (hw->phy_type) {
3552 case SK_PHY_XMAC:
3553 hw->phy_addr = PHY_ADDR_XMAC;
3554 break;
3555 case SK_PHY_BCOM:
3556 hw->phy_addr = PHY_ADDR_BCOM;
3557 break;
3558 default:
3559 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3560 hw->phy_type);
3561 return -EOPNOTSUPP;
3562 }
3563 break;
3564#else
3565 dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n");
3566 return -EOPNOTSUPP;
3567#endif
3568
3569 case CHIP_ID_YUKON:
3570 case CHIP_ID_YUKON_LITE:
3571 case CHIP_ID_YUKON_LP:
3572 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3573 hw->copper = 1;
3574
3575 hw->phy_addr = PHY_ADDR_MARV;
3576 break;
3577
3578 default:
3579 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3580 hw->chip_id);
3581 return -EOPNOTSUPP;
3582 }
3583
3584 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3585 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3586 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3587
3588 /* read the adapters RAM size */
3589 t8 = skge_read8(hw, B2_E_0);
3590 if (is_genesis(hw)) {
3591 if (t8 == 3) {
3592 /* special case: 4 x 64k x 36, offset = 0x80000 */
3593 hw->ram_size = 0x100000;
3594 hw->ram_offset = 0x80000;
3595 } else
3596 hw->ram_size = t8 * 512;
3597 } else if (t8 == 0)
3598 hw->ram_size = 0x20000;
3599 else
3600 hw->ram_size = t8 * 4096;
3601
3602 hw->intr_mask = IS_HW_ERR;
3603
3604 /* Use PHY IRQ for all but fiber based Genesis board */
3605 if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC))
3606 hw->intr_mask |= IS_EXT_REG;
3607
3608 if (is_genesis(hw))
3609 genesis_init(hw);
3610 else {
3611 /* switch power to VCC (WA for VAUX problem) */
3612 skge_write8(hw, B0_POWER_CTRL,
3613 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3614
3615 /* avoid boards with stuck Hardware error bits */
3616 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3617 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3618 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3619 hw->intr_mask &= ~IS_HW_ERR;
3620 }
3621
3622 /* Clear PHY COMA */
3623 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3624 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
3625 reg &= ~PCI_PHY_COMA;
3626 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3627 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3628
3629
3630 for (i = 0; i < hw->ports; i++) {
3631 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3632 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3633 }
3634 }
3635
3636 /* turn off hardware timer (unused) */
3637 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3638 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3639 skge_write8(hw, B0_LED, LED_STAT_ON);
3640
3641 /* enable the Tx Arbiters */
3642 for (i = 0; i < hw->ports; i++)
3643 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3644
3645 /* Initialize ram interface */
3646 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3647
3648 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3649 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3650 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3651 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3652 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3653 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3654 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3655 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3656 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3657 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3658 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3659 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3660
3661 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3662
3663 /* Set interrupt moderation for Transmit only
3664 * Receive interrupts avoided by NAPI
3665 */
3666 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3667 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3668 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3669
3670 /* Leave irq disabled until first port is brought up. */
3671 skge_write32(hw, B0_IMSK, 0);
3672
3673 for (i = 0; i < hw->ports; i++) {
3674 if (is_genesis(hw))
3675 genesis_reset(hw, i);
3676 else
3677 yukon_reset(hw, i);
3678 }
3679
3680 return 0;
3681}
3682
3683
3684#ifdef CONFIG_SKGE_DEBUG
3685
3686static struct dentry *skge_debug;
3687
3688static int skge_debug_show(struct seq_file *seq, void *v)
3689{
3690 struct net_device *dev = seq->private;
3691 const struct skge_port *skge = netdev_priv(dev);
3692 const struct skge_hw *hw = skge->hw;
3693 const struct skge_element *e;
3694
3695 if (!netif_running(dev))
3696 return -ENETDOWN;
3697
3698 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3699 skge_read32(hw, B0_IMSK));
3700
3701 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3702 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3703 const struct skge_tx_desc *t = e->desc;
3704 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3705 t->control, t->dma_hi, t->dma_lo, t->status,
3706 t->csum_offs, t->csum_write, t->csum_start);
3707 }
3708
3709 seq_puts(seq, "\nRx Ring:\n");
3710 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3711 const struct skge_rx_desc *r = e->desc;
3712
3713 if (r->control & BMU_OWN)
3714 break;
3715
3716 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3717 r->control, r->dma_hi, r->dma_lo, r->status,
3718 r->timestamp, r->csum1, r->csum1_start);
3719 }
3720
3721 return 0;
3722}
3723DEFINE_SHOW_ATTRIBUTE(skge_debug);
3724
3725/*
3726 * Use network device events to create/remove/rename
3727 * debugfs file entries
3728 */
3729static int skge_device_event(struct notifier_block *unused,
3730 unsigned long event, void *ptr)
3731{
3732 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
3733 struct skge_port *skge;
3734
3735 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
3736 goto done;
3737
3738 skge = netdev_priv(dev);
3739 switch (event) {
3740 case NETDEV_CHANGENAME:
3741 if (skge->debugfs)
3742 skge->debugfs = debugfs_rename(skge_debug,
3743 skge->debugfs,
3744 skge_debug, dev->name);
3745 break;
3746
3747 case NETDEV_GOING_DOWN:
3748 debugfs_remove(skge->debugfs);
3749 skge->debugfs = NULL;
3750 break;
3751
3752 case NETDEV_UP:
3753 skge->debugfs = debugfs_create_file(dev->name, 0444, skge_debug,
3754 dev, &skge_debug_fops);
3755 break;
3756 }
3757
3758done:
3759 return NOTIFY_DONE;
3760}
3761
3762static struct notifier_block skge_notifier = {
3763 .notifier_call = skge_device_event,
3764};
3765
3766
3767static __init void skge_debug_init(void)
3768{
3769 skge_debug = debugfs_create_dir("skge", NULL);
3770
3771 register_netdevice_notifier(&skge_notifier);
3772}
3773
3774static __exit void skge_debug_cleanup(void)
3775{
3776 if (skge_debug) {
3777 unregister_netdevice_notifier(&skge_notifier);
3778 debugfs_remove(skge_debug);
3779 skge_debug = NULL;
3780 }
3781}
3782
3783#else
3784#define skge_debug_init()
3785#define skge_debug_cleanup()
3786#endif
3787
3788static const struct net_device_ops skge_netdev_ops = {
3789 .ndo_open = skge_up,
3790 .ndo_stop = skge_down,
3791 .ndo_start_xmit = skge_xmit_frame,
3792 .ndo_do_ioctl = skge_ioctl,
3793 .ndo_get_stats = skge_get_stats,
3794 .ndo_tx_timeout = skge_tx_timeout,
3795 .ndo_change_mtu = skge_change_mtu,
3796 .ndo_validate_addr = eth_validate_addr,
3797 .ndo_set_rx_mode = skge_set_multicast,
3798 .ndo_set_mac_address = skge_set_mac_address,
3799#ifdef CONFIG_NET_POLL_CONTROLLER
3800 .ndo_poll_controller = skge_netpoll,
3801#endif
3802};
3803
3804
3805/* Initialize network device */
3806static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3807 int highmem)
3808{
3809 struct skge_port *skge;
3810 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3811
3812 if (!dev)
3813 return NULL;
3814
3815 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3816 dev->netdev_ops = &skge_netdev_ops;
3817 dev->ethtool_ops = &skge_ethtool_ops;
3818 dev->watchdog_timeo = TX_WATCHDOG;
3819 dev->irq = hw->pdev->irq;
3820
3821 /* MTU range: 60 - 9000 */
3822 dev->min_mtu = ETH_ZLEN;
3823 dev->max_mtu = ETH_JUMBO_MTU;
3824
3825 if (highmem)
3826 dev->features |= NETIF_F_HIGHDMA;
3827
3828 skge = netdev_priv(dev);
3829 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
3830 skge->netdev = dev;
3831 skge->hw = hw;
3832 skge->msg_enable = netif_msg_init(debug, default_msg);
3833
3834 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3835 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3836
3837 /* Auto speed and flow control */
3838 skge->autoneg = AUTONEG_ENABLE;
3839 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3840 skge->duplex = -1;
3841 skge->speed = -1;
3842 skge->advertising = skge_supported_modes(hw);
3843
3844 if (device_can_wakeup(&hw->pdev->dev)) {
3845 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3846 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3847 }
3848
3849 hw->dev[port] = dev;
3850
3851 skge->port = port;
3852
3853 /* Only used for Genesis XMAC */
3854 if (is_genesis(hw))
3855 timer_setup(&skge->link_timer, xm_link_timer, 0);
3856 else {
3857 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3858 NETIF_F_RXCSUM;
3859 dev->features |= dev->hw_features;
3860 }
3861
3862 /* read the mac address */
3863 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3864
3865 return dev;
3866}
3867
3868static void skge_show_addr(struct net_device *dev)
3869{
3870 const struct skge_port *skge = netdev_priv(dev);
3871
3872 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
3873}
3874
3875static int only_32bit_dma;
3876
3877static int skge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3878{
3879 struct net_device *dev, *dev1;
3880 struct skge_hw *hw;
3881 int err, using_dac = 0;
3882
3883 err = pci_enable_device(pdev);
3884 if (err) {
3885 dev_err(&pdev->dev, "cannot enable PCI device\n");
3886 goto err_out;
3887 }
3888
3889 err = pci_request_regions(pdev, DRV_NAME);
3890 if (err) {
3891 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3892 goto err_out_disable_pdev;
3893 }
3894
3895 pci_set_master(pdev);
3896
3897 if (!only_32bit_dma && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3898 using_dac = 1;
3899 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3900 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
3901 using_dac = 0;
3902 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3903 }
3904
3905 if (err) {
3906 dev_err(&pdev->dev, "no usable DMA configuration\n");
3907 goto err_out_free_regions;
3908 }
3909
3910#ifdef __BIG_ENDIAN
3911 /* byte swap descriptors in hardware */
3912 {
3913 u32 reg;
3914
3915 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3916 reg |= PCI_REV_DESC;
3917 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3918 }
3919#endif
3920
3921 err = -ENOMEM;
3922 /* space for skge@pci:0000:04:00.0 */
3923 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
3924 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
3925 if (!hw)
3926 goto err_out_free_regions;
3927
3928 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
3929
3930 hw->pdev = pdev;
3931 spin_lock_init(&hw->hw_lock);
3932 spin_lock_init(&hw->phy_lock);
3933 tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw);
3934
3935 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3936 if (!hw->regs) {
3937 dev_err(&pdev->dev, "cannot map device registers\n");
3938 goto err_out_free_hw;
3939 }
3940
3941 err = skge_reset(hw);
3942 if (err)
3943 goto err_out_iounmap;
3944
3945 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
3946 DRV_VERSION,
3947 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3948 skge_board_name(hw), hw->chip_rev);
3949
3950 dev = skge_devinit(hw, 0, using_dac);
3951 if (!dev) {
3952 err = -ENOMEM;
3953 goto err_out_led_off;
3954 }
3955
3956 /* Some motherboards are broken and has zero in ROM. */
3957 if (!is_valid_ether_addr(dev->dev_addr))
3958 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3959
3960 err = register_netdev(dev);
3961 if (err) {
3962 dev_err(&pdev->dev, "cannot register net device\n");
3963 goto err_out_free_netdev;
3964 }
3965
3966 skge_show_addr(dev);
3967
3968 if (hw->ports > 1) {
3969 dev1 = skge_devinit(hw, 1, using_dac);
3970 if (!dev1) {
3971 err = -ENOMEM;
3972 goto err_out_unregister;
3973 }
3974
3975 err = register_netdev(dev1);
3976 if (err) {
3977 dev_err(&pdev->dev, "cannot register second net device\n");
3978 goto err_out_free_dev1;
3979 }
3980
3981 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED,
3982 hw->irq_name, hw);
3983 if (err) {
3984 dev_err(&pdev->dev, "cannot assign irq %d\n",
3985 pdev->irq);
3986 goto err_out_unregister_dev1;
3987 }
3988
3989 skge_show_addr(dev1);
3990 }
3991 pci_set_drvdata(pdev, hw);
3992
3993 return 0;
3994
3995err_out_unregister_dev1:
3996 unregister_netdev(dev1);
3997err_out_free_dev1:
3998 free_netdev(dev1);
3999err_out_unregister:
4000 unregister_netdev(dev);
4001err_out_free_netdev:
4002 free_netdev(dev);
4003err_out_led_off:
4004 skge_write16(hw, B0_LED, LED_STAT_OFF);
4005err_out_iounmap:
4006 iounmap(hw->regs);
4007err_out_free_hw:
4008 kfree(hw);
4009err_out_free_regions:
4010 pci_release_regions(pdev);
4011err_out_disable_pdev:
4012 pci_disable_device(pdev);
4013err_out:
4014 return err;
4015}
4016
4017static void skge_remove(struct pci_dev *pdev)
4018{
4019 struct skge_hw *hw = pci_get_drvdata(pdev);
4020 struct net_device *dev0, *dev1;
4021
4022 if (!hw)
4023 return;
4024
4025 dev1 = hw->dev[1];
4026 if (dev1)
4027 unregister_netdev(dev1);
4028 dev0 = hw->dev[0];
4029 unregister_netdev(dev0);
4030
4031 tasklet_kill(&hw->phy_task);
4032
4033 spin_lock_irq(&hw->hw_lock);
4034 hw->intr_mask = 0;
4035
4036 if (hw->ports > 1) {
4037 skge_write32(hw, B0_IMSK, 0);
4038 skge_read32(hw, B0_IMSK);
4039 }
4040 spin_unlock_irq(&hw->hw_lock);
4041
4042 skge_write16(hw, B0_LED, LED_STAT_OFF);
4043 skge_write8(hw, B0_CTST, CS_RST_SET);
4044
4045 if (hw->ports > 1)
4046 free_irq(pdev->irq, hw);
4047 pci_release_regions(pdev);
4048 pci_disable_device(pdev);
4049 if (dev1)
4050 free_netdev(dev1);
4051 free_netdev(dev0);
4052
4053 iounmap(hw->regs);
4054 kfree(hw);
4055}
4056
4057#ifdef CONFIG_PM_SLEEP
4058static int skge_suspend(struct device *dev)
4059{
4060 struct skge_hw *hw = dev_get_drvdata(dev);
4061 int i;
4062
4063 if (!hw)
4064 return 0;
4065
4066 for (i = 0; i < hw->ports; i++) {
4067 struct net_device *dev = hw->dev[i];
4068 struct skge_port *skge = netdev_priv(dev);
4069
4070 if (netif_running(dev))
4071 skge_down(dev);
4072
4073 if (skge->wol)
4074 skge_wol_init(skge);
4075 }
4076
4077 skge_write32(hw, B0_IMSK, 0);
4078
4079 return 0;
4080}
4081
4082static int skge_resume(struct device *dev)
4083{
4084 struct skge_hw *hw = dev_get_drvdata(dev);
4085 int i, err;
4086
4087 if (!hw)
4088 return 0;
4089
4090 err = skge_reset(hw);
4091 if (err)
4092 goto out;
4093
4094 for (i = 0; i < hw->ports; i++) {
4095 struct net_device *dev = hw->dev[i];
4096
4097 if (netif_running(dev)) {
4098 err = skge_up(dev);
4099
4100 if (err) {
4101 netdev_err(dev, "could not up: %d\n", err);
4102 dev_close(dev);
4103 goto out;
4104 }
4105 }
4106 }
4107out:
4108 return err;
4109}
4110
4111static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume);
4112#define SKGE_PM_OPS (&skge_pm_ops)
4113
4114#else
4115
4116#define SKGE_PM_OPS NULL
4117#endif /* CONFIG_PM_SLEEP */
4118
4119static void skge_shutdown(struct pci_dev *pdev)
4120{
4121 struct skge_hw *hw = pci_get_drvdata(pdev);
4122 int i;
4123
4124 if (!hw)
4125 return;
4126
4127 for (i = 0; i < hw->ports; i++) {
4128 struct net_device *dev = hw->dev[i];
4129 struct skge_port *skge = netdev_priv(dev);
4130
4131 if (skge->wol)
4132 skge_wol_init(skge);
4133 }
4134
4135 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
4136 pci_set_power_state(pdev, PCI_D3hot);
4137}
4138
4139static struct pci_driver skge_driver = {
4140 .name = DRV_NAME,
4141 .id_table = skge_id_table,
4142 .probe = skge_probe,
4143 .remove = skge_remove,
4144 .shutdown = skge_shutdown,
4145 .driver.pm = SKGE_PM_OPS,
4146};
4147
4148static const struct dmi_system_id skge_32bit_dma_boards[] = {
4149 {
4150 .ident = "Gigabyte nForce boards",
4151 .matches = {
4152 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"),
4153 DMI_MATCH(DMI_BOARD_NAME, "nForce"),
4154 },
4155 },
4156 {
4157 .ident = "ASUS P5NSLI",
4158 .matches = {
4159 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
4160 DMI_MATCH(DMI_BOARD_NAME, "P5NSLI")
4161 },
4162 },
4163 {
4164 .ident = "FUJITSU SIEMENS A8NE-FM",
4165 .matches = {
4166 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTek Computer INC."),
4167 DMI_MATCH(DMI_BOARD_NAME, "A8NE-FM")
4168 },
4169 },
4170 {}
4171};
4172
4173static int __init skge_init_module(void)
4174{
4175 if (dmi_check_system(skge_32bit_dma_boards))
4176 only_32bit_dma = 1;
4177 skge_debug_init();
4178 return pci_register_driver(&skge_driver);
4179}
4180
4181static void __exit skge_cleanup_module(void)
4182{
4183 pci_unregister_driver(&skge_driver);
4184 skge_debug_cleanup();
4185}
4186
4187module_init(skge_init_module);
4188module_exit(skge_cleanup_module);