1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Faraday FTGMAC100 Gigabit Ethernet
   4 *
   5 * (C) Copyright 2009-2011 Faraday Technology
   6 * Po-Yu Chuang <ratbert@faraday-tech.com>
   7 */
   8
   9#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
  10
  11#include <linux/clk.h>
  12#include <linux/dma-mapping.h>
  13#include <linux/etherdevice.h>
  14#include <linux/ethtool.h>
  15#include <linux/interrupt.h>
  16#include <linux/io.h>
  17#include <linux/module.h>
  18#include <linux/netdevice.h>
  19#include <linux/of.h>
  20#include <linux/of_mdio.h>
  21#include <linux/phy.h>
  22#include <linux/platform_device.h>
  23#include <linux/property.h>
  24#include <linux/crc32.h>
  25#include <linux/if_vlan.h>
  26#include <linux/of_net.h>
  27#include <net/ip.h>
  28#include <net/ncsi.h>
  29
  30#include "ftgmac100.h"
  31
  32#define DRV_NAME	"ftgmac100"
 
  33
  34/* Arbitrary values, I am not sure the HW has limits */
  35#define MAX_RX_QUEUE_ENTRIES	1024
  36#define MAX_TX_QUEUE_ENTRIES	1024
  37#define MIN_RX_QUEUE_ENTRIES	32
  38#define MIN_TX_QUEUE_ENTRIES	32
  39
  40/* Defaults */
  41#define DEF_RX_QUEUE_ENTRIES	128
  42#define DEF_TX_QUEUE_ENTRIES	128
  43
  44#define MAX_PKT_SIZE		1536
  45#define RX_BUF_SIZE		MAX_PKT_SIZE	/* must be smaller than 0x3fff */
  46
  47/* Min number of tx ring entries before stopping queue */
  48#define TX_THRESHOLD		(MAX_SKB_FRAGS + 1)
  49
  50#define FTGMAC_100MHZ		100000000
  51#define FTGMAC_25MHZ		25000000
  52
  53struct ftgmac100 {
  54	/* Registers */
  55	struct resource *res;
  56	void __iomem *base;
  57
  58	/* Rx ring */
  59	unsigned int rx_q_entries;
  60	struct ftgmac100_rxdes *rxdes;
  61	dma_addr_t rxdes_dma;
  62	struct sk_buff **rx_skbs;
  63	unsigned int rx_pointer;
  64	u32 rxdes0_edorr_mask;
  65
  66	/* Tx ring */
  67	unsigned int tx_q_entries;
  68	struct ftgmac100_txdes *txdes;
  69	dma_addr_t txdes_dma;
  70	struct sk_buff **tx_skbs;
  71	unsigned int tx_clean_pointer;
  72	unsigned int tx_pointer;
  73	u32 txdes0_edotr_mask;
  74
  75	/* Used to signal the reset task of ring change request */
  76	unsigned int new_rx_q_entries;
  77	unsigned int new_tx_q_entries;
  78
  79	/* Scratch page to use when rx skb alloc fails */
  80	void *rx_scratch;
  81	dma_addr_t rx_scratch_dma;
  82
  83	/* Component structures */
  84	struct net_device *netdev;
  85	struct device *dev;
  86	struct ncsi_dev *ndev;
  87	struct napi_struct napi;
  88	struct work_struct reset_task;
  89	struct mii_bus *mii_bus;
  90	struct clk *clk;
  91
  92	/* AST2500/AST2600 RMII ref clock gate */
  93	struct clk *rclk;
  94
  95	/* Link management */
  96	int cur_speed;
  97	int cur_duplex;
  98	bool use_ncsi;
  99
 100	/* Multicast filter settings */
 101	u32 maht0;
 102	u32 maht1;
 103
 104	/* Flow control settings */
 105	bool tx_pause;
 106	bool rx_pause;
 107	bool aneg_pause;
 108
 109	/* Misc */
 110	bool need_mac_restart;
 111	bool is_aspeed;
 112};
 113
 114static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr)
 115{
 116	struct net_device *netdev = priv->netdev;
 117	int i;
 118
 119	/* NOTE: reset clears all registers */
 120	iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
 121	iowrite32(maccr | FTGMAC100_MACCR_SW_RST,
 122		  priv->base + FTGMAC100_OFFSET_MACCR);
 123	for (i = 0; i < 200; i++) {
 124		unsigned int maccr;
 125
 126		maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
 127		if (!(maccr & FTGMAC100_MACCR_SW_RST))
 128			return 0;
 129
 130		udelay(1);
 131	}
 132
 133	netdev_err(netdev, "Hardware reset failed\n");
 134	return -EIO;
 135}
 136
 137static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv)
 138{
 139	u32 maccr = 0;
 140
 141	switch (priv->cur_speed) {
 142	case SPEED_10:
 143	case 0: /* no link */
 144		break;
 145
 146	case SPEED_100:
 147		maccr |= FTGMAC100_MACCR_FAST_MODE;
 148		break;
 149
 150	case SPEED_1000:
 151		maccr |= FTGMAC100_MACCR_GIGA_MODE;
 152		break;
 153	default:
 154		netdev_err(priv->netdev, "Unknown speed %d !\n",
 155			   priv->cur_speed);
 156		break;
 157	}
 158
 159	/* (Re)initialize the queue pointers */
 160	priv->rx_pointer = 0;
 161	priv->tx_clean_pointer = 0;
 162	priv->tx_pointer = 0;
 163
 164	/* The doc says reset twice with 10us interval */
 165	if (ftgmac100_reset_mac(priv, maccr))
 166		return -EIO;
 167	usleep_range(10, 1000);
 168	return ftgmac100_reset_mac(priv, maccr);
 169}
 170
 171static void ftgmac100_write_mac_addr(struct ftgmac100 *priv, const u8 *mac)
 172{
 173	unsigned int maddr = mac[0] << 8 | mac[1];
 174	unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
 175
 176	iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
 177	iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
 178}
 179
 180static int ftgmac100_initial_mac(struct ftgmac100 *priv)
 181{
 182	u8 mac[ETH_ALEN];
 183	unsigned int m;
 184	unsigned int l;
 185	int err;
 186
 187	err = of_get_ethdev_address(priv->dev->of_node, priv->netdev);
 188	if (err == -EPROBE_DEFER)
 189		return err;
 190	if (!err) {
 191		dev_info(priv->dev, "Read MAC address %pM from device tree\n",
 192			 priv->netdev->dev_addr);
 193		return 0;
 194	}
 195
 196	m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR);
 197	l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR);
 198
 199	mac[0] = (m >> 8) & 0xff;
 200	mac[1] = m & 0xff;
 201	mac[2] = (l >> 24) & 0xff;
 202	mac[3] = (l >> 16) & 0xff;
 203	mac[4] = (l >> 8) & 0xff;
 204	mac[5] = l & 0xff;
 205
 206	if (is_valid_ether_addr(mac)) {
 207		eth_hw_addr_set(priv->netdev, mac);
 208		dev_info(priv->dev, "Read MAC address %pM from chip\n", mac);
 209	} else {
 210		eth_hw_addr_random(priv->netdev);
 211		dev_info(priv->dev, "Generated random MAC address %pM\n",
 212			 priv->netdev->dev_addr);
 213	}
 214
 215	return 0;
 216}
 217
 218static int ftgmac100_set_mac_addr(struct net_device *dev, void *p)
 219{
 220	int ret;
 221
 222	ret = eth_prepare_mac_addr_change(dev, p);
 223	if (ret < 0)
 224		return ret;
 225
 226	eth_commit_mac_addr_change(dev, p);
 227	ftgmac100_write_mac_addr(netdev_priv(dev), dev->dev_addr);
 228
 229	return 0;
 230}
 231
 232static void ftgmac100_config_pause(struct ftgmac100 *priv)
 233{
 234	u32 fcr = FTGMAC100_FCR_PAUSE_TIME(16);
 235
 236	/* Throttle tx queue when receiving pause frames */
 237	if (priv->rx_pause)
 238		fcr |= FTGMAC100_FCR_FC_EN;
 239
 240	/* Enables sending pause frames when the RX queue is past a
 241	 * certain threshold.
 242	 */
 243	if (priv->tx_pause)
 244		fcr |= FTGMAC100_FCR_FCTHR_EN;
 245
 246	iowrite32(fcr, priv->base + FTGMAC100_OFFSET_FCR);
 247}
 248
 249static void ftgmac100_init_hw(struct ftgmac100 *priv)
 250{
 251	u32 reg, rfifo_sz, tfifo_sz;
 252
 253	/* Clear stale interrupts */
 254	reg = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
 255	iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR);
 256
 257	/* Setup RX ring buffer base */
 258	iowrite32(priv->rxdes_dma, priv->base + FTGMAC100_OFFSET_RXR_BADR);
 259
 260	/* Setup TX ring buffer base */
 261	iowrite32(priv->txdes_dma, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
 262
 263	/* Configure RX buffer size */
 264	iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE),
 265		  priv->base + FTGMAC100_OFFSET_RBSR);
 266
 267	/* Set RX descriptor autopoll */
 268	iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1),
 269		  priv->base + FTGMAC100_OFFSET_APTC);
 270
 271	/* Write MAC address */
 272	ftgmac100_write_mac_addr(priv, priv->netdev->dev_addr);
 273
 274	/* Write multicast filter */
 275	iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0);
 276	iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1);
 277
 278	/* Configure descriptor sizes and increase burst sizes according
 279	 * to values in Aspeed SDK. The FIFO arbitration is enabled and
 280	 * the thresholds set based on the recommended values in the
 281	 * AST2400 specification.
 282	 */
 283	iowrite32(FTGMAC100_DBLAC_RXDES_SIZE(2) |   /* 2*8 bytes RX descs */
 284		  FTGMAC100_DBLAC_TXDES_SIZE(2) |   /* 2*8 bytes TX descs */
 285		  FTGMAC100_DBLAC_RXBURST_SIZE(3) | /* 512 bytes max RX bursts */
 286		  FTGMAC100_DBLAC_TXBURST_SIZE(3) | /* 512 bytes max TX bursts */
 287		  FTGMAC100_DBLAC_RX_THR_EN |       /* Enable fifo threshold arb */
 288		  FTGMAC100_DBLAC_RXFIFO_HTHR(6) |  /* 6/8 of FIFO high threshold */
 289		  FTGMAC100_DBLAC_RXFIFO_LTHR(2),   /* 2/8 of FIFO low threshold */
 290		  priv->base + FTGMAC100_OFFSET_DBLAC);
 291
 292	/* Interrupt mitigation configured for 1 interrupt/packet. HW interrupt
 293	 * mitigation doesn't seem to provide any benefit with NAPI so leave
 294	 * it at that.
 295	 */
 296	iowrite32(FTGMAC100_ITC_RXINT_THR(1) |
 297		  FTGMAC100_ITC_TXINT_THR(1),
 298		  priv->base + FTGMAC100_OFFSET_ITC);
 299
 300	/* Configure FIFO sizes in the TPAFCR register */
 301	reg = ioread32(priv->base + FTGMAC100_OFFSET_FEAR);
 302	rfifo_sz = reg & 0x00000007;
 303	tfifo_sz = (reg >> 3) & 0x00000007;
 304	reg = ioread32(priv->base + FTGMAC100_OFFSET_TPAFCR);
 305	reg &= ~0x3f000000;
 306	reg |= (tfifo_sz << 27);
 307	reg |= (rfifo_sz << 24);
 308	iowrite32(reg, priv->base + FTGMAC100_OFFSET_TPAFCR);
 309}
 310
 311static void ftgmac100_start_hw(struct ftgmac100 *priv)
 312{
 313	u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
 314
 315	/* Keep the original GMAC and FAST bits */
 316	maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE);
 317
 318	/* Add all the main enable bits */
 319	maccr |= FTGMAC100_MACCR_TXDMA_EN	|
 320		 FTGMAC100_MACCR_RXDMA_EN	|
 321		 FTGMAC100_MACCR_TXMAC_EN	|
 322		 FTGMAC100_MACCR_RXMAC_EN	|
 323		 FTGMAC100_MACCR_CRC_APD	|
 324		 FTGMAC100_MACCR_PHY_LINK_LEVEL	|
 325		 FTGMAC100_MACCR_RX_RUNT	|
 326		 FTGMAC100_MACCR_RX_BROADPKT;
 327
 328	/* Add other bits as needed */
 329	if (priv->cur_duplex == DUPLEX_FULL)
 330		maccr |= FTGMAC100_MACCR_FULLDUP;
 331	if (priv->netdev->flags & IFF_PROMISC)
 332		maccr |= FTGMAC100_MACCR_RX_ALL;
 333	if (priv->netdev->flags & IFF_ALLMULTI)
 334		maccr |= FTGMAC100_MACCR_RX_MULTIPKT;
 335	else if (netdev_mc_count(priv->netdev))
 336		maccr |= FTGMAC100_MACCR_HT_MULTI_EN;
 337
 338	/* Vlan filtering enabled */
 339	if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
 340		maccr |= FTGMAC100_MACCR_RM_VLAN;
 341
 342	/* Hit the HW */
 343	iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
 344}
 345
 346static void ftgmac100_stop_hw(struct ftgmac100 *priv)
 347{
 348	iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
 349}
 350
 351static void ftgmac100_calc_mc_hash(struct ftgmac100 *priv)
 352{
 353	struct netdev_hw_addr *ha;
 354
 355	priv->maht1 = 0;
 356	priv->maht0 = 0;
 357	netdev_for_each_mc_addr(ha, priv->netdev) {
 358		u32 crc_val = ether_crc_le(ETH_ALEN, ha->addr);
 359
 360		crc_val = (~(crc_val >> 2)) & 0x3f;
 361		if (crc_val >= 32)
 362			priv->maht1 |= 1ul << (crc_val - 32);
 363		else
 364			priv->maht0 |= 1ul << (crc_val);
 365	}
 366}
 367
 368static void ftgmac100_set_rx_mode(struct net_device *netdev)
 369{
 370	struct ftgmac100 *priv = netdev_priv(netdev);
 371
 372	/* Setup the hash filter */
 373	ftgmac100_calc_mc_hash(priv);
 374
 375	/* Interface down ? that's all there is to do */
 376	if (!netif_running(netdev))
 377		return;
 378
 379	/* Update the HW */
 380	iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0);
 381	iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1);
 382
 383	/* Reconfigure MACCR */
 384	ftgmac100_start_hw(priv);
 385}
 386
 387static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry,
 388				  struct ftgmac100_rxdes *rxdes, gfp_t gfp)
 389{
 390	struct net_device *netdev = priv->netdev;
 391	struct sk_buff *skb;
 392	dma_addr_t map;
 393	int err = 0;
 394
 395	skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE);
 396	if (unlikely(!skb)) {
 397		if (net_ratelimit())
 398			netdev_warn(netdev, "failed to allocate rx skb\n");
 399		err = -ENOMEM;
 400		map = priv->rx_scratch_dma;
 401	} else {
 402		map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE,
 403				     DMA_FROM_DEVICE);
 404		if (unlikely(dma_mapping_error(priv->dev, map))) {
 405			if (net_ratelimit())
 406				netdev_err(netdev, "failed to map rx page\n");
 407			dev_kfree_skb_any(skb);
 408			map = priv->rx_scratch_dma;
 409			skb = NULL;
 410			err = -ENOMEM;
 411		}
 412	}
 413
 414	/* Store skb */
 415	priv->rx_skbs[entry] = skb;
 416
 417	/* Store DMA address into RX desc */
 418	rxdes->rxdes3 = cpu_to_le32(map);
 419
 420	/* Ensure the above is ordered vs clearing the OWN bit */
 421	dma_wmb();
 422
 423	/* Clean status (which resets own bit) */
 424	if (entry == (priv->rx_q_entries - 1))
 425		rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask);
 426	else
 427		rxdes->rxdes0 = 0;
 428
 429	return err;
 430}
 431
 432static unsigned int ftgmac100_next_rx_pointer(struct ftgmac100 *priv,
 433					      unsigned int pointer)
 434{
 435	return (pointer + 1) & (priv->rx_q_entries - 1);
 436}
 437
 438static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status)
 439{
 440	struct net_device *netdev = priv->netdev;
 441
 442	if (status & FTGMAC100_RXDES0_RX_ERR)
 443		netdev->stats.rx_errors++;
 444
 445	if (status & FTGMAC100_RXDES0_CRC_ERR)
 446		netdev->stats.rx_crc_errors++;
 447
 448	if (status & (FTGMAC100_RXDES0_FTL |
 449		      FTGMAC100_RXDES0_RUNT |
 450		      FTGMAC100_RXDES0_RX_ODD_NB))
 451		netdev->stats.rx_length_errors++;
 452}
 453
 454static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
 455{
 456	struct net_device *netdev = priv->netdev;
 457	struct ftgmac100_rxdes *rxdes;
 458	struct sk_buff *skb;
 459	unsigned int pointer, size;
 460	u32 status, csum_vlan;
 461	dma_addr_t map;
 462
 463	/* Grab next RX descriptor */
 464	pointer = priv->rx_pointer;
 465	rxdes = &priv->rxdes[pointer];
 466
 467	/* Grab descriptor status */
 468	status = le32_to_cpu(rxdes->rxdes0);
 469
 470	/* Do we have a packet ? */
 471	if (!(status & FTGMAC100_RXDES0_RXPKT_RDY))
 472		return false;
 473
 474	/* Order subsequent reads with the test for the ready bit */
 475	dma_rmb();
 476
 477	/* We don't cope with fragmented RX packets */
 478	if (unlikely(!(status & FTGMAC100_RXDES0_FRS) ||
 479		     !(status & FTGMAC100_RXDES0_LRS)))
 480		goto drop;
 481
 482	/* Grab received size and csum vlan field in the descriptor */
 483	size = status & FTGMAC100_RXDES0_VDBC;
 484	csum_vlan = le32_to_cpu(rxdes->rxdes1);
 485
 486	/* Any error (other than csum offload) flagged ? */
 487	if (unlikely(status & RXDES0_ANY_ERROR)) {
 488		/* Correct for incorrect flagging of runt packets
 489		 * with vlan tags... Just accept a runt packet that
 490		 * has been flagged as vlan and whose size is at
 491		 * least 60 bytes.
 492		 */
 493		if ((status & FTGMAC100_RXDES0_RUNT) &&
 494		    (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) &&
 495		    (size >= 60))
 496			status &= ~FTGMAC100_RXDES0_RUNT;
 497
 498		/* Any error still in there ? */
 499		if (status & RXDES0_ANY_ERROR) {
 500			ftgmac100_rx_packet_error(priv, status);
 501			goto drop;
 502		}
 503	}
 504
 505	/* If the packet had no skb (failed to allocate earlier)
 506	 * then try to allocate one and skip
 507	 */
 508	skb = priv->rx_skbs[pointer];
 509	if (!unlikely(skb)) {
 510		ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
 511		goto drop;
 512	}
 513
 514	if (unlikely(status & FTGMAC100_RXDES0_MULTICAST))
 515		netdev->stats.multicast++;
 516
 517	/* If the HW found checksum errors, bounce it to software.
 518	 *
 519	 * If we didn't, we need to see if the packet was recognized
 520	 * by HW as one of the supported checksummed protocols before
 521	 * we accept the HW test results.
 522	 */
 523	if (netdev->features & NETIF_F_RXCSUM) {
 524		u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR |
 525			FTGMAC100_RXDES1_UDP_CHKSUM_ERR |
 526			FTGMAC100_RXDES1_IP_CHKSUM_ERR;
 527		if ((csum_vlan & err_bits) ||
 528		    !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK))
 529			skb->ip_summed = CHECKSUM_NONE;
 530		else
 531			skb->ip_summed = CHECKSUM_UNNECESSARY;
 532	}
 533
 534	/* Transfer received size to skb */
 535	skb_put(skb, size);
 536
 537	/* Extract vlan tag */
 538	if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
 539	    (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL))
 540		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
 541				       csum_vlan & 0xffff);
 542
 543	/* Tear down DMA mapping, do necessary cache management */
 544	map = le32_to_cpu(rxdes->rxdes3);
 545
 546#if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU)
 547	/* When we don't have an iommu, we can save cycles by not
 548	 * invalidating the cache for the part of the packet that
 549	 * wasn't received.
 550	 */
 551	dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE);
 552#else
 553	dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
 554#endif
 555
 556
 557	/* Resplenish rx ring */
 558	ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
 559	priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
 560
 561	skb->protocol = eth_type_trans(skb, netdev);
 562
 563	netdev->stats.rx_packets++;
 564	netdev->stats.rx_bytes += size;
 565
 566	/* push packet to protocol stack */
 567	if (skb->ip_summed == CHECKSUM_NONE)
 568		netif_receive_skb(skb);
 569	else
 570		napi_gro_receive(&priv->napi, skb);
 571
 572	(*processed)++;
 573	return true;
 574
 575 drop:
 576	/* Clean rxdes0 (which resets own bit) */
 577	rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask);
 578	priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
 579	netdev->stats.rx_dropped++;
 580	return true;
 581}
 582
 583static u32 ftgmac100_base_tx_ctlstat(struct ftgmac100 *priv,
 584				     unsigned int index)
 585{
 586	if (index == (priv->tx_q_entries - 1))
 587		return priv->txdes0_edotr_mask;
 588	else
 589		return 0;
 590}
 591
 592static unsigned int ftgmac100_next_tx_pointer(struct ftgmac100 *priv,
 593					      unsigned int pointer)
 594{
 595	return (pointer + 1) & (priv->tx_q_entries - 1);
 596}
 597
 598static u32 ftgmac100_tx_buf_avail(struct ftgmac100 *priv)
 599{
 600	/* Returns the number of available slots in the TX queue
 601	 *
 602	 * This always leaves one free slot so we don't have to
 603	 * worry about empty vs. full, and this simplifies the
 604	 * test for ftgmac100_tx_buf_cleanable() below
 605	 */
 606	return (priv->tx_clean_pointer - priv->tx_pointer - 1) &
 607		(priv->tx_q_entries - 1);
 608}
 609
 610static bool ftgmac100_tx_buf_cleanable(struct ftgmac100 *priv)
 611{
 612	return priv->tx_pointer != priv->tx_clean_pointer;
 613}
 614
 615static void ftgmac100_free_tx_packet(struct ftgmac100 *priv,
 616				     unsigned int pointer,
 617				     struct sk_buff *skb,
 618				     struct ftgmac100_txdes *txdes,
 619				     u32 ctl_stat)
 620{
 621	dma_addr_t map = le32_to_cpu(txdes->txdes3);
 622	size_t len;
 623
 624	if (ctl_stat & FTGMAC100_TXDES0_FTS) {
 625		len = skb_headlen(skb);
 626		dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE);
 627	} else {
 628		len = FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat);
 629		dma_unmap_page(priv->dev, map, len, DMA_TO_DEVICE);
 630	}
 631
 632	/* Free SKB on last segment */
 633	if (ctl_stat & FTGMAC100_TXDES0_LTS)
 634		dev_kfree_skb(skb);
 635	priv->tx_skbs[pointer] = NULL;
 636}
 637
 638static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
 639{
 640	struct net_device *netdev = priv->netdev;
 641	struct ftgmac100_txdes *txdes;
 642	struct sk_buff *skb;
 643	unsigned int pointer;
 644	u32 ctl_stat;
 645
 646	pointer = priv->tx_clean_pointer;
 647	txdes = &priv->txdes[pointer];
 648
 649	ctl_stat = le32_to_cpu(txdes->txdes0);
 650	if (ctl_stat & FTGMAC100_TXDES0_TXDMA_OWN)
 651		return false;
 652
 653	skb = priv->tx_skbs[pointer];
 654	netdev->stats.tx_packets++;
 655	netdev->stats.tx_bytes += skb->len;
 656	ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
 657	txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
 658
 659	priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv, pointer);
 660
 661	return true;
 662}
 663
 664static void ftgmac100_tx_complete(struct ftgmac100 *priv)
 665{
 666	struct net_device *netdev = priv->netdev;
 667
 668	/* Process all completed packets */
 669	while (ftgmac100_tx_buf_cleanable(priv) &&
 670	       ftgmac100_tx_complete_packet(priv))
 671		;
 672
 673	/* Restart queue if needed */
 674	smp_mb();
 675	if (unlikely(netif_queue_stopped(netdev) &&
 676		     ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)) {
 677		struct netdev_queue *txq;
 678
 679		txq = netdev_get_tx_queue(netdev, 0);
 680		__netif_tx_lock(txq, smp_processor_id());
 681		if (netif_queue_stopped(netdev) &&
 682		    ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
 683			netif_wake_queue(netdev);
 684		__netif_tx_unlock(txq);
 685	}
 686}
 687
 688static bool ftgmac100_prep_tx_csum(struct sk_buff *skb, u32 *csum_vlan)
 689{
 690	if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
 691		u8 ip_proto = ip_hdr(skb)->protocol;
 692
 693		*csum_vlan |= FTGMAC100_TXDES1_IP_CHKSUM;
 694		switch(ip_proto) {
 695		case IPPROTO_TCP:
 696			*csum_vlan |= FTGMAC100_TXDES1_TCP_CHKSUM;
 697			return true;
 698		case IPPROTO_UDP:
 699			*csum_vlan |= FTGMAC100_TXDES1_UDP_CHKSUM;
 700			return true;
 701		case IPPROTO_IP:
 702			return true;
 703		}
 704	}
 705	return skb_checksum_help(skb) == 0;
 706}
 707
 708static netdev_tx_t ftgmac100_hard_start_xmit(struct sk_buff *skb,
 709					     struct net_device *netdev)
 710{
 711	struct ftgmac100 *priv = netdev_priv(netdev);
 712	struct ftgmac100_txdes *txdes, *first;
 713	unsigned int pointer, nfrags, len, i, j;
 714	u32 f_ctl_stat, ctl_stat, csum_vlan;
 715	dma_addr_t map;
 716
 717	/* The HW doesn't pad small frames */
 718	if (eth_skb_pad(skb)) {
 719		netdev->stats.tx_dropped++;
 720		return NETDEV_TX_OK;
 721	}
 722
 723	/* Reject oversize packets */
 724	if (unlikely(skb->len > MAX_PKT_SIZE)) {
 725		if (net_ratelimit())
 726			netdev_dbg(netdev, "tx packet too big\n");
 727		goto drop;
 728	}
 729
 730	/* Do we have a limit on #fragments ? I yet have to get a reply
 731	 * from Aspeed. If there's one I haven't hit it.
 732	 */
 733	nfrags = skb_shinfo(skb)->nr_frags;
 734
 735	/* Setup HW checksumming */
 736	csum_vlan = 0;
 737	if (skb->ip_summed == CHECKSUM_PARTIAL &&
 738	    !ftgmac100_prep_tx_csum(skb, &csum_vlan))
 739		goto drop;
 740
 741	/* Add VLAN tag */
 742	if (skb_vlan_tag_present(skb)) {
 743		csum_vlan |= FTGMAC100_TXDES1_INS_VLANTAG;
 744		csum_vlan |= skb_vlan_tag_get(skb) & 0xffff;
 745	}
 746
 747	/* Get header len */
 748	len = skb_headlen(skb);
 749
 750	/* Map the packet head */
 751	map = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE);
 752	if (dma_mapping_error(priv->dev, map)) {
 753		if (net_ratelimit())
 754			netdev_err(netdev, "map tx packet head failed\n");
 755		goto drop;
 756	}
 757
 758	/* Grab the next free tx descriptor */
 759	pointer = priv->tx_pointer;
 760	txdes = first = &priv->txdes[pointer];
 761
 762	/* Setup it up with the packet head. Don't write the head to the
 763	 * ring just yet
 764	 */
 765	priv->tx_skbs[pointer] = skb;
 766	f_ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
 767	f_ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
 768	f_ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
 769	f_ctl_stat |= FTGMAC100_TXDES0_FTS;
 770	if (nfrags == 0)
 771		f_ctl_stat |= FTGMAC100_TXDES0_LTS;
 772	txdes->txdes3 = cpu_to_le32(map);
 773	txdes->txdes1 = cpu_to_le32(csum_vlan);
 774
 775	/* Next descriptor */
 776	pointer = ftgmac100_next_tx_pointer(priv, pointer);
 777
 778	/* Add the fragments */
 779	for (i = 0; i < nfrags; i++) {
 780		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 781
 782		len = skb_frag_size(frag);
 783
 784		/* Map it */
 785		map = skb_frag_dma_map(priv->dev, frag, 0, len,
 786				       DMA_TO_DEVICE);
 787		if (dma_mapping_error(priv->dev, map))
 788			goto dma_err;
 789
 790		/* Setup descriptor */
 791		priv->tx_skbs[pointer] = skb;
 792		txdes = &priv->txdes[pointer];
 793		ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
 794		ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
 795		ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
 796		if (i == (nfrags - 1))
 797			ctl_stat |= FTGMAC100_TXDES0_LTS;
 798		txdes->txdes0 = cpu_to_le32(ctl_stat);
 799		txdes->txdes1 = 0;
 800		txdes->txdes3 = cpu_to_le32(map);
 801
 802		/* Next one */
 803		pointer = ftgmac100_next_tx_pointer(priv, pointer);
 804	}
 805
 806	/* Order the previous packet and descriptor udpates
 807	 * before setting the OWN bit on the first descriptor.
 808	 */
 809	dma_wmb();
 810	first->txdes0 = cpu_to_le32(f_ctl_stat);
 811
 812	/* Update next TX pointer */
 813	priv->tx_pointer = pointer;
 814
 815	/* If there isn't enough room for all the fragments of a new packet
 816	 * in the TX ring, stop the queue. The sequence below is race free
 817	 * vs. a concurrent restart in ftgmac100_poll()
 818	 */
 819	if (unlikely(ftgmac100_tx_buf_avail(priv) < TX_THRESHOLD)) {
 820		netif_stop_queue(netdev);
 821		/* Order the queue stop with the test below */
 822		smp_mb();
 823		if (ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
 824			netif_wake_queue(netdev);
 825	}
 826
 827	/* Poke transmitter to read the updated TX descriptors */
 828	iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
 829
 830	return NETDEV_TX_OK;
 831
 832 dma_err:
 833	if (net_ratelimit())
 834		netdev_err(netdev, "map tx fragment failed\n");
 835
 836	/* Free head */
 837	pointer = priv->tx_pointer;
 838	ftgmac100_free_tx_packet(priv, pointer, skb, first, f_ctl_stat);
 839	first->txdes0 = cpu_to_le32(f_ctl_stat & priv->txdes0_edotr_mask);
 840
 841	/* Then all fragments */
 842	for (j = 0; j < i; j++) {
 843		pointer = ftgmac100_next_tx_pointer(priv, pointer);
 844		txdes = &priv->txdes[pointer];
 845		ctl_stat = le32_to_cpu(txdes->txdes0);
 846		ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
 847		txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
 848	}
 849
 850	/* This cannot be reached if we successfully mapped the
 851	 * last fragment, so we know ftgmac100_free_tx_packet()
 852	 * hasn't freed the skb yet.
 853	 */
 854 drop:
 855	/* Drop the packet */
 856	dev_kfree_skb_any(skb);
 857	netdev->stats.tx_dropped++;
 858
 859	return NETDEV_TX_OK;
 860}
 861
 862static void ftgmac100_free_buffers(struct ftgmac100 *priv)
 863{
 864	int i;
 865
 866	/* Free all RX buffers */
 867	for (i = 0; i < priv->rx_q_entries; i++) {
 868		struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
 869		struct sk_buff *skb = priv->rx_skbs[i];
 870		dma_addr_t map = le32_to_cpu(rxdes->rxdes3);
 871
 872		if (!skb)
 873			continue;
 874
 875		priv->rx_skbs[i] = NULL;
 876		dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
 877		dev_kfree_skb_any(skb);
 878	}
 879
 880	/* Free all TX buffers */
 881	for (i = 0; i < priv->tx_q_entries; i++) {
 882		struct ftgmac100_txdes *txdes = &priv->txdes[i];
 883		struct sk_buff *skb = priv->tx_skbs[i];
 884
 885		if (!skb)
 886			continue;
 887		ftgmac100_free_tx_packet(priv, i, skb, txdes,
 888					 le32_to_cpu(txdes->txdes0));
 889	}
 890}
 891
 892static void ftgmac100_free_rings(struct ftgmac100 *priv)
 893{
 894	/* Free skb arrays */
 895	kfree(priv->rx_skbs);
 896	kfree(priv->tx_skbs);
 897
 898	/* Free descriptors */
 899	if (priv->rxdes)
 900		dma_free_coherent(priv->dev, MAX_RX_QUEUE_ENTRIES *
 901				  sizeof(struct ftgmac100_rxdes),
 902				  priv->rxdes, priv->rxdes_dma);
 903	priv->rxdes = NULL;
 904
 905	if (priv->txdes)
 906		dma_free_coherent(priv->dev, MAX_TX_QUEUE_ENTRIES *
 907				  sizeof(struct ftgmac100_txdes),
 908				  priv->txdes, priv->txdes_dma);
 909	priv->txdes = NULL;
 910
 911	/* Free scratch packet buffer */
 912	if (priv->rx_scratch)
 913		dma_free_coherent(priv->dev, RX_BUF_SIZE,
 914				  priv->rx_scratch, priv->rx_scratch_dma);
 915}
 916
 917static int ftgmac100_alloc_rings(struct ftgmac100 *priv)
 918{
 919	/* Allocate skb arrays */
 920	priv->rx_skbs = kcalloc(MAX_RX_QUEUE_ENTRIES, sizeof(void *),
 921				GFP_KERNEL);
 922	if (!priv->rx_skbs)
 923		return -ENOMEM;
 924	priv->tx_skbs = kcalloc(MAX_TX_QUEUE_ENTRIES, sizeof(void *),
 925				GFP_KERNEL);
 926	if (!priv->tx_skbs)
 927		return -ENOMEM;
 928
 929	/* Allocate descriptors */
 930	priv->rxdes = dma_alloc_coherent(priv->dev,
 931					 MAX_RX_QUEUE_ENTRIES * sizeof(struct ftgmac100_rxdes),
 932					 &priv->rxdes_dma, GFP_KERNEL);
 933	if (!priv->rxdes)
 934		return -ENOMEM;
 935	priv->txdes = dma_alloc_coherent(priv->dev,
 936					 MAX_TX_QUEUE_ENTRIES * sizeof(struct ftgmac100_txdes),
 937					 &priv->txdes_dma, GFP_KERNEL);
 938	if (!priv->txdes)
 939		return -ENOMEM;
 940
 941	/* Allocate scratch packet buffer */
 942	priv->rx_scratch = dma_alloc_coherent(priv->dev,
 943					      RX_BUF_SIZE,
 944					      &priv->rx_scratch_dma,
 945					      GFP_KERNEL);
 946	if (!priv->rx_scratch)
 947		return -ENOMEM;
 948
 949	return 0;
 950}
 951
 952static void ftgmac100_init_rings(struct ftgmac100 *priv)
 953{
 954	struct ftgmac100_rxdes *rxdes = NULL;
 955	struct ftgmac100_txdes *txdes = NULL;
 956	int i;
 957
 958	/* Update entries counts */
 959	priv->rx_q_entries = priv->new_rx_q_entries;
 960	priv->tx_q_entries = priv->new_tx_q_entries;
 961
 962	if (WARN_ON(priv->rx_q_entries < MIN_RX_QUEUE_ENTRIES))
 963		return;
 964
 965	/* Initialize RX ring */
 966	for (i = 0; i < priv->rx_q_entries; i++) {
 967		rxdes = &priv->rxdes[i];
 968		rxdes->rxdes0 = 0;
 969		rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma);
 970	}
 971	/* Mark the end of the ring */
 972	rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask);
 973
 974	if (WARN_ON(priv->tx_q_entries < MIN_RX_QUEUE_ENTRIES))
 975		return;
 976
 977	/* Initialize TX ring */
 978	for (i = 0; i < priv->tx_q_entries; i++) {
 979		txdes = &priv->txdes[i];
 980		txdes->txdes0 = 0;
 981	}
 982	txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask);
 983}
 984
 985static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv)
 986{
 987	int i;
 988
 989	for (i = 0; i < priv->rx_q_entries; i++) {
 990		struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
 991
 992		if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL))
 993			return -ENOMEM;
 994	}
 995	return 0;
 996}
 997
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 998static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
 999{
1000	struct net_device *netdev = bus->priv;
1001	struct ftgmac100 *priv = netdev_priv(netdev);
1002	unsigned int phycr;
1003	int i;
1004
1005	phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1006
1007	/* preserve MDC cycle threshold */
1008	phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1009
1010	phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1011		 FTGMAC100_PHYCR_REGAD(regnum) |
1012		 FTGMAC100_PHYCR_MIIRD;
1013
1014	iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1015
1016	for (i = 0; i < 10; i++) {
1017		phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1018
1019		if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
1020			int data;
1021
1022			data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
1023			return FTGMAC100_PHYDATA_MIIRDATA(data);
1024		}
1025
1026		udelay(100);
1027	}
1028
1029	netdev_err(netdev, "mdio read timed out\n");
1030	return -EIO;
1031}
1032
1033static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
1034				   int regnum, u16 value)
1035{
1036	struct net_device *netdev = bus->priv;
1037	struct ftgmac100 *priv = netdev_priv(netdev);
1038	unsigned int phycr;
1039	int data;
1040	int i;
1041
1042	phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1043
1044	/* preserve MDC cycle threshold */
1045	phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1046
1047	phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1048		 FTGMAC100_PHYCR_REGAD(regnum) |
1049		 FTGMAC100_PHYCR_MIIWR;
1050
1051	data = FTGMAC100_PHYDATA_MIIWDATA(value);
1052
1053	iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
1054	iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1055
1056	for (i = 0; i < 10; i++) {
1057		phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1058
1059		if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
1060			return 0;
1061
1062		udelay(100);
1063	}
1064
1065	netdev_err(netdev, "mdio write timed out\n");
1066	return -EIO;
1067}
1068
1069static void ftgmac100_get_drvinfo(struct net_device *netdev,
1070				  struct ethtool_drvinfo *info)
1071{
1072	strscpy(info->driver, DRV_NAME, sizeof(info->driver));
1073	strscpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
 
1074}
1075
1076static void
1077ftgmac100_get_ringparam(struct net_device *netdev,
1078			struct ethtool_ringparam *ering,
1079			struct kernel_ethtool_ringparam *kernel_ering,
1080			struct netlink_ext_ack *extack)
1081{
1082	struct ftgmac100 *priv = netdev_priv(netdev);
1083
1084	memset(ering, 0, sizeof(*ering));
1085	ering->rx_max_pending = MAX_RX_QUEUE_ENTRIES;
1086	ering->tx_max_pending = MAX_TX_QUEUE_ENTRIES;
1087	ering->rx_pending = priv->rx_q_entries;
1088	ering->tx_pending = priv->tx_q_entries;
1089}
1090
1091static int
1092ftgmac100_set_ringparam(struct net_device *netdev,
1093			struct ethtool_ringparam *ering,
1094			struct kernel_ethtool_ringparam *kernel_ering,
1095			struct netlink_ext_ack *extack)
1096{
1097	struct ftgmac100 *priv = netdev_priv(netdev);
1098
1099	if (ering->rx_pending > MAX_RX_QUEUE_ENTRIES ||
1100	    ering->tx_pending > MAX_TX_QUEUE_ENTRIES ||
1101	    ering->rx_pending < MIN_RX_QUEUE_ENTRIES ||
1102	    ering->tx_pending < MIN_TX_QUEUE_ENTRIES ||
1103	    !is_power_of_2(ering->rx_pending) ||
1104	    !is_power_of_2(ering->tx_pending))
1105		return -EINVAL;
1106
1107	priv->new_rx_q_entries = ering->rx_pending;
1108	priv->new_tx_q_entries = ering->tx_pending;
1109	if (netif_running(netdev))
1110		schedule_work(&priv->reset_task);
1111
1112	return 0;
1113}
1114
1115static void ftgmac100_get_pauseparam(struct net_device *netdev,
1116				     struct ethtool_pauseparam *pause)
1117{
1118	struct ftgmac100 *priv = netdev_priv(netdev);
1119
1120	pause->autoneg = priv->aneg_pause;
1121	pause->tx_pause = priv->tx_pause;
1122	pause->rx_pause = priv->rx_pause;
1123}
1124
1125static int ftgmac100_set_pauseparam(struct net_device *netdev,
1126				    struct ethtool_pauseparam *pause)
1127{
1128	struct ftgmac100 *priv = netdev_priv(netdev);
1129	struct phy_device *phydev = netdev->phydev;
1130
1131	priv->aneg_pause = pause->autoneg;
1132	priv->tx_pause = pause->tx_pause;
1133	priv->rx_pause = pause->rx_pause;
1134
1135	if (phydev)
1136		phy_set_asym_pause(phydev, pause->rx_pause, pause->tx_pause);
1137
1138	if (netif_running(netdev)) {
1139		if (!(phydev && priv->aneg_pause))
1140			ftgmac100_config_pause(priv);
1141	}
1142
1143	return 0;
1144}
1145
1146static const struct ethtool_ops ftgmac100_ethtool_ops = {
1147	.get_drvinfo		= ftgmac100_get_drvinfo,
1148	.get_link		= ethtool_op_get_link,
1149	.get_link_ksettings	= phy_ethtool_get_link_ksettings,
1150	.set_link_ksettings	= phy_ethtool_set_link_ksettings,
1151	.nway_reset		= phy_ethtool_nway_reset,
1152	.get_ringparam		= ftgmac100_get_ringparam,
1153	.set_ringparam		= ftgmac100_set_ringparam,
1154	.get_pauseparam		= ftgmac100_get_pauseparam,
1155	.set_pauseparam		= ftgmac100_set_pauseparam,
1156};
1157
1158static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
1159{
1160	struct net_device *netdev = dev_id;
1161	struct ftgmac100 *priv = netdev_priv(netdev);
1162	unsigned int status, new_mask = FTGMAC100_INT_BAD;
1163
1164	/* Fetch and clear interrupt bits, process abnormal ones */
1165	status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1166	iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
1167	if (unlikely(status & FTGMAC100_INT_BAD)) {
1168
1169		/* RX buffer unavailable */
1170		if (status & FTGMAC100_INT_NO_RXBUF)
1171			netdev->stats.rx_over_errors++;
1172
1173		/* received packet lost due to RX FIFO full */
1174		if (status & FTGMAC100_INT_RPKT_LOST)
1175			netdev->stats.rx_fifo_errors++;
1176
1177		/* sent packet lost due to excessive TX collision */
1178		if (status & FTGMAC100_INT_XPKT_LOST)
1179			netdev->stats.tx_fifo_errors++;
1180
1181		/* AHB error -> Reset the chip */
1182		if (status & FTGMAC100_INT_AHB_ERR) {
1183			if (net_ratelimit())
1184				netdev_warn(netdev,
1185					   "AHB bus error ! Resetting chip.\n");
1186			iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1187			schedule_work(&priv->reset_task);
1188			return IRQ_HANDLED;
1189		}
1190
1191		/* We may need to restart the MAC after such errors, delay
1192		 * this until after we have freed some Rx buffers though
1193		 */
1194		priv->need_mac_restart = true;
1195
1196		/* Disable those errors until we restart */
1197		new_mask &= ~status;
1198	}
1199
1200	/* Only enable "bad" interrupts while NAPI is on */
1201	iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER);
1202
1203	/* Schedule NAPI bh */
1204	napi_schedule_irqoff(&priv->napi);
1205
1206	return IRQ_HANDLED;
1207}
1208
1209static bool ftgmac100_check_rx(struct ftgmac100 *priv)
1210{
1211	struct ftgmac100_rxdes *rxdes = &priv->rxdes[priv->rx_pointer];
1212
1213	/* Do we have a packet ? */
1214	return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY));
1215}
1216
1217static int ftgmac100_poll(struct napi_struct *napi, int budget)
1218{
1219	struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1220	int work_done = 0;
1221	bool more;
1222
1223	/* Handle TX completions */
1224	if (ftgmac100_tx_buf_cleanable(priv))
1225		ftgmac100_tx_complete(priv);
1226
1227	/* Handle RX packets */
1228	do {
1229		more = ftgmac100_rx_packet(priv, &work_done);
1230	} while (more && work_done < budget);
1231
1232
1233	/* The interrupt is telling us to kick the MAC back to life
1234	 * after an RX overflow
1235	 */
1236	if (unlikely(priv->need_mac_restart)) {
1237		ftgmac100_start_hw(priv);
1238		priv->need_mac_restart = false;
1239
1240		/* Re-enable "bad" interrupts */
1241		iowrite32(FTGMAC100_INT_BAD,
1242			  priv->base + FTGMAC100_OFFSET_IER);
1243	}
1244
1245	/* As long as we are waiting for transmit packets to be
1246	 * completed we keep NAPI going
1247	 */
1248	if (ftgmac100_tx_buf_cleanable(priv))
1249		work_done = budget;
1250
1251	if (work_done < budget) {
1252		/* We are about to re-enable all interrupts. However
1253		 * the HW has been latching RX/TX packet interrupts while
1254		 * they were masked. So we clear them first, then we need
1255		 * to re-check if there's something to process
1256		 */
1257		iowrite32(FTGMAC100_INT_RXTX,
1258			  priv->base + FTGMAC100_OFFSET_ISR);
1259
1260		/* Push the above (and provides a barrier vs. subsequent
1261		 * reads of the descriptor).
1262		 */
1263		ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1264
1265		/* Check RX and TX descriptors for more work to do */
1266		if (ftgmac100_check_rx(priv) ||
1267		    ftgmac100_tx_buf_cleanable(priv))
1268			return budget;
1269
1270		/* deschedule NAPI */
1271		napi_complete(napi);
1272
1273		/* enable all interrupts */
1274		iowrite32(FTGMAC100_INT_ALL,
1275			  priv->base + FTGMAC100_OFFSET_IER);
1276	}
1277
1278	return work_done;
1279}
1280
1281static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err)
1282{
1283	int err = 0;
1284
1285	/* Re-init descriptors (adjust queue sizes) */
1286	ftgmac100_init_rings(priv);
1287
1288	/* Realloc rx descriptors */
1289	err = ftgmac100_alloc_rx_buffers(priv);
1290	if (err && !ignore_alloc_err)
1291		return err;
1292
1293	/* Reinit and restart HW */
1294	ftgmac100_init_hw(priv);
1295	ftgmac100_config_pause(priv);
1296	ftgmac100_start_hw(priv);
1297
1298	/* Re-enable the device */
1299	napi_enable(&priv->napi);
1300	netif_start_queue(priv->netdev);
1301
1302	/* Enable all interrupts */
1303	iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER);
1304
1305	return err;
1306}
1307
1308static void ftgmac100_reset(struct ftgmac100 *priv)
1309{
 
 
1310	struct net_device *netdev = priv->netdev;
1311	int err;
1312
1313	netdev_dbg(netdev, "Resetting NIC...\n");
1314
1315	/* Lock the world */
1316	rtnl_lock();
1317	if (netdev->phydev)
1318		mutex_lock(&netdev->phydev->lock);
1319	if (priv->mii_bus)
1320		mutex_lock(&priv->mii_bus->mdio_lock);
1321
1322
1323	/* Check if the interface is still up */
1324	if (!netif_running(netdev))
1325		goto bail;
1326
1327	/* Stop the network stack */
1328	netif_trans_update(netdev);
1329	napi_disable(&priv->napi);
1330	netif_tx_disable(netdev);
1331
1332	/* Stop and reset the MAC */
1333	ftgmac100_stop_hw(priv);
1334	err = ftgmac100_reset_and_config_mac(priv);
1335	if (err) {
1336		/* Not much we can do ... it might come back... */
1337		netdev_err(netdev, "attempting to continue...\n");
1338	}
1339
1340	/* Free all rx and tx buffers */
1341	ftgmac100_free_buffers(priv);
1342
1343	/* Setup everything again and restart chip */
1344	ftgmac100_init_all(priv, true);
1345
1346	netdev_dbg(netdev, "Reset done !\n");
1347 bail:
1348	if (priv->mii_bus)
1349		mutex_unlock(&priv->mii_bus->mdio_lock);
1350	if (netdev->phydev)
1351		mutex_unlock(&netdev->phydev->lock);
1352	rtnl_unlock();
1353}
1354
1355static void ftgmac100_reset_task(struct work_struct *work)
1356{
1357	struct ftgmac100 *priv = container_of(work, struct ftgmac100,
1358					      reset_task);
1359
1360	ftgmac100_reset(priv);
1361}
1362
1363static void ftgmac100_adjust_link(struct net_device *netdev)
1364{
1365	struct ftgmac100 *priv = netdev_priv(netdev);
1366	struct phy_device *phydev = netdev->phydev;
1367	bool tx_pause, rx_pause;
1368	int new_speed;
1369
1370	/* We store "no link" as speed 0 */
1371	if (!phydev->link)
1372		new_speed = 0;
1373	else
1374		new_speed = phydev->speed;
1375
1376	/* Grab pause settings from PHY if configured to do so */
1377	if (priv->aneg_pause) {
1378		rx_pause = tx_pause = phydev->pause;
1379		if (phydev->asym_pause)
1380			tx_pause = !rx_pause;
1381	} else {
1382		rx_pause = priv->rx_pause;
1383		tx_pause = priv->tx_pause;
1384	}
1385
1386	/* Link hasn't changed, do nothing */
1387	if (phydev->speed == priv->cur_speed &&
1388	    phydev->duplex == priv->cur_duplex &&
1389	    rx_pause == priv->rx_pause &&
1390	    tx_pause == priv->tx_pause)
1391		return;
1392
1393	/* Print status if we have a link or we had one and just lost it,
1394	 * don't print otherwise.
1395	 */
1396	if (new_speed || priv->cur_speed)
1397		phy_print_status(phydev);
1398
1399	priv->cur_speed = new_speed;
1400	priv->cur_duplex = phydev->duplex;
1401	priv->rx_pause = rx_pause;
1402	priv->tx_pause = tx_pause;
1403
1404	/* Link is down, do nothing else */
1405	if (!new_speed)
1406		return;
1407
1408	/* Disable all interrupts */
1409	iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1410
1411	/* Release phy lock to allow ftgmac100_reset to aquire it, keeping lock
1412	 * order consistent to prevent dead lock.
1413	 */
1414	if (netdev->phydev)
1415		mutex_unlock(&netdev->phydev->lock);
1416
1417	ftgmac100_reset(priv);
1418
1419	if (netdev->phydev)
1420		mutex_lock(&netdev->phydev->lock);
1421
1422}
1423
1424static int ftgmac100_mii_probe(struct net_device *netdev)
1425{
1426	struct ftgmac100 *priv = netdev_priv(netdev);
1427	struct platform_device *pdev = to_platform_device(priv->dev);
1428	struct device_node *np = pdev->dev.of_node;
1429	struct phy_device *phydev;
1430	phy_interface_t phy_intf;
1431	int err;
1432
1433	/* Default to RGMII. It's a gigabit part after all */
1434	err = of_get_phy_mode(np, &phy_intf);
1435	if (err)
1436		phy_intf = PHY_INTERFACE_MODE_RGMII;
1437
1438	/* Aspeed only supports these. I don't know about other IP
1439	 * block vendors so I'm going to just let them through for
1440	 * now. Note that this is only a warning if for some obscure
1441	 * reason the DT really means to lie about it or it's a newer
1442	 * part we don't know about.
1443	 *
1444	 * On the Aspeed SoC there are additionally straps and SCU
1445	 * control bits that could tell us what the interface is
1446	 * (or allow us to configure it while the IP block is held
1447	 * in reset). For now I chose to keep this driver away from
1448	 * those SoC specific bits and assume the device-tree is
1449	 * right and the SCU has been configured properly by pinmux
1450	 * or the firmware.
1451	 */
1452	if (priv->is_aspeed && !(phy_interface_mode_is_rgmii(phy_intf))) {
1453		netdev_warn(netdev,
1454			    "Unsupported PHY mode %s !\n",
1455			    phy_modes(phy_intf));
1456	}
1457
1458	phydev = phy_find_first(priv->mii_bus);
1459	if (!phydev) {
1460		netdev_info(netdev, "%s: no PHY found\n", netdev->name);
1461		return -ENODEV;
1462	}
1463
1464	phydev = phy_connect(netdev, phydev_name(phydev),
1465			     &ftgmac100_adjust_link, phy_intf);
1466
1467	if (IS_ERR(phydev)) {
1468		netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
1469		return PTR_ERR(phydev);
1470	}
1471
1472	/* Indicate that we support PAUSE frames (see comment in
1473	 * Documentation/networking/phy.rst)
1474	 */
1475	phy_support_asym_pause(phydev);
1476
1477	/* Display what we found */
1478	phy_attached_info(phydev);
1479
1480	return 0;
1481}
1482
1483static int ftgmac100_open(struct net_device *netdev)
1484{
1485	struct ftgmac100 *priv = netdev_priv(netdev);
1486	int err;
1487
1488	/* Allocate ring buffers  */
1489	err = ftgmac100_alloc_rings(priv);
1490	if (err) {
1491		netdev_err(netdev, "Failed to allocate descriptors\n");
1492		return err;
1493	}
1494
1495	/* When using NC-SI we force the speed to 100Mbit/s full duplex,
1496	 *
1497	 * Otherwise we leave it set to 0 (no link), the link
1498	 * message from the PHY layer will handle setting it up to
1499	 * something else if needed.
1500	 */
1501	if (priv->use_ncsi) {
1502		priv->cur_duplex = DUPLEX_FULL;
1503		priv->cur_speed = SPEED_100;
1504	} else {
1505		priv->cur_duplex = 0;
1506		priv->cur_speed = 0;
1507	}
1508
1509	/* Reset the hardware */
1510	err = ftgmac100_reset_and_config_mac(priv);
1511	if (err)
1512		goto err_hw;
1513
1514	/* Initialize NAPI */
1515	netif_napi_add(netdev, &priv->napi, ftgmac100_poll);
1516
1517	/* Grab our interrupt */
1518	err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1519	if (err) {
1520		netdev_err(netdev, "failed to request irq %d\n", netdev->irq);
1521		goto err_irq;
1522	}
1523
1524	/* Start things up */
1525	err = ftgmac100_init_all(priv, false);
1526	if (err) {
1527		netdev_err(netdev, "Failed to allocate packet buffers\n");
1528		goto err_alloc;
1529	}
1530
1531	if (netdev->phydev) {
1532		/* If we have a PHY, start polling */
1533		phy_start(netdev->phydev);
1534	} else if (priv->use_ncsi) {
1535		/* If using NC-SI, set our carrier on and start the stack */
1536		netif_carrier_on(netdev);
1537
1538		/* Start the NCSI device */
1539		err = ncsi_start_dev(priv->ndev);
1540		if (err)
1541			goto err_ncsi;
1542	}
1543
1544	return 0;
1545
1546 err_ncsi:
1547	napi_disable(&priv->napi);
1548	netif_stop_queue(netdev);
1549 err_alloc:
1550	ftgmac100_free_buffers(priv);
1551	free_irq(netdev->irq, netdev);
1552 err_irq:
1553	netif_napi_del(&priv->napi);
1554 err_hw:
1555	iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1556	ftgmac100_free_rings(priv);
1557	return err;
1558}
1559
1560static int ftgmac100_stop(struct net_device *netdev)
1561{
1562	struct ftgmac100 *priv = netdev_priv(netdev);
1563
1564	/* Note about the reset task: We are called with the rtnl lock
1565	 * held, so we are synchronized against the core of the reset
1566	 * task. We must not try to synchronously cancel it otherwise
1567	 * we can deadlock. But since it will test for netif_running()
1568	 * which has already been cleared by the net core, we don't
1569	 * anything special to do.
1570	 */
1571
1572	/* disable all interrupts */
1573	iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1574
1575	netif_stop_queue(netdev);
1576	napi_disable(&priv->napi);
1577	netif_napi_del(&priv->napi);
1578	if (netdev->phydev)
1579		phy_stop(netdev->phydev);
1580	else if (priv->use_ncsi)
1581		ncsi_stop_dev(priv->ndev);
1582
1583	ftgmac100_stop_hw(priv);
1584	free_irq(netdev->irq, netdev);
1585	ftgmac100_free_buffers(priv);
1586	ftgmac100_free_rings(priv);
1587
1588	return 0;
1589}
1590
1591static void ftgmac100_tx_timeout(struct net_device *netdev, unsigned int txqueue)
 
 
 
 
 
 
 
 
 
1592{
1593	struct ftgmac100 *priv = netdev_priv(netdev);
1594
1595	/* Disable all interrupts */
1596	iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1597
1598	/* Do the reset outside of interrupt context */
1599	schedule_work(&priv->reset_task);
1600}
1601
1602static int ftgmac100_set_features(struct net_device *netdev,
1603				  netdev_features_t features)
1604{
1605	struct ftgmac100 *priv = netdev_priv(netdev);
1606	netdev_features_t changed = netdev->features ^ features;
1607
1608	if (!netif_running(netdev))
1609		return 0;
1610
1611	/* Update the vlan filtering bit */
1612	if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
1613		u32 maccr;
1614
1615		maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
1616		if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
1617			maccr |= FTGMAC100_MACCR_RM_VLAN;
1618		else
1619			maccr &= ~FTGMAC100_MACCR_RM_VLAN;
1620		iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
1621	}
1622
1623	return 0;
1624}
1625
1626#ifdef CONFIG_NET_POLL_CONTROLLER
1627static void ftgmac100_poll_controller(struct net_device *netdev)
1628{
1629	unsigned long flags;
1630
1631	local_irq_save(flags);
1632	ftgmac100_interrupt(netdev->irq, netdev);
1633	local_irq_restore(flags);
1634}
1635#endif
1636
1637static const struct net_device_ops ftgmac100_netdev_ops = {
1638	.ndo_open		= ftgmac100_open,
1639	.ndo_stop		= ftgmac100_stop,
1640	.ndo_start_xmit		= ftgmac100_hard_start_xmit,
1641	.ndo_set_mac_address	= ftgmac100_set_mac_addr,
1642	.ndo_validate_addr	= eth_validate_addr,
1643	.ndo_eth_ioctl		= phy_do_ioctl,
1644	.ndo_tx_timeout		= ftgmac100_tx_timeout,
1645	.ndo_set_rx_mode	= ftgmac100_set_rx_mode,
1646	.ndo_set_features	= ftgmac100_set_features,
1647#ifdef CONFIG_NET_POLL_CONTROLLER
1648	.ndo_poll_controller	= ftgmac100_poll_controller,
1649#endif
1650	.ndo_vlan_rx_add_vid	= ncsi_vlan_rx_add_vid,
1651	.ndo_vlan_rx_kill_vid	= ncsi_vlan_rx_kill_vid,
1652};
1653
1654static int ftgmac100_setup_mdio(struct net_device *netdev)
1655{
1656	struct ftgmac100 *priv = netdev_priv(netdev);
1657	struct platform_device *pdev = to_platform_device(priv->dev);
 
1658	struct device_node *np = pdev->dev.of_node;
1659	struct device_node *mdio_np;
1660	int i, err = 0;
1661	u32 reg;
1662
1663	/* initialize mdio bus */
1664	priv->mii_bus = mdiobus_alloc();
1665	if (!priv->mii_bus)
1666		return -EIO;
1667
1668	if (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1669	    of_device_is_compatible(np, "aspeed,ast2500-mac")) {
1670		/* The AST2600 has a separate MDIO controller */
1671
1672		/* For the AST2400 and AST2500 this driver only supports the
1673		 * old MDIO interface
1674		 */
1675		reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR);
1676		reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;
1677		iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR);
1678	}
1679
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1680	priv->mii_bus->name = "ftgmac100_mdio";
1681	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1682		 pdev->name, pdev->id);
1683	priv->mii_bus->parent = priv->dev;
1684	priv->mii_bus->priv = priv->netdev;
1685	priv->mii_bus->read = ftgmac100_mdiobus_read;
1686	priv->mii_bus->write = ftgmac100_mdiobus_write;
1687
1688	for (i = 0; i < PHY_MAX_ADDR; i++)
1689		priv->mii_bus->irq[i] = PHY_POLL;
1690
1691	mdio_np = of_get_child_by_name(np, "mdio");
1692
1693	err = of_mdiobus_register(priv->mii_bus, mdio_np);
1694	if (err) {
1695		dev_err(priv->dev, "Cannot register MDIO bus!\n");
1696		goto err_register_mdiobus;
1697	}
1698
1699	of_node_put(mdio_np);
 
 
 
 
1700
1701	return 0;
1702
 
 
1703err_register_mdiobus:
1704	mdiobus_free(priv->mii_bus);
1705	return err;
1706}
1707
1708static void ftgmac100_phy_disconnect(struct net_device *netdev)
1709{
1710	struct ftgmac100 *priv = netdev_priv(netdev);
1711
1712	if (!netdev->phydev)
1713		return;
1714
1715	phy_disconnect(netdev->phydev);
1716	if (of_phy_is_fixed_link(priv->dev->of_node))
1717		of_phy_deregister_fixed_link(priv->dev->of_node);
1718}
1719
1720static void ftgmac100_destroy_mdio(struct net_device *netdev)
1721{
1722	struct ftgmac100 *priv = netdev_priv(netdev);
1723
1724	if (!priv->mii_bus)
1725		return;
1726
1727	mdiobus_unregister(priv->mii_bus);
1728	mdiobus_free(priv->mii_bus);
1729}
1730
1731static void ftgmac100_ncsi_handler(struct ncsi_dev *nd)
1732{
1733	if (unlikely(nd->state != ncsi_dev_state_functional))
1734		return;
1735
1736	netdev_dbg(nd->dev, "NCSI interface %s\n",
1737		   nd->link_up ? "up" : "down");
1738}
1739
1740static int ftgmac100_setup_clk(struct ftgmac100 *priv)
1741{
1742	struct clk *clk;
1743	int rc;
 
1744
1745	clk = devm_clk_get(priv->dev, NULL /* MACCLK */);
1746	if (IS_ERR(clk))
1747		return PTR_ERR(clk);
1748	priv->clk = clk;
1749	rc = clk_prepare_enable(priv->clk);
1750	if (rc)
1751		return rc;
1752
1753	/* Aspeed specifies a 100MHz clock is required for up to
1754	 * 1000Mbit link speeds. As NCSI is limited to 100Mbit, 25MHz
1755	 * is sufficient
1756	 */
1757	rc = clk_set_rate(priv->clk, priv->use_ncsi ? FTGMAC_25MHZ :
1758			  FTGMAC_100MHZ);
1759	if (rc)
1760		goto cleanup_clk;
1761
1762	/* RCLK is for RMII, typically used for NCSI. Optional because it's not
1763	 * necessary if it's the AST2400 MAC, or the MAC is configured for
1764	 * RGMII, or the controller is not an ASPEED-based controller.
1765	 */
1766	priv->rclk = devm_clk_get_optional(priv->dev, "RCLK");
1767	rc = clk_prepare_enable(priv->rclk);
1768	if (!rc)
1769		return 0;
1770
1771cleanup_clk:
1772	clk_disable_unprepare(priv->clk);
1773
1774	return rc;
1775}
1776
1777static bool ftgmac100_has_child_node(struct device_node *np, const char *name)
1778{
1779	struct device_node *child_np = of_get_child_by_name(np, name);
1780	bool ret = false;
1781
1782	if (child_np) {
1783		ret = true;
1784		of_node_put(child_np);
1785	}
1786
1787	return ret;
1788}
1789
1790static int ftgmac100_probe(struct platform_device *pdev)
1791{
1792	struct resource *res;
1793	int irq;
1794	struct net_device *netdev;
1795	struct ftgmac100 *priv;
1796	struct device_node *np;
1797	int err = 0;
1798
 
 
 
1799	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1800	if (!res)
1801		return -ENXIO;
1802
1803	irq = platform_get_irq(pdev, 0);
1804	if (irq < 0)
1805		return irq;
1806
1807	/* setup net_device */
1808	netdev = alloc_etherdev(sizeof(*priv));
1809	if (!netdev) {
1810		err = -ENOMEM;
1811		goto err_alloc_etherdev;
1812	}
1813
1814	SET_NETDEV_DEV(netdev, &pdev->dev);
1815
1816	netdev->ethtool_ops = &ftgmac100_ethtool_ops;
1817	netdev->netdev_ops = &ftgmac100_netdev_ops;
1818	netdev->watchdog_timeo = 5 * HZ;
1819
1820	platform_set_drvdata(pdev, netdev);
1821
1822	/* setup private data */
1823	priv = netdev_priv(netdev);
1824	priv->netdev = netdev;
1825	priv->dev = &pdev->dev;
1826	INIT_WORK(&priv->reset_task, ftgmac100_reset_task);
1827
1828	/* map io memory */
1829	priv->res = request_mem_region(res->start, resource_size(res),
1830				       dev_name(&pdev->dev));
1831	if (!priv->res) {
1832		dev_err(&pdev->dev, "Could not reserve memory region\n");
1833		err = -ENOMEM;
1834		goto err_req_mem;
1835	}
1836
1837	priv->base = ioremap(res->start, resource_size(res));
1838	if (!priv->base) {
1839		dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1840		err = -EIO;
1841		goto err_ioremap;
1842	}
1843
1844	netdev->irq = irq;
1845
1846	/* Enable pause */
1847	priv->tx_pause = true;
1848	priv->rx_pause = true;
1849	priv->aneg_pause = true;
1850
1851	/* MAC address from chip or random one */
1852	err = ftgmac100_initial_mac(priv);
1853	if (err)
1854		goto err_phy_connect;
1855
1856	np = pdev->dev.of_node;
1857	if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1858		   of_device_is_compatible(np, "aspeed,ast2500-mac") ||
1859		   of_device_is_compatible(np, "aspeed,ast2600-mac"))) {
1860		priv->rxdes0_edorr_mask = BIT(30);
1861		priv->txdes0_edotr_mask = BIT(30);
1862		priv->is_aspeed = true;
1863	} else {
1864		priv->rxdes0_edorr_mask = BIT(15);
1865		priv->txdes0_edotr_mask = BIT(15);
1866	}
1867
1868	if (np && of_get_property(np, "use-ncsi", NULL)) {
1869		if (!IS_ENABLED(CONFIG_NET_NCSI)) {
1870			dev_err(&pdev->dev, "NCSI stack not enabled\n");
1871			err = -EINVAL;
1872			goto err_phy_connect;
1873		}
1874
1875		dev_info(&pdev->dev, "Using NCSI interface\n");
1876		priv->use_ncsi = true;
1877		priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler);
1878		if (!priv->ndev) {
1879			err = -EINVAL;
1880			goto err_phy_connect;
1881		}
1882	} else if (np && of_phy_is_fixed_link(np)) {
1883		struct phy_device *phy;
1884
1885		err = of_phy_register_fixed_link(np);
1886		if (err) {
1887			dev_err(&pdev->dev, "Failed to register fixed PHY\n");
1888			goto err_phy_connect;
1889		}
1890
1891		phy = of_phy_get_and_connect(priv->netdev, np,
1892					     &ftgmac100_adjust_link);
1893		if (!phy) {
1894			dev_err(&pdev->dev, "Failed to connect to fixed PHY\n");
1895			of_phy_deregister_fixed_link(np);
1896			err = -EINVAL;
1897			goto err_phy_connect;
1898		}
1899
1900		/* Display what we found */
1901		phy_attached_info(phy);
1902	} else if (np && of_get_property(np, "phy-handle", NULL)) {
1903		struct phy_device *phy;
1904
1905		/* Support "mdio"/"phy" child nodes for ast2400/2500 with
1906		 * an embedded MDIO controller. Automatically scan the DTS for
1907		 * available PHYs and register them.
1908		 */
1909		if (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1910		    of_device_is_compatible(np, "aspeed,ast2500-mac")) {
1911			err = ftgmac100_setup_mdio(netdev);
1912			if (err)
1913				goto err_setup_mdio;
1914		}
1915
1916		phy = of_phy_get_and_connect(priv->netdev, np,
1917					     &ftgmac100_adjust_link);
1918		if (!phy) {
1919			dev_err(&pdev->dev, "Failed to connect to phy\n");
1920			err = -EINVAL;
1921			goto err_phy_connect;
1922		}
1923
1924		/* Indicate that we support PAUSE frames (see comment in
1925		 * Documentation/networking/phy.rst)
1926		 */
1927		phy_support_asym_pause(phy);
1928
1929		/* Display what we found */
1930		phy_attached_info(phy);
1931	} else if (np && !ftgmac100_has_child_node(np, "mdio")) {
1932		/* Support legacy ASPEED devicetree descriptions that decribe a
1933		 * MAC with an embedded MDIO controller but have no "mdio"
1934		 * child node. Automatically scan the MDIO bus for available
1935		 * PHYs.
1936		 */
1937		priv->use_ncsi = false;
1938		err = ftgmac100_setup_mdio(netdev);
1939		if (err)
1940			goto err_setup_mdio;
1941
1942		err = ftgmac100_mii_probe(netdev);
1943		if (err) {
1944			dev_err(priv->dev, "MII probe failed!\n");
1945			goto err_ncsi_dev;
1946		}
1947
1948	}
1949
1950	if (priv->is_aspeed) {
1951		err = ftgmac100_setup_clk(priv);
1952		if (err)
1953			goto err_phy_connect;
1954
1955		/* Disable ast2600 problematic HW arbitration */
1956		if (of_device_is_compatible(np, "aspeed,ast2600-mac"))
1957			iowrite32(FTGMAC100_TM_DEFAULT,
1958				  priv->base + FTGMAC100_OFFSET_TM);
1959	}
1960
1961	/* Default ring sizes */
1962	priv->rx_q_entries = priv->new_rx_q_entries = DEF_RX_QUEUE_ENTRIES;
1963	priv->tx_q_entries = priv->new_tx_q_entries = DEF_TX_QUEUE_ENTRIES;
1964
1965	/* Base feature set */
1966	netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM |
1967		NETIF_F_GRO | NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_RX |
1968		NETIF_F_HW_VLAN_CTAG_TX;
1969
1970	if (priv->use_ncsi)
1971		netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1972
1973	/* AST2400  doesn't have working HW checksum generation */
1974	if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac")))
1975		netdev->hw_features &= ~NETIF_F_HW_CSUM;
1976
1977	/* AST2600 tx checksum with NCSI is broken */
1978	if (priv->use_ncsi && of_device_is_compatible(np, "aspeed,ast2600-mac"))
1979		netdev->hw_features &= ~NETIF_F_HW_CSUM;
1980
1981	if (np && of_get_property(np, "no-hw-checksum", NULL))
1982		netdev->hw_features &= ~(NETIF_F_HW_CSUM | NETIF_F_RXCSUM);
1983	netdev->features |= netdev->hw_features;
1984
1985	/* register network device */
1986	err = register_netdev(netdev);
1987	if (err) {
1988		dev_err(&pdev->dev, "Failed to register netdev\n");
1989		goto err_register_netdev;
1990	}
1991
1992	netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base);
1993
1994	return 0;
1995
1996err_register_netdev:
1997	clk_disable_unprepare(priv->rclk);
1998	clk_disable_unprepare(priv->clk);
1999err_phy_connect:
2000	ftgmac100_phy_disconnect(netdev);
2001err_ncsi_dev:
2002	if (priv->ndev)
2003		ncsi_unregister_dev(priv->ndev);
2004	ftgmac100_destroy_mdio(netdev);
2005err_setup_mdio:
2006	iounmap(priv->base);
2007err_ioremap:
2008	release_resource(priv->res);
2009err_req_mem:
2010	free_netdev(netdev);
2011err_alloc_etherdev:
2012	return err;
2013}
2014
2015static void ftgmac100_remove(struct platform_device *pdev)
2016{
2017	struct net_device *netdev;
2018	struct ftgmac100 *priv;
2019
2020	netdev = platform_get_drvdata(pdev);
2021	priv = netdev_priv(netdev);
2022
2023	if (priv->ndev)
2024		ncsi_unregister_dev(priv->ndev);
2025	unregister_netdev(netdev);
2026
2027	clk_disable_unprepare(priv->rclk);
2028	clk_disable_unprepare(priv->clk);
2029
2030	/* There's a small chance the reset task will have been re-queued,
2031	 * during stop, make sure it's gone before we free the structure.
2032	 */
2033	cancel_work_sync(&priv->reset_task);
2034
2035	ftgmac100_phy_disconnect(netdev);
2036	ftgmac100_destroy_mdio(netdev);
2037
2038	iounmap(priv->base);
2039	release_resource(priv->res);
2040
2041	netif_napi_del(&priv->napi);
2042	free_netdev(netdev);
 
2043}
2044
2045static const struct of_device_id ftgmac100_of_match[] = {
2046	{ .compatible = "faraday,ftgmac100" },
2047	{ }
2048};
2049MODULE_DEVICE_TABLE(of, ftgmac100_of_match);
2050
2051static struct platform_driver ftgmac100_driver = {
2052	.probe	= ftgmac100_probe,
2053	.remove_new = ftgmac100_remove,
2054	.driver	= {
2055		.name		= DRV_NAME,
2056		.of_match_table	= ftgmac100_of_match,
2057	},
2058};
2059module_platform_driver(ftgmac100_driver);
2060
2061MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
2062MODULE_DESCRIPTION("FTGMAC100 driver");
2063MODULE_LICENSE("GPL");