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1/* typhoon.c: A Linux Ethernet device driver for 3Com 3CR990 family of NICs */
2/*
3 Written 2002-2004 by David Dillow <dave@thedillows.org>
4 Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and
5 Linux 2.2.x driver by David P. McLean <davidpmclean@yahoo.com>.
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
13
14 This software is available on a public web site. It may enable
15 cryptographic capabilities of the 3Com hardware, and may be
16 exported from the United States under License Exception "TSU"
17 pursuant to 15 C.F.R. Section 740.13(e).
18
19 This work was funded by the National Library of Medicine under
20 the Department of Energy project number 0274DD06D1 and NLM project
21 number Y1-LM-2015-01.
22
23 This driver is designed for the 3Com 3CR990 Family of cards with the
24 3XP Processor. It has been tested on x86 and sparc64.
25
26 KNOWN ISSUES:
27 *) Cannot DMA Rx packets to a 2 byte aligned address. Also firmware
28 issue. Hopefully 3Com will fix it.
29 *) Waiting for a command response takes 8ms due to non-preemptable
30 polling. Only significant for getting stats and creating
31 SAs, but an ugly wart never the less.
32
33 TODO:
34 *) Doesn't do IPSEC offloading. Yet. Keep yer pants on, it's coming.
35 *) Add more support for ethtool (especially for NIC stats)
36 *) Allow disabling of RX checksum offloading
37 *) Fix MAC changing to work while the interface is up
38 (Need to put commands on the TX ring, which changes
39 the locking)
40 *) Add in FCS to {rx,tx}_bytes, since the hardware doesn't. See
41 http://oss.sgi.com/cgi-bin/mesg.cgi?a=netdev&i=20031215152211.7003fe8e.rddunlap%40osdl.org
42*/
43
44/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
45 * Setting to > 1518 effectively disables this feature.
46 */
47static int rx_copybreak = 200;
48
49/* Should we use MMIO or Port IO?
50 * 0: Port IO
51 * 1: MMIO
52 * 2: Try MMIO, fallback to Port IO
53 */
54static unsigned int use_mmio = 2;
55
56/* end user-configurable values */
57
58/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
59 */
60static const int multicast_filter_limit = 32;
61
62/* Operational parameters that are set at compile time. */
63
64/* Keep the ring sizes a power of two for compile efficiency.
65 * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
66 * Making the Tx ring too large decreases the effectiveness of channel
67 * bonding and packet priority.
68 * There are no ill effects from too-large receive rings.
69 *
70 * We don't currently use the Hi Tx ring so, don't make it very big.
71 *
72 * Beware that if we start using the Hi Tx ring, we will need to change
73 * typhoon_num_free_tx() and typhoon_tx_complete() to account for that.
74 */
75#define TXHI_ENTRIES 2
76#define TXLO_ENTRIES 128
77#define RX_ENTRIES 32
78#define COMMAND_ENTRIES 16
79#define RESPONSE_ENTRIES 32
80
81#define COMMAND_RING_SIZE (COMMAND_ENTRIES * sizeof(struct cmd_desc))
82#define RESPONSE_RING_SIZE (RESPONSE_ENTRIES * sizeof(struct resp_desc))
83
84/* The 3XP will preload and remove 64 entries from the free buffer
85 * list, and we need one entry to keep the ring from wrapping, so
86 * to keep this a power of two, we use 128 entries.
87 */
88#define RXFREE_ENTRIES 128
89#define RXENT_ENTRIES (RXFREE_ENTRIES - 1)
90
91/* Operational parameters that usually are not changed. */
92
93/* Time in jiffies before concluding the transmitter is hung. */
94#define TX_TIMEOUT (2*HZ)
95
96#define PKT_BUF_SZ 1536
97#define FIRMWARE_NAME "3com/typhoon.bin"
98
99#define pr_fmt(fmt) KBUILD_MODNAME " " fmt
100
101#include <linux/module.h>
102#include <linux/kernel.h>
103#include <linux/sched.h>
104#include <linux/string.h>
105#include <linux/timer.h>
106#include <linux/errno.h>
107#include <linux/ioport.h>
108#include <linux/interrupt.h>
109#include <linux/pci.h>
110#include <linux/netdevice.h>
111#include <linux/etherdevice.h>
112#include <linux/skbuff.h>
113#include <linux/mm.h>
114#include <linux/init.h>
115#include <linux/delay.h>
116#include <linux/ethtool.h>
117#include <linux/if_vlan.h>
118#include <linux/crc32.h>
119#include <linux/bitops.h>
120#include <asm/processor.h>
121#include <asm/io.h>
122#include <linux/uaccess.h>
123#include <linux/in6.h>
124#include <linux/dma-mapping.h>
125#include <linux/firmware.h>
126
127#include "typhoon.h"
128
129MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
130MODULE_LICENSE("GPL");
131MODULE_FIRMWARE(FIRMWARE_NAME);
132MODULE_DESCRIPTION("3Com Typhoon Family (3C990, 3CR990, and variants)");
133MODULE_PARM_DESC(rx_copybreak, "Packets smaller than this are copied and "
134 "the buffer given back to the NIC. Default "
135 "is 200.");
136MODULE_PARM_DESC(use_mmio, "Use MMIO (1) or PIO(0) to access the NIC. "
137 "Default is to try MMIO and fallback to PIO.");
138module_param(rx_copybreak, int, 0);
139module_param(use_mmio, int, 0);
140
141#if TXLO_ENTRIES <= (2 * MAX_SKB_FRAGS)
142#error TX ring too small!
143#endif
144
145struct typhoon_card_info {
146 const char *name;
147 const int capabilities;
148};
149
150#define TYPHOON_CRYPTO_NONE 0x00
151#define TYPHOON_CRYPTO_DES 0x01
152#define TYPHOON_CRYPTO_3DES 0x02
153#define TYPHOON_CRYPTO_VARIABLE 0x04
154#define TYPHOON_FIBER 0x08
155#define TYPHOON_WAKEUP_NEEDS_RESET 0x10
156
157enum typhoon_cards {
158 TYPHOON_TX = 0, TYPHOON_TX95, TYPHOON_TX97, TYPHOON_SVR,
159 TYPHOON_SVR95, TYPHOON_SVR97, TYPHOON_TXM, TYPHOON_BSVR,
160 TYPHOON_FX95, TYPHOON_FX97, TYPHOON_FX95SVR, TYPHOON_FX97SVR,
161 TYPHOON_FXM,
162};
163
164/* directly indexed by enum typhoon_cards, above */
165static struct typhoon_card_info typhoon_card_info[] = {
166 { "3Com Typhoon (3C990-TX)",
167 TYPHOON_CRYPTO_NONE},
168 { "3Com Typhoon (3CR990-TX-95)",
169 TYPHOON_CRYPTO_DES},
170 { "3Com Typhoon (3CR990-TX-97)",
171 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
172 { "3Com Typhoon (3C990SVR)",
173 TYPHOON_CRYPTO_NONE},
174 { "3Com Typhoon (3CR990SVR95)",
175 TYPHOON_CRYPTO_DES},
176 { "3Com Typhoon (3CR990SVR97)",
177 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
178 { "3Com Typhoon2 (3C990B-TX-M)",
179 TYPHOON_CRYPTO_VARIABLE},
180 { "3Com Typhoon2 (3C990BSVR)",
181 TYPHOON_CRYPTO_VARIABLE},
182 { "3Com Typhoon (3CR990-FX-95)",
183 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
184 { "3Com Typhoon (3CR990-FX-97)",
185 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
186 { "3Com Typhoon (3CR990-FX-95 Server)",
187 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
188 { "3Com Typhoon (3CR990-FX-97 Server)",
189 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
190 { "3Com Typhoon2 (3C990B-FX-97)",
191 TYPHOON_CRYPTO_VARIABLE | TYPHOON_FIBER},
192};
193
194/* Notes on the new subsystem numbering scheme:
195 * bits 0-1 indicate crypto capabilities: (0) variable, (1) DES, or (2) 3DES
196 * bit 4 indicates if this card has secured firmware (we don't support it)
197 * bit 8 indicates if this is a (0) copper or (1) fiber card
198 * bits 12-16 indicate card type: (0) client and (1) server
199 */
200static const struct pci_device_id typhoon_pci_tbl[] = {
201 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0,TYPHOON_TX },
203 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_95,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX95 },
205 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_97,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX97 },
207 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
208 PCI_ANY_ID, 0x1000, 0, 0, TYPHOON_TXM },
209 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
210 PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FXM },
211 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
212 PCI_ANY_ID, 0x2000, 0, 0, TYPHOON_BSVR },
213 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
214 PCI_ANY_ID, 0x1101, 0, 0, TYPHOON_FX95 },
215 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
216 PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FX97 },
217 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
218 PCI_ANY_ID, 0x2101, 0, 0, TYPHOON_FX95SVR },
219 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
220 PCI_ANY_ID, 0x2102, 0, 0, TYPHOON_FX97SVR },
221 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR95,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR95 },
223 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR97,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR97 },
225 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR },
227 { 0, }
228};
229MODULE_DEVICE_TABLE(pci, typhoon_pci_tbl);
230
231/* Define the shared memory area
232 * Align everything the 3XP will normally be using.
233 * We'll need to move/align txHi if we start using that ring.
234 */
235#define __3xp_aligned ____cacheline_aligned
236struct typhoon_shared {
237 struct typhoon_interface iface;
238 struct typhoon_indexes indexes __3xp_aligned;
239 struct tx_desc txLo[TXLO_ENTRIES] __3xp_aligned;
240 struct rx_desc rxLo[RX_ENTRIES] __3xp_aligned;
241 struct rx_desc rxHi[RX_ENTRIES] __3xp_aligned;
242 struct cmd_desc cmd[COMMAND_ENTRIES] __3xp_aligned;
243 struct resp_desc resp[RESPONSE_ENTRIES] __3xp_aligned;
244 struct rx_free rxBuff[RXFREE_ENTRIES] __3xp_aligned;
245 u32 zeroWord;
246 struct tx_desc txHi[TXHI_ENTRIES];
247} __packed;
248
249struct rxbuff_ent {
250 struct sk_buff *skb;
251 dma_addr_t dma_addr;
252};
253
254struct typhoon {
255 /* Tx cache line section */
256 struct transmit_ring txLoRing ____cacheline_aligned;
257 struct pci_dev * tx_pdev;
258 void __iomem *tx_ioaddr;
259 u32 txlo_dma_addr;
260
261 /* Irq/Rx cache line section */
262 void __iomem *ioaddr ____cacheline_aligned;
263 struct typhoon_indexes *indexes;
264 u8 awaiting_resp;
265 u8 duplex;
266 u8 speed;
267 u8 card_state;
268 struct basic_ring rxLoRing;
269 struct pci_dev * pdev;
270 struct net_device * dev;
271 struct napi_struct napi;
272 struct basic_ring rxHiRing;
273 struct basic_ring rxBuffRing;
274 struct rxbuff_ent rxbuffers[RXENT_ENTRIES];
275
276 /* general section */
277 spinlock_t command_lock ____cacheline_aligned;
278 struct basic_ring cmdRing;
279 struct basic_ring respRing;
280 struct net_device_stats stats_saved;
281 struct typhoon_shared * shared;
282 dma_addr_t shared_dma;
283 __le16 xcvr_select;
284 __le16 wol_events;
285 __le32 offload;
286
287 /* unused stuff (future use) */
288 int capabilities;
289 struct transmit_ring txHiRing;
290};
291
292enum completion_wait_values {
293 NoWait = 0, WaitNoSleep, WaitSleep,
294};
295
296/* These are the values for the typhoon.card_state variable.
297 * These determine where the statistics will come from in get_stats().
298 * The sleep image does not support the statistics we need.
299 */
300enum state_values {
301 Sleeping = 0, Running,
302};
303
304/* PCI writes are not guaranteed to be posted in order, but outstanding writes
305 * cannot pass a read, so this forces current writes to post.
306 */
307#define typhoon_post_pci_writes(x) \
308 do { if (likely(use_mmio)) ioread32(x+TYPHOON_REG_HEARTBEAT); } while (0)
309
310/* We'll wait up to six seconds for a reset, and half a second normally.
311 */
312#define TYPHOON_UDELAY 50
313#define TYPHOON_RESET_TIMEOUT_SLEEP (6 * HZ)
314#define TYPHOON_RESET_TIMEOUT_NOSLEEP ((6 * 1000000) / TYPHOON_UDELAY)
315#define TYPHOON_WAIT_TIMEOUT ((1000000 / 2) / TYPHOON_UDELAY)
316
317#if defined(NETIF_F_TSO)
318#define skb_tso_size(x) (skb_shinfo(x)->gso_size)
319#define TSO_NUM_DESCRIPTORS 2
320#define TSO_OFFLOAD_ON TYPHOON_OFFLOAD_TCP_SEGMENT
321#else
322#define NETIF_F_TSO 0
323#define skb_tso_size(x) 0
324#define TSO_NUM_DESCRIPTORS 0
325#define TSO_OFFLOAD_ON 0
326#endif
327
328static inline void
329typhoon_inc_index(u32 *index, const int count, const int num_entries)
330{
331 /* Increment a ring index -- we can use this for all rings execept
332 * the Rx rings, as they use different size descriptors
333 * otherwise, everything is the same size as a cmd_desc
334 */
335 *index += count * sizeof(struct cmd_desc);
336 *index %= num_entries * sizeof(struct cmd_desc);
337}
338
339static inline void
340typhoon_inc_cmd_index(u32 *index, const int count)
341{
342 typhoon_inc_index(index, count, COMMAND_ENTRIES);
343}
344
345static inline void
346typhoon_inc_resp_index(u32 *index, const int count)
347{
348 typhoon_inc_index(index, count, RESPONSE_ENTRIES);
349}
350
351static inline void
352typhoon_inc_rxfree_index(u32 *index, const int count)
353{
354 typhoon_inc_index(index, count, RXFREE_ENTRIES);
355}
356
357static inline void
358typhoon_inc_tx_index(u32 *index, const int count)
359{
360 /* if we start using the Hi Tx ring, this needs updating */
361 typhoon_inc_index(index, count, TXLO_ENTRIES);
362}
363
364static inline void
365typhoon_inc_rx_index(u32 *index, const int count)
366{
367 /* sizeof(struct rx_desc) != sizeof(struct cmd_desc) */
368 *index += count * sizeof(struct rx_desc);
369 *index %= RX_ENTRIES * sizeof(struct rx_desc);
370}
371
372static int
373typhoon_reset(void __iomem *ioaddr, int wait_type)
374{
375 int i, err = 0;
376 int timeout;
377
378 if (wait_type == WaitNoSleep)
379 timeout = TYPHOON_RESET_TIMEOUT_NOSLEEP;
380 else
381 timeout = TYPHOON_RESET_TIMEOUT_SLEEP;
382
383 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
384 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
385
386 iowrite32(TYPHOON_RESET_ALL, ioaddr + TYPHOON_REG_SOFT_RESET);
387 typhoon_post_pci_writes(ioaddr);
388 udelay(1);
389 iowrite32(TYPHOON_RESET_NONE, ioaddr + TYPHOON_REG_SOFT_RESET);
390
391 if (wait_type != NoWait) {
392 for (i = 0; i < timeout; i++) {
393 if (ioread32(ioaddr + TYPHOON_REG_STATUS) ==
394 TYPHOON_STATUS_WAITING_FOR_HOST)
395 goto out;
396
397 if (wait_type == WaitSleep)
398 schedule_timeout_uninterruptible(1);
399 else
400 udelay(TYPHOON_UDELAY);
401 }
402
403 err = -ETIMEDOUT;
404 }
405
406out:
407 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
408 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
409
410 /* The 3XP seems to need a little extra time to complete the load
411 * of the sleep image before we can reliably boot it. Failure to
412 * do this occasionally results in a hung adapter after boot in
413 * typhoon_init_one() while trying to read the MAC address or
414 * putting the card to sleep. 3Com's driver waits 5ms, but
415 * that seems to be overkill. However, if we can sleep, we might
416 * as well give it that much time. Otherwise, we'll give it 500us,
417 * which should be enough (I've see it work well at 100us, but still
418 * saw occasional problems.)
419 */
420 if (wait_type == WaitSleep)
421 msleep(5);
422 else
423 udelay(500);
424 return err;
425}
426
427static int
428typhoon_wait_status(void __iomem *ioaddr, u32 wait_value)
429{
430 int i, err = 0;
431
432 for (i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
433 if (ioread32(ioaddr + TYPHOON_REG_STATUS) == wait_value)
434 goto out;
435 udelay(TYPHOON_UDELAY);
436 }
437
438 err = -ETIMEDOUT;
439
440out:
441 return err;
442}
443
444static inline void
445typhoon_media_status(struct net_device *dev, struct resp_desc *resp)
446{
447 if (resp->parm1 & TYPHOON_MEDIA_STAT_NO_LINK)
448 netif_carrier_off(dev);
449 else
450 netif_carrier_on(dev);
451}
452
453static inline void
454typhoon_hello(struct typhoon *tp)
455{
456 struct basic_ring *ring = &tp->cmdRing;
457 struct cmd_desc *cmd;
458
459 /* We only get a hello request if we've not sent anything to the
460 * card in a long while. If the lock is held, then we're in the
461 * process of issuing a command, so we don't need to respond.
462 */
463 if (spin_trylock(&tp->command_lock)) {
464 cmd = (struct cmd_desc *)(ring->ringBase + ring->lastWrite);
465 typhoon_inc_cmd_index(&ring->lastWrite, 1);
466
467 INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP);
468 wmb();
469 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
470 spin_unlock(&tp->command_lock);
471 }
472}
473
474static int
475typhoon_process_response(struct typhoon *tp, int resp_size,
476 struct resp_desc *resp_save)
477{
478 struct typhoon_indexes *indexes = tp->indexes;
479 struct resp_desc *resp;
480 u8 *base = tp->respRing.ringBase;
481 int count, len, wrap_len;
482 u32 cleared;
483 u32 ready;
484
485 cleared = le32_to_cpu(indexes->respCleared);
486 ready = le32_to_cpu(indexes->respReady);
487 while (cleared != ready) {
488 resp = (struct resp_desc *)(base + cleared);
489 count = resp->numDesc + 1;
490 if (resp_save && resp->seqNo) {
491 if (count > resp_size) {
492 resp_save->flags = TYPHOON_RESP_ERROR;
493 goto cleanup;
494 }
495
496 wrap_len = 0;
497 len = count * sizeof(*resp);
498 if (unlikely(cleared + len > RESPONSE_RING_SIZE)) {
499 wrap_len = cleared + len - RESPONSE_RING_SIZE;
500 len = RESPONSE_RING_SIZE - cleared;
501 }
502
503 memcpy(resp_save, resp, len);
504 if (unlikely(wrap_len)) {
505 resp_save += len / sizeof(*resp);
506 memcpy(resp_save, base, wrap_len);
507 }
508
509 resp_save = NULL;
510 } else if (resp->cmd == TYPHOON_CMD_READ_MEDIA_STATUS) {
511 typhoon_media_status(tp->dev, resp);
512 } else if (resp->cmd == TYPHOON_CMD_HELLO_RESP) {
513 typhoon_hello(tp);
514 } else {
515 netdev_err(tp->dev,
516 "dumping unexpected response 0x%04x:%d:0x%02x:0x%04x:%08x:%08x\n",
517 le16_to_cpu(resp->cmd),
518 resp->numDesc, resp->flags,
519 le16_to_cpu(resp->parm1),
520 le32_to_cpu(resp->parm2),
521 le32_to_cpu(resp->parm3));
522 }
523
524cleanup:
525 typhoon_inc_resp_index(&cleared, count);
526 }
527
528 indexes->respCleared = cpu_to_le32(cleared);
529 wmb();
530 return resp_save == NULL;
531}
532
533static inline int
534typhoon_num_free(int lastWrite, int lastRead, int ringSize)
535{
536 /* this works for all descriptors but rx_desc, as they are a
537 * different size than the cmd_desc -- everyone else is the same
538 */
539 lastWrite /= sizeof(struct cmd_desc);
540 lastRead /= sizeof(struct cmd_desc);
541 return (ringSize + lastRead - lastWrite - 1) % ringSize;
542}
543
544static inline int
545typhoon_num_free_cmd(struct typhoon *tp)
546{
547 int lastWrite = tp->cmdRing.lastWrite;
548 int cmdCleared = le32_to_cpu(tp->indexes->cmdCleared);
549
550 return typhoon_num_free(lastWrite, cmdCleared, COMMAND_ENTRIES);
551}
552
553static inline int
554typhoon_num_free_resp(struct typhoon *tp)
555{
556 int respReady = le32_to_cpu(tp->indexes->respReady);
557 int respCleared = le32_to_cpu(tp->indexes->respCleared);
558
559 return typhoon_num_free(respReady, respCleared, RESPONSE_ENTRIES);
560}
561
562static inline int
563typhoon_num_free_tx(struct transmit_ring *ring)
564{
565 /* if we start using the Hi Tx ring, this needs updating */
566 return typhoon_num_free(ring->lastWrite, ring->lastRead, TXLO_ENTRIES);
567}
568
569static int
570typhoon_issue_command(struct typhoon *tp, int num_cmd, struct cmd_desc *cmd,
571 int num_resp, struct resp_desc *resp)
572{
573 struct typhoon_indexes *indexes = tp->indexes;
574 struct basic_ring *ring = &tp->cmdRing;
575 struct resp_desc local_resp;
576 int i, err = 0;
577 int got_resp;
578 int freeCmd, freeResp;
579 int len, wrap_len;
580
581 spin_lock(&tp->command_lock);
582
583 freeCmd = typhoon_num_free_cmd(tp);
584 freeResp = typhoon_num_free_resp(tp);
585
586 if (freeCmd < num_cmd || freeResp < num_resp) {
587 netdev_err(tp->dev, "no descs for cmd, had (needed) %d (%d) cmd, %d (%d) resp\n",
588 freeCmd, num_cmd, freeResp, num_resp);
589 err = -ENOMEM;
590 goto out;
591 }
592
593 if (cmd->flags & TYPHOON_CMD_RESPOND) {
594 /* If we're expecting a response, but the caller hasn't given
595 * us a place to put it, we'll provide one.
596 */
597 tp->awaiting_resp = 1;
598 if (resp == NULL) {
599 resp = &local_resp;
600 num_resp = 1;
601 }
602 }
603
604 wrap_len = 0;
605 len = num_cmd * sizeof(*cmd);
606 if (unlikely(ring->lastWrite + len > COMMAND_RING_SIZE)) {
607 wrap_len = ring->lastWrite + len - COMMAND_RING_SIZE;
608 len = COMMAND_RING_SIZE - ring->lastWrite;
609 }
610
611 memcpy(ring->ringBase + ring->lastWrite, cmd, len);
612 if (unlikely(wrap_len)) {
613 struct cmd_desc *wrap_ptr = cmd;
614 wrap_ptr += len / sizeof(*cmd);
615 memcpy(ring->ringBase, wrap_ptr, wrap_len);
616 }
617
618 typhoon_inc_cmd_index(&ring->lastWrite, num_cmd);
619
620 /* "I feel a presence... another warrior is on the mesa."
621 */
622 wmb();
623 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
624 typhoon_post_pci_writes(tp->ioaddr);
625
626 if ((cmd->flags & TYPHOON_CMD_RESPOND) == 0)
627 goto out;
628
629 /* Ugh. We'll be here about 8ms, spinning our thumbs, unable to
630 * preempt or do anything other than take interrupts. So, don't
631 * wait for a response unless you have to.
632 *
633 * I've thought about trying to sleep here, but we're called
634 * from many contexts that don't allow that. Also, given the way
635 * 3Com has implemented irq coalescing, we would likely timeout --
636 * this has been observed in real life!
637 *
638 * The big killer is we have to wait to get stats from the card,
639 * though we could go to a periodic refresh of those if we don't
640 * mind them getting somewhat stale. The rest of the waiting
641 * commands occur during open/close/suspend/resume, so they aren't
642 * time critical. Creating SAs in the future will also have to
643 * wait here.
644 */
645 got_resp = 0;
646 for (i = 0; i < TYPHOON_WAIT_TIMEOUT && !got_resp; i++) {
647 if (indexes->respCleared != indexes->respReady)
648 got_resp = typhoon_process_response(tp, num_resp,
649 resp);
650 udelay(TYPHOON_UDELAY);
651 }
652
653 if (!got_resp) {
654 err = -ETIMEDOUT;
655 goto out;
656 }
657
658 /* Collect the error response even if we don't care about the
659 * rest of the response
660 */
661 if (resp->flags & TYPHOON_RESP_ERROR)
662 err = -EIO;
663
664out:
665 if (tp->awaiting_resp) {
666 tp->awaiting_resp = 0;
667 smp_wmb();
668
669 /* Ugh. If a response was added to the ring between
670 * the call to typhoon_process_response() and the clearing
671 * of tp->awaiting_resp, we could have missed the interrupt
672 * and it could hang in the ring an indeterminate amount of
673 * time. So, check for it, and interrupt ourselves if this
674 * is the case.
675 */
676 if (indexes->respCleared != indexes->respReady)
677 iowrite32(1, tp->ioaddr + TYPHOON_REG_SELF_INTERRUPT);
678 }
679
680 spin_unlock(&tp->command_lock);
681 return err;
682}
683
684static inline void
685typhoon_tso_fill(struct sk_buff *skb, struct transmit_ring *txRing,
686 u32 ring_dma)
687{
688 struct tcpopt_desc *tcpd;
689 u32 tcpd_offset = ring_dma;
690
691 tcpd = (struct tcpopt_desc *) (txRing->ringBase + txRing->lastWrite);
692 tcpd_offset += txRing->lastWrite;
693 tcpd_offset += offsetof(struct tcpopt_desc, bytesTx);
694 typhoon_inc_tx_index(&txRing->lastWrite, 1);
695
696 tcpd->flags = TYPHOON_OPT_DESC | TYPHOON_OPT_TCP_SEG;
697 tcpd->numDesc = 1;
698 tcpd->mss_flags = cpu_to_le16(skb_tso_size(skb));
699 tcpd->mss_flags |= TYPHOON_TSO_FIRST | TYPHOON_TSO_LAST;
700 tcpd->respAddrLo = cpu_to_le32(tcpd_offset);
701 tcpd->bytesTx = cpu_to_le32(skb->len);
702 tcpd->status = 0;
703}
704
705static netdev_tx_t
706typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
707{
708 struct typhoon *tp = netdev_priv(dev);
709 struct transmit_ring *txRing;
710 struct tx_desc *txd, *first_txd;
711 dma_addr_t skb_dma;
712 int numDesc;
713
714 /* we have two rings to choose from, but we only use txLo for now
715 * If we start using the Hi ring as well, we'll need to update
716 * typhoon_stop_runtime(), typhoon_interrupt(), typhoon_num_free_tx(),
717 * and TXHI_ENTRIES to match, as well as update the TSO code below
718 * to get the right DMA address
719 */
720 txRing = &tp->txLoRing;
721
722 /* We need one descriptor for each fragment of the sk_buff, plus the
723 * one for the ->data area of it.
724 *
725 * The docs say a maximum of 16 fragment descriptors per TCP option
726 * descriptor, then make a new packet descriptor and option descriptor
727 * for the next 16 fragments. The engineers say just an option
728 * descriptor is needed. I've tested up to 26 fragments with a single
729 * packet descriptor/option descriptor combo, so I use that for now.
730 *
731 * If problems develop with TSO, check this first.
732 */
733 numDesc = skb_shinfo(skb)->nr_frags + 1;
734 if (skb_is_gso(skb))
735 numDesc++;
736
737 /* When checking for free space in the ring, we need to also
738 * account for the initial Tx descriptor, and we always must leave
739 * at least one descriptor unused in the ring so that it doesn't
740 * wrap and look empty.
741 *
742 * The only time we should loop here is when we hit the race
743 * between marking the queue awake and updating the cleared index.
744 * Just loop and it will appear. This comes from the acenic driver.
745 */
746 while (unlikely(typhoon_num_free_tx(txRing) < (numDesc + 2)))
747 smp_rmb();
748
749 first_txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
750 typhoon_inc_tx_index(&txRing->lastWrite, 1);
751
752 first_txd->flags = TYPHOON_TX_DESC | TYPHOON_DESC_VALID;
753 first_txd->numDesc = 0;
754 first_txd->len = 0;
755 first_txd->tx_addr = (u64)((unsigned long) skb);
756 first_txd->processFlags = 0;
757
758 if (skb->ip_summed == CHECKSUM_PARTIAL) {
759 /* The 3XP will figure out if this is UDP/TCP */
760 first_txd->processFlags |= TYPHOON_TX_PF_TCP_CHKSUM;
761 first_txd->processFlags |= TYPHOON_TX_PF_UDP_CHKSUM;
762 first_txd->processFlags |= TYPHOON_TX_PF_IP_CHKSUM;
763 }
764
765 if (skb_vlan_tag_present(skb)) {
766 first_txd->processFlags |=
767 TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY;
768 first_txd->processFlags |=
769 cpu_to_le32(htons(skb_vlan_tag_get(skb)) <<
770 TYPHOON_TX_PF_VLAN_TAG_SHIFT);
771 }
772
773 if (skb_is_gso(skb)) {
774 first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
775 first_txd->numDesc++;
776
777 typhoon_tso_fill(skb, txRing, tp->txlo_dma_addr);
778 }
779
780 txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
781 typhoon_inc_tx_index(&txRing->lastWrite, 1);
782
783 /* No need to worry about padding packet -- the firmware pads
784 * it with zeros to ETH_ZLEN for us.
785 */
786 if (skb_shinfo(skb)->nr_frags == 0) {
787 skb_dma = dma_map_single(&tp->tx_pdev->dev, skb->data,
788 skb->len, DMA_TO_DEVICE);
789 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
790 txd->len = cpu_to_le16(skb->len);
791 txd->frag.addr = cpu_to_le32(skb_dma);
792 txd->frag.addrHi = 0;
793 first_txd->numDesc++;
794 } else {
795 int i, len;
796
797 len = skb_headlen(skb);
798 skb_dma = dma_map_single(&tp->tx_pdev->dev, skb->data, len,
799 DMA_TO_DEVICE);
800 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
801 txd->len = cpu_to_le16(len);
802 txd->frag.addr = cpu_to_le32(skb_dma);
803 txd->frag.addrHi = 0;
804 first_txd->numDesc++;
805
806 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
807 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
808 void *frag_addr;
809
810 txd = (struct tx_desc *) (txRing->ringBase +
811 txRing->lastWrite);
812 typhoon_inc_tx_index(&txRing->lastWrite, 1);
813
814 len = skb_frag_size(frag);
815 frag_addr = skb_frag_address(frag);
816 skb_dma = dma_map_single(&tp->tx_pdev->dev, frag_addr,
817 len, DMA_TO_DEVICE);
818 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
819 txd->len = cpu_to_le16(len);
820 txd->frag.addr = cpu_to_le32(skb_dma);
821 txd->frag.addrHi = 0;
822 first_txd->numDesc++;
823 }
824 }
825
826 /* Kick the 3XP
827 */
828 wmb();
829 iowrite32(txRing->lastWrite, tp->tx_ioaddr + txRing->writeRegister);
830
831 /* If we don't have room to put the worst case packet on the
832 * queue, then we must stop the queue. We need 2 extra
833 * descriptors -- one to prevent ring wrap, and one for the
834 * Tx header.
835 */
836 numDesc = MAX_SKB_FRAGS + TSO_NUM_DESCRIPTORS + 1;
837
838 if (typhoon_num_free_tx(txRing) < (numDesc + 2)) {
839 netif_stop_queue(dev);
840
841 /* A Tx complete IRQ could have gotten between, making
842 * the ring free again. Only need to recheck here, since
843 * Tx is serialized.
844 */
845 if (typhoon_num_free_tx(txRing) >= (numDesc + 2))
846 netif_wake_queue(dev);
847 }
848
849 return NETDEV_TX_OK;
850}
851
852static void
853typhoon_set_rx_mode(struct net_device *dev)
854{
855 struct typhoon *tp = netdev_priv(dev);
856 struct cmd_desc xp_cmd;
857 u32 mc_filter[2];
858 __le16 filter;
859
860 filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
861 if (dev->flags & IFF_PROMISC) {
862 filter |= TYPHOON_RX_FILTER_PROMISCOUS;
863 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
864 (dev->flags & IFF_ALLMULTI)) {
865 /* Too many to match, or accept all multicasts. */
866 filter |= TYPHOON_RX_FILTER_ALL_MCAST;
867 } else if (!netdev_mc_empty(dev)) {
868 struct netdev_hw_addr *ha;
869
870 memset(mc_filter, 0, sizeof(mc_filter));
871 netdev_for_each_mc_addr(ha, dev) {
872 int bit = ether_crc(ETH_ALEN, ha->addr) & 0x3f;
873 mc_filter[bit >> 5] |= 1 << (bit & 0x1f);
874 }
875
876 INIT_COMMAND_NO_RESPONSE(&xp_cmd,
877 TYPHOON_CMD_SET_MULTICAST_HASH);
878 xp_cmd.parm1 = TYPHOON_MCAST_HASH_SET;
879 xp_cmd.parm2 = cpu_to_le32(mc_filter[0]);
880 xp_cmd.parm3 = cpu_to_le32(mc_filter[1]);
881 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
882
883 filter |= TYPHOON_RX_FILTER_MCAST_HASH;
884 }
885
886 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
887 xp_cmd.parm1 = filter;
888 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
889}
890
891static int
892typhoon_do_get_stats(struct typhoon *tp)
893{
894 struct net_device_stats *stats = &tp->dev->stats;
895 struct net_device_stats *saved = &tp->stats_saved;
896 struct cmd_desc xp_cmd;
897 struct resp_desc xp_resp[7];
898 struct stats_resp *s = (struct stats_resp *) xp_resp;
899 int err;
900
901 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_STATS);
902 err = typhoon_issue_command(tp, 1, &xp_cmd, 7, xp_resp);
903 if (err < 0)
904 return err;
905
906 /* 3Com's Linux driver uses txMultipleCollisions as it's
907 * collisions value, but there is some other collision info as well...
908 *
909 * The extra status reported would be a good candidate for
910 * ethtool_ops->get_{strings,stats}()
911 */
912 stats->tx_packets = le32_to_cpu(s->txPackets) +
913 saved->tx_packets;
914 stats->tx_bytes = le64_to_cpu(s->txBytes) +
915 saved->tx_bytes;
916 stats->tx_errors = le32_to_cpu(s->txCarrierLost) +
917 saved->tx_errors;
918 stats->tx_carrier_errors = le32_to_cpu(s->txCarrierLost) +
919 saved->tx_carrier_errors;
920 stats->collisions = le32_to_cpu(s->txMultipleCollisions) +
921 saved->collisions;
922 stats->rx_packets = le32_to_cpu(s->rxPacketsGood) +
923 saved->rx_packets;
924 stats->rx_bytes = le64_to_cpu(s->rxBytesGood) +
925 saved->rx_bytes;
926 stats->rx_fifo_errors = le32_to_cpu(s->rxFifoOverruns) +
927 saved->rx_fifo_errors;
928 stats->rx_errors = le32_to_cpu(s->rxFifoOverruns) +
929 le32_to_cpu(s->BadSSD) + le32_to_cpu(s->rxCrcErrors) +
930 saved->rx_errors;
931 stats->rx_crc_errors = le32_to_cpu(s->rxCrcErrors) +
932 saved->rx_crc_errors;
933 stats->rx_length_errors = le32_to_cpu(s->rxOversized) +
934 saved->rx_length_errors;
935 tp->speed = (s->linkStatus & TYPHOON_LINK_100MBPS) ?
936 SPEED_100 : SPEED_10;
937 tp->duplex = (s->linkStatus & TYPHOON_LINK_FULL_DUPLEX) ?
938 DUPLEX_FULL : DUPLEX_HALF;
939
940 return 0;
941}
942
943static struct net_device_stats *
944typhoon_get_stats(struct net_device *dev)
945{
946 struct typhoon *tp = netdev_priv(dev);
947 struct net_device_stats *stats = &tp->dev->stats;
948 struct net_device_stats *saved = &tp->stats_saved;
949
950 smp_rmb();
951 if (tp->card_state == Sleeping)
952 return saved;
953
954 if (typhoon_do_get_stats(tp) < 0) {
955 netdev_err(dev, "error getting stats\n");
956 return saved;
957 }
958
959 return stats;
960}
961
962static void
963typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
964{
965 struct typhoon *tp = netdev_priv(dev);
966 struct pci_dev *pci_dev = tp->pdev;
967 struct cmd_desc xp_cmd;
968 struct resp_desc xp_resp[3];
969
970 smp_rmb();
971 if (tp->card_state == Sleeping) {
972 strscpy(info->fw_version, "Sleep image",
973 sizeof(info->fw_version));
974 } else {
975 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
976 if (typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
977 strscpy(info->fw_version, "Unknown runtime",
978 sizeof(info->fw_version));
979 } else {
980 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
981 snprintf(info->fw_version, sizeof(info->fw_version),
982 "%02x.%03x.%03x", sleep_ver >> 24,
983 (sleep_ver >> 12) & 0xfff, sleep_ver & 0xfff);
984 }
985 }
986
987 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
988 strscpy(info->bus_info, pci_name(pci_dev), sizeof(info->bus_info));
989}
990
991static int
992typhoon_get_link_ksettings(struct net_device *dev,
993 struct ethtool_link_ksettings *cmd)
994{
995 struct typhoon *tp = netdev_priv(dev);
996 u32 supported, advertising = 0;
997
998 supported = SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
999 SUPPORTED_Autoneg;
1000
1001 switch (tp->xcvr_select) {
1002 case TYPHOON_XCVR_10HALF:
1003 advertising = ADVERTISED_10baseT_Half;
1004 break;
1005 case TYPHOON_XCVR_10FULL:
1006 advertising = ADVERTISED_10baseT_Full;
1007 break;
1008 case TYPHOON_XCVR_100HALF:
1009 advertising = ADVERTISED_100baseT_Half;
1010 break;
1011 case TYPHOON_XCVR_100FULL:
1012 advertising = ADVERTISED_100baseT_Full;
1013 break;
1014 case TYPHOON_XCVR_AUTONEG:
1015 advertising = ADVERTISED_10baseT_Half |
1016 ADVERTISED_10baseT_Full |
1017 ADVERTISED_100baseT_Half |
1018 ADVERTISED_100baseT_Full |
1019 ADVERTISED_Autoneg;
1020 break;
1021 }
1022
1023 if (tp->capabilities & TYPHOON_FIBER) {
1024 supported |= SUPPORTED_FIBRE;
1025 advertising |= ADVERTISED_FIBRE;
1026 cmd->base.port = PORT_FIBRE;
1027 } else {
1028 supported |= SUPPORTED_10baseT_Half |
1029 SUPPORTED_10baseT_Full |
1030 SUPPORTED_TP;
1031 advertising |= ADVERTISED_TP;
1032 cmd->base.port = PORT_TP;
1033 }
1034
1035 /* need to get stats to make these link speed/duplex valid */
1036 typhoon_do_get_stats(tp);
1037 cmd->base.speed = tp->speed;
1038 cmd->base.duplex = tp->duplex;
1039 cmd->base.phy_address = 0;
1040 if (tp->xcvr_select == TYPHOON_XCVR_AUTONEG)
1041 cmd->base.autoneg = AUTONEG_ENABLE;
1042 else
1043 cmd->base.autoneg = AUTONEG_DISABLE;
1044
1045 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1046 supported);
1047 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1048 advertising);
1049
1050 return 0;
1051}
1052
1053static int
1054typhoon_set_link_ksettings(struct net_device *dev,
1055 const struct ethtool_link_ksettings *cmd)
1056{
1057 struct typhoon *tp = netdev_priv(dev);
1058 u32 speed = cmd->base.speed;
1059 struct cmd_desc xp_cmd;
1060 __le16 xcvr;
1061 int err;
1062
1063 err = -EINVAL;
1064 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1065 xcvr = TYPHOON_XCVR_AUTONEG;
1066 } else {
1067 if (cmd->base.duplex == DUPLEX_HALF) {
1068 if (speed == SPEED_10)
1069 xcvr = TYPHOON_XCVR_10HALF;
1070 else if (speed == SPEED_100)
1071 xcvr = TYPHOON_XCVR_100HALF;
1072 else
1073 goto out;
1074 } else if (cmd->base.duplex == DUPLEX_FULL) {
1075 if (speed == SPEED_10)
1076 xcvr = TYPHOON_XCVR_10FULL;
1077 else if (speed == SPEED_100)
1078 xcvr = TYPHOON_XCVR_100FULL;
1079 else
1080 goto out;
1081 } else
1082 goto out;
1083 }
1084
1085 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1086 xp_cmd.parm1 = xcvr;
1087 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1088 if (err < 0)
1089 goto out;
1090
1091 tp->xcvr_select = xcvr;
1092 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1093 tp->speed = 0xff; /* invalid */
1094 tp->duplex = 0xff; /* invalid */
1095 } else {
1096 tp->speed = speed;
1097 tp->duplex = cmd->base.duplex;
1098 }
1099
1100out:
1101 return err;
1102}
1103
1104static void
1105typhoon_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1106{
1107 struct typhoon *tp = netdev_priv(dev);
1108
1109 wol->supported = WAKE_PHY | WAKE_MAGIC;
1110 wol->wolopts = 0;
1111 if (tp->wol_events & TYPHOON_WAKE_LINK_EVENT)
1112 wol->wolopts |= WAKE_PHY;
1113 if (tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
1114 wol->wolopts |= WAKE_MAGIC;
1115 memset(&wol->sopass, 0, sizeof(wol->sopass));
1116}
1117
1118static int
1119typhoon_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1120{
1121 struct typhoon *tp = netdev_priv(dev);
1122
1123 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
1124 return -EINVAL;
1125
1126 tp->wol_events = 0;
1127 if (wol->wolopts & WAKE_PHY)
1128 tp->wol_events |= TYPHOON_WAKE_LINK_EVENT;
1129 if (wol->wolopts & WAKE_MAGIC)
1130 tp->wol_events |= TYPHOON_WAKE_MAGIC_PKT;
1131
1132 return 0;
1133}
1134
1135static void
1136typhoon_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering,
1137 struct kernel_ethtool_ringparam *kernel_ering,
1138 struct netlink_ext_ack *extack)
1139{
1140 ering->rx_max_pending = RXENT_ENTRIES;
1141 ering->tx_max_pending = TXLO_ENTRIES - 1;
1142
1143 ering->rx_pending = RXENT_ENTRIES;
1144 ering->tx_pending = TXLO_ENTRIES - 1;
1145}
1146
1147static const struct ethtool_ops typhoon_ethtool_ops = {
1148 .get_drvinfo = typhoon_get_drvinfo,
1149 .get_wol = typhoon_get_wol,
1150 .set_wol = typhoon_set_wol,
1151 .get_link = ethtool_op_get_link,
1152 .get_ringparam = typhoon_get_ringparam,
1153 .get_link_ksettings = typhoon_get_link_ksettings,
1154 .set_link_ksettings = typhoon_set_link_ksettings,
1155};
1156
1157static int
1158typhoon_wait_interrupt(void __iomem *ioaddr)
1159{
1160 int i, err = 0;
1161
1162 for (i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1163 if (ioread32(ioaddr + TYPHOON_REG_INTR_STATUS) &
1164 TYPHOON_INTR_BOOTCMD)
1165 goto out;
1166 udelay(TYPHOON_UDELAY);
1167 }
1168
1169 err = -ETIMEDOUT;
1170
1171out:
1172 iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1173 return err;
1174}
1175
1176#define shared_offset(x) offsetof(struct typhoon_shared, x)
1177
1178static void
1179typhoon_init_interface(struct typhoon *tp)
1180{
1181 struct typhoon_interface *iface = &tp->shared->iface;
1182 dma_addr_t shared_dma;
1183
1184 memset(tp->shared, 0, sizeof(struct typhoon_shared));
1185
1186 /* The *Hi members of iface are all init'd to zero by the memset().
1187 */
1188 shared_dma = tp->shared_dma + shared_offset(indexes);
1189 iface->ringIndex = cpu_to_le32(shared_dma);
1190
1191 shared_dma = tp->shared_dma + shared_offset(txLo);
1192 iface->txLoAddr = cpu_to_le32(shared_dma);
1193 iface->txLoSize = cpu_to_le32(TXLO_ENTRIES * sizeof(struct tx_desc));
1194
1195 shared_dma = tp->shared_dma + shared_offset(txHi);
1196 iface->txHiAddr = cpu_to_le32(shared_dma);
1197 iface->txHiSize = cpu_to_le32(TXHI_ENTRIES * sizeof(struct tx_desc));
1198
1199 shared_dma = tp->shared_dma + shared_offset(rxBuff);
1200 iface->rxBuffAddr = cpu_to_le32(shared_dma);
1201 iface->rxBuffSize = cpu_to_le32(RXFREE_ENTRIES *
1202 sizeof(struct rx_free));
1203
1204 shared_dma = tp->shared_dma + shared_offset(rxLo);
1205 iface->rxLoAddr = cpu_to_le32(shared_dma);
1206 iface->rxLoSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1207
1208 shared_dma = tp->shared_dma + shared_offset(rxHi);
1209 iface->rxHiAddr = cpu_to_le32(shared_dma);
1210 iface->rxHiSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1211
1212 shared_dma = tp->shared_dma + shared_offset(cmd);
1213 iface->cmdAddr = cpu_to_le32(shared_dma);
1214 iface->cmdSize = cpu_to_le32(COMMAND_RING_SIZE);
1215
1216 shared_dma = tp->shared_dma + shared_offset(resp);
1217 iface->respAddr = cpu_to_le32(shared_dma);
1218 iface->respSize = cpu_to_le32(RESPONSE_RING_SIZE);
1219
1220 shared_dma = tp->shared_dma + shared_offset(zeroWord);
1221 iface->zeroAddr = cpu_to_le32(shared_dma);
1222
1223 tp->indexes = &tp->shared->indexes;
1224 tp->txLoRing.ringBase = (u8 *) tp->shared->txLo;
1225 tp->txHiRing.ringBase = (u8 *) tp->shared->txHi;
1226 tp->rxLoRing.ringBase = (u8 *) tp->shared->rxLo;
1227 tp->rxHiRing.ringBase = (u8 *) tp->shared->rxHi;
1228 tp->rxBuffRing.ringBase = (u8 *) tp->shared->rxBuff;
1229 tp->cmdRing.ringBase = (u8 *) tp->shared->cmd;
1230 tp->respRing.ringBase = (u8 *) tp->shared->resp;
1231
1232 tp->txLoRing.writeRegister = TYPHOON_REG_TX_LO_READY;
1233 tp->txHiRing.writeRegister = TYPHOON_REG_TX_HI_READY;
1234
1235 tp->txlo_dma_addr = le32_to_cpu(iface->txLoAddr);
1236 tp->card_state = Sleeping;
1237
1238 tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM;
1239 tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON;
1240 tp->offload |= TYPHOON_OFFLOAD_VLAN;
1241
1242 spin_lock_init(&tp->command_lock);
1243
1244 /* Force the writes to the shared memory area out before continuing. */
1245 wmb();
1246}
1247
1248static void
1249typhoon_init_rings(struct typhoon *tp)
1250{
1251 memset(tp->indexes, 0, sizeof(struct typhoon_indexes));
1252
1253 tp->txLoRing.lastWrite = 0;
1254 tp->txHiRing.lastWrite = 0;
1255 tp->rxLoRing.lastWrite = 0;
1256 tp->rxHiRing.lastWrite = 0;
1257 tp->rxBuffRing.lastWrite = 0;
1258 tp->cmdRing.lastWrite = 0;
1259 tp->respRing.lastWrite = 0;
1260
1261 tp->txLoRing.lastRead = 0;
1262 tp->txHiRing.lastRead = 0;
1263}
1264
1265static const struct firmware *typhoon_fw;
1266
1267static int
1268typhoon_request_firmware(struct typhoon *tp)
1269{
1270 const struct typhoon_file_header *fHdr;
1271 const struct typhoon_section_header *sHdr;
1272 const u8 *image_data;
1273 u32 numSections;
1274 u32 section_len;
1275 u32 remaining;
1276 int err;
1277
1278 if (typhoon_fw)
1279 return 0;
1280
1281 err = request_firmware(&typhoon_fw, FIRMWARE_NAME, &tp->pdev->dev);
1282 if (err) {
1283 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
1284 FIRMWARE_NAME);
1285 return err;
1286 }
1287
1288 image_data = typhoon_fw->data;
1289 remaining = typhoon_fw->size;
1290 if (remaining < sizeof(struct typhoon_file_header))
1291 goto invalid_fw;
1292
1293 fHdr = (struct typhoon_file_header *) image_data;
1294 if (memcmp(fHdr->tag, "TYPHOON", 8))
1295 goto invalid_fw;
1296
1297 numSections = le32_to_cpu(fHdr->numSections);
1298 image_data += sizeof(struct typhoon_file_header);
1299 remaining -= sizeof(struct typhoon_file_header);
1300
1301 while (numSections--) {
1302 if (remaining < sizeof(struct typhoon_section_header))
1303 goto invalid_fw;
1304
1305 sHdr = (struct typhoon_section_header *) image_data;
1306 image_data += sizeof(struct typhoon_section_header);
1307 section_len = le32_to_cpu(sHdr->len);
1308
1309 if (remaining < section_len)
1310 goto invalid_fw;
1311
1312 image_data += section_len;
1313 remaining -= section_len;
1314 }
1315
1316 return 0;
1317
1318invalid_fw:
1319 netdev_err(tp->dev, "Invalid firmware image\n");
1320 release_firmware(typhoon_fw);
1321 typhoon_fw = NULL;
1322 return -EINVAL;
1323}
1324
1325static int
1326typhoon_download_firmware(struct typhoon *tp)
1327{
1328 void __iomem *ioaddr = tp->ioaddr;
1329 struct pci_dev *pdev = tp->pdev;
1330 const struct typhoon_file_header *fHdr;
1331 const struct typhoon_section_header *sHdr;
1332 const u8 *image_data;
1333 void *dpage;
1334 dma_addr_t dpage_dma;
1335 __sum16 csum;
1336 u32 irqEnabled;
1337 u32 irqMasked;
1338 u32 numSections;
1339 u32 section_len;
1340 u32 len;
1341 u32 load_addr;
1342 u32 hmac;
1343 int i;
1344 int err;
1345
1346 image_data = typhoon_fw->data;
1347 fHdr = (struct typhoon_file_header *) image_data;
1348
1349 /* Cannot just map the firmware image using dma_map_single() as
1350 * the firmware is vmalloc()'d and may not be physically contiguous,
1351 * so we allocate some coherent memory to copy the sections into.
1352 */
1353 err = -ENOMEM;
1354 dpage = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &dpage_dma, GFP_ATOMIC);
1355 if (!dpage) {
1356 netdev_err(tp->dev, "no DMA mem for firmware\n");
1357 goto err_out;
1358 }
1359
1360 irqEnabled = ioread32(ioaddr + TYPHOON_REG_INTR_ENABLE);
1361 iowrite32(irqEnabled | TYPHOON_INTR_BOOTCMD,
1362 ioaddr + TYPHOON_REG_INTR_ENABLE);
1363 irqMasked = ioread32(ioaddr + TYPHOON_REG_INTR_MASK);
1364 iowrite32(irqMasked | TYPHOON_INTR_BOOTCMD,
1365 ioaddr + TYPHOON_REG_INTR_MASK);
1366
1367 err = -ETIMEDOUT;
1368 if (typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
1369 netdev_err(tp->dev, "card ready timeout\n");
1370 goto err_out_irq;
1371 }
1372
1373 numSections = le32_to_cpu(fHdr->numSections);
1374 load_addr = le32_to_cpu(fHdr->startAddr);
1375
1376 iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1377 iowrite32(load_addr, ioaddr + TYPHOON_REG_DOWNLOAD_BOOT_ADDR);
1378 hmac = le32_to_cpu(fHdr->hmacDigest[0]);
1379 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_0);
1380 hmac = le32_to_cpu(fHdr->hmacDigest[1]);
1381 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_1);
1382 hmac = le32_to_cpu(fHdr->hmacDigest[2]);
1383 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_2);
1384 hmac = le32_to_cpu(fHdr->hmacDigest[3]);
1385 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_3);
1386 hmac = le32_to_cpu(fHdr->hmacDigest[4]);
1387 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_4);
1388 typhoon_post_pci_writes(ioaddr);
1389 iowrite32(TYPHOON_BOOTCMD_RUNTIME_IMAGE, ioaddr + TYPHOON_REG_COMMAND);
1390
1391 image_data += sizeof(struct typhoon_file_header);
1392
1393 /* The ioread32() in typhoon_wait_interrupt() will force the
1394 * last write to the command register to post, so
1395 * we don't need a typhoon_post_pci_writes() after it.
1396 */
1397 for (i = 0; i < numSections; i++) {
1398 sHdr = (struct typhoon_section_header *) image_data;
1399 image_data += sizeof(struct typhoon_section_header);
1400 load_addr = le32_to_cpu(sHdr->startAddr);
1401 section_len = le32_to_cpu(sHdr->len);
1402
1403 while (section_len) {
1404 len = min_t(u32, section_len, PAGE_SIZE);
1405
1406 if (typhoon_wait_interrupt(ioaddr) < 0 ||
1407 ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1408 TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1409 netdev_err(tp->dev, "segment ready timeout\n");
1410 goto err_out_irq;
1411 }
1412
1413 /* Do an pseudo IPv4 checksum on the data -- first
1414 * need to convert each u16 to cpu order before
1415 * summing. Fortunately, due to the properties of
1416 * the checksum, we can do this once, at the end.
1417 */
1418 csum = csum_fold(csum_partial_copy_nocheck(image_data,
1419 dpage, len));
1420
1421 iowrite32(len, ioaddr + TYPHOON_REG_BOOT_LENGTH);
1422 iowrite32(le16_to_cpu((__force __le16)csum),
1423 ioaddr + TYPHOON_REG_BOOT_CHECKSUM);
1424 iowrite32(load_addr,
1425 ioaddr + TYPHOON_REG_BOOT_DEST_ADDR);
1426 iowrite32(0, ioaddr + TYPHOON_REG_BOOT_DATA_HI);
1427 iowrite32(dpage_dma, ioaddr + TYPHOON_REG_BOOT_DATA_LO);
1428 typhoon_post_pci_writes(ioaddr);
1429 iowrite32(TYPHOON_BOOTCMD_SEG_AVAILABLE,
1430 ioaddr + TYPHOON_REG_COMMAND);
1431
1432 image_data += len;
1433 load_addr += len;
1434 section_len -= len;
1435 }
1436 }
1437
1438 if (typhoon_wait_interrupt(ioaddr) < 0 ||
1439 ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1440 TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1441 netdev_err(tp->dev, "final segment ready timeout\n");
1442 goto err_out_irq;
1443 }
1444
1445 iowrite32(TYPHOON_BOOTCMD_DNLD_COMPLETE, ioaddr + TYPHOON_REG_COMMAND);
1446
1447 if (typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1448 netdev_err(tp->dev, "boot ready timeout, status 0x%0x\n",
1449 ioread32(ioaddr + TYPHOON_REG_STATUS));
1450 goto err_out_irq;
1451 }
1452
1453 err = 0;
1454
1455err_out_irq:
1456 iowrite32(irqMasked, ioaddr + TYPHOON_REG_INTR_MASK);
1457 iowrite32(irqEnabled, ioaddr + TYPHOON_REG_INTR_ENABLE);
1458
1459 dma_free_coherent(&pdev->dev, PAGE_SIZE, dpage, dpage_dma);
1460
1461err_out:
1462 return err;
1463}
1464
1465static int
1466typhoon_boot_3XP(struct typhoon *tp, u32 initial_status)
1467{
1468 void __iomem *ioaddr = tp->ioaddr;
1469
1470 if (typhoon_wait_status(ioaddr, initial_status) < 0) {
1471 netdev_err(tp->dev, "boot ready timeout\n");
1472 goto out_timeout;
1473 }
1474
1475 iowrite32(0, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_HI);
1476 iowrite32(tp->shared_dma, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_LO);
1477 typhoon_post_pci_writes(ioaddr);
1478 iowrite32(TYPHOON_BOOTCMD_REG_BOOT_RECORD,
1479 ioaddr + TYPHOON_REG_COMMAND);
1480
1481 if (typhoon_wait_status(ioaddr, TYPHOON_STATUS_RUNNING) < 0) {
1482 netdev_err(tp->dev, "boot finish timeout (status 0x%x)\n",
1483 ioread32(ioaddr + TYPHOON_REG_STATUS));
1484 goto out_timeout;
1485 }
1486
1487 /* Clear the Transmit and Command ready registers
1488 */
1489 iowrite32(0, ioaddr + TYPHOON_REG_TX_HI_READY);
1490 iowrite32(0, ioaddr + TYPHOON_REG_CMD_READY);
1491 iowrite32(0, ioaddr + TYPHOON_REG_TX_LO_READY);
1492 typhoon_post_pci_writes(ioaddr);
1493 iowrite32(TYPHOON_BOOTCMD_BOOT, ioaddr + TYPHOON_REG_COMMAND);
1494
1495 return 0;
1496
1497out_timeout:
1498 return -ETIMEDOUT;
1499}
1500
1501static u32
1502typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing,
1503 volatile __le32 * index)
1504{
1505 u32 lastRead = txRing->lastRead;
1506 struct tx_desc *tx;
1507 dma_addr_t skb_dma;
1508 int dma_len;
1509 int type;
1510
1511 while (lastRead != le32_to_cpu(*index)) {
1512 tx = (struct tx_desc *) (txRing->ringBase + lastRead);
1513 type = tx->flags & TYPHOON_TYPE_MASK;
1514
1515 if (type == TYPHOON_TX_DESC) {
1516 /* This tx_desc describes a packet.
1517 */
1518 unsigned long ptr = tx->tx_addr;
1519 struct sk_buff *skb = (struct sk_buff *) ptr;
1520 dev_kfree_skb_irq(skb);
1521 } else if (type == TYPHOON_FRAG_DESC) {
1522 /* This tx_desc describes a memory mapping. Free it.
1523 */
1524 skb_dma = (dma_addr_t) le32_to_cpu(tx->frag.addr);
1525 dma_len = le16_to_cpu(tx->len);
1526 dma_unmap_single(&tp->pdev->dev, skb_dma, dma_len,
1527 DMA_TO_DEVICE);
1528 }
1529
1530 tx->flags = 0;
1531 typhoon_inc_tx_index(&lastRead, 1);
1532 }
1533
1534 return lastRead;
1535}
1536
1537static void
1538typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing,
1539 volatile __le32 * index)
1540{
1541 u32 lastRead;
1542 int numDesc = MAX_SKB_FRAGS + 1;
1543
1544 /* This will need changing if we start to use the Hi Tx ring. */
1545 lastRead = typhoon_clean_tx(tp, txRing, index);
1546 if (netif_queue_stopped(tp->dev) && typhoon_num_free(txRing->lastWrite,
1547 lastRead, TXLO_ENTRIES) > (numDesc + 2))
1548 netif_wake_queue(tp->dev);
1549
1550 txRing->lastRead = lastRead;
1551 smp_wmb();
1552}
1553
1554static void
1555typhoon_recycle_rx_skb(struct typhoon *tp, u32 idx)
1556{
1557 struct typhoon_indexes *indexes = tp->indexes;
1558 struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1559 struct basic_ring *ring = &tp->rxBuffRing;
1560 struct rx_free *r;
1561
1562 if ((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1563 le32_to_cpu(indexes->rxBuffCleared)) {
1564 /* no room in ring, just drop the skb
1565 */
1566 dev_kfree_skb_any(rxb->skb);
1567 rxb->skb = NULL;
1568 return;
1569 }
1570
1571 r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1572 typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1573 r->virtAddr = idx;
1574 r->physAddr = cpu_to_le32(rxb->dma_addr);
1575
1576 /* Tell the card about it */
1577 wmb();
1578 indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1579}
1580
1581static int
1582typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx)
1583{
1584 struct typhoon_indexes *indexes = tp->indexes;
1585 struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1586 struct basic_ring *ring = &tp->rxBuffRing;
1587 struct rx_free *r;
1588 struct sk_buff *skb;
1589 dma_addr_t dma_addr;
1590
1591 rxb->skb = NULL;
1592
1593 if ((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1594 le32_to_cpu(indexes->rxBuffCleared))
1595 return -ENOMEM;
1596
1597 skb = netdev_alloc_skb(tp->dev, PKT_BUF_SZ);
1598 if (!skb)
1599 return -ENOMEM;
1600
1601#if 0
1602 /* Please, 3com, fix the firmware to allow DMA to a unaligned
1603 * address! Pretty please?
1604 */
1605 skb_reserve(skb, 2);
1606#endif
1607
1608 dma_addr = dma_map_single(&tp->pdev->dev, skb->data, PKT_BUF_SZ,
1609 DMA_FROM_DEVICE);
1610
1611 /* Since no card does 64 bit DAC, the high bits will never
1612 * change from zero.
1613 */
1614 r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1615 typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1616 r->virtAddr = idx;
1617 r->physAddr = cpu_to_le32(dma_addr);
1618 rxb->skb = skb;
1619 rxb->dma_addr = dma_addr;
1620
1621 /* Tell the card about it */
1622 wmb();
1623 indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1624 return 0;
1625}
1626
1627static int
1628typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile __le32 * ready,
1629 volatile __le32 * cleared, int budget)
1630{
1631 struct rx_desc *rx;
1632 struct sk_buff *skb, *new_skb;
1633 struct rxbuff_ent *rxb;
1634 dma_addr_t dma_addr;
1635 u32 local_ready;
1636 u32 rxaddr;
1637 int pkt_len;
1638 u32 idx;
1639 __le32 csum_bits;
1640 int received;
1641
1642 received = 0;
1643 local_ready = le32_to_cpu(*ready);
1644 rxaddr = le32_to_cpu(*cleared);
1645 while (rxaddr != local_ready && budget > 0) {
1646 rx = (struct rx_desc *) (rxRing->ringBase + rxaddr);
1647 idx = rx->addr;
1648 rxb = &tp->rxbuffers[idx];
1649 skb = rxb->skb;
1650 dma_addr = rxb->dma_addr;
1651
1652 typhoon_inc_rx_index(&rxaddr, 1);
1653
1654 if (rx->flags & TYPHOON_RX_ERROR) {
1655 typhoon_recycle_rx_skb(tp, idx);
1656 continue;
1657 }
1658
1659 pkt_len = le16_to_cpu(rx->frameLen);
1660
1661 if (pkt_len < rx_copybreak &&
1662 (new_skb = netdev_alloc_skb(tp->dev, pkt_len + 2)) != NULL) {
1663 skb_reserve(new_skb, 2);
1664 dma_sync_single_for_cpu(&tp->pdev->dev, dma_addr,
1665 PKT_BUF_SZ, DMA_FROM_DEVICE);
1666 skb_copy_to_linear_data(new_skb, skb->data, pkt_len);
1667 dma_sync_single_for_device(&tp->pdev->dev, dma_addr,
1668 PKT_BUF_SZ,
1669 DMA_FROM_DEVICE);
1670 skb_put(new_skb, pkt_len);
1671 typhoon_recycle_rx_skb(tp, idx);
1672 } else {
1673 new_skb = skb;
1674 skb_put(new_skb, pkt_len);
1675 dma_unmap_single(&tp->pdev->dev, dma_addr, PKT_BUF_SZ,
1676 DMA_FROM_DEVICE);
1677 typhoon_alloc_rx_skb(tp, idx);
1678 }
1679 new_skb->protocol = eth_type_trans(new_skb, tp->dev);
1680 csum_bits = rx->rxStatus & (TYPHOON_RX_IP_CHK_GOOD |
1681 TYPHOON_RX_UDP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD);
1682 if (csum_bits ==
1683 (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD) ||
1684 csum_bits ==
1685 (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_UDP_CHK_GOOD)) {
1686 new_skb->ip_summed = CHECKSUM_UNNECESSARY;
1687 } else
1688 skb_checksum_none_assert(new_skb);
1689
1690 if (rx->rxStatus & TYPHOON_RX_VLAN)
1691 __vlan_hwaccel_put_tag(new_skb, htons(ETH_P_8021Q),
1692 ntohl(rx->vlanTag) & 0xffff);
1693 netif_receive_skb(new_skb);
1694
1695 received++;
1696 budget--;
1697 }
1698 *cleared = cpu_to_le32(rxaddr);
1699
1700 return received;
1701}
1702
1703static void
1704typhoon_fill_free_ring(struct typhoon *tp)
1705{
1706 u32 i;
1707
1708 for (i = 0; i < RXENT_ENTRIES; i++) {
1709 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1710 if (rxb->skb)
1711 continue;
1712 if (typhoon_alloc_rx_skb(tp, i) < 0)
1713 break;
1714 }
1715}
1716
1717static int
1718typhoon_poll(struct napi_struct *napi, int budget)
1719{
1720 struct typhoon *tp = container_of(napi, struct typhoon, napi);
1721 struct typhoon_indexes *indexes = tp->indexes;
1722 int work_done;
1723
1724 rmb();
1725 if (!tp->awaiting_resp && indexes->respReady != indexes->respCleared)
1726 typhoon_process_response(tp, 0, NULL);
1727
1728 if (le32_to_cpu(indexes->txLoCleared) != tp->txLoRing.lastRead)
1729 typhoon_tx_complete(tp, &tp->txLoRing, &indexes->txLoCleared);
1730
1731 work_done = 0;
1732
1733 if (indexes->rxHiCleared != indexes->rxHiReady) {
1734 work_done += typhoon_rx(tp, &tp->rxHiRing, &indexes->rxHiReady,
1735 &indexes->rxHiCleared, budget);
1736 }
1737
1738 if (indexes->rxLoCleared != indexes->rxLoReady) {
1739 work_done += typhoon_rx(tp, &tp->rxLoRing, &indexes->rxLoReady,
1740 &indexes->rxLoCleared, budget - work_done);
1741 }
1742
1743 if (le32_to_cpu(indexes->rxBuffCleared) == tp->rxBuffRing.lastWrite) {
1744 /* rxBuff ring is empty, try to fill it. */
1745 typhoon_fill_free_ring(tp);
1746 }
1747
1748 if (work_done < budget) {
1749 napi_complete_done(napi, work_done);
1750 iowrite32(TYPHOON_INTR_NONE,
1751 tp->ioaddr + TYPHOON_REG_INTR_MASK);
1752 typhoon_post_pci_writes(tp->ioaddr);
1753 }
1754
1755 return work_done;
1756}
1757
1758static irqreturn_t
1759typhoon_interrupt(int irq, void *dev_instance)
1760{
1761 struct net_device *dev = dev_instance;
1762 struct typhoon *tp = netdev_priv(dev);
1763 void __iomem *ioaddr = tp->ioaddr;
1764 u32 intr_status;
1765
1766 intr_status = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
1767 if (!(intr_status & TYPHOON_INTR_HOST_INT))
1768 return IRQ_NONE;
1769
1770 iowrite32(intr_status, ioaddr + TYPHOON_REG_INTR_STATUS);
1771
1772 if (napi_schedule_prep(&tp->napi)) {
1773 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
1774 typhoon_post_pci_writes(ioaddr);
1775 __napi_schedule(&tp->napi);
1776 } else {
1777 netdev_err(dev, "Error, poll already scheduled\n");
1778 }
1779 return IRQ_HANDLED;
1780}
1781
1782static void
1783typhoon_free_rx_rings(struct typhoon *tp)
1784{
1785 u32 i;
1786
1787 for (i = 0; i < RXENT_ENTRIES; i++) {
1788 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1789 if (rxb->skb) {
1790 dma_unmap_single(&tp->pdev->dev, rxb->dma_addr,
1791 PKT_BUF_SZ, DMA_FROM_DEVICE);
1792 dev_kfree_skb(rxb->skb);
1793 rxb->skb = NULL;
1794 }
1795 }
1796}
1797
1798static int
1799typhoon_sleep_early(struct typhoon *tp, __le16 events)
1800{
1801 void __iomem *ioaddr = tp->ioaddr;
1802 struct cmd_desc xp_cmd;
1803 int err;
1804
1805 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_ENABLE_WAKE_EVENTS);
1806 xp_cmd.parm1 = events;
1807 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1808 if (err < 0) {
1809 netdev_err(tp->dev, "typhoon_sleep(): wake events cmd err %d\n",
1810 err);
1811 return err;
1812 }
1813
1814 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_GOTO_SLEEP);
1815 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1816 if (err < 0) {
1817 netdev_err(tp->dev, "typhoon_sleep(): sleep cmd err %d\n", err);
1818 return err;
1819 }
1820
1821 if (typhoon_wait_status(ioaddr, TYPHOON_STATUS_SLEEPING) < 0)
1822 return -ETIMEDOUT;
1823
1824 /* Since we cannot monitor the status of the link while sleeping,
1825 * tell the world it went away.
1826 */
1827 netif_carrier_off(tp->dev);
1828
1829 return 0;
1830}
1831
1832static int
1833typhoon_sleep(struct typhoon *tp, pci_power_t state, __le16 events)
1834{
1835 int err;
1836
1837 err = typhoon_sleep_early(tp, events);
1838
1839 if (err)
1840 return err;
1841
1842 pci_enable_wake(tp->pdev, state, 1);
1843 pci_disable_device(tp->pdev);
1844 return pci_set_power_state(tp->pdev, state);
1845}
1846
1847static int
1848typhoon_wakeup(struct typhoon *tp, int wait_type)
1849{
1850 void __iomem *ioaddr = tp->ioaddr;
1851
1852 /* Post 2.x.x versions of the Sleep Image require a reset before
1853 * we can download the Runtime Image. But let's not make users of
1854 * the old firmware pay for the reset.
1855 */
1856 iowrite32(TYPHOON_BOOTCMD_WAKEUP, ioaddr + TYPHOON_REG_COMMAND);
1857 if (typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0 ||
1858 (tp->capabilities & TYPHOON_WAKEUP_NEEDS_RESET))
1859 return typhoon_reset(ioaddr, wait_type);
1860
1861 return 0;
1862}
1863
1864static int
1865typhoon_start_runtime(struct typhoon *tp)
1866{
1867 struct net_device *dev = tp->dev;
1868 void __iomem *ioaddr = tp->ioaddr;
1869 struct cmd_desc xp_cmd;
1870 int err;
1871
1872 typhoon_init_rings(tp);
1873 typhoon_fill_free_ring(tp);
1874
1875 err = typhoon_download_firmware(tp);
1876 if (err < 0) {
1877 netdev_err(tp->dev, "cannot load runtime on 3XP\n");
1878 goto error_out;
1879 }
1880
1881 if (typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1882 netdev_err(tp->dev, "cannot boot 3XP\n");
1883 err = -EIO;
1884 goto error_out;
1885 }
1886
1887 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAX_PKT_SIZE);
1888 xp_cmd.parm1 = cpu_to_le16(PKT_BUF_SZ);
1889 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1890 if (err < 0)
1891 goto error_out;
1892
1893 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
1894 xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
1895 xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
1896 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1897 if (err < 0)
1898 goto error_out;
1899
1900 /* Disable IRQ coalescing -- we can reenable it when 3Com gives
1901 * us some more information on how to control it.
1902 */
1903 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_IRQ_COALESCE_CTRL);
1904 xp_cmd.parm1 = 0;
1905 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1906 if (err < 0)
1907 goto error_out;
1908
1909 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1910 xp_cmd.parm1 = tp->xcvr_select;
1911 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1912 if (err < 0)
1913 goto error_out;
1914
1915 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE);
1916 xp_cmd.parm1 = cpu_to_le16(ETH_P_8021Q);
1917 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1918 if (err < 0)
1919 goto error_out;
1920
1921 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_OFFLOAD_TASKS);
1922 xp_cmd.parm2 = tp->offload;
1923 xp_cmd.parm3 = tp->offload;
1924 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1925 if (err < 0)
1926 goto error_out;
1927
1928 typhoon_set_rx_mode(dev);
1929
1930 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_ENABLE);
1931 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1932 if (err < 0)
1933 goto error_out;
1934
1935 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_ENABLE);
1936 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1937 if (err < 0)
1938 goto error_out;
1939
1940 tp->card_state = Running;
1941 smp_wmb();
1942
1943 iowrite32(TYPHOON_INTR_ENABLE_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
1944 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_MASK);
1945 typhoon_post_pci_writes(ioaddr);
1946
1947 return 0;
1948
1949error_out:
1950 typhoon_reset(ioaddr, WaitNoSleep);
1951 typhoon_free_rx_rings(tp);
1952 typhoon_init_rings(tp);
1953 return err;
1954}
1955
1956static int
1957typhoon_stop_runtime(struct typhoon *tp, int wait_type)
1958{
1959 struct typhoon_indexes *indexes = tp->indexes;
1960 struct transmit_ring *txLo = &tp->txLoRing;
1961 void __iomem *ioaddr = tp->ioaddr;
1962 struct cmd_desc xp_cmd;
1963 int i;
1964
1965 /* Disable interrupts early, since we can't schedule a poll
1966 * when called with !netif_running(). This will be posted
1967 * when we force the posting of the command.
1968 */
1969 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
1970
1971 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_DISABLE);
1972 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1973
1974 /* Wait 1/2 sec for any outstanding transmits to occur
1975 * We'll cleanup after the reset if this times out.
1976 */
1977 for (i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1978 if (indexes->txLoCleared == cpu_to_le32(txLo->lastWrite))
1979 break;
1980 udelay(TYPHOON_UDELAY);
1981 }
1982
1983 if (i == TYPHOON_WAIT_TIMEOUT)
1984 netdev_err(tp->dev, "halt timed out waiting for Tx to complete\n");
1985
1986 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_DISABLE);
1987 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1988
1989 /* save the statistics so when we bring the interface up again,
1990 * the values reported to userspace are correct.
1991 */
1992 tp->card_state = Sleeping;
1993 smp_wmb();
1994 typhoon_do_get_stats(tp);
1995 memcpy(&tp->stats_saved, &tp->dev->stats, sizeof(struct net_device_stats));
1996
1997 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_HALT);
1998 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1999
2000 if (typhoon_wait_status(ioaddr, TYPHOON_STATUS_HALTED) < 0)
2001 netdev_err(tp->dev, "timed out waiting for 3XP to halt\n");
2002
2003 if (typhoon_reset(ioaddr, wait_type) < 0) {
2004 netdev_err(tp->dev, "unable to reset 3XP\n");
2005 return -ETIMEDOUT;
2006 }
2007
2008 /* cleanup any outstanding Tx packets */
2009 if (indexes->txLoCleared != cpu_to_le32(txLo->lastWrite)) {
2010 indexes->txLoCleared = cpu_to_le32(txLo->lastWrite);
2011 typhoon_clean_tx(tp, &tp->txLoRing, &indexes->txLoCleared);
2012 }
2013
2014 return 0;
2015}
2016
2017static void
2018typhoon_tx_timeout(struct net_device *dev, unsigned int txqueue)
2019{
2020 struct typhoon *tp = netdev_priv(dev);
2021
2022 if (typhoon_reset(tp->ioaddr, WaitNoSleep) < 0) {
2023 netdev_warn(dev, "could not reset in tx timeout\n");
2024 goto truly_dead;
2025 }
2026
2027 /* If we ever start using the Hi ring, it will need cleaning too */
2028 typhoon_clean_tx(tp, &tp->txLoRing, &tp->indexes->txLoCleared);
2029 typhoon_free_rx_rings(tp);
2030
2031 if (typhoon_start_runtime(tp) < 0) {
2032 netdev_err(dev, "could not start runtime in tx timeout\n");
2033 goto truly_dead;
2034 }
2035
2036 netif_wake_queue(dev);
2037 return;
2038
2039truly_dead:
2040 /* Reset the hardware, and turn off carrier to avoid more timeouts */
2041 typhoon_reset(tp->ioaddr, NoWait);
2042 netif_carrier_off(dev);
2043}
2044
2045static int
2046typhoon_open(struct net_device *dev)
2047{
2048 struct typhoon *tp = netdev_priv(dev);
2049 int err;
2050
2051 err = typhoon_request_firmware(tp);
2052 if (err)
2053 goto out;
2054
2055 pci_set_power_state(tp->pdev, PCI_D0);
2056 pci_restore_state(tp->pdev);
2057
2058 err = typhoon_wakeup(tp, WaitSleep);
2059 if (err < 0) {
2060 netdev_err(dev, "unable to wakeup device\n");
2061 goto out_sleep;
2062 }
2063
2064 err = request_irq(dev->irq, typhoon_interrupt, IRQF_SHARED,
2065 dev->name, dev);
2066 if (err < 0)
2067 goto out_sleep;
2068
2069 napi_enable(&tp->napi);
2070
2071 err = typhoon_start_runtime(tp);
2072 if (err < 0) {
2073 napi_disable(&tp->napi);
2074 goto out_irq;
2075 }
2076
2077 netif_start_queue(dev);
2078 return 0;
2079
2080out_irq:
2081 free_irq(dev->irq, dev);
2082
2083out_sleep:
2084 if (typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2085 netdev_err(dev, "unable to reboot into sleep img\n");
2086 typhoon_reset(tp->ioaddr, NoWait);
2087 goto out;
2088 }
2089
2090 if (typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2091 netdev_err(dev, "unable to go back to sleep\n");
2092
2093out:
2094 return err;
2095}
2096
2097static int
2098typhoon_close(struct net_device *dev)
2099{
2100 struct typhoon *tp = netdev_priv(dev);
2101
2102 netif_stop_queue(dev);
2103 napi_disable(&tp->napi);
2104
2105 if (typhoon_stop_runtime(tp, WaitSleep) < 0)
2106 netdev_err(dev, "unable to stop runtime\n");
2107
2108 /* Make sure there is no irq handler running on a different CPU. */
2109 free_irq(dev->irq, dev);
2110
2111 typhoon_free_rx_rings(tp);
2112 typhoon_init_rings(tp);
2113
2114 if (typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0)
2115 netdev_err(dev, "unable to boot sleep image\n");
2116
2117 if (typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2118 netdev_err(dev, "unable to put card to sleep\n");
2119
2120 return 0;
2121}
2122
2123static int __maybe_unused
2124typhoon_resume(struct device *dev_d)
2125{
2126 struct net_device *dev = dev_get_drvdata(dev_d);
2127 struct typhoon *tp = netdev_priv(dev);
2128
2129 /* If we're down, resume when we are upped.
2130 */
2131 if (!netif_running(dev))
2132 return 0;
2133
2134 if (typhoon_wakeup(tp, WaitNoSleep) < 0) {
2135 netdev_err(dev, "critical: could not wake up in resume\n");
2136 goto reset;
2137 }
2138
2139 if (typhoon_start_runtime(tp) < 0) {
2140 netdev_err(dev, "critical: could not start runtime in resume\n");
2141 goto reset;
2142 }
2143
2144 netif_device_attach(dev);
2145 return 0;
2146
2147reset:
2148 typhoon_reset(tp->ioaddr, NoWait);
2149 return -EBUSY;
2150}
2151
2152static int __maybe_unused
2153typhoon_suspend(struct device *dev_d)
2154{
2155 struct pci_dev *pdev = to_pci_dev(dev_d);
2156 struct net_device *dev = pci_get_drvdata(pdev);
2157 struct typhoon *tp = netdev_priv(dev);
2158 struct cmd_desc xp_cmd;
2159
2160 /* If we're down, we're already suspended.
2161 */
2162 if (!netif_running(dev))
2163 return 0;
2164
2165 /* TYPHOON_OFFLOAD_VLAN is always on now, so this doesn't work */
2166 if (tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
2167 netdev_warn(dev, "cannot do WAKE_MAGIC with VLAN offloading\n");
2168
2169 netif_device_detach(dev);
2170
2171 if (typhoon_stop_runtime(tp, WaitNoSleep) < 0) {
2172 netdev_err(dev, "unable to stop runtime\n");
2173 goto need_resume;
2174 }
2175
2176 typhoon_free_rx_rings(tp);
2177 typhoon_init_rings(tp);
2178
2179 if (typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2180 netdev_err(dev, "unable to boot sleep image\n");
2181 goto need_resume;
2182 }
2183
2184 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
2185 xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
2186 xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
2187 if (typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2188 netdev_err(dev, "unable to set mac address in suspend\n");
2189 goto need_resume;
2190 }
2191
2192 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
2193 xp_cmd.parm1 = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
2194 if (typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2195 netdev_err(dev, "unable to set rx filter in suspend\n");
2196 goto need_resume;
2197 }
2198
2199 if (typhoon_sleep_early(tp, tp->wol_events) < 0) {
2200 netdev_err(dev, "unable to put card to sleep\n");
2201 goto need_resume;
2202 }
2203
2204 device_wakeup_enable(dev_d);
2205
2206 return 0;
2207
2208need_resume:
2209 typhoon_resume(dev_d);
2210 return -EBUSY;
2211}
2212
2213static int
2214typhoon_test_mmio(struct pci_dev *pdev)
2215{
2216 void __iomem *ioaddr = pci_iomap(pdev, 1, 128);
2217 int mode = 0;
2218 u32 val;
2219
2220 if (!ioaddr)
2221 goto out;
2222
2223 if (ioread32(ioaddr + TYPHOON_REG_STATUS) !=
2224 TYPHOON_STATUS_WAITING_FOR_HOST)
2225 goto out_unmap;
2226
2227 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2228 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2229 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
2230
2231 /* Ok, see if we can change our interrupt status register by
2232 * sending ourselves an interrupt. If so, then MMIO works.
2233 * The 50usec delay is arbitrary -- it could probably be smaller.
2234 */
2235 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2236 if ((val & TYPHOON_INTR_SELF) == 0) {
2237 iowrite32(1, ioaddr + TYPHOON_REG_SELF_INTERRUPT);
2238 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2239 udelay(50);
2240 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2241 if (val & TYPHOON_INTR_SELF)
2242 mode = 1;
2243 }
2244
2245 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2246 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2247 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2248 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2249
2250out_unmap:
2251 pci_iounmap(pdev, ioaddr);
2252
2253out:
2254 if (!mode)
2255 pr_info("%s: falling back to port IO\n", pci_name(pdev));
2256 return mode;
2257}
2258
2259#if MAX_SKB_FRAGS > 32
2260
2261#include <net/vxlan.h>
2262
2263static netdev_features_t typhoon_features_check(struct sk_buff *skb,
2264 struct net_device *dev,
2265 netdev_features_t features)
2266{
2267 if (skb_shinfo(skb)->nr_frags > 32 && skb_is_gso(skb))
2268 features &= ~NETIF_F_GSO_MASK;
2269
2270 features = vlan_features_check(skb, features);
2271 return vxlan_features_check(skb, features);
2272}
2273#endif
2274
2275static const struct net_device_ops typhoon_netdev_ops = {
2276 .ndo_open = typhoon_open,
2277 .ndo_stop = typhoon_close,
2278#if MAX_SKB_FRAGS > 32
2279 .ndo_features_check = typhoon_features_check,
2280#endif
2281 .ndo_start_xmit = typhoon_start_tx,
2282 .ndo_set_rx_mode = typhoon_set_rx_mode,
2283 .ndo_tx_timeout = typhoon_tx_timeout,
2284 .ndo_get_stats = typhoon_get_stats,
2285 .ndo_validate_addr = eth_validate_addr,
2286 .ndo_set_mac_address = eth_mac_addr,
2287};
2288
2289static int
2290typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2291{
2292 struct net_device *dev;
2293 struct typhoon *tp;
2294 int card_id = (int) ent->driver_data;
2295 u8 addr[ETH_ALEN] __aligned(4);
2296 void __iomem *ioaddr;
2297 void *shared;
2298 dma_addr_t shared_dma;
2299 struct cmd_desc xp_cmd;
2300 struct resp_desc xp_resp[3];
2301 int err = 0;
2302 const char *err_msg;
2303
2304 dev = alloc_etherdev(sizeof(*tp));
2305 if (dev == NULL) {
2306 err_msg = "unable to alloc new net device";
2307 err = -ENOMEM;
2308 goto error_out;
2309 }
2310 SET_NETDEV_DEV(dev, &pdev->dev);
2311
2312 err = pci_enable_device(pdev);
2313 if (err < 0) {
2314 err_msg = "unable to enable device";
2315 goto error_out_dev;
2316 }
2317
2318 err = pci_set_mwi(pdev);
2319 if (err < 0) {
2320 err_msg = "unable to set MWI";
2321 goto error_out_disable;
2322 }
2323
2324 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
2325 if (err < 0) {
2326 err_msg = "No usable DMA configuration";
2327 goto error_out_mwi;
2328 }
2329
2330 /* sanity checks on IO and MMIO BARs
2331 */
2332 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2333 err_msg = "region #1 not a PCI IO resource, aborting";
2334 err = -ENODEV;
2335 goto error_out_mwi;
2336 }
2337 if (pci_resource_len(pdev, 0) < 128) {
2338 err_msg = "Invalid PCI IO region size, aborting";
2339 err = -ENODEV;
2340 goto error_out_mwi;
2341 }
2342 if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
2343 err_msg = "region #1 not a PCI MMIO resource, aborting";
2344 err = -ENODEV;
2345 goto error_out_mwi;
2346 }
2347 if (pci_resource_len(pdev, 1) < 128) {
2348 err_msg = "Invalid PCI MMIO region size, aborting";
2349 err = -ENODEV;
2350 goto error_out_mwi;
2351 }
2352
2353 err = pci_request_regions(pdev, KBUILD_MODNAME);
2354 if (err < 0) {
2355 err_msg = "could not request regions";
2356 goto error_out_mwi;
2357 }
2358
2359 /* map our registers
2360 */
2361 if (use_mmio != 0 && use_mmio != 1)
2362 use_mmio = typhoon_test_mmio(pdev);
2363
2364 ioaddr = pci_iomap(pdev, use_mmio, 128);
2365 if (!ioaddr) {
2366 err_msg = "cannot remap registers, aborting";
2367 err = -EIO;
2368 goto error_out_regions;
2369 }
2370
2371 /* allocate pci dma space for rx and tx descriptor rings
2372 */
2373 shared = dma_alloc_coherent(&pdev->dev, sizeof(struct typhoon_shared),
2374 &shared_dma, GFP_KERNEL);
2375 if (!shared) {
2376 err_msg = "could not allocate DMA memory";
2377 err = -ENOMEM;
2378 goto error_out_remap;
2379 }
2380
2381 dev->irq = pdev->irq;
2382 tp = netdev_priv(dev);
2383 tp->shared = shared;
2384 tp->shared_dma = shared_dma;
2385 tp->pdev = pdev;
2386 tp->tx_pdev = pdev;
2387 tp->ioaddr = ioaddr;
2388 tp->tx_ioaddr = ioaddr;
2389 tp->dev = dev;
2390
2391 /* Init sequence:
2392 * 1) Reset the adapter to clear any bad juju
2393 * 2) Reload the sleep image
2394 * 3) Boot the sleep image
2395 * 4) Get the hardware address.
2396 * 5) Put the card to sleep.
2397 */
2398 err = typhoon_reset(ioaddr, WaitSleep);
2399 if (err < 0) {
2400 err_msg = "could not reset 3XP";
2401 goto error_out_dma;
2402 }
2403
2404 /* Now that we've reset the 3XP and are sure it's not going to
2405 * write all over memory, enable bus mastering, and save our
2406 * state for resuming after a suspend.
2407 */
2408 pci_set_master(pdev);
2409 pci_save_state(pdev);
2410
2411 typhoon_init_interface(tp);
2412 typhoon_init_rings(tp);
2413
2414 err = typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST);
2415 if (err < 0) {
2416 err_msg = "cannot boot 3XP sleep image";
2417 goto error_out_reset;
2418 }
2419
2420 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_MAC_ADDRESS);
2421 err = typhoon_issue_command(tp, 1, &xp_cmd, 1, xp_resp);
2422 if (err < 0) {
2423 err_msg = "cannot read MAC address";
2424 goto error_out_reset;
2425 }
2426
2427 *(__be16 *)&addr[0] = htons(le16_to_cpu(xp_resp[0].parm1));
2428 *(__be32 *)&addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2));
2429 eth_hw_addr_set(dev, addr);
2430
2431 if (!is_valid_ether_addr(dev->dev_addr)) {
2432 err_msg = "Could not obtain valid ethernet address, aborting";
2433 err = -EIO;
2434 goto error_out_reset;
2435 }
2436
2437 /* Read the Sleep Image version last, so the response is valid
2438 * later when we print out the version reported.
2439 */
2440 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
2441 err = typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp);
2442 if (err < 0) {
2443 err_msg = "Could not get Sleep Image version";
2444 goto error_out_reset;
2445 }
2446
2447 tp->capabilities = typhoon_card_info[card_id].capabilities;
2448 tp->xcvr_select = TYPHOON_XCVR_AUTONEG;
2449
2450 /* Typhoon 1.0 Sleep Images return one response descriptor to the
2451 * READ_VERSIONS command. Those versions are OK after waking up
2452 * from sleep without needing a reset. Typhoon 1.1+ Sleep Images
2453 * seem to need a little extra help to get started. Since we don't
2454 * know how to nudge it along, just kick it.
2455 */
2456 if (xp_resp[0].numDesc != 0)
2457 tp->capabilities |= TYPHOON_WAKEUP_NEEDS_RESET;
2458
2459 err = typhoon_sleep(tp, PCI_D3hot, 0);
2460 if (err < 0) {
2461 err_msg = "cannot put adapter to sleep";
2462 goto error_out_reset;
2463 }
2464
2465 /* The chip-specific entries in the device structure. */
2466 dev->netdev_ops = &typhoon_netdev_ops;
2467 netif_napi_add_weight(dev, &tp->napi, typhoon_poll, 16);
2468 dev->watchdog_timeo = TX_TIMEOUT;
2469
2470 dev->ethtool_ops = &typhoon_ethtool_ops;
2471
2472 /* We can handle scatter gather, up to 16 entries, and
2473 * we can do IP checksumming (only version 4, doh...)
2474 *
2475 * There's no way to turn off the RX VLAN offloading and stripping
2476 * on the current 3XP firmware -- it does not respect the offload
2477 * settings -- so we only allow the user to toggle the TX processing.
2478 */
2479 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
2480 NETIF_F_HW_VLAN_CTAG_TX;
2481 dev->features = dev->hw_features |
2482 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_RXCSUM;
2483
2484 err = register_netdev(dev);
2485 if (err < 0) {
2486 err_msg = "unable to register netdev";
2487 goto error_out_reset;
2488 }
2489
2490 pci_set_drvdata(pdev, dev);
2491
2492 netdev_info(dev, "%s at %s 0x%llx, %pM\n",
2493 typhoon_card_info[card_id].name,
2494 use_mmio ? "MMIO" : "IO",
2495 (unsigned long long)pci_resource_start(pdev, use_mmio),
2496 dev->dev_addr);
2497
2498 /* xp_resp still contains the response to the READ_VERSIONS command.
2499 * For debugging, let the user know what version he has.
2500 */
2501 if (xp_resp[0].numDesc == 0) {
2502 /* This is the Typhoon 1.0 type Sleep Image, last 16 bits
2503 * of version is Month/Day of build.
2504 */
2505 u16 monthday = le32_to_cpu(xp_resp[0].parm2) & 0xffff;
2506 netdev_info(dev, "Typhoon 1.0 Sleep Image built %02u/%02u/2000\n",
2507 monthday >> 8, monthday & 0xff);
2508 } else if (xp_resp[0].numDesc == 2) {
2509 /* This is the Typhoon 1.1+ type Sleep Image
2510 */
2511 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
2512 u8 *ver_string = (u8 *) &xp_resp[1];
2513 ver_string[25] = 0;
2514 netdev_info(dev, "Typhoon 1.1+ Sleep Image version %02x.%03x.%03x %s\n",
2515 sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
2516 sleep_ver & 0xfff, ver_string);
2517 } else {
2518 netdev_warn(dev, "Unknown Sleep Image version (%u:%04x)\n",
2519 xp_resp[0].numDesc, le32_to_cpu(xp_resp[0].parm2));
2520 }
2521
2522 return 0;
2523
2524error_out_reset:
2525 typhoon_reset(ioaddr, NoWait);
2526
2527error_out_dma:
2528 dma_free_coherent(&pdev->dev, sizeof(struct typhoon_shared), shared,
2529 shared_dma);
2530error_out_remap:
2531 pci_iounmap(pdev, ioaddr);
2532error_out_regions:
2533 pci_release_regions(pdev);
2534error_out_mwi:
2535 pci_clear_mwi(pdev);
2536error_out_disable:
2537 pci_disable_device(pdev);
2538error_out_dev:
2539 free_netdev(dev);
2540error_out:
2541 pr_err("%s: %s\n", pci_name(pdev), err_msg);
2542 return err;
2543}
2544
2545static void
2546typhoon_remove_one(struct pci_dev *pdev)
2547{
2548 struct net_device *dev = pci_get_drvdata(pdev);
2549 struct typhoon *tp = netdev_priv(dev);
2550
2551 unregister_netdev(dev);
2552 pci_set_power_state(pdev, PCI_D0);
2553 pci_restore_state(pdev);
2554 typhoon_reset(tp->ioaddr, NoWait);
2555 pci_iounmap(pdev, tp->ioaddr);
2556 dma_free_coherent(&pdev->dev, sizeof(struct typhoon_shared),
2557 tp->shared, tp->shared_dma);
2558 pci_release_regions(pdev);
2559 pci_clear_mwi(pdev);
2560 pci_disable_device(pdev);
2561 free_netdev(dev);
2562}
2563
2564static SIMPLE_DEV_PM_OPS(typhoon_pm_ops, typhoon_suspend, typhoon_resume);
2565
2566static struct pci_driver typhoon_driver = {
2567 .name = KBUILD_MODNAME,
2568 .id_table = typhoon_pci_tbl,
2569 .probe = typhoon_init_one,
2570 .remove = typhoon_remove_one,
2571 .driver.pm = &typhoon_pm_ops,
2572};
2573
2574static int __init
2575typhoon_init(void)
2576{
2577 return pci_register_driver(&typhoon_driver);
2578}
2579
2580static void __exit
2581typhoon_cleanup(void)
2582{
2583 release_firmware(typhoon_fw);
2584 pci_unregister_driver(&typhoon_driver);
2585}
2586
2587module_init(typhoon_init);
2588module_exit(typhoon_cleanup);
1/* typhoon.c: A Linux Ethernet device driver for 3Com 3CR990 family of NICs */
2/*
3 Written 2002-2004 by David Dillow <dave@thedillows.org>
4 Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and
5 Linux 2.2.x driver by David P. McLean <davidpmclean@yahoo.com>.
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
13
14 This software is available on a public web site. It may enable
15 cryptographic capabilities of the 3Com hardware, and may be
16 exported from the United States under License Exception "TSU"
17 pursuant to 15 C.F.R. Section 740.13(e).
18
19 This work was funded by the National Library of Medicine under
20 the Department of Energy project number 0274DD06D1 and NLM project
21 number Y1-LM-2015-01.
22
23 This driver is designed for the 3Com 3CR990 Family of cards with the
24 3XP Processor. It has been tested on x86 and sparc64.
25
26 KNOWN ISSUES:
27 *) Cannot DMA Rx packets to a 2 byte aligned address. Also firmware
28 issue. Hopefully 3Com will fix it.
29 *) Waiting for a command response takes 8ms due to non-preemptable
30 polling. Only significant for getting stats and creating
31 SAs, but an ugly wart never the less.
32
33 TODO:
34 *) Doesn't do IPSEC offloading. Yet. Keep yer pants on, it's coming.
35 *) Add more support for ethtool (especially for NIC stats)
36 *) Allow disabling of RX checksum offloading
37 *) Fix MAC changing to work while the interface is up
38 (Need to put commands on the TX ring, which changes
39 the locking)
40 *) Add in FCS to {rx,tx}_bytes, since the hardware doesn't. See
41 http://oss.sgi.com/cgi-bin/mesg.cgi?a=netdev&i=20031215152211.7003fe8e.rddunlap%40osdl.org
42*/
43
44/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
45 * Setting to > 1518 effectively disables this feature.
46 */
47static int rx_copybreak = 200;
48
49/* Should we use MMIO or Port IO?
50 * 0: Port IO
51 * 1: MMIO
52 * 2: Try MMIO, fallback to Port IO
53 */
54static unsigned int use_mmio = 2;
55
56/* end user-configurable values */
57
58/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
59 */
60static const int multicast_filter_limit = 32;
61
62/* Operational parameters that are set at compile time. */
63
64/* Keep the ring sizes a power of two for compile efficiency.
65 * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
66 * Making the Tx ring too large decreases the effectiveness of channel
67 * bonding and packet priority.
68 * There are no ill effects from too-large receive rings.
69 *
70 * We don't currently use the Hi Tx ring so, don't make it very big.
71 *
72 * Beware that if we start using the Hi Tx ring, we will need to change
73 * typhoon_num_free_tx() and typhoon_tx_complete() to account for that.
74 */
75#define TXHI_ENTRIES 2
76#define TXLO_ENTRIES 128
77#define RX_ENTRIES 32
78#define COMMAND_ENTRIES 16
79#define RESPONSE_ENTRIES 32
80
81#define COMMAND_RING_SIZE (COMMAND_ENTRIES * sizeof(struct cmd_desc))
82#define RESPONSE_RING_SIZE (RESPONSE_ENTRIES * sizeof(struct resp_desc))
83
84/* The 3XP will preload and remove 64 entries from the free buffer
85 * list, and we need one entry to keep the ring from wrapping, so
86 * to keep this a power of two, we use 128 entries.
87 */
88#define RXFREE_ENTRIES 128
89#define RXENT_ENTRIES (RXFREE_ENTRIES - 1)
90
91/* Operational parameters that usually are not changed. */
92
93/* Time in jiffies before concluding the transmitter is hung. */
94#define TX_TIMEOUT (2*HZ)
95
96#define PKT_BUF_SZ 1536
97#define FIRMWARE_NAME "3com/typhoon.bin"
98
99#define pr_fmt(fmt) KBUILD_MODNAME " " fmt
100
101#include <linux/module.h>
102#include <linux/kernel.h>
103#include <linux/sched.h>
104#include <linux/string.h>
105#include <linux/timer.h>
106#include <linux/errno.h>
107#include <linux/ioport.h>
108#include <linux/interrupt.h>
109#include <linux/pci.h>
110#include <linux/netdevice.h>
111#include <linux/etherdevice.h>
112#include <linux/skbuff.h>
113#include <linux/mm.h>
114#include <linux/init.h>
115#include <linux/delay.h>
116#include <linux/ethtool.h>
117#include <linux/if_vlan.h>
118#include <linux/crc32.h>
119#include <linux/bitops.h>
120#include <asm/processor.h>
121#include <asm/io.h>
122#include <linux/uaccess.h>
123#include <linux/in6.h>
124#include <linux/dma-mapping.h>
125#include <linux/firmware.h>
126
127#include "typhoon.h"
128
129MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
130MODULE_VERSION("1.0");
131MODULE_LICENSE("GPL");
132MODULE_FIRMWARE(FIRMWARE_NAME);
133MODULE_DESCRIPTION("3Com Typhoon Family (3C990, 3CR990, and variants)");
134MODULE_PARM_DESC(rx_copybreak, "Packets smaller than this are copied and "
135 "the buffer given back to the NIC. Default "
136 "is 200.");
137MODULE_PARM_DESC(use_mmio, "Use MMIO (1) or PIO(0) to access the NIC. "
138 "Default is to try MMIO and fallback to PIO.");
139module_param(rx_copybreak, int, 0);
140module_param(use_mmio, int, 0);
141
142#if defined(NETIF_F_TSO) && MAX_SKB_FRAGS > 32
143#warning Typhoon only supports 32 entries in its SG list for TSO, disabling TSO
144#undef NETIF_F_TSO
145#endif
146
147#if TXLO_ENTRIES <= (2 * MAX_SKB_FRAGS)
148#error TX ring too small!
149#endif
150
151struct typhoon_card_info {
152 const char *name;
153 const int capabilities;
154};
155
156#define TYPHOON_CRYPTO_NONE 0x00
157#define TYPHOON_CRYPTO_DES 0x01
158#define TYPHOON_CRYPTO_3DES 0x02
159#define TYPHOON_CRYPTO_VARIABLE 0x04
160#define TYPHOON_FIBER 0x08
161#define TYPHOON_WAKEUP_NEEDS_RESET 0x10
162
163enum typhoon_cards {
164 TYPHOON_TX = 0, TYPHOON_TX95, TYPHOON_TX97, TYPHOON_SVR,
165 TYPHOON_SVR95, TYPHOON_SVR97, TYPHOON_TXM, TYPHOON_BSVR,
166 TYPHOON_FX95, TYPHOON_FX97, TYPHOON_FX95SVR, TYPHOON_FX97SVR,
167 TYPHOON_FXM,
168};
169
170/* directly indexed by enum typhoon_cards, above */
171static struct typhoon_card_info typhoon_card_info[] = {
172 { "3Com Typhoon (3C990-TX)",
173 TYPHOON_CRYPTO_NONE},
174 { "3Com Typhoon (3CR990-TX-95)",
175 TYPHOON_CRYPTO_DES},
176 { "3Com Typhoon (3CR990-TX-97)",
177 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
178 { "3Com Typhoon (3C990SVR)",
179 TYPHOON_CRYPTO_NONE},
180 { "3Com Typhoon (3CR990SVR95)",
181 TYPHOON_CRYPTO_DES},
182 { "3Com Typhoon (3CR990SVR97)",
183 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
184 { "3Com Typhoon2 (3C990B-TX-M)",
185 TYPHOON_CRYPTO_VARIABLE},
186 { "3Com Typhoon2 (3C990BSVR)",
187 TYPHOON_CRYPTO_VARIABLE},
188 { "3Com Typhoon (3CR990-FX-95)",
189 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
190 { "3Com Typhoon (3CR990-FX-97)",
191 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
192 { "3Com Typhoon (3CR990-FX-95 Server)",
193 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
194 { "3Com Typhoon (3CR990-FX-97 Server)",
195 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
196 { "3Com Typhoon2 (3C990B-FX-97)",
197 TYPHOON_CRYPTO_VARIABLE | TYPHOON_FIBER},
198};
199
200/* Notes on the new subsystem numbering scheme:
201 * bits 0-1 indicate crypto capabilities: (0) variable, (1) DES, or (2) 3DES
202 * bit 4 indicates if this card has secured firmware (we don't support it)
203 * bit 8 indicates if this is a (0) copper or (1) fiber card
204 * bits 12-16 indicate card type: (0) client and (1) server
205 */
206static const struct pci_device_id typhoon_pci_tbl[] = {
207 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,TYPHOON_TX },
209 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_95,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX95 },
211 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_97,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX97 },
213 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
214 PCI_ANY_ID, 0x1000, 0, 0, TYPHOON_TXM },
215 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
216 PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FXM },
217 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
218 PCI_ANY_ID, 0x2000, 0, 0, TYPHOON_BSVR },
219 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
220 PCI_ANY_ID, 0x1101, 0, 0, TYPHOON_FX95 },
221 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
222 PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FX97 },
223 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
224 PCI_ANY_ID, 0x2101, 0, 0, TYPHOON_FX95SVR },
225 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
226 PCI_ANY_ID, 0x2102, 0, 0, TYPHOON_FX97SVR },
227 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR95,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR95 },
229 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR97,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR97 },
231 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR },
233 { 0, }
234};
235MODULE_DEVICE_TABLE(pci, typhoon_pci_tbl);
236
237/* Define the shared memory area
238 * Align everything the 3XP will normally be using.
239 * We'll need to move/align txHi if we start using that ring.
240 */
241#define __3xp_aligned ____cacheline_aligned
242struct typhoon_shared {
243 struct typhoon_interface iface;
244 struct typhoon_indexes indexes __3xp_aligned;
245 struct tx_desc txLo[TXLO_ENTRIES] __3xp_aligned;
246 struct rx_desc rxLo[RX_ENTRIES] __3xp_aligned;
247 struct rx_desc rxHi[RX_ENTRIES] __3xp_aligned;
248 struct cmd_desc cmd[COMMAND_ENTRIES] __3xp_aligned;
249 struct resp_desc resp[RESPONSE_ENTRIES] __3xp_aligned;
250 struct rx_free rxBuff[RXFREE_ENTRIES] __3xp_aligned;
251 u32 zeroWord;
252 struct tx_desc txHi[TXHI_ENTRIES];
253} __packed;
254
255struct rxbuff_ent {
256 struct sk_buff *skb;
257 dma_addr_t dma_addr;
258};
259
260struct typhoon {
261 /* Tx cache line section */
262 struct transmit_ring txLoRing ____cacheline_aligned;
263 struct pci_dev * tx_pdev;
264 void __iomem *tx_ioaddr;
265 u32 txlo_dma_addr;
266
267 /* Irq/Rx cache line section */
268 void __iomem *ioaddr ____cacheline_aligned;
269 struct typhoon_indexes *indexes;
270 u8 awaiting_resp;
271 u8 duplex;
272 u8 speed;
273 u8 card_state;
274 struct basic_ring rxLoRing;
275 struct pci_dev * pdev;
276 struct net_device * dev;
277 struct napi_struct napi;
278 struct basic_ring rxHiRing;
279 struct basic_ring rxBuffRing;
280 struct rxbuff_ent rxbuffers[RXENT_ENTRIES];
281
282 /* general section */
283 spinlock_t command_lock ____cacheline_aligned;
284 struct basic_ring cmdRing;
285 struct basic_ring respRing;
286 struct net_device_stats stats_saved;
287 struct typhoon_shared * shared;
288 dma_addr_t shared_dma;
289 __le16 xcvr_select;
290 __le16 wol_events;
291 __le32 offload;
292
293 /* unused stuff (future use) */
294 int capabilities;
295 struct transmit_ring txHiRing;
296};
297
298enum completion_wait_values {
299 NoWait = 0, WaitNoSleep, WaitSleep,
300};
301
302/* These are the values for the typhoon.card_state variable.
303 * These determine where the statistics will come from in get_stats().
304 * The sleep image does not support the statistics we need.
305 */
306enum state_values {
307 Sleeping = 0, Running,
308};
309
310/* PCI writes are not guaranteed to be posted in order, but outstanding writes
311 * cannot pass a read, so this forces current writes to post.
312 */
313#define typhoon_post_pci_writes(x) \
314 do { if(likely(use_mmio)) ioread32(x+TYPHOON_REG_HEARTBEAT); } while(0)
315
316/* We'll wait up to six seconds for a reset, and half a second normally.
317 */
318#define TYPHOON_UDELAY 50
319#define TYPHOON_RESET_TIMEOUT_SLEEP (6 * HZ)
320#define TYPHOON_RESET_TIMEOUT_NOSLEEP ((6 * 1000000) / TYPHOON_UDELAY)
321#define TYPHOON_WAIT_TIMEOUT ((1000000 / 2) / TYPHOON_UDELAY)
322
323#if defined(NETIF_F_TSO)
324#define skb_tso_size(x) (skb_shinfo(x)->gso_size)
325#define TSO_NUM_DESCRIPTORS 2
326#define TSO_OFFLOAD_ON TYPHOON_OFFLOAD_TCP_SEGMENT
327#else
328#define NETIF_F_TSO 0
329#define skb_tso_size(x) 0
330#define TSO_NUM_DESCRIPTORS 0
331#define TSO_OFFLOAD_ON 0
332#endif
333
334static inline void
335typhoon_inc_index(u32 *index, const int count, const int num_entries)
336{
337 /* Increment a ring index -- we can use this for all rings execept
338 * the Rx rings, as they use different size descriptors
339 * otherwise, everything is the same size as a cmd_desc
340 */
341 *index += count * sizeof(struct cmd_desc);
342 *index %= num_entries * sizeof(struct cmd_desc);
343}
344
345static inline void
346typhoon_inc_cmd_index(u32 *index, const int count)
347{
348 typhoon_inc_index(index, count, COMMAND_ENTRIES);
349}
350
351static inline void
352typhoon_inc_resp_index(u32 *index, const int count)
353{
354 typhoon_inc_index(index, count, RESPONSE_ENTRIES);
355}
356
357static inline void
358typhoon_inc_rxfree_index(u32 *index, const int count)
359{
360 typhoon_inc_index(index, count, RXFREE_ENTRIES);
361}
362
363static inline void
364typhoon_inc_tx_index(u32 *index, const int count)
365{
366 /* if we start using the Hi Tx ring, this needs updating */
367 typhoon_inc_index(index, count, TXLO_ENTRIES);
368}
369
370static inline void
371typhoon_inc_rx_index(u32 *index, const int count)
372{
373 /* sizeof(struct rx_desc) != sizeof(struct cmd_desc) */
374 *index += count * sizeof(struct rx_desc);
375 *index %= RX_ENTRIES * sizeof(struct rx_desc);
376}
377
378static int
379typhoon_reset(void __iomem *ioaddr, int wait_type)
380{
381 int i, err = 0;
382 int timeout;
383
384 if(wait_type == WaitNoSleep)
385 timeout = TYPHOON_RESET_TIMEOUT_NOSLEEP;
386 else
387 timeout = TYPHOON_RESET_TIMEOUT_SLEEP;
388
389 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
390 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
391
392 iowrite32(TYPHOON_RESET_ALL, ioaddr + TYPHOON_REG_SOFT_RESET);
393 typhoon_post_pci_writes(ioaddr);
394 udelay(1);
395 iowrite32(TYPHOON_RESET_NONE, ioaddr + TYPHOON_REG_SOFT_RESET);
396
397 if(wait_type != NoWait) {
398 for(i = 0; i < timeout; i++) {
399 if(ioread32(ioaddr + TYPHOON_REG_STATUS) ==
400 TYPHOON_STATUS_WAITING_FOR_HOST)
401 goto out;
402
403 if(wait_type == WaitSleep)
404 schedule_timeout_uninterruptible(1);
405 else
406 udelay(TYPHOON_UDELAY);
407 }
408
409 err = -ETIMEDOUT;
410 }
411
412out:
413 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
414 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
415
416 /* The 3XP seems to need a little extra time to complete the load
417 * of the sleep image before we can reliably boot it. Failure to
418 * do this occasionally results in a hung adapter after boot in
419 * typhoon_init_one() while trying to read the MAC address or
420 * putting the card to sleep. 3Com's driver waits 5ms, but
421 * that seems to be overkill. However, if we can sleep, we might
422 * as well give it that much time. Otherwise, we'll give it 500us,
423 * which should be enough (I've see it work well at 100us, but still
424 * saw occasional problems.)
425 */
426 if(wait_type == WaitSleep)
427 msleep(5);
428 else
429 udelay(500);
430 return err;
431}
432
433static int
434typhoon_wait_status(void __iomem *ioaddr, u32 wait_value)
435{
436 int i, err = 0;
437
438 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
439 if(ioread32(ioaddr + TYPHOON_REG_STATUS) == wait_value)
440 goto out;
441 udelay(TYPHOON_UDELAY);
442 }
443
444 err = -ETIMEDOUT;
445
446out:
447 return err;
448}
449
450static inline void
451typhoon_media_status(struct net_device *dev, struct resp_desc *resp)
452{
453 if(resp->parm1 & TYPHOON_MEDIA_STAT_NO_LINK)
454 netif_carrier_off(dev);
455 else
456 netif_carrier_on(dev);
457}
458
459static inline void
460typhoon_hello(struct typhoon *tp)
461{
462 struct basic_ring *ring = &tp->cmdRing;
463 struct cmd_desc *cmd;
464
465 /* We only get a hello request if we've not sent anything to the
466 * card in a long while. If the lock is held, then we're in the
467 * process of issuing a command, so we don't need to respond.
468 */
469 if(spin_trylock(&tp->command_lock)) {
470 cmd = (struct cmd_desc *)(ring->ringBase + ring->lastWrite);
471 typhoon_inc_cmd_index(&ring->lastWrite, 1);
472
473 INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP);
474 wmb();
475 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
476 spin_unlock(&tp->command_lock);
477 }
478}
479
480static int
481typhoon_process_response(struct typhoon *tp, int resp_size,
482 struct resp_desc *resp_save)
483{
484 struct typhoon_indexes *indexes = tp->indexes;
485 struct resp_desc *resp;
486 u8 *base = tp->respRing.ringBase;
487 int count, len, wrap_len;
488 u32 cleared;
489 u32 ready;
490
491 cleared = le32_to_cpu(indexes->respCleared);
492 ready = le32_to_cpu(indexes->respReady);
493 while(cleared != ready) {
494 resp = (struct resp_desc *)(base + cleared);
495 count = resp->numDesc + 1;
496 if(resp_save && resp->seqNo) {
497 if(count > resp_size) {
498 resp_save->flags = TYPHOON_RESP_ERROR;
499 goto cleanup;
500 }
501
502 wrap_len = 0;
503 len = count * sizeof(*resp);
504 if(unlikely(cleared + len > RESPONSE_RING_SIZE)) {
505 wrap_len = cleared + len - RESPONSE_RING_SIZE;
506 len = RESPONSE_RING_SIZE - cleared;
507 }
508
509 memcpy(resp_save, resp, len);
510 if(unlikely(wrap_len)) {
511 resp_save += len / sizeof(*resp);
512 memcpy(resp_save, base, wrap_len);
513 }
514
515 resp_save = NULL;
516 } else if(resp->cmd == TYPHOON_CMD_READ_MEDIA_STATUS) {
517 typhoon_media_status(tp->dev, resp);
518 } else if(resp->cmd == TYPHOON_CMD_HELLO_RESP) {
519 typhoon_hello(tp);
520 } else {
521 netdev_err(tp->dev,
522 "dumping unexpected response 0x%04x:%d:0x%02x:0x%04x:%08x:%08x\n",
523 le16_to_cpu(resp->cmd),
524 resp->numDesc, resp->flags,
525 le16_to_cpu(resp->parm1),
526 le32_to_cpu(resp->parm2),
527 le32_to_cpu(resp->parm3));
528 }
529
530cleanup:
531 typhoon_inc_resp_index(&cleared, count);
532 }
533
534 indexes->respCleared = cpu_to_le32(cleared);
535 wmb();
536 return resp_save == NULL;
537}
538
539static inline int
540typhoon_num_free(int lastWrite, int lastRead, int ringSize)
541{
542 /* this works for all descriptors but rx_desc, as they are a
543 * different size than the cmd_desc -- everyone else is the same
544 */
545 lastWrite /= sizeof(struct cmd_desc);
546 lastRead /= sizeof(struct cmd_desc);
547 return (ringSize + lastRead - lastWrite - 1) % ringSize;
548}
549
550static inline int
551typhoon_num_free_cmd(struct typhoon *tp)
552{
553 int lastWrite = tp->cmdRing.lastWrite;
554 int cmdCleared = le32_to_cpu(tp->indexes->cmdCleared);
555
556 return typhoon_num_free(lastWrite, cmdCleared, COMMAND_ENTRIES);
557}
558
559static inline int
560typhoon_num_free_resp(struct typhoon *tp)
561{
562 int respReady = le32_to_cpu(tp->indexes->respReady);
563 int respCleared = le32_to_cpu(tp->indexes->respCleared);
564
565 return typhoon_num_free(respReady, respCleared, RESPONSE_ENTRIES);
566}
567
568static inline int
569typhoon_num_free_tx(struct transmit_ring *ring)
570{
571 /* if we start using the Hi Tx ring, this needs updating */
572 return typhoon_num_free(ring->lastWrite, ring->lastRead, TXLO_ENTRIES);
573}
574
575static int
576typhoon_issue_command(struct typhoon *tp, int num_cmd, struct cmd_desc *cmd,
577 int num_resp, struct resp_desc *resp)
578{
579 struct typhoon_indexes *indexes = tp->indexes;
580 struct basic_ring *ring = &tp->cmdRing;
581 struct resp_desc local_resp;
582 int i, err = 0;
583 int got_resp;
584 int freeCmd, freeResp;
585 int len, wrap_len;
586
587 spin_lock(&tp->command_lock);
588
589 freeCmd = typhoon_num_free_cmd(tp);
590 freeResp = typhoon_num_free_resp(tp);
591
592 if(freeCmd < num_cmd || freeResp < num_resp) {
593 netdev_err(tp->dev, "no descs for cmd, had (needed) %d (%d) cmd, %d (%d) resp\n",
594 freeCmd, num_cmd, freeResp, num_resp);
595 err = -ENOMEM;
596 goto out;
597 }
598
599 if(cmd->flags & TYPHOON_CMD_RESPOND) {
600 /* If we're expecting a response, but the caller hasn't given
601 * us a place to put it, we'll provide one.
602 */
603 tp->awaiting_resp = 1;
604 if(resp == NULL) {
605 resp = &local_resp;
606 num_resp = 1;
607 }
608 }
609
610 wrap_len = 0;
611 len = num_cmd * sizeof(*cmd);
612 if(unlikely(ring->lastWrite + len > COMMAND_RING_SIZE)) {
613 wrap_len = ring->lastWrite + len - COMMAND_RING_SIZE;
614 len = COMMAND_RING_SIZE - ring->lastWrite;
615 }
616
617 memcpy(ring->ringBase + ring->lastWrite, cmd, len);
618 if(unlikely(wrap_len)) {
619 struct cmd_desc *wrap_ptr = cmd;
620 wrap_ptr += len / sizeof(*cmd);
621 memcpy(ring->ringBase, wrap_ptr, wrap_len);
622 }
623
624 typhoon_inc_cmd_index(&ring->lastWrite, num_cmd);
625
626 /* "I feel a presence... another warrior is on the mesa."
627 */
628 wmb();
629 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
630 typhoon_post_pci_writes(tp->ioaddr);
631
632 if((cmd->flags & TYPHOON_CMD_RESPOND) == 0)
633 goto out;
634
635 /* Ugh. We'll be here about 8ms, spinning our thumbs, unable to
636 * preempt or do anything other than take interrupts. So, don't
637 * wait for a response unless you have to.
638 *
639 * I've thought about trying to sleep here, but we're called
640 * from many contexts that don't allow that. Also, given the way
641 * 3Com has implemented irq coalescing, we would likely timeout --
642 * this has been observed in real life!
643 *
644 * The big killer is we have to wait to get stats from the card,
645 * though we could go to a periodic refresh of those if we don't
646 * mind them getting somewhat stale. The rest of the waiting
647 * commands occur during open/close/suspend/resume, so they aren't
648 * time critical. Creating SAs in the future will also have to
649 * wait here.
650 */
651 got_resp = 0;
652 for(i = 0; i < TYPHOON_WAIT_TIMEOUT && !got_resp; i++) {
653 if(indexes->respCleared != indexes->respReady)
654 got_resp = typhoon_process_response(tp, num_resp,
655 resp);
656 udelay(TYPHOON_UDELAY);
657 }
658
659 if(!got_resp) {
660 err = -ETIMEDOUT;
661 goto out;
662 }
663
664 /* Collect the error response even if we don't care about the
665 * rest of the response
666 */
667 if(resp->flags & TYPHOON_RESP_ERROR)
668 err = -EIO;
669
670out:
671 if(tp->awaiting_resp) {
672 tp->awaiting_resp = 0;
673 smp_wmb();
674
675 /* Ugh. If a response was added to the ring between
676 * the call to typhoon_process_response() and the clearing
677 * of tp->awaiting_resp, we could have missed the interrupt
678 * and it could hang in the ring an indeterminate amount of
679 * time. So, check for it, and interrupt ourselves if this
680 * is the case.
681 */
682 if(indexes->respCleared != indexes->respReady)
683 iowrite32(1, tp->ioaddr + TYPHOON_REG_SELF_INTERRUPT);
684 }
685
686 spin_unlock(&tp->command_lock);
687 return err;
688}
689
690static inline void
691typhoon_tso_fill(struct sk_buff *skb, struct transmit_ring *txRing,
692 u32 ring_dma)
693{
694 struct tcpopt_desc *tcpd;
695 u32 tcpd_offset = ring_dma;
696
697 tcpd = (struct tcpopt_desc *) (txRing->ringBase + txRing->lastWrite);
698 tcpd_offset += txRing->lastWrite;
699 tcpd_offset += offsetof(struct tcpopt_desc, bytesTx);
700 typhoon_inc_tx_index(&txRing->lastWrite, 1);
701
702 tcpd->flags = TYPHOON_OPT_DESC | TYPHOON_OPT_TCP_SEG;
703 tcpd->numDesc = 1;
704 tcpd->mss_flags = cpu_to_le16(skb_tso_size(skb));
705 tcpd->mss_flags |= TYPHOON_TSO_FIRST | TYPHOON_TSO_LAST;
706 tcpd->respAddrLo = cpu_to_le32(tcpd_offset);
707 tcpd->bytesTx = cpu_to_le32(skb->len);
708 tcpd->status = 0;
709}
710
711static netdev_tx_t
712typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
713{
714 struct typhoon *tp = netdev_priv(dev);
715 struct transmit_ring *txRing;
716 struct tx_desc *txd, *first_txd;
717 dma_addr_t skb_dma;
718 int numDesc;
719
720 /* we have two rings to choose from, but we only use txLo for now
721 * If we start using the Hi ring as well, we'll need to update
722 * typhoon_stop_runtime(), typhoon_interrupt(), typhoon_num_free_tx(),
723 * and TXHI_ENTRIES to match, as well as update the TSO code below
724 * to get the right DMA address
725 */
726 txRing = &tp->txLoRing;
727
728 /* We need one descriptor for each fragment of the sk_buff, plus the
729 * one for the ->data area of it.
730 *
731 * The docs say a maximum of 16 fragment descriptors per TCP option
732 * descriptor, then make a new packet descriptor and option descriptor
733 * for the next 16 fragments. The engineers say just an option
734 * descriptor is needed. I've tested up to 26 fragments with a single
735 * packet descriptor/option descriptor combo, so I use that for now.
736 *
737 * If problems develop with TSO, check this first.
738 */
739 numDesc = skb_shinfo(skb)->nr_frags + 1;
740 if (skb_is_gso(skb))
741 numDesc++;
742
743 /* When checking for free space in the ring, we need to also
744 * account for the initial Tx descriptor, and we always must leave
745 * at least one descriptor unused in the ring so that it doesn't
746 * wrap and look empty.
747 *
748 * The only time we should loop here is when we hit the race
749 * between marking the queue awake and updating the cleared index.
750 * Just loop and it will appear. This comes from the acenic driver.
751 */
752 while(unlikely(typhoon_num_free_tx(txRing) < (numDesc + 2)))
753 smp_rmb();
754
755 first_txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
756 typhoon_inc_tx_index(&txRing->lastWrite, 1);
757
758 first_txd->flags = TYPHOON_TX_DESC | TYPHOON_DESC_VALID;
759 first_txd->numDesc = 0;
760 first_txd->len = 0;
761 first_txd->tx_addr = (u64)((unsigned long) skb);
762 first_txd->processFlags = 0;
763
764 if(skb->ip_summed == CHECKSUM_PARTIAL) {
765 /* The 3XP will figure out if this is UDP/TCP */
766 first_txd->processFlags |= TYPHOON_TX_PF_TCP_CHKSUM;
767 first_txd->processFlags |= TYPHOON_TX_PF_UDP_CHKSUM;
768 first_txd->processFlags |= TYPHOON_TX_PF_IP_CHKSUM;
769 }
770
771 if (skb_vlan_tag_present(skb)) {
772 first_txd->processFlags |=
773 TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY;
774 first_txd->processFlags |=
775 cpu_to_le32(htons(skb_vlan_tag_get(skb)) <<
776 TYPHOON_TX_PF_VLAN_TAG_SHIFT);
777 }
778
779 if (skb_is_gso(skb)) {
780 first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
781 first_txd->numDesc++;
782
783 typhoon_tso_fill(skb, txRing, tp->txlo_dma_addr);
784 }
785
786 txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
787 typhoon_inc_tx_index(&txRing->lastWrite, 1);
788
789 /* No need to worry about padding packet -- the firmware pads
790 * it with zeros to ETH_ZLEN for us.
791 */
792 if(skb_shinfo(skb)->nr_frags == 0) {
793 skb_dma = pci_map_single(tp->tx_pdev, skb->data, skb->len,
794 PCI_DMA_TODEVICE);
795 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
796 txd->len = cpu_to_le16(skb->len);
797 txd->frag.addr = cpu_to_le32(skb_dma);
798 txd->frag.addrHi = 0;
799 first_txd->numDesc++;
800 } else {
801 int i, len;
802
803 len = skb_headlen(skb);
804 skb_dma = pci_map_single(tp->tx_pdev, skb->data, len,
805 PCI_DMA_TODEVICE);
806 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
807 txd->len = cpu_to_le16(len);
808 txd->frag.addr = cpu_to_le32(skb_dma);
809 txd->frag.addrHi = 0;
810 first_txd->numDesc++;
811
812 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
813 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
814 void *frag_addr;
815
816 txd = (struct tx_desc *) (txRing->ringBase +
817 txRing->lastWrite);
818 typhoon_inc_tx_index(&txRing->lastWrite, 1);
819
820 len = skb_frag_size(frag);
821 frag_addr = skb_frag_address(frag);
822 skb_dma = pci_map_single(tp->tx_pdev, frag_addr, len,
823 PCI_DMA_TODEVICE);
824 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
825 txd->len = cpu_to_le16(len);
826 txd->frag.addr = cpu_to_le32(skb_dma);
827 txd->frag.addrHi = 0;
828 first_txd->numDesc++;
829 }
830 }
831
832 /* Kick the 3XP
833 */
834 wmb();
835 iowrite32(txRing->lastWrite, tp->tx_ioaddr + txRing->writeRegister);
836
837 /* If we don't have room to put the worst case packet on the
838 * queue, then we must stop the queue. We need 2 extra
839 * descriptors -- one to prevent ring wrap, and one for the
840 * Tx header.
841 */
842 numDesc = MAX_SKB_FRAGS + TSO_NUM_DESCRIPTORS + 1;
843
844 if(typhoon_num_free_tx(txRing) < (numDesc + 2)) {
845 netif_stop_queue(dev);
846
847 /* A Tx complete IRQ could have gotten between, making
848 * the ring free again. Only need to recheck here, since
849 * Tx is serialized.
850 */
851 if(typhoon_num_free_tx(txRing) >= (numDesc + 2))
852 netif_wake_queue(dev);
853 }
854
855 return NETDEV_TX_OK;
856}
857
858static void
859typhoon_set_rx_mode(struct net_device *dev)
860{
861 struct typhoon *tp = netdev_priv(dev);
862 struct cmd_desc xp_cmd;
863 u32 mc_filter[2];
864 __le16 filter;
865
866 filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
867 if(dev->flags & IFF_PROMISC) {
868 filter |= TYPHOON_RX_FILTER_PROMISCOUS;
869 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
870 (dev->flags & IFF_ALLMULTI)) {
871 /* Too many to match, or accept all multicasts. */
872 filter |= TYPHOON_RX_FILTER_ALL_MCAST;
873 } else if (!netdev_mc_empty(dev)) {
874 struct netdev_hw_addr *ha;
875
876 memset(mc_filter, 0, sizeof(mc_filter));
877 netdev_for_each_mc_addr(ha, dev) {
878 int bit = ether_crc(ETH_ALEN, ha->addr) & 0x3f;
879 mc_filter[bit >> 5] |= 1 << (bit & 0x1f);
880 }
881
882 INIT_COMMAND_NO_RESPONSE(&xp_cmd,
883 TYPHOON_CMD_SET_MULTICAST_HASH);
884 xp_cmd.parm1 = TYPHOON_MCAST_HASH_SET;
885 xp_cmd.parm2 = cpu_to_le32(mc_filter[0]);
886 xp_cmd.parm3 = cpu_to_le32(mc_filter[1]);
887 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
888
889 filter |= TYPHOON_RX_FILTER_MCAST_HASH;
890 }
891
892 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
893 xp_cmd.parm1 = filter;
894 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
895}
896
897static int
898typhoon_do_get_stats(struct typhoon *tp)
899{
900 struct net_device_stats *stats = &tp->dev->stats;
901 struct net_device_stats *saved = &tp->stats_saved;
902 struct cmd_desc xp_cmd;
903 struct resp_desc xp_resp[7];
904 struct stats_resp *s = (struct stats_resp *) xp_resp;
905 int err;
906
907 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_STATS);
908 err = typhoon_issue_command(tp, 1, &xp_cmd, 7, xp_resp);
909 if(err < 0)
910 return err;
911
912 /* 3Com's Linux driver uses txMultipleCollisions as it's
913 * collisions value, but there is some other collision info as well...
914 *
915 * The extra status reported would be a good candidate for
916 * ethtool_ops->get_{strings,stats}()
917 */
918 stats->tx_packets = le32_to_cpu(s->txPackets) +
919 saved->tx_packets;
920 stats->tx_bytes = le64_to_cpu(s->txBytes) +
921 saved->tx_bytes;
922 stats->tx_errors = le32_to_cpu(s->txCarrierLost) +
923 saved->tx_errors;
924 stats->tx_carrier_errors = le32_to_cpu(s->txCarrierLost) +
925 saved->tx_carrier_errors;
926 stats->collisions = le32_to_cpu(s->txMultipleCollisions) +
927 saved->collisions;
928 stats->rx_packets = le32_to_cpu(s->rxPacketsGood) +
929 saved->rx_packets;
930 stats->rx_bytes = le64_to_cpu(s->rxBytesGood) +
931 saved->rx_bytes;
932 stats->rx_fifo_errors = le32_to_cpu(s->rxFifoOverruns) +
933 saved->rx_fifo_errors;
934 stats->rx_errors = le32_to_cpu(s->rxFifoOverruns) +
935 le32_to_cpu(s->BadSSD) + le32_to_cpu(s->rxCrcErrors) +
936 saved->rx_errors;
937 stats->rx_crc_errors = le32_to_cpu(s->rxCrcErrors) +
938 saved->rx_crc_errors;
939 stats->rx_length_errors = le32_to_cpu(s->rxOversized) +
940 saved->rx_length_errors;
941 tp->speed = (s->linkStatus & TYPHOON_LINK_100MBPS) ?
942 SPEED_100 : SPEED_10;
943 tp->duplex = (s->linkStatus & TYPHOON_LINK_FULL_DUPLEX) ?
944 DUPLEX_FULL : DUPLEX_HALF;
945
946 return 0;
947}
948
949static struct net_device_stats *
950typhoon_get_stats(struct net_device *dev)
951{
952 struct typhoon *tp = netdev_priv(dev);
953 struct net_device_stats *stats = &tp->dev->stats;
954 struct net_device_stats *saved = &tp->stats_saved;
955
956 smp_rmb();
957 if(tp->card_state == Sleeping)
958 return saved;
959
960 if(typhoon_do_get_stats(tp) < 0) {
961 netdev_err(dev, "error getting stats\n");
962 return saved;
963 }
964
965 return stats;
966}
967
968static void
969typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
970{
971 struct typhoon *tp = netdev_priv(dev);
972 struct pci_dev *pci_dev = tp->pdev;
973 struct cmd_desc xp_cmd;
974 struct resp_desc xp_resp[3];
975
976 smp_rmb();
977 if(tp->card_state == Sleeping) {
978 strlcpy(info->fw_version, "Sleep image",
979 sizeof(info->fw_version));
980 } else {
981 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
982 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
983 strlcpy(info->fw_version, "Unknown runtime",
984 sizeof(info->fw_version));
985 } else {
986 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
987 snprintf(info->fw_version, sizeof(info->fw_version),
988 "%02x.%03x.%03x", sleep_ver >> 24,
989 (sleep_ver >> 12) & 0xfff, sleep_ver & 0xfff);
990 }
991 }
992
993 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
994 strlcpy(info->bus_info, pci_name(pci_dev), sizeof(info->bus_info));
995}
996
997static int
998typhoon_get_link_ksettings(struct net_device *dev,
999 struct ethtool_link_ksettings *cmd)
1000{
1001 struct typhoon *tp = netdev_priv(dev);
1002 u32 supported, advertising = 0;
1003
1004 supported = SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1005 SUPPORTED_Autoneg;
1006
1007 switch (tp->xcvr_select) {
1008 case TYPHOON_XCVR_10HALF:
1009 advertising = ADVERTISED_10baseT_Half;
1010 break;
1011 case TYPHOON_XCVR_10FULL:
1012 advertising = ADVERTISED_10baseT_Full;
1013 break;
1014 case TYPHOON_XCVR_100HALF:
1015 advertising = ADVERTISED_100baseT_Half;
1016 break;
1017 case TYPHOON_XCVR_100FULL:
1018 advertising = ADVERTISED_100baseT_Full;
1019 break;
1020 case TYPHOON_XCVR_AUTONEG:
1021 advertising = ADVERTISED_10baseT_Half |
1022 ADVERTISED_10baseT_Full |
1023 ADVERTISED_100baseT_Half |
1024 ADVERTISED_100baseT_Full |
1025 ADVERTISED_Autoneg;
1026 break;
1027 }
1028
1029 if(tp->capabilities & TYPHOON_FIBER) {
1030 supported |= SUPPORTED_FIBRE;
1031 advertising |= ADVERTISED_FIBRE;
1032 cmd->base.port = PORT_FIBRE;
1033 } else {
1034 supported |= SUPPORTED_10baseT_Half |
1035 SUPPORTED_10baseT_Full |
1036 SUPPORTED_TP;
1037 advertising |= ADVERTISED_TP;
1038 cmd->base.port = PORT_TP;
1039 }
1040
1041 /* need to get stats to make these link speed/duplex valid */
1042 typhoon_do_get_stats(tp);
1043 cmd->base.speed = tp->speed;
1044 cmd->base.duplex = tp->duplex;
1045 cmd->base.phy_address = 0;
1046 if(tp->xcvr_select == TYPHOON_XCVR_AUTONEG)
1047 cmd->base.autoneg = AUTONEG_ENABLE;
1048 else
1049 cmd->base.autoneg = AUTONEG_DISABLE;
1050
1051 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1052 supported);
1053 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1054 advertising);
1055
1056 return 0;
1057}
1058
1059static int
1060typhoon_set_link_ksettings(struct net_device *dev,
1061 const struct ethtool_link_ksettings *cmd)
1062{
1063 struct typhoon *tp = netdev_priv(dev);
1064 u32 speed = cmd->base.speed;
1065 struct cmd_desc xp_cmd;
1066 __le16 xcvr;
1067 int err;
1068
1069 err = -EINVAL;
1070 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1071 xcvr = TYPHOON_XCVR_AUTONEG;
1072 } else {
1073 if (cmd->base.duplex == DUPLEX_HALF) {
1074 if (speed == SPEED_10)
1075 xcvr = TYPHOON_XCVR_10HALF;
1076 else if (speed == SPEED_100)
1077 xcvr = TYPHOON_XCVR_100HALF;
1078 else
1079 goto out;
1080 } else if (cmd->base.duplex == DUPLEX_FULL) {
1081 if (speed == SPEED_10)
1082 xcvr = TYPHOON_XCVR_10FULL;
1083 else if (speed == SPEED_100)
1084 xcvr = TYPHOON_XCVR_100FULL;
1085 else
1086 goto out;
1087 } else
1088 goto out;
1089 }
1090
1091 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1092 xp_cmd.parm1 = xcvr;
1093 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1094 if(err < 0)
1095 goto out;
1096
1097 tp->xcvr_select = xcvr;
1098 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1099 tp->speed = 0xff; /* invalid */
1100 tp->duplex = 0xff; /* invalid */
1101 } else {
1102 tp->speed = speed;
1103 tp->duplex = cmd->base.duplex;
1104 }
1105
1106out:
1107 return err;
1108}
1109
1110static void
1111typhoon_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1112{
1113 struct typhoon *tp = netdev_priv(dev);
1114
1115 wol->supported = WAKE_PHY | WAKE_MAGIC;
1116 wol->wolopts = 0;
1117 if(tp->wol_events & TYPHOON_WAKE_LINK_EVENT)
1118 wol->wolopts |= WAKE_PHY;
1119 if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
1120 wol->wolopts |= WAKE_MAGIC;
1121 memset(&wol->sopass, 0, sizeof(wol->sopass));
1122}
1123
1124static int
1125typhoon_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1126{
1127 struct typhoon *tp = netdev_priv(dev);
1128
1129 if(wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
1130 return -EINVAL;
1131
1132 tp->wol_events = 0;
1133 if(wol->wolopts & WAKE_PHY)
1134 tp->wol_events |= TYPHOON_WAKE_LINK_EVENT;
1135 if(wol->wolopts & WAKE_MAGIC)
1136 tp->wol_events |= TYPHOON_WAKE_MAGIC_PKT;
1137
1138 return 0;
1139}
1140
1141static void
1142typhoon_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
1143{
1144 ering->rx_max_pending = RXENT_ENTRIES;
1145 ering->tx_max_pending = TXLO_ENTRIES - 1;
1146
1147 ering->rx_pending = RXENT_ENTRIES;
1148 ering->tx_pending = TXLO_ENTRIES - 1;
1149}
1150
1151static const struct ethtool_ops typhoon_ethtool_ops = {
1152 .get_drvinfo = typhoon_get_drvinfo,
1153 .get_wol = typhoon_get_wol,
1154 .set_wol = typhoon_set_wol,
1155 .get_link = ethtool_op_get_link,
1156 .get_ringparam = typhoon_get_ringparam,
1157 .get_link_ksettings = typhoon_get_link_ksettings,
1158 .set_link_ksettings = typhoon_set_link_ksettings,
1159};
1160
1161static int
1162typhoon_wait_interrupt(void __iomem *ioaddr)
1163{
1164 int i, err = 0;
1165
1166 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1167 if(ioread32(ioaddr + TYPHOON_REG_INTR_STATUS) &
1168 TYPHOON_INTR_BOOTCMD)
1169 goto out;
1170 udelay(TYPHOON_UDELAY);
1171 }
1172
1173 err = -ETIMEDOUT;
1174
1175out:
1176 iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1177 return err;
1178}
1179
1180#define shared_offset(x) offsetof(struct typhoon_shared, x)
1181
1182static void
1183typhoon_init_interface(struct typhoon *tp)
1184{
1185 struct typhoon_interface *iface = &tp->shared->iface;
1186 dma_addr_t shared_dma;
1187
1188 memset(tp->shared, 0, sizeof(struct typhoon_shared));
1189
1190 /* The *Hi members of iface are all init'd to zero by the memset().
1191 */
1192 shared_dma = tp->shared_dma + shared_offset(indexes);
1193 iface->ringIndex = cpu_to_le32(shared_dma);
1194
1195 shared_dma = tp->shared_dma + shared_offset(txLo);
1196 iface->txLoAddr = cpu_to_le32(shared_dma);
1197 iface->txLoSize = cpu_to_le32(TXLO_ENTRIES * sizeof(struct tx_desc));
1198
1199 shared_dma = tp->shared_dma + shared_offset(txHi);
1200 iface->txHiAddr = cpu_to_le32(shared_dma);
1201 iface->txHiSize = cpu_to_le32(TXHI_ENTRIES * sizeof(struct tx_desc));
1202
1203 shared_dma = tp->shared_dma + shared_offset(rxBuff);
1204 iface->rxBuffAddr = cpu_to_le32(shared_dma);
1205 iface->rxBuffSize = cpu_to_le32(RXFREE_ENTRIES *
1206 sizeof(struct rx_free));
1207
1208 shared_dma = tp->shared_dma + shared_offset(rxLo);
1209 iface->rxLoAddr = cpu_to_le32(shared_dma);
1210 iface->rxLoSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1211
1212 shared_dma = tp->shared_dma + shared_offset(rxHi);
1213 iface->rxHiAddr = cpu_to_le32(shared_dma);
1214 iface->rxHiSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1215
1216 shared_dma = tp->shared_dma + shared_offset(cmd);
1217 iface->cmdAddr = cpu_to_le32(shared_dma);
1218 iface->cmdSize = cpu_to_le32(COMMAND_RING_SIZE);
1219
1220 shared_dma = tp->shared_dma + shared_offset(resp);
1221 iface->respAddr = cpu_to_le32(shared_dma);
1222 iface->respSize = cpu_to_le32(RESPONSE_RING_SIZE);
1223
1224 shared_dma = tp->shared_dma + shared_offset(zeroWord);
1225 iface->zeroAddr = cpu_to_le32(shared_dma);
1226
1227 tp->indexes = &tp->shared->indexes;
1228 tp->txLoRing.ringBase = (u8 *) tp->shared->txLo;
1229 tp->txHiRing.ringBase = (u8 *) tp->shared->txHi;
1230 tp->rxLoRing.ringBase = (u8 *) tp->shared->rxLo;
1231 tp->rxHiRing.ringBase = (u8 *) tp->shared->rxHi;
1232 tp->rxBuffRing.ringBase = (u8 *) tp->shared->rxBuff;
1233 tp->cmdRing.ringBase = (u8 *) tp->shared->cmd;
1234 tp->respRing.ringBase = (u8 *) tp->shared->resp;
1235
1236 tp->txLoRing.writeRegister = TYPHOON_REG_TX_LO_READY;
1237 tp->txHiRing.writeRegister = TYPHOON_REG_TX_HI_READY;
1238
1239 tp->txlo_dma_addr = le32_to_cpu(iface->txLoAddr);
1240 tp->card_state = Sleeping;
1241
1242 tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM;
1243 tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON;
1244 tp->offload |= TYPHOON_OFFLOAD_VLAN;
1245
1246 spin_lock_init(&tp->command_lock);
1247
1248 /* Force the writes to the shared memory area out before continuing. */
1249 wmb();
1250}
1251
1252static void
1253typhoon_init_rings(struct typhoon *tp)
1254{
1255 memset(tp->indexes, 0, sizeof(struct typhoon_indexes));
1256
1257 tp->txLoRing.lastWrite = 0;
1258 tp->txHiRing.lastWrite = 0;
1259 tp->rxLoRing.lastWrite = 0;
1260 tp->rxHiRing.lastWrite = 0;
1261 tp->rxBuffRing.lastWrite = 0;
1262 tp->cmdRing.lastWrite = 0;
1263 tp->respRing.lastWrite = 0;
1264
1265 tp->txLoRing.lastRead = 0;
1266 tp->txHiRing.lastRead = 0;
1267}
1268
1269static const struct firmware *typhoon_fw;
1270
1271static int
1272typhoon_request_firmware(struct typhoon *tp)
1273{
1274 const struct typhoon_file_header *fHdr;
1275 const struct typhoon_section_header *sHdr;
1276 const u8 *image_data;
1277 u32 numSections;
1278 u32 section_len;
1279 u32 remaining;
1280 int err;
1281
1282 if (typhoon_fw)
1283 return 0;
1284
1285 err = request_firmware(&typhoon_fw, FIRMWARE_NAME, &tp->pdev->dev);
1286 if (err) {
1287 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
1288 FIRMWARE_NAME);
1289 return err;
1290 }
1291
1292 image_data = typhoon_fw->data;
1293 remaining = typhoon_fw->size;
1294 if (remaining < sizeof(struct typhoon_file_header))
1295 goto invalid_fw;
1296
1297 fHdr = (struct typhoon_file_header *) image_data;
1298 if (memcmp(fHdr->tag, "TYPHOON", 8))
1299 goto invalid_fw;
1300
1301 numSections = le32_to_cpu(fHdr->numSections);
1302 image_data += sizeof(struct typhoon_file_header);
1303 remaining -= sizeof(struct typhoon_file_header);
1304
1305 while (numSections--) {
1306 if (remaining < sizeof(struct typhoon_section_header))
1307 goto invalid_fw;
1308
1309 sHdr = (struct typhoon_section_header *) image_data;
1310 image_data += sizeof(struct typhoon_section_header);
1311 section_len = le32_to_cpu(sHdr->len);
1312
1313 if (remaining < section_len)
1314 goto invalid_fw;
1315
1316 image_data += section_len;
1317 remaining -= section_len;
1318 }
1319
1320 return 0;
1321
1322invalid_fw:
1323 netdev_err(tp->dev, "Invalid firmware image\n");
1324 release_firmware(typhoon_fw);
1325 typhoon_fw = NULL;
1326 return -EINVAL;
1327}
1328
1329static int
1330typhoon_download_firmware(struct typhoon *tp)
1331{
1332 void __iomem *ioaddr = tp->ioaddr;
1333 struct pci_dev *pdev = tp->pdev;
1334 const struct typhoon_file_header *fHdr;
1335 const struct typhoon_section_header *sHdr;
1336 const u8 *image_data;
1337 void *dpage;
1338 dma_addr_t dpage_dma;
1339 __sum16 csum;
1340 u32 irqEnabled;
1341 u32 irqMasked;
1342 u32 numSections;
1343 u32 section_len;
1344 u32 len;
1345 u32 load_addr;
1346 u32 hmac;
1347 int i;
1348 int err;
1349
1350 image_data = typhoon_fw->data;
1351 fHdr = (struct typhoon_file_header *) image_data;
1352
1353 /* Cannot just map the firmware image using pci_map_single() as
1354 * the firmware is vmalloc()'d and may not be physically contiguous,
1355 * so we allocate some consistent memory to copy the sections into.
1356 */
1357 err = -ENOMEM;
1358 dpage = pci_alloc_consistent(pdev, PAGE_SIZE, &dpage_dma);
1359 if(!dpage) {
1360 netdev_err(tp->dev, "no DMA mem for firmware\n");
1361 goto err_out;
1362 }
1363
1364 irqEnabled = ioread32(ioaddr + TYPHOON_REG_INTR_ENABLE);
1365 iowrite32(irqEnabled | TYPHOON_INTR_BOOTCMD,
1366 ioaddr + TYPHOON_REG_INTR_ENABLE);
1367 irqMasked = ioread32(ioaddr + TYPHOON_REG_INTR_MASK);
1368 iowrite32(irqMasked | TYPHOON_INTR_BOOTCMD,
1369 ioaddr + TYPHOON_REG_INTR_MASK);
1370
1371 err = -ETIMEDOUT;
1372 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
1373 netdev_err(tp->dev, "card ready timeout\n");
1374 goto err_out_irq;
1375 }
1376
1377 numSections = le32_to_cpu(fHdr->numSections);
1378 load_addr = le32_to_cpu(fHdr->startAddr);
1379
1380 iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1381 iowrite32(load_addr, ioaddr + TYPHOON_REG_DOWNLOAD_BOOT_ADDR);
1382 hmac = le32_to_cpu(fHdr->hmacDigest[0]);
1383 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_0);
1384 hmac = le32_to_cpu(fHdr->hmacDigest[1]);
1385 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_1);
1386 hmac = le32_to_cpu(fHdr->hmacDigest[2]);
1387 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_2);
1388 hmac = le32_to_cpu(fHdr->hmacDigest[3]);
1389 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_3);
1390 hmac = le32_to_cpu(fHdr->hmacDigest[4]);
1391 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_4);
1392 typhoon_post_pci_writes(ioaddr);
1393 iowrite32(TYPHOON_BOOTCMD_RUNTIME_IMAGE, ioaddr + TYPHOON_REG_COMMAND);
1394
1395 image_data += sizeof(struct typhoon_file_header);
1396
1397 /* The ioread32() in typhoon_wait_interrupt() will force the
1398 * last write to the command register to post, so
1399 * we don't need a typhoon_post_pci_writes() after it.
1400 */
1401 for(i = 0; i < numSections; i++) {
1402 sHdr = (struct typhoon_section_header *) image_data;
1403 image_data += sizeof(struct typhoon_section_header);
1404 load_addr = le32_to_cpu(sHdr->startAddr);
1405 section_len = le32_to_cpu(sHdr->len);
1406
1407 while(section_len) {
1408 len = min_t(u32, section_len, PAGE_SIZE);
1409
1410 if(typhoon_wait_interrupt(ioaddr) < 0 ||
1411 ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1412 TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1413 netdev_err(tp->dev, "segment ready timeout\n");
1414 goto err_out_irq;
1415 }
1416
1417 /* Do an pseudo IPv4 checksum on the data -- first
1418 * need to convert each u16 to cpu order before
1419 * summing. Fortunately, due to the properties of
1420 * the checksum, we can do this once, at the end.
1421 */
1422 csum = csum_fold(csum_partial_copy_nocheck(image_data,
1423 dpage, len,
1424 0));
1425
1426 iowrite32(len, ioaddr + TYPHOON_REG_BOOT_LENGTH);
1427 iowrite32(le16_to_cpu((__force __le16)csum),
1428 ioaddr + TYPHOON_REG_BOOT_CHECKSUM);
1429 iowrite32(load_addr,
1430 ioaddr + TYPHOON_REG_BOOT_DEST_ADDR);
1431 iowrite32(0, ioaddr + TYPHOON_REG_BOOT_DATA_HI);
1432 iowrite32(dpage_dma, ioaddr + TYPHOON_REG_BOOT_DATA_LO);
1433 typhoon_post_pci_writes(ioaddr);
1434 iowrite32(TYPHOON_BOOTCMD_SEG_AVAILABLE,
1435 ioaddr + TYPHOON_REG_COMMAND);
1436
1437 image_data += len;
1438 load_addr += len;
1439 section_len -= len;
1440 }
1441 }
1442
1443 if(typhoon_wait_interrupt(ioaddr) < 0 ||
1444 ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1445 TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1446 netdev_err(tp->dev, "final segment ready timeout\n");
1447 goto err_out_irq;
1448 }
1449
1450 iowrite32(TYPHOON_BOOTCMD_DNLD_COMPLETE, ioaddr + TYPHOON_REG_COMMAND);
1451
1452 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1453 netdev_err(tp->dev, "boot ready timeout, status 0x%0x\n",
1454 ioread32(ioaddr + TYPHOON_REG_STATUS));
1455 goto err_out_irq;
1456 }
1457
1458 err = 0;
1459
1460err_out_irq:
1461 iowrite32(irqMasked, ioaddr + TYPHOON_REG_INTR_MASK);
1462 iowrite32(irqEnabled, ioaddr + TYPHOON_REG_INTR_ENABLE);
1463
1464 pci_free_consistent(pdev, PAGE_SIZE, dpage, dpage_dma);
1465
1466err_out:
1467 return err;
1468}
1469
1470static int
1471typhoon_boot_3XP(struct typhoon *tp, u32 initial_status)
1472{
1473 void __iomem *ioaddr = tp->ioaddr;
1474
1475 if(typhoon_wait_status(ioaddr, initial_status) < 0) {
1476 netdev_err(tp->dev, "boot ready timeout\n");
1477 goto out_timeout;
1478 }
1479
1480 iowrite32(0, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_HI);
1481 iowrite32(tp->shared_dma, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_LO);
1482 typhoon_post_pci_writes(ioaddr);
1483 iowrite32(TYPHOON_BOOTCMD_REG_BOOT_RECORD,
1484 ioaddr + TYPHOON_REG_COMMAND);
1485
1486 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_RUNNING) < 0) {
1487 netdev_err(tp->dev, "boot finish timeout (status 0x%x)\n",
1488 ioread32(ioaddr + TYPHOON_REG_STATUS));
1489 goto out_timeout;
1490 }
1491
1492 /* Clear the Transmit and Command ready registers
1493 */
1494 iowrite32(0, ioaddr + TYPHOON_REG_TX_HI_READY);
1495 iowrite32(0, ioaddr + TYPHOON_REG_CMD_READY);
1496 iowrite32(0, ioaddr + TYPHOON_REG_TX_LO_READY);
1497 typhoon_post_pci_writes(ioaddr);
1498 iowrite32(TYPHOON_BOOTCMD_BOOT, ioaddr + TYPHOON_REG_COMMAND);
1499
1500 return 0;
1501
1502out_timeout:
1503 return -ETIMEDOUT;
1504}
1505
1506static u32
1507typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing,
1508 volatile __le32 * index)
1509{
1510 u32 lastRead = txRing->lastRead;
1511 struct tx_desc *tx;
1512 dma_addr_t skb_dma;
1513 int dma_len;
1514 int type;
1515
1516 while(lastRead != le32_to_cpu(*index)) {
1517 tx = (struct tx_desc *) (txRing->ringBase + lastRead);
1518 type = tx->flags & TYPHOON_TYPE_MASK;
1519
1520 if(type == TYPHOON_TX_DESC) {
1521 /* This tx_desc describes a packet.
1522 */
1523 unsigned long ptr = tx->tx_addr;
1524 struct sk_buff *skb = (struct sk_buff *) ptr;
1525 dev_kfree_skb_irq(skb);
1526 } else if(type == TYPHOON_FRAG_DESC) {
1527 /* This tx_desc describes a memory mapping. Free it.
1528 */
1529 skb_dma = (dma_addr_t) le32_to_cpu(tx->frag.addr);
1530 dma_len = le16_to_cpu(tx->len);
1531 pci_unmap_single(tp->pdev, skb_dma, dma_len,
1532 PCI_DMA_TODEVICE);
1533 }
1534
1535 tx->flags = 0;
1536 typhoon_inc_tx_index(&lastRead, 1);
1537 }
1538
1539 return lastRead;
1540}
1541
1542static void
1543typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing,
1544 volatile __le32 * index)
1545{
1546 u32 lastRead;
1547 int numDesc = MAX_SKB_FRAGS + 1;
1548
1549 /* This will need changing if we start to use the Hi Tx ring. */
1550 lastRead = typhoon_clean_tx(tp, txRing, index);
1551 if(netif_queue_stopped(tp->dev) && typhoon_num_free(txRing->lastWrite,
1552 lastRead, TXLO_ENTRIES) > (numDesc + 2))
1553 netif_wake_queue(tp->dev);
1554
1555 txRing->lastRead = lastRead;
1556 smp_wmb();
1557}
1558
1559static void
1560typhoon_recycle_rx_skb(struct typhoon *tp, u32 idx)
1561{
1562 struct typhoon_indexes *indexes = tp->indexes;
1563 struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1564 struct basic_ring *ring = &tp->rxBuffRing;
1565 struct rx_free *r;
1566
1567 if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1568 le32_to_cpu(indexes->rxBuffCleared)) {
1569 /* no room in ring, just drop the skb
1570 */
1571 dev_kfree_skb_any(rxb->skb);
1572 rxb->skb = NULL;
1573 return;
1574 }
1575
1576 r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1577 typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1578 r->virtAddr = idx;
1579 r->physAddr = cpu_to_le32(rxb->dma_addr);
1580
1581 /* Tell the card about it */
1582 wmb();
1583 indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1584}
1585
1586static int
1587typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx)
1588{
1589 struct typhoon_indexes *indexes = tp->indexes;
1590 struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1591 struct basic_ring *ring = &tp->rxBuffRing;
1592 struct rx_free *r;
1593 struct sk_buff *skb;
1594 dma_addr_t dma_addr;
1595
1596 rxb->skb = NULL;
1597
1598 if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1599 le32_to_cpu(indexes->rxBuffCleared))
1600 return -ENOMEM;
1601
1602 skb = netdev_alloc_skb(tp->dev, PKT_BUF_SZ);
1603 if(!skb)
1604 return -ENOMEM;
1605
1606#if 0
1607 /* Please, 3com, fix the firmware to allow DMA to a unaligned
1608 * address! Pretty please?
1609 */
1610 skb_reserve(skb, 2);
1611#endif
1612
1613 dma_addr = pci_map_single(tp->pdev, skb->data,
1614 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
1615
1616 /* Since no card does 64 bit DAC, the high bits will never
1617 * change from zero.
1618 */
1619 r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1620 typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1621 r->virtAddr = idx;
1622 r->physAddr = cpu_to_le32(dma_addr);
1623 rxb->skb = skb;
1624 rxb->dma_addr = dma_addr;
1625
1626 /* Tell the card about it */
1627 wmb();
1628 indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1629 return 0;
1630}
1631
1632static int
1633typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile __le32 * ready,
1634 volatile __le32 * cleared, int budget)
1635{
1636 struct rx_desc *rx;
1637 struct sk_buff *skb, *new_skb;
1638 struct rxbuff_ent *rxb;
1639 dma_addr_t dma_addr;
1640 u32 local_ready;
1641 u32 rxaddr;
1642 int pkt_len;
1643 u32 idx;
1644 __le32 csum_bits;
1645 int received;
1646
1647 received = 0;
1648 local_ready = le32_to_cpu(*ready);
1649 rxaddr = le32_to_cpu(*cleared);
1650 while(rxaddr != local_ready && budget > 0) {
1651 rx = (struct rx_desc *) (rxRing->ringBase + rxaddr);
1652 idx = rx->addr;
1653 rxb = &tp->rxbuffers[idx];
1654 skb = rxb->skb;
1655 dma_addr = rxb->dma_addr;
1656
1657 typhoon_inc_rx_index(&rxaddr, 1);
1658
1659 if(rx->flags & TYPHOON_RX_ERROR) {
1660 typhoon_recycle_rx_skb(tp, idx);
1661 continue;
1662 }
1663
1664 pkt_len = le16_to_cpu(rx->frameLen);
1665
1666 if(pkt_len < rx_copybreak &&
1667 (new_skb = netdev_alloc_skb(tp->dev, pkt_len + 2)) != NULL) {
1668 skb_reserve(new_skb, 2);
1669 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr,
1670 PKT_BUF_SZ,
1671 PCI_DMA_FROMDEVICE);
1672 skb_copy_to_linear_data(new_skb, skb->data, pkt_len);
1673 pci_dma_sync_single_for_device(tp->pdev, dma_addr,
1674 PKT_BUF_SZ,
1675 PCI_DMA_FROMDEVICE);
1676 skb_put(new_skb, pkt_len);
1677 typhoon_recycle_rx_skb(tp, idx);
1678 } else {
1679 new_skb = skb;
1680 skb_put(new_skb, pkt_len);
1681 pci_unmap_single(tp->pdev, dma_addr, PKT_BUF_SZ,
1682 PCI_DMA_FROMDEVICE);
1683 typhoon_alloc_rx_skb(tp, idx);
1684 }
1685 new_skb->protocol = eth_type_trans(new_skb, tp->dev);
1686 csum_bits = rx->rxStatus & (TYPHOON_RX_IP_CHK_GOOD |
1687 TYPHOON_RX_UDP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD);
1688 if(csum_bits ==
1689 (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD) ||
1690 csum_bits ==
1691 (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_UDP_CHK_GOOD)) {
1692 new_skb->ip_summed = CHECKSUM_UNNECESSARY;
1693 } else
1694 skb_checksum_none_assert(new_skb);
1695
1696 if (rx->rxStatus & TYPHOON_RX_VLAN)
1697 __vlan_hwaccel_put_tag(new_skb, htons(ETH_P_8021Q),
1698 ntohl(rx->vlanTag) & 0xffff);
1699 netif_receive_skb(new_skb);
1700
1701 received++;
1702 budget--;
1703 }
1704 *cleared = cpu_to_le32(rxaddr);
1705
1706 return received;
1707}
1708
1709static void
1710typhoon_fill_free_ring(struct typhoon *tp)
1711{
1712 u32 i;
1713
1714 for(i = 0; i < RXENT_ENTRIES; i++) {
1715 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1716 if(rxb->skb)
1717 continue;
1718 if(typhoon_alloc_rx_skb(tp, i) < 0)
1719 break;
1720 }
1721}
1722
1723static int
1724typhoon_poll(struct napi_struct *napi, int budget)
1725{
1726 struct typhoon *tp = container_of(napi, struct typhoon, napi);
1727 struct typhoon_indexes *indexes = tp->indexes;
1728 int work_done;
1729
1730 rmb();
1731 if(!tp->awaiting_resp && indexes->respReady != indexes->respCleared)
1732 typhoon_process_response(tp, 0, NULL);
1733
1734 if(le32_to_cpu(indexes->txLoCleared) != tp->txLoRing.lastRead)
1735 typhoon_tx_complete(tp, &tp->txLoRing, &indexes->txLoCleared);
1736
1737 work_done = 0;
1738
1739 if(indexes->rxHiCleared != indexes->rxHiReady) {
1740 work_done += typhoon_rx(tp, &tp->rxHiRing, &indexes->rxHiReady,
1741 &indexes->rxHiCleared, budget);
1742 }
1743
1744 if(indexes->rxLoCleared != indexes->rxLoReady) {
1745 work_done += typhoon_rx(tp, &tp->rxLoRing, &indexes->rxLoReady,
1746 &indexes->rxLoCleared, budget - work_done);
1747 }
1748
1749 if(le32_to_cpu(indexes->rxBuffCleared) == tp->rxBuffRing.lastWrite) {
1750 /* rxBuff ring is empty, try to fill it. */
1751 typhoon_fill_free_ring(tp);
1752 }
1753
1754 if (work_done < budget) {
1755 napi_complete_done(napi, work_done);
1756 iowrite32(TYPHOON_INTR_NONE,
1757 tp->ioaddr + TYPHOON_REG_INTR_MASK);
1758 typhoon_post_pci_writes(tp->ioaddr);
1759 }
1760
1761 return work_done;
1762}
1763
1764static irqreturn_t
1765typhoon_interrupt(int irq, void *dev_instance)
1766{
1767 struct net_device *dev = dev_instance;
1768 struct typhoon *tp = netdev_priv(dev);
1769 void __iomem *ioaddr = tp->ioaddr;
1770 u32 intr_status;
1771
1772 intr_status = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
1773 if(!(intr_status & TYPHOON_INTR_HOST_INT))
1774 return IRQ_NONE;
1775
1776 iowrite32(intr_status, ioaddr + TYPHOON_REG_INTR_STATUS);
1777
1778 if (napi_schedule_prep(&tp->napi)) {
1779 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
1780 typhoon_post_pci_writes(ioaddr);
1781 __napi_schedule(&tp->napi);
1782 } else {
1783 netdev_err(dev, "Error, poll already scheduled\n");
1784 }
1785 return IRQ_HANDLED;
1786}
1787
1788static void
1789typhoon_free_rx_rings(struct typhoon *tp)
1790{
1791 u32 i;
1792
1793 for(i = 0; i < RXENT_ENTRIES; i++) {
1794 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1795 if(rxb->skb) {
1796 pci_unmap_single(tp->pdev, rxb->dma_addr, PKT_BUF_SZ,
1797 PCI_DMA_FROMDEVICE);
1798 dev_kfree_skb(rxb->skb);
1799 rxb->skb = NULL;
1800 }
1801 }
1802}
1803
1804static int
1805typhoon_sleep(struct typhoon *tp, pci_power_t state, __le16 events)
1806{
1807 struct pci_dev *pdev = tp->pdev;
1808 void __iomem *ioaddr = tp->ioaddr;
1809 struct cmd_desc xp_cmd;
1810 int err;
1811
1812 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_ENABLE_WAKE_EVENTS);
1813 xp_cmd.parm1 = events;
1814 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1815 if(err < 0) {
1816 netdev_err(tp->dev, "typhoon_sleep(): wake events cmd err %d\n",
1817 err);
1818 return err;
1819 }
1820
1821 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_GOTO_SLEEP);
1822 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1823 if(err < 0) {
1824 netdev_err(tp->dev, "typhoon_sleep(): sleep cmd err %d\n", err);
1825 return err;
1826 }
1827
1828 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_SLEEPING) < 0)
1829 return -ETIMEDOUT;
1830
1831 /* Since we cannot monitor the status of the link while sleeping,
1832 * tell the world it went away.
1833 */
1834 netif_carrier_off(tp->dev);
1835
1836 pci_enable_wake(tp->pdev, state, 1);
1837 pci_disable_device(pdev);
1838 return pci_set_power_state(pdev, state);
1839}
1840
1841static int
1842typhoon_wakeup(struct typhoon *tp, int wait_type)
1843{
1844 struct pci_dev *pdev = tp->pdev;
1845 void __iomem *ioaddr = tp->ioaddr;
1846
1847 pci_set_power_state(pdev, PCI_D0);
1848 pci_restore_state(pdev);
1849
1850 /* Post 2.x.x versions of the Sleep Image require a reset before
1851 * we can download the Runtime Image. But let's not make users of
1852 * the old firmware pay for the reset.
1853 */
1854 iowrite32(TYPHOON_BOOTCMD_WAKEUP, ioaddr + TYPHOON_REG_COMMAND);
1855 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0 ||
1856 (tp->capabilities & TYPHOON_WAKEUP_NEEDS_RESET))
1857 return typhoon_reset(ioaddr, wait_type);
1858
1859 return 0;
1860}
1861
1862static int
1863typhoon_start_runtime(struct typhoon *tp)
1864{
1865 struct net_device *dev = tp->dev;
1866 void __iomem *ioaddr = tp->ioaddr;
1867 struct cmd_desc xp_cmd;
1868 int err;
1869
1870 typhoon_init_rings(tp);
1871 typhoon_fill_free_ring(tp);
1872
1873 err = typhoon_download_firmware(tp);
1874 if(err < 0) {
1875 netdev_err(tp->dev, "cannot load runtime on 3XP\n");
1876 goto error_out;
1877 }
1878
1879 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1880 netdev_err(tp->dev, "cannot boot 3XP\n");
1881 err = -EIO;
1882 goto error_out;
1883 }
1884
1885 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAX_PKT_SIZE);
1886 xp_cmd.parm1 = cpu_to_le16(PKT_BUF_SZ);
1887 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1888 if(err < 0)
1889 goto error_out;
1890
1891 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
1892 xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
1893 xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
1894 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1895 if(err < 0)
1896 goto error_out;
1897
1898 /* Disable IRQ coalescing -- we can reenable it when 3Com gives
1899 * us some more information on how to control it.
1900 */
1901 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_IRQ_COALESCE_CTRL);
1902 xp_cmd.parm1 = 0;
1903 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1904 if(err < 0)
1905 goto error_out;
1906
1907 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1908 xp_cmd.parm1 = tp->xcvr_select;
1909 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1910 if(err < 0)
1911 goto error_out;
1912
1913 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE);
1914 xp_cmd.parm1 = cpu_to_le16(ETH_P_8021Q);
1915 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1916 if(err < 0)
1917 goto error_out;
1918
1919 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_OFFLOAD_TASKS);
1920 xp_cmd.parm2 = tp->offload;
1921 xp_cmd.parm3 = tp->offload;
1922 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1923 if(err < 0)
1924 goto error_out;
1925
1926 typhoon_set_rx_mode(dev);
1927
1928 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_ENABLE);
1929 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1930 if(err < 0)
1931 goto error_out;
1932
1933 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_ENABLE);
1934 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1935 if(err < 0)
1936 goto error_out;
1937
1938 tp->card_state = Running;
1939 smp_wmb();
1940
1941 iowrite32(TYPHOON_INTR_ENABLE_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
1942 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_MASK);
1943 typhoon_post_pci_writes(ioaddr);
1944
1945 return 0;
1946
1947error_out:
1948 typhoon_reset(ioaddr, WaitNoSleep);
1949 typhoon_free_rx_rings(tp);
1950 typhoon_init_rings(tp);
1951 return err;
1952}
1953
1954static int
1955typhoon_stop_runtime(struct typhoon *tp, int wait_type)
1956{
1957 struct typhoon_indexes *indexes = tp->indexes;
1958 struct transmit_ring *txLo = &tp->txLoRing;
1959 void __iomem *ioaddr = tp->ioaddr;
1960 struct cmd_desc xp_cmd;
1961 int i;
1962
1963 /* Disable interrupts early, since we can't schedule a poll
1964 * when called with !netif_running(). This will be posted
1965 * when we force the posting of the command.
1966 */
1967 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
1968
1969 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_DISABLE);
1970 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1971
1972 /* Wait 1/2 sec for any outstanding transmits to occur
1973 * We'll cleanup after the reset if this times out.
1974 */
1975 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1976 if(indexes->txLoCleared == cpu_to_le32(txLo->lastWrite))
1977 break;
1978 udelay(TYPHOON_UDELAY);
1979 }
1980
1981 if(i == TYPHOON_WAIT_TIMEOUT)
1982 netdev_err(tp->dev, "halt timed out waiting for Tx to complete\n");
1983
1984 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_DISABLE);
1985 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1986
1987 /* save the statistics so when we bring the interface up again,
1988 * the values reported to userspace are correct.
1989 */
1990 tp->card_state = Sleeping;
1991 smp_wmb();
1992 typhoon_do_get_stats(tp);
1993 memcpy(&tp->stats_saved, &tp->dev->stats, sizeof(struct net_device_stats));
1994
1995 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_HALT);
1996 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1997
1998 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_HALTED) < 0)
1999 netdev_err(tp->dev, "timed out waiting for 3XP to halt\n");
2000
2001 if(typhoon_reset(ioaddr, wait_type) < 0) {
2002 netdev_err(tp->dev, "unable to reset 3XP\n");
2003 return -ETIMEDOUT;
2004 }
2005
2006 /* cleanup any outstanding Tx packets */
2007 if(indexes->txLoCleared != cpu_to_le32(txLo->lastWrite)) {
2008 indexes->txLoCleared = cpu_to_le32(txLo->lastWrite);
2009 typhoon_clean_tx(tp, &tp->txLoRing, &indexes->txLoCleared);
2010 }
2011
2012 return 0;
2013}
2014
2015static void
2016typhoon_tx_timeout(struct net_device *dev)
2017{
2018 struct typhoon *tp = netdev_priv(dev);
2019
2020 if(typhoon_reset(tp->ioaddr, WaitNoSleep) < 0) {
2021 netdev_warn(dev, "could not reset in tx timeout\n");
2022 goto truly_dead;
2023 }
2024
2025 /* If we ever start using the Hi ring, it will need cleaning too */
2026 typhoon_clean_tx(tp, &tp->txLoRing, &tp->indexes->txLoCleared);
2027 typhoon_free_rx_rings(tp);
2028
2029 if(typhoon_start_runtime(tp) < 0) {
2030 netdev_err(dev, "could not start runtime in tx timeout\n");
2031 goto truly_dead;
2032 }
2033
2034 netif_wake_queue(dev);
2035 return;
2036
2037truly_dead:
2038 /* Reset the hardware, and turn off carrier to avoid more timeouts */
2039 typhoon_reset(tp->ioaddr, NoWait);
2040 netif_carrier_off(dev);
2041}
2042
2043static int
2044typhoon_open(struct net_device *dev)
2045{
2046 struct typhoon *tp = netdev_priv(dev);
2047 int err;
2048
2049 err = typhoon_request_firmware(tp);
2050 if (err)
2051 goto out;
2052
2053 err = typhoon_wakeup(tp, WaitSleep);
2054 if(err < 0) {
2055 netdev_err(dev, "unable to wakeup device\n");
2056 goto out_sleep;
2057 }
2058
2059 err = request_irq(dev->irq, typhoon_interrupt, IRQF_SHARED,
2060 dev->name, dev);
2061 if(err < 0)
2062 goto out_sleep;
2063
2064 napi_enable(&tp->napi);
2065
2066 err = typhoon_start_runtime(tp);
2067 if(err < 0) {
2068 napi_disable(&tp->napi);
2069 goto out_irq;
2070 }
2071
2072 netif_start_queue(dev);
2073 return 0;
2074
2075out_irq:
2076 free_irq(dev->irq, dev);
2077
2078out_sleep:
2079 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2080 netdev_err(dev, "unable to reboot into sleep img\n");
2081 typhoon_reset(tp->ioaddr, NoWait);
2082 goto out;
2083 }
2084
2085 if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2086 netdev_err(dev, "unable to go back to sleep\n");
2087
2088out:
2089 return err;
2090}
2091
2092static int
2093typhoon_close(struct net_device *dev)
2094{
2095 struct typhoon *tp = netdev_priv(dev);
2096
2097 netif_stop_queue(dev);
2098 napi_disable(&tp->napi);
2099
2100 if(typhoon_stop_runtime(tp, WaitSleep) < 0)
2101 netdev_err(dev, "unable to stop runtime\n");
2102
2103 /* Make sure there is no irq handler running on a different CPU. */
2104 free_irq(dev->irq, dev);
2105
2106 typhoon_free_rx_rings(tp);
2107 typhoon_init_rings(tp);
2108
2109 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0)
2110 netdev_err(dev, "unable to boot sleep image\n");
2111
2112 if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2113 netdev_err(dev, "unable to put card to sleep\n");
2114
2115 return 0;
2116}
2117
2118#ifdef CONFIG_PM
2119static int
2120typhoon_resume(struct pci_dev *pdev)
2121{
2122 struct net_device *dev = pci_get_drvdata(pdev);
2123 struct typhoon *tp = netdev_priv(dev);
2124
2125 /* If we're down, resume when we are upped.
2126 */
2127 if(!netif_running(dev))
2128 return 0;
2129
2130 if(typhoon_wakeup(tp, WaitNoSleep) < 0) {
2131 netdev_err(dev, "critical: could not wake up in resume\n");
2132 goto reset;
2133 }
2134
2135 if(typhoon_start_runtime(tp) < 0) {
2136 netdev_err(dev, "critical: could not start runtime in resume\n");
2137 goto reset;
2138 }
2139
2140 netif_device_attach(dev);
2141 return 0;
2142
2143reset:
2144 typhoon_reset(tp->ioaddr, NoWait);
2145 return -EBUSY;
2146}
2147
2148static int
2149typhoon_suspend(struct pci_dev *pdev, pm_message_t state)
2150{
2151 struct net_device *dev = pci_get_drvdata(pdev);
2152 struct typhoon *tp = netdev_priv(dev);
2153 struct cmd_desc xp_cmd;
2154
2155 /* If we're down, we're already suspended.
2156 */
2157 if(!netif_running(dev))
2158 return 0;
2159
2160 /* TYPHOON_OFFLOAD_VLAN is always on now, so this doesn't work */
2161 if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
2162 netdev_warn(dev, "cannot do WAKE_MAGIC with VLAN offloading\n");
2163
2164 netif_device_detach(dev);
2165
2166 if(typhoon_stop_runtime(tp, WaitNoSleep) < 0) {
2167 netdev_err(dev, "unable to stop runtime\n");
2168 goto need_resume;
2169 }
2170
2171 typhoon_free_rx_rings(tp);
2172 typhoon_init_rings(tp);
2173
2174 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2175 netdev_err(dev, "unable to boot sleep image\n");
2176 goto need_resume;
2177 }
2178
2179 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
2180 xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
2181 xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
2182 if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2183 netdev_err(dev, "unable to set mac address in suspend\n");
2184 goto need_resume;
2185 }
2186
2187 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
2188 xp_cmd.parm1 = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
2189 if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2190 netdev_err(dev, "unable to set rx filter in suspend\n");
2191 goto need_resume;
2192 }
2193
2194 if(typhoon_sleep(tp, pci_choose_state(pdev, state), tp->wol_events) < 0) {
2195 netdev_err(dev, "unable to put card to sleep\n");
2196 goto need_resume;
2197 }
2198
2199 return 0;
2200
2201need_resume:
2202 typhoon_resume(pdev);
2203 return -EBUSY;
2204}
2205#endif
2206
2207static int
2208typhoon_test_mmio(struct pci_dev *pdev)
2209{
2210 void __iomem *ioaddr = pci_iomap(pdev, 1, 128);
2211 int mode = 0;
2212 u32 val;
2213
2214 if(!ioaddr)
2215 goto out;
2216
2217 if(ioread32(ioaddr + TYPHOON_REG_STATUS) !=
2218 TYPHOON_STATUS_WAITING_FOR_HOST)
2219 goto out_unmap;
2220
2221 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2222 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2223 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
2224
2225 /* Ok, see if we can change our interrupt status register by
2226 * sending ourselves an interrupt. If so, then MMIO works.
2227 * The 50usec delay is arbitrary -- it could probably be smaller.
2228 */
2229 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2230 if((val & TYPHOON_INTR_SELF) == 0) {
2231 iowrite32(1, ioaddr + TYPHOON_REG_SELF_INTERRUPT);
2232 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2233 udelay(50);
2234 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2235 if(val & TYPHOON_INTR_SELF)
2236 mode = 1;
2237 }
2238
2239 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2240 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2241 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2242 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2243
2244out_unmap:
2245 pci_iounmap(pdev, ioaddr);
2246
2247out:
2248 if(!mode)
2249 pr_info("%s: falling back to port IO\n", pci_name(pdev));
2250 return mode;
2251}
2252
2253static const struct net_device_ops typhoon_netdev_ops = {
2254 .ndo_open = typhoon_open,
2255 .ndo_stop = typhoon_close,
2256 .ndo_start_xmit = typhoon_start_tx,
2257 .ndo_set_rx_mode = typhoon_set_rx_mode,
2258 .ndo_tx_timeout = typhoon_tx_timeout,
2259 .ndo_get_stats = typhoon_get_stats,
2260 .ndo_validate_addr = eth_validate_addr,
2261 .ndo_set_mac_address = eth_mac_addr,
2262};
2263
2264static int
2265typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2266{
2267 struct net_device *dev;
2268 struct typhoon *tp;
2269 int card_id = (int) ent->driver_data;
2270 void __iomem *ioaddr;
2271 void *shared;
2272 dma_addr_t shared_dma;
2273 struct cmd_desc xp_cmd;
2274 struct resp_desc xp_resp[3];
2275 int err = 0;
2276 const char *err_msg;
2277
2278 dev = alloc_etherdev(sizeof(*tp));
2279 if(dev == NULL) {
2280 err_msg = "unable to alloc new net device";
2281 err = -ENOMEM;
2282 goto error_out;
2283 }
2284 SET_NETDEV_DEV(dev, &pdev->dev);
2285
2286 err = pci_enable_device(pdev);
2287 if(err < 0) {
2288 err_msg = "unable to enable device";
2289 goto error_out_dev;
2290 }
2291
2292 err = pci_set_mwi(pdev);
2293 if(err < 0) {
2294 err_msg = "unable to set MWI";
2295 goto error_out_disable;
2296 }
2297
2298 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2299 if(err < 0) {
2300 err_msg = "No usable DMA configuration";
2301 goto error_out_mwi;
2302 }
2303
2304 /* sanity checks on IO and MMIO BARs
2305 */
2306 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2307 err_msg = "region #1 not a PCI IO resource, aborting";
2308 err = -ENODEV;
2309 goto error_out_mwi;
2310 }
2311 if(pci_resource_len(pdev, 0) < 128) {
2312 err_msg = "Invalid PCI IO region size, aborting";
2313 err = -ENODEV;
2314 goto error_out_mwi;
2315 }
2316 if(!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
2317 err_msg = "region #1 not a PCI MMIO resource, aborting";
2318 err = -ENODEV;
2319 goto error_out_mwi;
2320 }
2321 if(pci_resource_len(pdev, 1) < 128) {
2322 err_msg = "Invalid PCI MMIO region size, aborting";
2323 err = -ENODEV;
2324 goto error_out_mwi;
2325 }
2326
2327 err = pci_request_regions(pdev, KBUILD_MODNAME);
2328 if(err < 0) {
2329 err_msg = "could not request regions";
2330 goto error_out_mwi;
2331 }
2332
2333 /* map our registers
2334 */
2335 if(use_mmio != 0 && use_mmio != 1)
2336 use_mmio = typhoon_test_mmio(pdev);
2337
2338 ioaddr = pci_iomap(pdev, use_mmio, 128);
2339 if (!ioaddr) {
2340 err_msg = "cannot remap registers, aborting";
2341 err = -EIO;
2342 goto error_out_regions;
2343 }
2344
2345 /* allocate pci dma space for rx and tx descriptor rings
2346 */
2347 shared = pci_alloc_consistent(pdev, sizeof(struct typhoon_shared),
2348 &shared_dma);
2349 if(!shared) {
2350 err_msg = "could not allocate DMA memory";
2351 err = -ENOMEM;
2352 goto error_out_remap;
2353 }
2354
2355 dev->irq = pdev->irq;
2356 tp = netdev_priv(dev);
2357 tp->shared = shared;
2358 tp->shared_dma = shared_dma;
2359 tp->pdev = pdev;
2360 tp->tx_pdev = pdev;
2361 tp->ioaddr = ioaddr;
2362 tp->tx_ioaddr = ioaddr;
2363 tp->dev = dev;
2364
2365 /* Init sequence:
2366 * 1) Reset the adapter to clear any bad juju
2367 * 2) Reload the sleep image
2368 * 3) Boot the sleep image
2369 * 4) Get the hardware address.
2370 * 5) Put the card to sleep.
2371 */
2372 err = typhoon_reset(ioaddr, WaitSleep);
2373 if (err < 0) {
2374 err_msg = "could not reset 3XP";
2375 goto error_out_dma;
2376 }
2377
2378 /* Now that we've reset the 3XP and are sure it's not going to
2379 * write all over memory, enable bus mastering, and save our
2380 * state for resuming after a suspend.
2381 */
2382 pci_set_master(pdev);
2383 pci_save_state(pdev);
2384
2385 typhoon_init_interface(tp);
2386 typhoon_init_rings(tp);
2387
2388 err = typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST);
2389 if (err < 0) {
2390 err_msg = "cannot boot 3XP sleep image";
2391 goto error_out_reset;
2392 }
2393
2394 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_MAC_ADDRESS);
2395 err = typhoon_issue_command(tp, 1, &xp_cmd, 1, xp_resp);
2396 if (err < 0) {
2397 err_msg = "cannot read MAC address";
2398 goto error_out_reset;
2399 }
2400
2401 *(__be16 *)&dev->dev_addr[0] = htons(le16_to_cpu(xp_resp[0].parm1));
2402 *(__be32 *)&dev->dev_addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2));
2403
2404 if (!is_valid_ether_addr(dev->dev_addr)) {
2405 err_msg = "Could not obtain valid ethernet address, aborting";
2406 err = -EIO;
2407 goto error_out_reset;
2408 }
2409
2410 /* Read the Sleep Image version last, so the response is valid
2411 * later when we print out the version reported.
2412 */
2413 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
2414 err = typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp);
2415 if (err < 0) {
2416 err_msg = "Could not get Sleep Image version";
2417 goto error_out_reset;
2418 }
2419
2420 tp->capabilities = typhoon_card_info[card_id].capabilities;
2421 tp->xcvr_select = TYPHOON_XCVR_AUTONEG;
2422
2423 /* Typhoon 1.0 Sleep Images return one response descriptor to the
2424 * READ_VERSIONS command. Those versions are OK after waking up
2425 * from sleep without needing a reset. Typhoon 1.1+ Sleep Images
2426 * seem to need a little extra help to get started. Since we don't
2427 * know how to nudge it along, just kick it.
2428 */
2429 if(xp_resp[0].numDesc != 0)
2430 tp->capabilities |= TYPHOON_WAKEUP_NEEDS_RESET;
2431
2432 err = typhoon_sleep(tp, PCI_D3hot, 0);
2433 if (err < 0) {
2434 err_msg = "cannot put adapter to sleep";
2435 goto error_out_reset;
2436 }
2437
2438 /* The chip-specific entries in the device structure. */
2439 dev->netdev_ops = &typhoon_netdev_ops;
2440 netif_napi_add(dev, &tp->napi, typhoon_poll, 16);
2441 dev->watchdog_timeo = TX_TIMEOUT;
2442
2443 dev->ethtool_ops = &typhoon_ethtool_ops;
2444
2445 /* We can handle scatter gather, up to 16 entries, and
2446 * we can do IP checksumming (only version 4, doh...)
2447 *
2448 * There's no way to turn off the RX VLAN offloading and stripping
2449 * on the current 3XP firmware -- it does not respect the offload
2450 * settings -- so we only allow the user to toggle the TX processing.
2451 */
2452 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
2453 NETIF_F_HW_VLAN_CTAG_TX;
2454 dev->features = dev->hw_features |
2455 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_RXCSUM;
2456
2457 err = register_netdev(dev);
2458 if (err < 0) {
2459 err_msg = "unable to register netdev";
2460 goto error_out_reset;
2461 }
2462
2463 pci_set_drvdata(pdev, dev);
2464
2465 netdev_info(dev, "%s at %s 0x%llx, %pM\n",
2466 typhoon_card_info[card_id].name,
2467 use_mmio ? "MMIO" : "IO",
2468 (unsigned long long)pci_resource_start(pdev, use_mmio),
2469 dev->dev_addr);
2470
2471 /* xp_resp still contains the response to the READ_VERSIONS command.
2472 * For debugging, let the user know what version he has.
2473 */
2474 if(xp_resp[0].numDesc == 0) {
2475 /* This is the Typhoon 1.0 type Sleep Image, last 16 bits
2476 * of version is Month/Day of build.
2477 */
2478 u16 monthday = le32_to_cpu(xp_resp[0].parm2) & 0xffff;
2479 netdev_info(dev, "Typhoon 1.0 Sleep Image built %02u/%02u/2000\n",
2480 monthday >> 8, monthday & 0xff);
2481 } else if(xp_resp[0].numDesc == 2) {
2482 /* This is the Typhoon 1.1+ type Sleep Image
2483 */
2484 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
2485 u8 *ver_string = (u8 *) &xp_resp[1];
2486 ver_string[25] = 0;
2487 netdev_info(dev, "Typhoon 1.1+ Sleep Image version %02x.%03x.%03x %s\n",
2488 sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
2489 sleep_ver & 0xfff, ver_string);
2490 } else {
2491 netdev_warn(dev, "Unknown Sleep Image version (%u:%04x)\n",
2492 xp_resp[0].numDesc, le32_to_cpu(xp_resp[0].parm2));
2493 }
2494
2495 return 0;
2496
2497error_out_reset:
2498 typhoon_reset(ioaddr, NoWait);
2499
2500error_out_dma:
2501 pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2502 shared, shared_dma);
2503error_out_remap:
2504 pci_iounmap(pdev, ioaddr);
2505error_out_regions:
2506 pci_release_regions(pdev);
2507error_out_mwi:
2508 pci_clear_mwi(pdev);
2509error_out_disable:
2510 pci_disable_device(pdev);
2511error_out_dev:
2512 free_netdev(dev);
2513error_out:
2514 pr_err("%s: %s\n", pci_name(pdev), err_msg);
2515 return err;
2516}
2517
2518static void
2519typhoon_remove_one(struct pci_dev *pdev)
2520{
2521 struct net_device *dev = pci_get_drvdata(pdev);
2522 struct typhoon *tp = netdev_priv(dev);
2523
2524 unregister_netdev(dev);
2525 pci_set_power_state(pdev, PCI_D0);
2526 pci_restore_state(pdev);
2527 typhoon_reset(tp->ioaddr, NoWait);
2528 pci_iounmap(pdev, tp->ioaddr);
2529 pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2530 tp->shared, tp->shared_dma);
2531 pci_release_regions(pdev);
2532 pci_clear_mwi(pdev);
2533 pci_disable_device(pdev);
2534 free_netdev(dev);
2535}
2536
2537static struct pci_driver typhoon_driver = {
2538 .name = KBUILD_MODNAME,
2539 .id_table = typhoon_pci_tbl,
2540 .probe = typhoon_init_one,
2541 .remove = typhoon_remove_one,
2542#ifdef CONFIG_PM
2543 .suspend = typhoon_suspend,
2544 .resume = typhoon_resume,
2545#endif
2546};
2547
2548static int __init
2549typhoon_init(void)
2550{
2551 return pci_register_driver(&typhoon_driver);
2552}
2553
2554static void __exit
2555typhoon_cleanup(void)
2556{
2557 release_firmware(typhoon_fw);
2558 pci_unregister_driver(&typhoon_driver);
2559}
2560
2561module_init(typhoon_init);
2562module_exit(typhoon_cleanup);