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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Wei WANG <wei_wang@realsil.com.cn>
8 */
9
10#ifndef __RTSX_PCR_H
11#define __RTSX_PCR_H
12
13#include <linux/rtsx_pci.h>
14
15#define MIN_DIV_N_PCR 80
16#define MAX_DIV_N_PCR 208
17
18#define RTS522A_PME_FORCE_CTL 0xFF78
19#define RTS522A_AUTOLOAD_CFG1 0xFF7C
20#define RTS522A_PM_CTRL3 0xFF7E
21
22#define RTS524A_PME_FORCE_CTL 0xFF78
23#define REG_EFUSE_BYPASS 0x08
24#define REG_EFUSE_POR 0x04
25#define REG_EFUSE_POWER_MASK 0x03
26#define REG_EFUSE_POWERON 0x03
27#define REG_EFUSE_POWEROFF 0x00
28#define RTS5250_CLK_CFG3 0xFF79
29#define RTS525A_CFG_MEM_PD 0xF0
30#define RTS524A_AUTOLOAD_CFG1 0xFF7C
31#define RTS524A_PM_CTRL3 0xFF7E
32#define RTS525A_BIOS_CFG 0xFF2D
33#define RTS525A_LOAD_BIOS_FLAG 0x01
34#define RTS525A_CLEAR_BIOS_FLAG 0x00
35
36#define RTS525A_EFUSE_CTL 0xFC32
37#define REG_EFUSE_ENABLE 0x80
38#define REG_EFUSE_MODE 0x40
39#define RTS525A_EFUSE_ADD 0xFC33
40#define REG_EFUSE_ADD_MASK 0x3F
41#define RTS525A_EFUSE_DATA 0xFC35
42
43#define LTR_ACTIVE_LATENCY_DEF 0x883C
44#define LTR_IDLE_LATENCY_DEF 0x892C
45#define LTR_L1OFF_LATENCY_DEF 0x9003
46#define L1_SNOOZE_DELAY_DEF 1
47#define LTR_L1OFF_SSPWRGATE_5249_DEF 0xAF
48#define LTR_L1OFF_SSPWRGATE_5250_DEF 0xFF
49#define LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF 0xAC
50#define LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF 0xF8
51#define CMD_TIMEOUT_DEF 100
52#define MASK_8_BIT_DEF 0xFF
53
54#define SSC_CLOCK_STABLE_WAIT 130
55
56#define RTS524A_OCP_THD_800 0x04
57#define RTS525A_OCP_THD_800 0x05
58#define RTS522A_OCP_THD_800 0x06
59
60
61int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
62int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
63
64void rts5209_init_params(struct rtsx_pcr *pcr);
65void rts5229_init_params(struct rtsx_pcr *pcr);
66void rtl8411_init_params(struct rtsx_pcr *pcr);
67void rtl8402_init_params(struct rtsx_pcr *pcr);
68void rts5227_init_params(struct rtsx_pcr *pcr);
69void rts522a_init_params(struct rtsx_pcr *pcr);
70void rts5249_init_params(struct rtsx_pcr *pcr);
71void rts524a_init_params(struct rtsx_pcr *pcr);
72void rts525a_init_params(struct rtsx_pcr *pcr);
73void rtl8411b_init_params(struct rtsx_pcr *pcr);
74void rts5260_init_params(struct rtsx_pcr *pcr);
75void rts5261_init_params(struct rtsx_pcr *pcr);
76void rts5228_init_params(struct rtsx_pcr *pcr);
77void rts5264_init_params(struct rtsx_pcr *pcr);
78
79static inline u8 map_sd_drive(int idx)
80{
81 u8 sd_drive[4] = {
82 0x01, /* Type D */
83 0x02, /* Type C */
84 0x05, /* Type A */
85 0x03 /* Type B */
86 };
87
88 return sd_drive[idx];
89}
90
91#define rtsx_vendor_setting_valid(reg) (!((reg) & 0x1000000))
92#define rts5209_vendor_setting1_valid(reg) (!((reg) & 0x80))
93#define rts5209_vendor_setting2_valid(reg) ((reg) & 0x80)
94
95#define rtsx_check_mmc_support(reg) ((reg) & 0x10)
96#define rtsx_reg_to_rtd3(reg) ((reg) & 0x02)
97#define rtsx_reg_to_rtd3_uhsii(reg) ((reg) & 0x04)
98#define rtsx_reg_to_aspm(reg) (((reg) >> 28) & 0x03)
99#define rtsx_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 26) & 0x03)
100#define rtsx_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x03)
101#define rtsx_reg_to_card_drive_sel(reg) ((((reg) >> 25) & 0x01) << 6)
102#define rtsx_reg_check_reverse_socket(reg) ((reg) & 0x4000)
103#define rts5209_reg_to_aspm(reg) (((reg) >> 5) & 0x03)
104#define rts5209_reg_check_ms_pmos(reg) (!((reg) & 0x08))
105#define rts5209_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 3) & 0x07)
106#define rts5209_reg_to_sd30_drive_sel_3v3(reg) ((reg) & 0x07)
107#define rts5209_reg_to_card_drive_sel(reg) ((reg) >> 8)
108#define rtl8411_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x07)
109#define rtl8411b_reg_to_sd30_drive_sel_3v3(reg) ((reg) & 0x03)
110
111#define set_pull_ctrl_tables(pcr, __device) \
112do { \
113 pcr->sd_pull_ctl_enable_tbl = __device##_sd_pull_ctl_enable_tbl; \
114 pcr->sd_pull_ctl_disable_tbl = __device##_sd_pull_ctl_disable_tbl; \
115 pcr->ms_pull_ctl_enable_tbl = __device##_ms_pull_ctl_enable_tbl; \
116 pcr->ms_pull_ctl_disable_tbl = __device##_ms_pull_ctl_disable_tbl; \
117} while (0)
118
119/* generic operations */
120int rtsx_gops_pm_reset(struct rtsx_pcr *pcr);
121int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency);
122int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val);
123void rtsx_pci_init_ocp(struct rtsx_pcr *pcr);
124void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr);
125void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr);
126int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val);
127void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr);
128void rtsx_pci_enable_oobs_polling(struct rtsx_pcr *pcr);
129void rtsx_pci_disable_oobs_polling(struct rtsx_pcr *pcr);
130int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr);
131int rtsx_ms_power_off_card3v3(struct rtsx_pcr *pcr);
132
133#endif
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Wei WANG <wei_wang@realsil.com.cn>
8 */
9
10#ifndef __RTSX_PCR_H
11#define __RTSX_PCR_H
12
13#include <linux/rtsx_pci.h>
14
15#define MIN_DIV_N_PCR 80
16#define MAX_DIV_N_PCR 208
17
18#define RTS522A_PM_CTRL3 0xFF7E
19
20#define RTS524A_PME_FORCE_CTL 0xFF78
21#define RTS524A_PM_CTRL3 0xFF7E
22
23#define LTR_ACTIVE_LATENCY_DEF 0x883C
24#define LTR_IDLE_LATENCY_DEF 0x892C
25#define LTR_L1OFF_LATENCY_DEF 0x9003
26#define L1_SNOOZE_DELAY_DEF 1
27#define LTR_L1OFF_SSPWRGATE_5249_DEF 0xAF
28#define LTR_L1OFF_SSPWRGATE_5250_DEF 0xFF
29#define LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF 0xAC
30#define LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF 0xF8
31#define CMD_TIMEOUT_DEF 100
32#define ASPM_MASK_NEG 0xFC
33#define MASK_8_BIT_DEF 0xFF
34
35#define SSC_CLOCK_STABLE_WAIT 130
36
37#define RTS524A_OCP_THD_800 0x04
38#define RTS525A_OCP_THD_800 0x05
39#define RTS522A_OCP_THD_800 0x06
40
41
42int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
43int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
44
45void rts5209_init_params(struct rtsx_pcr *pcr);
46void rts5229_init_params(struct rtsx_pcr *pcr);
47void rtl8411_init_params(struct rtsx_pcr *pcr);
48void rtl8402_init_params(struct rtsx_pcr *pcr);
49void rts5227_init_params(struct rtsx_pcr *pcr);
50void rts522a_init_params(struct rtsx_pcr *pcr);
51void rts5249_init_params(struct rtsx_pcr *pcr);
52void rts524a_init_params(struct rtsx_pcr *pcr);
53void rts525a_init_params(struct rtsx_pcr *pcr);
54void rtl8411b_init_params(struct rtsx_pcr *pcr);
55void rts5260_init_params(struct rtsx_pcr *pcr);
56
57static inline u8 map_sd_drive(int idx)
58{
59 u8 sd_drive[4] = {
60 0x01, /* Type D */
61 0x02, /* Type C */
62 0x05, /* Type A */
63 0x03 /* Type B */
64 };
65
66 return sd_drive[idx];
67}
68
69#define rtsx_vendor_setting_valid(reg) (!((reg) & 0x1000000))
70#define rts5209_vendor_setting1_valid(reg) (!((reg) & 0x80))
71#define rts5209_vendor_setting2_valid(reg) ((reg) & 0x80)
72
73#define rtsx_reg_to_aspm(reg) (((reg) >> 28) & 0x03)
74#define rtsx_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 26) & 0x03)
75#define rtsx_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x03)
76#define rtsx_reg_to_card_drive_sel(reg) ((((reg) >> 25) & 0x01) << 6)
77#define rtsx_reg_check_reverse_socket(reg) ((reg) & 0x4000)
78#define rts5209_reg_to_aspm(reg) (((reg) >> 5) & 0x03)
79#define rts5209_reg_check_ms_pmos(reg) (!((reg) & 0x08))
80#define rts5209_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 3) & 0x07)
81#define rts5209_reg_to_sd30_drive_sel_3v3(reg) ((reg) & 0x07)
82#define rts5209_reg_to_card_drive_sel(reg) ((reg) >> 8)
83#define rtl8411_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x07)
84#define rtl8411b_reg_to_sd30_drive_sel_3v3(reg) ((reg) & 0x03)
85
86#define set_pull_ctrl_tables(pcr, __device) \
87do { \
88 pcr->sd_pull_ctl_enable_tbl = __device##_sd_pull_ctl_enable_tbl; \
89 pcr->sd_pull_ctl_disable_tbl = __device##_sd_pull_ctl_disable_tbl; \
90 pcr->ms_pull_ctl_enable_tbl = __device##_ms_pull_ctl_enable_tbl; \
91 pcr->ms_pull_ctl_disable_tbl = __device##_ms_pull_ctl_disable_tbl; \
92} while (0)
93
94/* generic operations */
95int rtsx_gops_pm_reset(struct rtsx_pcr *pcr);
96int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency);
97int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val);
98void rtsx_pci_init_ocp(struct rtsx_pcr *pcr);
99void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr);
100void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr);
101int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val);
102void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr);
103int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr);
104int rtsx_ms_power_off_card3v3(struct rtsx_pcr *pcr);
105
106#endif