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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
4 *
5 * Author:
6 * Mikko Perttunen <mperttunen@nvidia.com>
7 */
8
9#include <linux/clk-provider.h>
10#include <linux/clk.h>
11#include <linux/clkdev.h>
12#include <linux/clk/tegra.h>
13#include <linux/debugfs.h>
14#include <linux/delay.h>
15#include <linux/interconnect-provider.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/mutex.h>
19#include <linux/of_address.h>
20#include <linux/of_platform.h>
21#include <linux/platform_device.h>
22#include <linux/pm_opp.h>
23#include <linux/sort.h>
24#include <linux/string.h>
25
26#include <soc/tegra/fuse.h>
27#include <soc/tegra/mc.h>
28
29#include "mc.h"
30
31#define EMC_FBIO_CFG5 0x104
32#define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
33#define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0
34#define EMC_FBIO_CFG5_DRAM_WIDTH_X64 BIT(4)
35
36#define EMC_INTSTATUS 0x0
37#define EMC_INTSTATUS_CLKCHANGE_COMPLETE BIT(4)
38
39#define EMC_CFG 0xc
40#define EMC_CFG_DRAM_CLKSTOP_PD BIT(31)
41#define EMC_CFG_DRAM_CLKSTOP_SR BIT(30)
42#define EMC_CFG_DRAM_ACPD BIT(29)
43#define EMC_CFG_DYN_SREF BIT(28)
44#define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18))
45#define EMC_CFG_DSR_VTTGEN_DRV_EN BIT(18)
46
47#define EMC_REFCTRL 0x20
48#define EMC_REFCTRL_DEV_SEL_SHIFT 0
49#define EMC_REFCTRL_ENABLE BIT(31)
50
51#define EMC_TIMING_CONTROL 0x28
52#define EMC_RC 0x2c
53#define EMC_RFC 0x30
54#define EMC_RAS 0x34
55#define EMC_RP 0x38
56#define EMC_R2W 0x3c
57#define EMC_W2R 0x40
58#define EMC_R2P 0x44
59#define EMC_W2P 0x48
60#define EMC_RD_RCD 0x4c
61#define EMC_WR_RCD 0x50
62#define EMC_RRD 0x54
63#define EMC_REXT 0x58
64#define EMC_WDV 0x5c
65#define EMC_QUSE 0x60
66#define EMC_QRST 0x64
67#define EMC_QSAFE 0x68
68#define EMC_RDV 0x6c
69#define EMC_REFRESH 0x70
70#define EMC_BURST_REFRESH_NUM 0x74
71#define EMC_PDEX2WR 0x78
72#define EMC_PDEX2RD 0x7c
73#define EMC_PCHG2PDEN 0x80
74#define EMC_ACT2PDEN 0x84
75#define EMC_AR2PDEN 0x88
76#define EMC_RW2PDEN 0x8c
77#define EMC_TXSR 0x90
78#define EMC_TCKE 0x94
79#define EMC_TFAW 0x98
80#define EMC_TRPAB 0x9c
81#define EMC_TCLKSTABLE 0xa0
82#define EMC_TCLKSTOP 0xa4
83#define EMC_TREFBW 0xa8
84#define EMC_ODT_WRITE 0xb0
85#define EMC_ODT_READ 0xb4
86#define EMC_WEXT 0xb8
87#define EMC_CTT 0xbc
88#define EMC_RFC_SLR 0xc0
89#define EMC_MRS_WAIT_CNT2 0xc4
90
91#define EMC_MRS_WAIT_CNT 0xc8
92#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0
93#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \
94 (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
95#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16
96#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \
97 (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
98
99#define EMC_MRS 0xcc
100#define EMC_MODE_SET_DLL_RESET BIT(8)
101#define EMC_MODE_SET_LONG_CNT BIT(26)
102#define EMC_EMRS 0xd0
103#define EMC_REF 0xd4
104#define EMC_PRE 0xd8
105
106#define EMC_SELF_REF 0xe0
107#define EMC_SELF_REF_CMD_ENABLED BIT(0)
108#define EMC_SELF_REF_DEV_SEL_SHIFT 30
109
110#define EMC_MRW 0xe8
111
112#define EMC_MRR 0xec
113#define EMC_MRR_MA_SHIFT 16
114#define LPDDR2_MR4_TEMP_SHIFT 0
115
116#define EMC_XM2DQSPADCTRL3 0xf8
117#define EMC_FBIO_SPARE 0x100
118
119#define EMC_FBIO_CFG6 0x114
120#define EMC_EMRS2 0x12c
121#define EMC_MRW2 0x134
122#define EMC_MRW4 0x13c
123#define EMC_EINPUT 0x14c
124#define EMC_EINPUT_DURATION 0x150
125#define EMC_PUTERM_EXTRA 0x154
126#define EMC_TCKESR 0x158
127#define EMC_TPD 0x15c
128
129#define EMC_AUTO_CAL_CONFIG 0x2a4
130#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START BIT(31)
131#define EMC_AUTO_CAL_INTERVAL 0x2a8
132#define EMC_AUTO_CAL_STATUS 0x2ac
133#define EMC_AUTO_CAL_STATUS_ACTIVE BIT(31)
134#define EMC_STATUS 0x2b4
135#define EMC_STATUS_TIMING_UPDATE_STALLED BIT(23)
136
137#define EMC_CFG_2 0x2b8
138#define EMC_CFG_2_MODE_SHIFT 0
139#define EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR BIT(6)
140
141#define EMC_CFG_DIG_DLL 0x2bc
142#define EMC_CFG_DIG_DLL_PERIOD 0x2c0
143#define EMC_RDV_MASK 0x2cc
144#define EMC_WDV_MASK 0x2d0
145#define EMC_CTT_DURATION 0x2d8
146#define EMC_CTT_TERM_CTRL 0x2dc
147#define EMC_ZCAL_INTERVAL 0x2e0
148#define EMC_ZCAL_WAIT_CNT 0x2e4
149
150#define EMC_ZQ_CAL 0x2ec
151#define EMC_ZQ_CAL_CMD BIT(0)
152#define EMC_ZQ_CAL_LONG BIT(4)
153#define EMC_ZQ_CAL_LONG_CMD_DEV0 \
154 (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
155#define EMC_ZQ_CAL_LONG_CMD_DEV1 \
156 (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
157
158#define EMC_XM2CMDPADCTRL 0x2f0
159#define EMC_XM2DQSPADCTRL 0x2f8
160#define EMC_XM2DQSPADCTRL2 0x2fc
161#define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE BIT(0)
162#define EMC_XM2DQSPADCTRL2_VREF_ENABLE BIT(5)
163#define EMC_XM2DQPADCTRL 0x300
164#define EMC_XM2DQPADCTRL2 0x304
165#define EMC_XM2CLKPADCTRL 0x308
166#define EMC_XM2COMPPADCTRL 0x30c
167#define EMC_XM2VTTGENPADCTRL 0x310
168#define EMC_XM2VTTGENPADCTRL2 0x314
169#define EMC_XM2VTTGENPADCTRL3 0x318
170#define EMC_XM2DQSPADCTRL4 0x320
171#define EMC_DLL_XFORM_DQS0 0x328
172#define EMC_DLL_XFORM_DQS1 0x32c
173#define EMC_DLL_XFORM_DQS2 0x330
174#define EMC_DLL_XFORM_DQS3 0x334
175#define EMC_DLL_XFORM_DQS4 0x338
176#define EMC_DLL_XFORM_DQS5 0x33c
177#define EMC_DLL_XFORM_DQS6 0x340
178#define EMC_DLL_XFORM_DQS7 0x344
179#define EMC_DLL_XFORM_QUSE0 0x348
180#define EMC_DLL_XFORM_QUSE1 0x34c
181#define EMC_DLL_XFORM_QUSE2 0x350
182#define EMC_DLL_XFORM_QUSE3 0x354
183#define EMC_DLL_XFORM_QUSE4 0x358
184#define EMC_DLL_XFORM_QUSE5 0x35c
185#define EMC_DLL_XFORM_QUSE6 0x360
186#define EMC_DLL_XFORM_QUSE7 0x364
187#define EMC_DLL_XFORM_DQ0 0x368
188#define EMC_DLL_XFORM_DQ1 0x36c
189#define EMC_DLL_XFORM_DQ2 0x370
190#define EMC_DLL_XFORM_DQ3 0x374
191#define EMC_DLI_TRIM_TXDQS0 0x3a8
192#define EMC_DLI_TRIM_TXDQS1 0x3ac
193#define EMC_DLI_TRIM_TXDQS2 0x3b0
194#define EMC_DLI_TRIM_TXDQS3 0x3b4
195#define EMC_DLI_TRIM_TXDQS4 0x3b8
196#define EMC_DLI_TRIM_TXDQS5 0x3bc
197#define EMC_DLI_TRIM_TXDQS6 0x3c0
198#define EMC_DLI_TRIM_TXDQS7 0x3c4
199#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc
200#define EMC_SEL_DPD_CTRL 0x3d8
201#define EMC_SEL_DPD_CTRL_DATA_SEL_DPD BIT(8)
202#define EMC_SEL_DPD_CTRL_ODT_SEL_DPD BIT(5)
203#define EMC_SEL_DPD_CTRL_RESET_SEL_DPD BIT(4)
204#define EMC_SEL_DPD_CTRL_CA_SEL_DPD BIT(3)
205#define EMC_SEL_DPD_CTRL_CLK_SEL_DPD BIT(2)
206#define EMC_SEL_DPD_CTRL_DDR3_MASK \
207 ((0xf << 2) | BIT(8))
208#define EMC_SEL_DPD_CTRL_MASK \
209 ((0x3 << 2) | BIT(5) | BIT(8))
210#define EMC_PRE_REFRESH_REQ_CNT 0x3dc
211#define EMC_DYN_SELF_REF_CONTROL 0x3e0
212#define EMC_TXSRDLL 0x3e4
213#define EMC_CCFIFO_ADDR 0x3e8
214#define EMC_CCFIFO_DATA 0x3ec
215#define EMC_CCFIFO_STATUS 0x3f0
216#define EMC_CDB_CNTL_1 0x3f4
217#define EMC_CDB_CNTL_2 0x3f8
218#define EMC_XM2CLKPADCTRL2 0x3fc
219#define EMC_AUTO_CAL_CONFIG2 0x458
220#define EMC_AUTO_CAL_CONFIG3 0x45c
221#define EMC_IBDLY 0x468
222#define EMC_DLL_XFORM_ADDR0 0x46c
223#define EMC_DLL_XFORM_ADDR1 0x470
224#define EMC_DLL_XFORM_ADDR2 0x474
225#define EMC_DSR_VTTGEN_DRV 0x47c
226#define EMC_TXDSRVTTGEN 0x480
227#define EMC_XM2CMDPADCTRL4 0x484
228#define EMC_XM2CMDPADCTRL5 0x488
229#define EMC_DLL_XFORM_DQS8 0x4a0
230#define EMC_DLL_XFORM_DQS9 0x4a4
231#define EMC_DLL_XFORM_DQS10 0x4a8
232#define EMC_DLL_XFORM_DQS11 0x4ac
233#define EMC_DLL_XFORM_DQS12 0x4b0
234#define EMC_DLL_XFORM_DQS13 0x4b4
235#define EMC_DLL_XFORM_DQS14 0x4b8
236#define EMC_DLL_XFORM_DQS15 0x4bc
237#define EMC_DLL_XFORM_QUSE8 0x4c0
238#define EMC_DLL_XFORM_QUSE9 0x4c4
239#define EMC_DLL_XFORM_QUSE10 0x4c8
240#define EMC_DLL_XFORM_QUSE11 0x4cc
241#define EMC_DLL_XFORM_QUSE12 0x4d0
242#define EMC_DLL_XFORM_QUSE13 0x4d4
243#define EMC_DLL_XFORM_QUSE14 0x4d8
244#define EMC_DLL_XFORM_QUSE15 0x4dc
245#define EMC_DLL_XFORM_DQ4 0x4e0
246#define EMC_DLL_XFORM_DQ5 0x4e4
247#define EMC_DLL_XFORM_DQ6 0x4e8
248#define EMC_DLL_XFORM_DQ7 0x4ec
249#define EMC_DLI_TRIM_TXDQS8 0x520
250#define EMC_DLI_TRIM_TXDQS9 0x524
251#define EMC_DLI_TRIM_TXDQS10 0x528
252#define EMC_DLI_TRIM_TXDQS11 0x52c
253#define EMC_DLI_TRIM_TXDQS12 0x530
254#define EMC_DLI_TRIM_TXDQS13 0x534
255#define EMC_DLI_TRIM_TXDQS14 0x538
256#define EMC_DLI_TRIM_TXDQS15 0x53c
257#define EMC_CDB_CNTL_3 0x540
258#define EMC_XM2DQSPADCTRL5 0x544
259#define EMC_XM2DQSPADCTRL6 0x548
260#define EMC_XM2DQPADCTRL3 0x54c
261#define EMC_DLL_XFORM_ADDR3 0x550
262#define EMC_DLL_XFORM_ADDR4 0x554
263#define EMC_DLL_XFORM_ADDR5 0x558
264#define EMC_CFG_PIPE 0x560
265#define EMC_QPOP 0x564
266#define EMC_QUSE_WIDTH 0x568
267#define EMC_PUTERM_WIDTH 0x56c
268#define EMC_BGBIAS_CTL0 0x570
269#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX BIT(3)
270#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN BIT(2)
271#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD BIT(1)
272#define EMC_PUTERM_ADJ 0x574
273
274#define DRAM_DEV_SEL_ALL 0
275#define DRAM_DEV_SEL_0 BIT(31)
276#define DRAM_DEV_SEL_1 BIT(30)
277
278#define EMC_CFG_POWER_FEATURES_MASK \
279 (EMC_CFG_DYN_SREF | EMC_CFG_DRAM_ACPD | EMC_CFG_DRAM_CLKSTOP_SR | \
280 EMC_CFG_DRAM_CLKSTOP_PD | EMC_CFG_DSR_VTTGEN_DRV_EN)
281#define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
282#define EMC_DRAM_DEV_SEL(n) ((n > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
283
284/* Maximum amount of time in us. to wait for changes to become effective */
285#define EMC_STATUS_UPDATE_TIMEOUT 1000
286
287enum emc_dram_type {
288 DRAM_TYPE_DDR3 = 0,
289 DRAM_TYPE_DDR1 = 1,
290 DRAM_TYPE_LPDDR3 = 2,
291 DRAM_TYPE_DDR2 = 3
292};
293
294enum emc_dll_change {
295 DLL_CHANGE_NONE,
296 DLL_CHANGE_ON,
297 DLL_CHANGE_OFF
298};
299
300static const unsigned long emc_burst_regs[] = {
301 EMC_RC,
302 EMC_RFC,
303 EMC_RFC_SLR,
304 EMC_RAS,
305 EMC_RP,
306 EMC_R2W,
307 EMC_W2R,
308 EMC_R2P,
309 EMC_W2P,
310 EMC_RD_RCD,
311 EMC_WR_RCD,
312 EMC_RRD,
313 EMC_REXT,
314 EMC_WEXT,
315 EMC_WDV,
316 EMC_WDV_MASK,
317 EMC_QUSE,
318 EMC_QUSE_WIDTH,
319 EMC_IBDLY,
320 EMC_EINPUT,
321 EMC_EINPUT_DURATION,
322 EMC_PUTERM_EXTRA,
323 EMC_PUTERM_WIDTH,
324 EMC_PUTERM_ADJ,
325 EMC_CDB_CNTL_1,
326 EMC_CDB_CNTL_2,
327 EMC_CDB_CNTL_3,
328 EMC_QRST,
329 EMC_QSAFE,
330 EMC_RDV,
331 EMC_RDV_MASK,
332 EMC_REFRESH,
333 EMC_BURST_REFRESH_NUM,
334 EMC_PRE_REFRESH_REQ_CNT,
335 EMC_PDEX2WR,
336 EMC_PDEX2RD,
337 EMC_PCHG2PDEN,
338 EMC_ACT2PDEN,
339 EMC_AR2PDEN,
340 EMC_RW2PDEN,
341 EMC_TXSR,
342 EMC_TXSRDLL,
343 EMC_TCKE,
344 EMC_TCKESR,
345 EMC_TPD,
346 EMC_TFAW,
347 EMC_TRPAB,
348 EMC_TCLKSTABLE,
349 EMC_TCLKSTOP,
350 EMC_TREFBW,
351 EMC_FBIO_CFG6,
352 EMC_ODT_WRITE,
353 EMC_ODT_READ,
354 EMC_FBIO_CFG5,
355 EMC_CFG_DIG_DLL,
356 EMC_CFG_DIG_DLL_PERIOD,
357 EMC_DLL_XFORM_DQS0,
358 EMC_DLL_XFORM_DQS1,
359 EMC_DLL_XFORM_DQS2,
360 EMC_DLL_XFORM_DQS3,
361 EMC_DLL_XFORM_DQS4,
362 EMC_DLL_XFORM_DQS5,
363 EMC_DLL_XFORM_DQS6,
364 EMC_DLL_XFORM_DQS7,
365 EMC_DLL_XFORM_DQS8,
366 EMC_DLL_XFORM_DQS9,
367 EMC_DLL_XFORM_DQS10,
368 EMC_DLL_XFORM_DQS11,
369 EMC_DLL_XFORM_DQS12,
370 EMC_DLL_XFORM_DQS13,
371 EMC_DLL_XFORM_DQS14,
372 EMC_DLL_XFORM_DQS15,
373 EMC_DLL_XFORM_QUSE0,
374 EMC_DLL_XFORM_QUSE1,
375 EMC_DLL_XFORM_QUSE2,
376 EMC_DLL_XFORM_QUSE3,
377 EMC_DLL_XFORM_QUSE4,
378 EMC_DLL_XFORM_QUSE5,
379 EMC_DLL_XFORM_QUSE6,
380 EMC_DLL_XFORM_QUSE7,
381 EMC_DLL_XFORM_ADDR0,
382 EMC_DLL_XFORM_ADDR1,
383 EMC_DLL_XFORM_ADDR2,
384 EMC_DLL_XFORM_ADDR3,
385 EMC_DLL_XFORM_ADDR4,
386 EMC_DLL_XFORM_ADDR5,
387 EMC_DLL_XFORM_QUSE8,
388 EMC_DLL_XFORM_QUSE9,
389 EMC_DLL_XFORM_QUSE10,
390 EMC_DLL_XFORM_QUSE11,
391 EMC_DLL_XFORM_QUSE12,
392 EMC_DLL_XFORM_QUSE13,
393 EMC_DLL_XFORM_QUSE14,
394 EMC_DLL_XFORM_QUSE15,
395 EMC_DLI_TRIM_TXDQS0,
396 EMC_DLI_TRIM_TXDQS1,
397 EMC_DLI_TRIM_TXDQS2,
398 EMC_DLI_TRIM_TXDQS3,
399 EMC_DLI_TRIM_TXDQS4,
400 EMC_DLI_TRIM_TXDQS5,
401 EMC_DLI_TRIM_TXDQS6,
402 EMC_DLI_TRIM_TXDQS7,
403 EMC_DLI_TRIM_TXDQS8,
404 EMC_DLI_TRIM_TXDQS9,
405 EMC_DLI_TRIM_TXDQS10,
406 EMC_DLI_TRIM_TXDQS11,
407 EMC_DLI_TRIM_TXDQS12,
408 EMC_DLI_TRIM_TXDQS13,
409 EMC_DLI_TRIM_TXDQS14,
410 EMC_DLI_TRIM_TXDQS15,
411 EMC_DLL_XFORM_DQ0,
412 EMC_DLL_XFORM_DQ1,
413 EMC_DLL_XFORM_DQ2,
414 EMC_DLL_XFORM_DQ3,
415 EMC_DLL_XFORM_DQ4,
416 EMC_DLL_XFORM_DQ5,
417 EMC_DLL_XFORM_DQ6,
418 EMC_DLL_XFORM_DQ7,
419 EMC_XM2CMDPADCTRL,
420 EMC_XM2CMDPADCTRL4,
421 EMC_XM2CMDPADCTRL5,
422 EMC_XM2DQPADCTRL2,
423 EMC_XM2DQPADCTRL3,
424 EMC_XM2CLKPADCTRL,
425 EMC_XM2CLKPADCTRL2,
426 EMC_XM2COMPPADCTRL,
427 EMC_XM2VTTGENPADCTRL,
428 EMC_XM2VTTGENPADCTRL2,
429 EMC_XM2VTTGENPADCTRL3,
430 EMC_XM2DQSPADCTRL3,
431 EMC_XM2DQSPADCTRL4,
432 EMC_XM2DQSPADCTRL5,
433 EMC_XM2DQSPADCTRL6,
434 EMC_DSR_VTTGEN_DRV,
435 EMC_TXDSRVTTGEN,
436 EMC_FBIO_SPARE,
437 EMC_ZCAL_WAIT_CNT,
438 EMC_MRS_WAIT_CNT2,
439 EMC_CTT,
440 EMC_CTT_DURATION,
441 EMC_CFG_PIPE,
442 EMC_DYN_SELF_REF_CONTROL,
443 EMC_QPOP
444};
445
446struct emc_timing {
447 unsigned long rate;
448
449 u32 emc_burst_data[ARRAY_SIZE(emc_burst_regs)];
450
451 u32 emc_auto_cal_config;
452 u32 emc_auto_cal_config2;
453 u32 emc_auto_cal_config3;
454 u32 emc_auto_cal_interval;
455 u32 emc_bgbias_ctl0;
456 u32 emc_cfg;
457 u32 emc_cfg_2;
458 u32 emc_ctt_term_ctrl;
459 u32 emc_mode_1;
460 u32 emc_mode_2;
461 u32 emc_mode_4;
462 u32 emc_mode_reset;
463 u32 emc_mrs_wait_cnt;
464 u32 emc_sel_dpd_ctrl;
465 u32 emc_xm2dqspadctrl2;
466 u32 emc_zcal_cnt_long;
467 u32 emc_zcal_interval;
468};
469
470enum emc_rate_request_type {
471 EMC_RATE_DEBUG,
472 EMC_RATE_ICC,
473 EMC_RATE_TYPE_MAX,
474};
475
476struct emc_rate_request {
477 unsigned long min_rate;
478 unsigned long max_rate;
479};
480
481struct tegra_emc {
482 struct device *dev;
483
484 struct tegra_mc *mc;
485
486 void __iomem *regs;
487
488 struct clk *clk;
489
490 enum emc_dram_type dram_type;
491 unsigned int dram_bus_width;
492 unsigned int dram_num;
493
494 struct emc_timing last_timing;
495 struct emc_timing *timings;
496 unsigned int num_timings;
497
498 struct {
499 struct dentry *root;
500 unsigned long min_rate;
501 unsigned long max_rate;
502 } debugfs;
503
504 struct icc_provider provider;
505
506 /*
507 * There are multiple sources in the EMC driver which could request
508 * a min/max clock rate, these rates are contained in this array.
509 */
510 struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX];
511
512 /* protect shared rate-change code path */
513 struct mutex rate_lock;
514};
515
516/* Timing change sequence functions */
517
518static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value,
519 unsigned long offset)
520{
521 writel(value, emc->regs + EMC_CCFIFO_DATA);
522 writel(offset, emc->regs + EMC_CCFIFO_ADDR);
523}
524
525static void emc_seq_update_timing(struct tegra_emc *emc)
526{
527 unsigned int i;
528 u32 value;
529
530 writel(1, emc->regs + EMC_TIMING_CONTROL);
531
532 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
533 value = readl(emc->regs + EMC_STATUS);
534 if ((value & EMC_STATUS_TIMING_UPDATE_STALLED) == 0)
535 return;
536 udelay(1);
537 }
538
539 dev_err(emc->dev, "timing update timed out\n");
540}
541
542static void emc_seq_disable_auto_cal(struct tegra_emc *emc)
543{
544 unsigned int i;
545 u32 value;
546
547 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
548
549 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
550 value = readl(emc->regs + EMC_AUTO_CAL_STATUS);
551 if ((value & EMC_AUTO_CAL_STATUS_ACTIVE) == 0)
552 return;
553 udelay(1);
554 }
555
556 dev_err(emc->dev, "auto cal disable timed out\n");
557}
558
559static void emc_seq_wait_clkchange(struct tegra_emc *emc)
560{
561 unsigned int i;
562 u32 value;
563
564 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
565 value = readl(emc->regs + EMC_INTSTATUS);
566 if (value & EMC_INTSTATUS_CLKCHANGE_COMPLETE)
567 return;
568 udelay(1);
569 }
570
571 dev_err(emc->dev, "clock change timed out\n");
572}
573
574static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
575 unsigned long rate)
576{
577 struct emc_timing *timing = NULL;
578 unsigned int i;
579
580 for (i = 0; i < emc->num_timings; i++) {
581 if (emc->timings[i].rate == rate) {
582 timing = &emc->timings[i];
583 break;
584 }
585 }
586
587 if (!timing) {
588 dev_err(emc->dev, "no timing for rate %lu\n", rate);
589 return NULL;
590 }
591
592 return timing;
593}
594
595static int tegra_emc_prepare_timing_change(struct tegra_emc *emc,
596 unsigned long rate)
597{
598 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
599 struct emc_timing *last = &emc->last_timing;
600 enum emc_dll_change dll_change;
601 unsigned int pre_wait = 0;
602 u32 val, val2, mask;
603 bool update = false;
604 unsigned int i;
605
606 if (!timing)
607 return -ENOENT;
608
609 if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1))
610 dll_change = DLL_CHANGE_NONE;
611 else if (timing->emc_mode_1 & 0x1)
612 dll_change = DLL_CHANGE_ON;
613 else
614 dll_change = DLL_CHANGE_OFF;
615
616 /* Clear CLKCHANGE_COMPLETE interrupts */
617 writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS);
618
619 /* Disable dynamic self-refresh */
620 val = readl(emc->regs + EMC_CFG);
621 if (val & EMC_CFG_PWR_MASK) {
622 val &= ~EMC_CFG_POWER_FEATURES_MASK;
623 writel(val, emc->regs + EMC_CFG);
624
625 pre_wait = 5;
626 }
627
628 /* Disable SEL_DPD_CTRL for clock change */
629 if (emc->dram_type == DRAM_TYPE_DDR3)
630 mask = EMC_SEL_DPD_CTRL_DDR3_MASK;
631 else
632 mask = EMC_SEL_DPD_CTRL_MASK;
633
634 val = readl(emc->regs + EMC_SEL_DPD_CTRL);
635 if (val & mask) {
636 val &= ~mask;
637 writel(val, emc->regs + EMC_SEL_DPD_CTRL);
638 }
639
640 /* Prepare DQ/DQS for clock change */
641 val = readl(emc->regs + EMC_BGBIAS_CTL0);
642 val2 = last->emc_bgbias_ctl0;
643 if (!(timing->emc_bgbias_ctl0 &
644 EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) &&
645 (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX)) {
646 val2 &= ~EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX;
647 update = true;
648 }
649
650 if ((val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD) ||
651 (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN)) {
652 update = true;
653 }
654
655 if (update) {
656 writel(val2, emc->regs + EMC_BGBIAS_CTL0);
657 if (pre_wait < 5)
658 pre_wait = 5;
659 }
660
661 update = false;
662 val = readl(emc->regs + EMC_XM2DQSPADCTRL2);
663 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE &&
664 !(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) {
665 val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE;
666 update = true;
667 }
668
669 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE &&
670 !(val & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE)) {
671 val |= EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE;
672 update = true;
673 }
674
675 if (update) {
676 writel(val, emc->regs + EMC_XM2DQSPADCTRL2);
677 if (pre_wait < 30)
678 pre_wait = 30;
679 }
680
681 /* Wait to settle */
682 if (pre_wait) {
683 emc_seq_update_timing(emc);
684 udelay(pre_wait);
685 }
686
687 /* Program CTT_TERM control */
688 if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) {
689 emc_seq_disable_auto_cal(emc);
690 writel(timing->emc_ctt_term_ctrl,
691 emc->regs + EMC_CTT_TERM_CTRL);
692 emc_seq_update_timing(emc);
693 }
694
695 /* Program burst shadow registers */
696 for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i)
697 writel(timing->emc_burst_data[i],
698 emc->regs + emc_burst_regs[i]);
699
700 writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2);
701 writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL);
702
703 tegra_mc_write_emem_configuration(emc->mc, timing->rate);
704
705 val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK;
706 emc_ccfifo_writel(emc, val, EMC_CFG);
707
708 /* Program AUTO_CAL_CONFIG */
709 if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2)
710 emc_ccfifo_writel(emc, timing->emc_auto_cal_config2,
711 EMC_AUTO_CAL_CONFIG2);
712
713 if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3)
714 emc_ccfifo_writel(emc, timing->emc_auto_cal_config3,
715 EMC_AUTO_CAL_CONFIG3);
716
717 if (timing->emc_auto_cal_config != last->emc_auto_cal_config) {
718 val = timing->emc_auto_cal_config;
719 val &= EMC_AUTO_CAL_CONFIG_AUTO_CAL_START;
720 emc_ccfifo_writel(emc, val, EMC_AUTO_CAL_CONFIG);
721 }
722
723 /* DDR3: predict MRS long wait count */
724 if (emc->dram_type == DRAM_TYPE_DDR3 &&
725 dll_change == DLL_CHANGE_ON) {
726 u32 cnt = 512;
727
728 if (timing->emc_zcal_interval != 0 &&
729 last->emc_zcal_interval == 0)
730 cnt -= emc->dram_num * 256;
731
732 val = (timing->emc_mrs_wait_cnt
733 & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK)
734 >> EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT;
735 if (cnt < val)
736 cnt = val;
737
738 val = timing->emc_mrs_wait_cnt
739 & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
740 val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
741 & EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
742
743 writel(val, emc->regs + EMC_MRS_WAIT_CNT);
744 }
745
746 val = timing->emc_cfg_2;
747 val &= ~EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR;
748 emc_ccfifo_writel(emc, val, EMC_CFG_2);
749
750 /* DDR3: Turn off DLL and enter self-refresh */
751 if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF)
752 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
753
754 /* Disable refresh controller */
755 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num),
756 EMC_REFCTRL);
757 if (emc->dram_type == DRAM_TYPE_DDR3)
758 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num) |
759 EMC_SELF_REF_CMD_ENABLED,
760 EMC_SELF_REF);
761
762 /* Flow control marker */
763 emc_ccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
764
765 /* DDR3: Exit self-refresh */
766 if (emc->dram_type == DRAM_TYPE_DDR3)
767 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num),
768 EMC_SELF_REF);
769 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num) |
770 EMC_REFCTRL_ENABLE,
771 EMC_REFCTRL);
772
773 /* Set DRAM mode registers */
774 if (emc->dram_type == DRAM_TYPE_DDR3) {
775 if (timing->emc_mode_1 != last->emc_mode_1)
776 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
777 if (timing->emc_mode_2 != last->emc_mode_2)
778 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2);
779
780 if ((timing->emc_mode_reset != last->emc_mode_reset) ||
781 dll_change == DLL_CHANGE_ON) {
782 val = timing->emc_mode_reset;
783 if (dll_change == DLL_CHANGE_ON) {
784 val |= EMC_MODE_SET_DLL_RESET;
785 val |= EMC_MODE_SET_LONG_CNT;
786 } else {
787 val &= ~EMC_MODE_SET_DLL_RESET;
788 }
789 emc_ccfifo_writel(emc, val, EMC_MRS);
790 }
791 } else {
792 if (timing->emc_mode_2 != last->emc_mode_2)
793 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2);
794 if (timing->emc_mode_1 != last->emc_mode_1)
795 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW);
796 if (timing->emc_mode_4 != last->emc_mode_4)
797 emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4);
798 }
799
800 /* Issue ZCAL command if turning ZCAL on */
801 if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) {
802 emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL);
803 if (emc->dram_num > 1)
804 emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV1,
805 EMC_ZQ_CAL);
806 }
807
808 /* Write to RO register to remove stall after change */
809 emc_ccfifo_writel(emc, 0, EMC_CCFIFO_STATUS);
810
811 if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR)
812 emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2);
813
814 /* Disable AUTO_CAL for clock change */
815 emc_seq_disable_auto_cal(emc);
816
817 /* Read register to wait until programming has settled */
818 readl(emc->regs + EMC_INTSTATUS);
819
820 return 0;
821}
822
823static void tegra_emc_complete_timing_change(struct tegra_emc *emc,
824 unsigned long rate)
825{
826 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
827 struct emc_timing *last = &emc->last_timing;
828 u32 val;
829
830 if (!timing)
831 return;
832
833 /* Wait until the state machine has settled */
834 emc_seq_wait_clkchange(emc);
835
836 /* Restore AUTO_CAL */
837 if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl)
838 writel(timing->emc_auto_cal_interval,
839 emc->regs + EMC_AUTO_CAL_INTERVAL);
840
841 /* Restore dynamic self-refresh */
842 if (timing->emc_cfg & EMC_CFG_PWR_MASK)
843 writel(timing->emc_cfg, emc->regs + EMC_CFG);
844
845 /* Set ZCAL wait count */
846 writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT);
847
848 /* LPDDR3: Turn off BGBIAS if low frequency */
849 if (emc->dram_type == DRAM_TYPE_LPDDR3 &&
850 timing->emc_bgbias_ctl0 &
851 EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) {
852 val = timing->emc_bgbias_ctl0;
853 val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN;
854 val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD;
855 writel(val, emc->regs + EMC_BGBIAS_CTL0);
856 } else {
857 if (emc->dram_type == DRAM_TYPE_DDR3 &&
858 readl(emc->regs + EMC_BGBIAS_CTL0) !=
859 timing->emc_bgbias_ctl0) {
860 writel(timing->emc_bgbias_ctl0,
861 emc->regs + EMC_BGBIAS_CTL0);
862 }
863
864 writel(timing->emc_auto_cal_interval,
865 emc->regs + EMC_AUTO_CAL_INTERVAL);
866 }
867
868 /* Wait for timing to settle */
869 udelay(2);
870
871 /* Reprogram SEL_DPD_CTRL */
872 writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL);
873 emc_seq_update_timing(emc);
874
875 emc->last_timing = *timing;
876}
877
878/* Initialization and deinitialization */
879
880static void emc_read_current_timing(struct tegra_emc *emc,
881 struct emc_timing *timing)
882{
883 unsigned int i;
884
885 for (i = 0; i < ARRAY_SIZE(emc_burst_regs); ++i)
886 timing->emc_burst_data[i] =
887 readl(emc->regs + emc_burst_regs[i]);
888
889 timing->emc_cfg = readl(emc->regs + EMC_CFG);
890
891 timing->emc_auto_cal_interval = 0;
892 timing->emc_zcal_cnt_long = 0;
893 timing->emc_mode_1 = 0;
894 timing->emc_mode_2 = 0;
895 timing->emc_mode_4 = 0;
896 timing->emc_mode_reset = 0;
897}
898
899static int emc_init(struct tegra_emc *emc)
900{
901 emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5);
902
903 if (emc->dram_type & EMC_FBIO_CFG5_DRAM_WIDTH_X64)
904 emc->dram_bus_width = 64;
905 else
906 emc->dram_bus_width = 32;
907
908 dev_info_once(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width);
909
910 emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK;
911 emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT;
912
913 emc->dram_num = tegra_mc_get_emem_device_count(emc->mc);
914
915 emc_read_current_timing(emc, &emc->last_timing);
916
917 return 0;
918}
919
920static int load_one_timing_from_dt(struct tegra_emc *emc,
921 struct emc_timing *timing,
922 struct device_node *node)
923{
924 u32 value;
925 int err;
926
927 err = of_property_read_u32(node, "clock-frequency", &value);
928 if (err) {
929 dev_err(emc->dev, "timing %pOFn: failed to read rate: %d\n",
930 node, err);
931 return err;
932 }
933
934 timing->rate = value;
935
936 err = of_property_read_u32_array(node, "nvidia,emc-configuration",
937 timing->emc_burst_data,
938 ARRAY_SIZE(timing->emc_burst_data));
939 if (err) {
940 dev_err(emc->dev,
941 "timing %pOFn: failed to read emc burst data: %d\n",
942 node, err);
943 return err;
944 }
945
946#define EMC_READ_PROP(prop, dtprop) { \
947 err = of_property_read_u32(node, dtprop, &timing->prop); \
948 if (err) { \
949 dev_err(emc->dev, "timing %pOFn: failed to read " #prop ": %d\n", \
950 node, err); \
951 return err; \
952 } \
953}
954
955 EMC_READ_PROP(emc_auto_cal_config, "nvidia,emc-auto-cal-config")
956 EMC_READ_PROP(emc_auto_cal_config2, "nvidia,emc-auto-cal-config2")
957 EMC_READ_PROP(emc_auto_cal_config3, "nvidia,emc-auto-cal-config3")
958 EMC_READ_PROP(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval")
959 EMC_READ_PROP(emc_bgbias_ctl0, "nvidia,emc-bgbias-ctl0")
960 EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg")
961 EMC_READ_PROP(emc_cfg_2, "nvidia,emc-cfg-2")
962 EMC_READ_PROP(emc_ctt_term_ctrl, "nvidia,emc-ctt-term-ctrl")
963 EMC_READ_PROP(emc_mode_1, "nvidia,emc-mode-1")
964 EMC_READ_PROP(emc_mode_2, "nvidia,emc-mode-2")
965 EMC_READ_PROP(emc_mode_4, "nvidia,emc-mode-4")
966 EMC_READ_PROP(emc_mode_reset, "nvidia,emc-mode-reset")
967 EMC_READ_PROP(emc_mrs_wait_cnt, "nvidia,emc-mrs-wait-cnt")
968 EMC_READ_PROP(emc_sel_dpd_ctrl, "nvidia,emc-sel-dpd-ctrl")
969 EMC_READ_PROP(emc_xm2dqspadctrl2, "nvidia,emc-xm2dqspadctrl2")
970 EMC_READ_PROP(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long")
971 EMC_READ_PROP(emc_zcal_interval, "nvidia,emc-zcal-interval")
972
973#undef EMC_READ_PROP
974
975 return 0;
976}
977
978static int cmp_timings(const void *_a, const void *_b)
979{
980 const struct emc_timing *a = _a;
981 const struct emc_timing *b = _b;
982
983 if (a->rate < b->rate)
984 return -1;
985 else if (a->rate == b->rate)
986 return 0;
987 else
988 return 1;
989}
990
991static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
992 struct device_node *node)
993{
994 int child_count = of_get_child_count(node);
995 struct device_node *child;
996 struct emc_timing *timing;
997 unsigned int i = 0;
998 int err;
999
1000 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
1001 GFP_KERNEL);
1002 if (!emc->timings)
1003 return -ENOMEM;
1004
1005 emc->num_timings = child_count;
1006
1007 for_each_child_of_node(node, child) {
1008 timing = &emc->timings[i++];
1009
1010 err = load_one_timing_from_dt(emc, timing, child);
1011 if (err) {
1012 of_node_put(child);
1013 return err;
1014 }
1015 }
1016
1017 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
1018 NULL);
1019
1020 return 0;
1021}
1022
1023static const struct of_device_id tegra_emc_of_match[] = {
1024 { .compatible = "nvidia,tegra124-emc" },
1025 { .compatible = "nvidia,tegra132-emc" },
1026 {}
1027};
1028MODULE_DEVICE_TABLE(of, tegra_emc_of_match);
1029
1030static struct device_node *
1031tegra_emc_find_node_by_ram_code(struct device_node *node, u32 ram_code)
1032{
1033 struct device_node *np;
1034 int err;
1035
1036 for_each_child_of_node(node, np) {
1037 u32 value;
1038
1039 err = of_property_read_u32(np, "nvidia,ram-code", &value);
1040 if (err || (value != ram_code))
1041 continue;
1042
1043 return np;
1044 }
1045
1046 return NULL;
1047}
1048
1049static void tegra_emc_rate_requests_init(struct tegra_emc *emc)
1050{
1051 unsigned int i;
1052
1053 for (i = 0; i < EMC_RATE_TYPE_MAX; i++) {
1054 emc->requested_rate[i].min_rate = 0;
1055 emc->requested_rate[i].max_rate = ULONG_MAX;
1056 }
1057}
1058
1059static int emc_request_rate(struct tegra_emc *emc,
1060 unsigned long new_min_rate,
1061 unsigned long new_max_rate,
1062 enum emc_rate_request_type type)
1063{
1064 struct emc_rate_request *req = emc->requested_rate;
1065 unsigned long min_rate = 0, max_rate = ULONG_MAX;
1066 unsigned int i;
1067 int err;
1068
1069 /* select minimum and maximum rates among the requested rates */
1070 for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) {
1071 if (i == type) {
1072 min_rate = max(new_min_rate, min_rate);
1073 max_rate = min(new_max_rate, max_rate);
1074 } else {
1075 min_rate = max(req->min_rate, min_rate);
1076 max_rate = min(req->max_rate, max_rate);
1077 }
1078 }
1079
1080 if (min_rate > max_rate) {
1081 dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n",
1082 __func__, type, min_rate, max_rate);
1083 return -ERANGE;
1084 }
1085
1086 /*
1087 * EMC rate-changes should go via OPP API because it manages voltage
1088 * changes.
1089 */
1090 err = dev_pm_opp_set_rate(emc->dev, min_rate);
1091 if (err)
1092 return err;
1093
1094 emc->requested_rate[type].min_rate = new_min_rate;
1095 emc->requested_rate[type].max_rate = new_max_rate;
1096
1097 return 0;
1098}
1099
1100static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,
1101 enum emc_rate_request_type type)
1102{
1103 struct emc_rate_request *req = &emc->requested_rate[type];
1104 int ret;
1105
1106 mutex_lock(&emc->rate_lock);
1107 ret = emc_request_rate(emc, rate, req->max_rate, type);
1108 mutex_unlock(&emc->rate_lock);
1109
1110 return ret;
1111}
1112
1113static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,
1114 enum emc_rate_request_type type)
1115{
1116 struct emc_rate_request *req = &emc->requested_rate[type];
1117 int ret;
1118
1119 mutex_lock(&emc->rate_lock);
1120 ret = emc_request_rate(emc, req->min_rate, rate, type);
1121 mutex_unlock(&emc->rate_lock);
1122
1123 return ret;
1124}
1125
1126/*
1127 * debugfs interface
1128 *
1129 * The memory controller driver exposes some files in debugfs that can be used
1130 * to control the EMC frequency. The top-level directory can be found here:
1131 *
1132 * /sys/kernel/debug/emc
1133 *
1134 * It contains the following files:
1135 *
1136 * - available_rates: This file contains a list of valid, space-separated
1137 * EMC frequencies.
1138 *
1139 * - min_rate: Writing a value to this file sets the given frequency as the
1140 * floor of the permitted range. If this is higher than the currently
1141 * configured EMC frequency, this will cause the frequency to be
1142 * increased so that it stays within the valid range.
1143 *
1144 * - max_rate: Similarily to the min_rate file, writing a value to this file
1145 * sets the given frequency as the ceiling of the permitted range. If
1146 * the value is lower than the currently configured EMC frequency, this
1147 * will cause the frequency to be decreased so that it stays within the
1148 * valid range.
1149 */
1150
1151static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
1152{
1153 unsigned int i;
1154
1155 for (i = 0; i < emc->num_timings; i++)
1156 if (rate == emc->timings[i].rate)
1157 return true;
1158
1159 return false;
1160}
1161
1162static int tegra_emc_debug_available_rates_show(struct seq_file *s,
1163 void *data)
1164{
1165 struct tegra_emc *emc = s->private;
1166 const char *prefix = "";
1167 unsigned int i;
1168
1169 for (i = 0; i < emc->num_timings; i++) {
1170 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
1171 prefix = " ";
1172 }
1173
1174 seq_puts(s, "\n");
1175
1176 return 0;
1177}
1178
1179DEFINE_SHOW_ATTRIBUTE(tegra_emc_debug_available_rates);
1180
1181static int tegra_emc_debug_min_rate_get(void *data, u64 *rate)
1182{
1183 struct tegra_emc *emc = data;
1184
1185 *rate = emc->debugfs.min_rate;
1186
1187 return 0;
1188}
1189
1190static int tegra_emc_debug_min_rate_set(void *data, u64 rate)
1191{
1192 struct tegra_emc *emc = data;
1193 int err;
1194
1195 if (!tegra_emc_validate_rate(emc, rate))
1196 return -EINVAL;
1197
1198 err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);
1199 if (err < 0)
1200 return err;
1201
1202 emc->debugfs.min_rate = rate;
1203
1204 return 0;
1205}
1206
1207DEFINE_DEBUGFS_ATTRIBUTE(tegra_emc_debug_min_rate_fops,
1208 tegra_emc_debug_min_rate_get,
1209 tegra_emc_debug_min_rate_set, "%llu\n");
1210
1211static int tegra_emc_debug_max_rate_get(void *data, u64 *rate)
1212{
1213 struct tegra_emc *emc = data;
1214
1215 *rate = emc->debugfs.max_rate;
1216
1217 return 0;
1218}
1219
1220static int tegra_emc_debug_max_rate_set(void *data, u64 rate)
1221{
1222 struct tegra_emc *emc = data;
1223 int err;
1224
1225 if (!tegra_emc_validate_rate(emc, rate))
1226 return -EINVAL;
1227
1228 err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);
1229 if (err < 0)
1230 return err;
1231
1232 emc->debugfs.max_rate = rate;
1233
1234 return 0;
1235}
1236
1237DEFINE_DEBUGFS_ATTRIBUTE(tegra_emc_debug_max_rate_fops,
1238 tegra_emc_debug_max_rate_get,
1239 tegra_emc_debug_max_rate_set, "%llu\n");
1240
1241static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc)
1242{
1243 unsigned int i;
1244 int err;
1245
1246 emc->debugfs.min_rate = ULONG_MAX;
1247 emc->debugfs.max_rate = 0;
1248
1249 for (i = 0; i < emc->num_timings; i++) {
1250 if (emc->timings[i].rate < emc->debugfs.min_rate)
1251 emc->debugfs.min_rate = emc->timings[i].rate;
1252
1253 if (emc->timings[i].rate > emc->debugfs.max_rate)
1254 emc->debugfs.max_rate = emc->timings[i].rate;
1255 }
1256
1257 if (!emc->num_timings) {
1258 emc->debugfs.min_rate = clk_get_rate(emc->clk);
1259 emc->debugfs.max_rate = emc->debugfs.min_rate;
1260 }
1261
1262 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
1263 emc->debugfs.max_rate);
1264 if (err < 0) {
1265 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
1266 emc->debugfs.min_rate, emc->debugfs.max_rate,
1267 emc->clk);
1268 return;
1269 }
1270
1271 emc->debugfs.root = debugfs_create_dir("emc", NULL);
1272
1273 debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc,
1274 &tegra_emc_debug_available_rates_fops);
1275 debugfs_create_file("min_rate", 0644, emc->debugfs.root,
1276 emc, &tegra_emc_debug_min_rate_fops);
1277 debugfs_create_file("max_rate", 0644, emc->debugfs.root,
1278 emc, &tegra_emc_debug_max_rate_fops);
1279}
1280
1281static inline struct tegra_emc *
1282to_tegra_emc_provider(struct icc_provider *provider)
1283{
1284 return container_of(provider, struct tegra_emc, provider);
1285}
1286
1287static struct icc_node_data *
1288emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
1289{
1290 struct icc_provider *provider = data;
1291 struct icc_node_data *ndata;
1292 struct icc_node *node;
1293
1294 /* External Memory is the only possible ICC route */
1295 list_for_each_entry(node, &provider->nodes, node_list) {
1296 if (node->id != TEGRA_ICC_EMEM)
1297 continue;
1298
1299 ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
1300 if (!ndata)
1301 return ERR_PTR(-ENOMEM);
1302
1303 /*
1304 * SRC and DST nodes should have matching TAG in order to have
1305 * it set by default for a requested path.
1306 */
1307 ndata->tag = TEGRA_MC_ICC_TAG_ISO;
1308 ndata->node = node;
1309
1310 return ndata;
1311 }
1312
1313 return ERR_PTR(-EPROBE_DEFER);
1314}
1315
1316static int emc_icc_set(struct icc_node *src, struct icc_node *dst)
1317{
1318 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider);
1319 unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw);
1320 unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw);
1321 unsigned long long rate = max(avg_bw, peak_bw);
1322 unsigned int dram_data_bus_width_bytes;
1323 const unsigned int ddr = 2;
1324 int err;
1325
1326 /*
1327 * Tegra124 EMC runs on a clock rate of SDRAM bus. This means that
1328 * EMC clock rate is twice smaller than the peak data rate because
1329 * data is sampled on both EMC clock edges.
1330 */
1331 dram_data_bus_width_bytes = emc->dram_bus_width / 8;
1332 do_div(rate, ddr * dram_data_bus_width_bytes);
1333 rate = min_t(u64, rate, U32_MAX);
1334
1335 err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);
1336 if (err)
1337 return err;
1338
1339 return 0;
1340}
1341
1342static int tegra_emc_interconnect_init(struct tegra_emc *emc)
1343{
1344 const struct tegra_mc_soc *soc = emc->mc->soc;
1345 struct icc_node *node;
1346 int err;
1347
1348 emc->provider.dev = emc->dev;
1349 emc->provider.set = emc_icc_set;
1350 emc->provider.data = &emc->provider;
1351 emc->provider.aggregate = soc->icc_ops->aggregate;
1352 emc->provider.xlate_extended = emc_of_icc_xlate_extended;
1353
1354 icc_provider_init(&emc->provider);
1355
1356 /* create External Memory Controller node */
1357 node = icc_node_create(TEGRA_ICC_EMC);
1358 if (IS_ERR(node)) {
1359 err = PTR_ERR(node);
1360 goto err_msg;
1361 }
1362
1363 node->name = "External Memory Controller";
1364 icc_node_add(node, &emc->provider);
1365
1366 /* link External Memory Controller to External Memory (DRAM) */
1367 err = icc_link_create(node, TEGRA_ICC_EMEM);
1368 if (err)
1369 goto remove_nodes;
1370
1371 /* create External Memory node */
1372 node = icc_node_create(TEGRA_ICC_EMEM);
1373 if (IS_ERR(node)) {
1374 err = PTR_ERR(node);
1375 goto remove_nodes;
1376 }
1377
1378 node->name = "External Memory (DRAM)";
1379 icc_node_add(node, &emc->provider);
1380
1381 err = icc_provider_register(&emc->provider);
1382 if (err)
1383 goto remove_nodes;
1384
1385 return 0;
1386
1387remove_nodes:
1388 icc_nodes_remove(&emc->provider);
1389err_msg:
1390 dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
1391
1392 return err;
1393}
1394
1395static int tegra_emc_opp_table_init(struct tegra_emc *emc)
1396{
1397 u32 hw_version = BIT(tegra_sku_info.soc_speedo_id);
1398 int opp_token, err;
1399
1400 err = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1);
1401 if (err < 0) {
1402 dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err);
1403 return err;
1404 }
1405 opp_token = err;
1406
1407 err = dev_pm_opp_of_add_table(emc->dev);
1408 if (err) {
1409 if (err == -ENODEV)
1410 dev_err(emc->dev, "OPP table not found, please update your device tree\n");
1411 else
1412 dev_err(emc->dev, "failed to add OPP table: %d\n", err);
1413
1414 goto put_hw_table;
1415 }
1416
1417 dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
1418 hw_version, clk_get_rate(emc->clk) / 1000000);
1419
1420 /* first dummy rate-set initializes voltage state */
1421 err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));
1422 if (err) {
1423 dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err);
1424 goto remove_table;
1425 }
1426
1427 return 0;
1428
1429remove_table:
1430 dev_pm_opp_of_remove_table(emc->dev);
1431put_hw_table:
1432 dev_pm_opp_put_supported_hw(opp_token);
1433
1434 return err;
1435}
1436
1437static void devm_tegra_emc_unset_callback(void *data)
1438{
1439 tegra124_clk_set_emc_callbacks(NULL, NULL);
1440}
1441
1442static int tegra_emc_probe(struct platform_device *pdev)
1443{
1444 struct device_node *np;
1445 struct tegra_emc *emc;
1446 u32 ram_code;
1447 int err;
1448
1449 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
1450 if (!emc)
1451 return -ENOMEM;
1452
1453 mutex_init(&emc->rate_lock);
1454 emc->dev = &pdev->dev;
1455
1456 emc->regs = devm_platform_ioremap_resource(pdev, 0);
1457 if (IS_ERR(emc->regs))
1458 return PTR_ERR(emc->regs);
1459
1460 emc->mc = devm_tegra_memory_controller_get(&pdev->dev);
1461 if (IS_ERR(emc->mc))
1462 return PTR_ERR(emc->mc);
1463
1464 ram_code = tegra_read_ram_code();
1465
1466 np = tegra_emc_find_node_by_ram_code(pdev->dev.of_node, ram_code);
1467 if (np) {
1468 err = tegra_emc_load_timings_from_dt(emc, np);
1469 of_node_put(np);
1470 if (err)
1471 return err;
1472 } else {
1473 dev_info_once(&pdev->dev,
1474 "no memory timings for RAM code %u found in DT\n",
1475 ram_code);
1476 }
1477
1478 err = emc_init(emc);
1479 if (err) {
1480 dev_err(&pdev->dev, "EMC initialization failed: %d\n", err);
1481 return err;
1482 }
1483
1484 platform_set_drvdata(pdev, emc);
1485
1486 tegra124_clk_set_emc_callbacks(tegra_emc_prepare_timing_change,
1487 tegra_emc_complete_timing_change);
1488
1489 err = devm_add_action_or_reset(&pdev->dev, devm_tegra_emc_unset_callback,
1490 NULL);
1491 if (err)
1492 return err;
1493
1494 emc->clk = devm_clk_get(&pdev->dev, "emc");
1495 if (IS_ERR(emc->clk)) {
1496 err = PTR_ERR(emc->clk);
1497 dev_err(&pdev->dev, "failed to get EMC clock: %d\n", err);
1498 return err;
1499 }
1500
1501 err = tegra_emc_opp_table_init(emc);
1502 if (err)
1503 return err;
1504
1505 tegra_emc_rate_requests_init(emc);
1506
1507 if (IS_ENABLED(CONFIG_DEBUG_FS))
1508 emc_debugfs_init(&pdev->dev, emc);
1509
1510 tegra_emc_interconnect_init(emc);
1511
1512 /*
1513 * Don't allow the kernel module to be unloaded. Unloading adds some
1514 * extra complexity which doesn't really worth the effort in a case of
1515 * this driver.
1516 */
1517 try_module_get(THIS_MODULE);
1518
1519 return 0;
1520};
1521
1522static struct platform_driver tegra_emc_driver = {
1523 .probe = tegra_emc_probe,
1524 .driver = {
1525 .name = "tegra-emc",
1526 .of_match_table = tegra_emc_of_match,
1527 .suppress_bind_attrs = true,
1528 .sync_state = icc_sync_state,
1529 },
1530};
1531module_platform_driver(tegra_emc_driver);
1532
1533MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
1534MODULE_DESCRIPTION("NVIDIA Tegra124 EMC driver");
1535MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
4 *
5 * Author:
6 * Mikko Perttunen <mperttunen@nvidia.com>
7 */
8
9#include <linux/clk-provider.h>
10#include <linux/clk.h>
11#include <linux/clkdev.h>
12#include <linux/debugfs.h>
13#include <linux/delay.h>
14#include <linux/io.h>
15#include <linux/of_address.h>
16#include <linux/of_platform.h>
17#include <linux/platform_device.h>
18#include <linux/sort.h>
19#include <linux/string.h>
20
21#include <soc/tegra/emc.h>
22#include <soc/tegra/fuse.h>
23#include <soc/tegra/mc.h>
24
25#define EMC_FBIO_CFG5 0x104
26#define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
27#define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0
28
29#define EMC_INTSTATUS 0x0
30#define EMC_INTSTATUS_CLKCHANGE_COMPLETE BIT(4)
31
32#define EMC_CFG 0xc
33#define EMC_CFG_DRAM_CLKSTOP_PD BIT(31)
34#define EMC_CFG_DRAM_CLKSTOP_SR BIT(30)
35#define EMC_CFG_DRAM_ACPD BIT(29)
36#define EMC_CFG_DYN_SREF BIT(28)
37#define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18))
38#define EMC_CFG_DSR_VTTGEN_DRV_EN BIT(18)
39
40#define EMC_REFCTRL 0x20
41#define EMC_REFCTRL_DEV_SEL_SHIFT 0
42#define EMC_REFCTRL_ENABLE BIT(31)
43
44#define EMC_TIMING_CONTROL 0x28
45#define EMC_RC 0x2c
46#define EMC_RFC 0x30
47#define EMC_RAS 0x34
48#define EMC_RP 0x38
49#define EMC_R2W 0x3c
50#define EMC_W2R 0x40
51#define EMC_R2P 0x44
52#define EMC_W2P 0x48
53#define EMC_RD_RCD 0x4c
54#define EMC_WR_RCD 0x50
55#define EMC_RRD 0x54
56#define EMC_REXT 0x58
57#define EMC_WDV 0x5c
58#define EMC_QUSE 0x60
59#define EMC_QRST 0x64
60#define EMC_QSAFE 0x68
61#define EMC_RDV 0x6c
62#define EMC_REFRESH 0x70
63#define EMC_BURST_REFRESH_NUM 0x74
64#define EMC_PDEX2WR 0x78
65#define EMC_PDEX2RD 0x7c
66#define EMC_PCHG2PDEN 0x80
67#define EMC_ACT2PDEN 0x84
68#define EMC_AR2PDEN 0x88
69#define EMC_RW2PDEN 0x8c
70#define EMC_TXSR 0x90
71#define EMC_TCKE 0x94
72#define EMC_TFAW 0x98
73#define EMC_TRPAB 0x9c
74#define EMC_TCLKSTABLE 0xa0
75#define EMC_TCLKSTOP 0xa4
76#define EMC_TREFBW 0xa8
77#define EMC_ODT_WRITE 0xb0
78#define EMC_ODT_READ 0xb4
79#define EMC_WEXT 0xb8
80#define EMC_CTT 0xbc
81#define EMC_RFC_SLR 0xc0
82#define EMC_MRS_WAIT_CNT2 0xc4
83
84#define EMC_MRS_WAIT_CNT 0xc8
85#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0
86#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \
87 (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
88#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16
89#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \
90 (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
91
92#define EMC_MRS 0xcc
93#define EMC_MODE_SET_DLL_RESET BIT(8)
94#define EMC_MODE_SET_LONG_CNT BIT(26)
95#define EMC_EMRS 0xd0
96#define EMC_REF 0xd4
97#define EMC_PRE 0xd8
98
99#define EMC_SELF_REF 0xe0
100#define EMC_SELF_REF_CMD_ENABLED BIT(0)
101#define EMC_SELF_REF_DEV_SEL_SHIFT 30
102
103#define EMC_MRW 0xe8
104
105#define EMC_MRR 0xec
106#define EMC_MRR_MA_SHIFT 16
107#define LPDDR2_MR4_TEMP_SHIFT 0
108
109#define EMC_XM2DQSPADCTRL3 0xf8
110#define EMC_FBIO_SPARE 0x100
111
112#define EMC_FBIO_CFG6 0x114
113#define EMC_EMRS2 0x12c
114#define EMC_MRW2 0x134
115#define EMC_MRW4 0x13c
116#define EMC_EINPUT 0x14c
117#define EMC_EINPUT_DURATION 0x150
118#define EMC_PUTERM_EXTRA 0x154
119#define EMC_TCKESR 0x158
120#define EMC_TPD 0x15c
121
122#define EMC_AUTO_CAL_CONFIG 0x2a4
123#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START BIT(31)
124#define EMC_AUTO_CAL_INTERVAL 0x2a8
125#define EMC_AUTO_CAL_STATUS 0x2ac
126#define EMC_AUTO_CAL_STATUS_ACTIVE BIT(31)
127#define EMC_STATUS 0x2b4
128#define EMC_STATUS_TIMING_UPDATE_STALLED BIT(23)
129
130#define EMC_CFG_2 0x2b8
131#define EMC_CFG_2_MODE_SHIFT 0
132#define EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR BIT(6)
133
134#define EMC_CFG_DIG_DLL 0x2bc
135#define EMC_CFG_DIG_DLL_PERIOD 0x2c0
136#define EMC_RDV_MASK 0x2cc
137#define EMC_WDV_MASK 0x2d0
138#define EMC_CTT_DURATION 0x2d8
139#define EMC_CTT_TERM_CTRL 0x2dc
140#define EMC_ZCAL_INTERVAL 0x2e0
141#define EMC_ZCAL_WAIT_CNT 0x2e4
142
143#define EMC_ZQ_CAL 0x2ec
144#define EMC_ZQ_CAL_CMD BIT(0)
145#define EMC_ZQ_CAL_LONG BIT(4)
146#define EMC_ZQ_CAL_LONG_CMD_DEV0 \
147 (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
148#define EMC_ZQ_CAL_LONG_CMD_DEV1 \
149 (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
150
151#define EMC_XM2CMDPADCTRL 0x2f0
152#define EMC_XM2DQSPADCTRL 0x2f8
153#define EMC_XM2DQSPADCTRL2 0x2fc
154#define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE BIT(0)
155#define EMC_XM2DQSPADCTRL2_VREF_ENABLE BIT(5)
156#define EMC_XM2DQPADCTRL 0x300
157#define EMC_XM2DQPADCTRL2 0x304
158#define EMC_XM2CLKPADCTRL 0x308
159#define EMC_XM2COMPPADCTRL 0x30c
160#define EMC_XM2VTTGENPADCTRL 0x310
161#define EMC_XM2VTTGENPADCTRL2 0x314
162#define EMC_XM2VTTGENPADCTRL3 0x318
163#define EMC_XM2DQSPADCTRL4 0x320
164#define EMC_DLL_XFORM_DQS0 0x328
165#define EMC_DLL_XFORM_DQS1 0x32c
166#define EMC_DLL_XFORM_DQS2 0x330
167#define EMC_DLL_XFORM_DQS3 0x334
168#define EMC_DLL_XFORM_DQS4 0x338
169#define EMC_DLL_XFORM_DQS5 0x33c
170#define EMC_DLL_XFORM_DQS6 0x340
171#define EMC_DLL_XFORM_DQS7 0x344
172#define EMC_DLL_XFORM_QUSE0 0x348
173#define EMC_DLL_XFORM_QUSE1 0x34c
174#define EMC_DLL_XFORM_QUSE2 0x350
175#define EMC_DLL_XFORM_QUSE3 0x354
176#define EMC_DLL_XFORM_QUSE4 0x358
177#define EMC_DLL_XFORM_QUSE5 0x35c
178#define EMC_DLL_XFORM_QUSE6 0x360
179#define EMC_DLL_XFORM_QUSE7 0x364
180#define EMC_DLL_XFORM_DQ0 0x368
181#define EMC_DLL_XFORM_DQ1 0x36c
182#define EMC_DLL_XFORM_DQ2 0x370
183#define EMC_DLL_XFORM_DQ3 0x374
184#define EMC_DLI_TRIM_TXDQS0 0x3a8
185#define EMC_DLI_TRIM_TXDQS1 0x3ac
186#define EMC_DLI_TRIM_TXDQS2 0x3b0
187#define EMC_DLI_TRIM_TXDQS3 0x3b4
188#define EMC_DLI_TRIM_TXDQS4 0x3b8
189#define EMC_DLI_TRIM_TXDQS5 0x3bc
190#define EMC_DLI_TRIM_TXDQS6 0x3c0
191#define EMC_DLI_TRIM_TXDQS7 0x3c4
192#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc
193#define EMC_SEL_DPD_CTRL 0x3d8
194#define EMC_SEL_DPD_CTRL_DATA_SEL_DPD BIT(8)
195#define EMC_SEL_DPD_CTRL_ODT_SEL_DPD BIT(5)
196#define EMC_SEL_DPD_CTRL_RESET_SEL_DPD BIT(4)
197#define EMC_SEL_DPD_CTRL_CA_SEL_DPD BIT(3)
198#define EMC_SEL_DPD_CTRL_CLK_SEL_DPD BIT(2)
199#define EMC_SEL_DPD_CTRL_DDR3_MASK \
200 ((0xf << 2) | BIT(8))
201#define EMC_SEL_DPD_CTRL_MASK \
202 ((0x3 << 2) | BIT(5) | BIT(8))
203#define EMC_PRE_REFRESH_REQ_CNT 0x3dc
204#define EMC_DYN_SELF_REF_CONTROL 0x3e0
205#define EMC_TXSRDLL 0x3e4
206#define EMC_CCFIFO_ADDR 0x3e8
207#define EMC_CCFIFO_DATA 0x3ec
208#define EMC_CCFIFO_STATUS 0x3f0
209#define EMC_CDB_CNTL_1 0x3f4
210#define EMC_CDB_CNTL_2 0x3f8
211#define EMC_XM2CLKPADCTRL2 0x3fc
212#define EMC_AUTO_CAL_CONFIG2 0x458
213#define EMC_AUTO_CAL_CONFIG3 0x45c
214#define EMC_IBDLY 0x468
215#define EMC_DLL_XFORM_ADDR0 0x46c
216#define EMC_DLL_XFORM_ADDR1 0x470
217#define EMC_DLL_XFORM_ADDR2 0x474
218#define EMC_DSR_VTTGEN_DRV 0x47c
219#define EMC_TXDSRVTTGEN 0x480
220#define EMC_XM2CMDPADCTRL4 0x484
221#define EMC_XM2CMDPADCTRL5 0x488
222#define EMC_DLL_XFORM_DQS8 0x4a0
223#define EMC_DLL_XFORM_DQS9 0x4a4
224#define EMC_DLL_XFORM_DQS10 0x4a8
225#define EMC_DLL_XFORM_DQS11 0x4ac
226#define EMC_DLL_XFORM_DQS12 0x4b0
227#define EMC_DLL_XFORM_DQS13 0x4b4
228#define EMC_DLL_XFORM_DQS14 0x4b8
229#define EMC_DLL_XFORM_DQS15 0x4bc
230#define EMC_DLL_XFORM_QUSE8 0x4c0
231#define EMC_DLL_XFORM_QUSE9 0x4c4
232#define EMC_DLL_XFORM_QUSE10 0x4c8
233#define EMC_DLL_XFORM_QUSE11 0x4cc
234#define EMC_DLL_XFORM_QUSE12 0x4d0
235#define EMC_DLL_XFORM_QUSE13 0x4d4
236#define EMC_DLL_XFORM_QUSE14 0x4d8
237#define EMC_DLL_XFORM_QUSE15 0x4dc
238#define EMC_DLL_XFORM_DQ4 0x4e0
239#define EMC_DLL_XFORM_DQ5 0x4e4
240#define EMC_DLL_XFORM_DQ6 0x4e8
241#define EMC_DLL_XFORM_DQ7 0x4ec
242#define EMC_DLI_TRIM_TXDQS8 0x520
243#define EMC_DLI_TRIM_TXDQS9 0x524
244#define EMC_DLI_TRIM_TXDQS10 0x528
245#define EMC_DLI_TRIM_TXDQS11 0x52c
246#define EMC_DLI_TRIM_TXDQS12 0x530
247#define EMC_DLI_TRIM_TXDQS13 0x534
248#define EMC_DLI_TRIM_TXDQS14 0x538
249#define EMC_DLI_TRIM_TXDQS15 0x53c
250#define EMC_CDB_CNTL_3 0x540
251#define EMC_XM2DQSPADCTRL5 0x544
252#define EMC_XM2DQSPADCTRL6 0x548
253#define EMC_XM2DQPADCTRL3 0x54c
254#define EMC_DLL_XFORM_ADDR3 0x550
255#define EMC_DLL_XFORM_ADDR4 0x554
256#define EMC_DLL_XFORM_ADDR5 0x558
257#define EMC_CFG_PIPE 0x560
258#define EMC_QPOP 0x564
259#define EMC_QUSE_WIDTH 0x568
260#define EMC_PUTERM_WIDTH 0x56c
261#define EMC_BGBIAS_CTL0 0x570
262#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX BIT(3)
263#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN BIT(2)
264#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD BIT(1)
265#define EMC_PUTERM_ADJ 0x574
266
267#define DRAM_DEV_SEL_ALL 0
268#define DRAM_DEV_SEL_0 (2 << 30)
269#define DRAM_DEV_SEL_1 (1 << 30)
270
271#define EMC_CFG_POWER_FEATURES_MASK \
272 (EMC_CFG_DYN_SREF | EMC_CFG_DRAM_ACPD | EMC_CFG_DRAM_CLKSTOP_SR | \
273 EMC_CFG_DRAM_CLKSTOP_PD | EMC_CFG_DSR_VTTGEN_DRV_EN)
274#define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
275#define EMC_DRAM_DEV_SEL(n) ((n > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
276
277/* Maximum amount of time in us. to wait for changes to become effective */
278#define EMC_STATUS_UPDATE_TIMEOUT 1000
279
280enum emc_dram_type {
281 DRAM_TYPE_DDR3 = 0,
282 DRAM_TYPE_DDR1 = 1,
283 DRAM_TYPE_LPDDR3 = 2,
284 DRAM_TYPE_DDR2 = 3
285};
286
287enum emc_dll_change {
288 DLL_CHANGE_NONE,
289 DLL_CHANGE_ON,
290 DLL_CHANGE_OFF
291};
292
293static const unsigned long emc_burst_regs[] = {
294 EMC_RC,
295 EMC_RFC,
296 EMC_RFC_SLR,
297 EMC_RAS,
298 EMC_RP,
299 EMC_R2W,
300 EMC_W2R,
301 EMC_R2P,
302 EMC_W2P,
303 EMC_RD_RCD,
304 EMC_WR_RCD,
305 EMC_RRD,
306 EMC_REXT,
307 EMC_WEXT,
308 EMC_WDV,
309 EMC_WDV_MASK,
310 EMC_QUSE,
311 EMC_QUSE_WIDTH,
312 EMC_IBDLY,
313 EMC_EINPUT,
314 EMC_EINPUT_DURATION,
315 EMC_PUTERM_EXTRA,
316 EMC_PUTERM_WIDTH,
317 EMC_PUTERM_ADJ,
318 EMC_CDB_CNTL_1,
319 EMC_CDB_CNTL_2,
320 EMC_CDB_CNTL_3,
321 EMC_QRST,
322 EMC_QSAFE,
323 EMC_RDV,
324 EMC_RDV_MASK,
325 EMC_REFRESH,
326 EMC_BURST_REFRESH_NUM,
327 EMC_PRE_REFRESH_REQ_CNT,
328 EMC_PDEX2WR,
329 EMC_PDEX2RD,
330 EMC_PCHG2PDEN,
331 EMC_ACT2PDEN,
332 EMC_AR2PDEN,
333 EMC_RW2PDEN,
334 EMC_TXSR,
335 EMC_TXSRDLL,
336 EMC_TCKE,
337 EMC_TCKESR,
338 EMC_TPD,
339 EMC_TFAW,
340 EMC_TRPAB,
341 EMC_TCLKSTABLE,
342 EMC_TCLKSTOP,
343 EMC_TREFBW,
344 EMC_FBIO_CFG6,
345 EMC_ODT_WRITE,
346 EMC_ODT_READ,
347 EMC_FBIO_CFG5,
348 EMC_CFG_DIG_DLL,
349 EMC_CFG_DIG_DLL_PERIOD,
350 EMC_DLL_XFORM_DQS0,
351 EMC_DLL_XFORM_DQS1,
352 EMC_DLL_XFORM_DQS2,
353 EMC_DLL_XFORM_DQS3,
354 EMC_DLL_XFORM_DQS4,
355 EMC_DLL_XFORM_DQS5,
356 EMC_DLL_XFORM_DQS6,
357 EMC_DLL_XFORM_DQS7,
358 EMC_DLL_XFORM_DQS8,
359 EMC_DLL_XFORM_DQS9,
360 EMC_DLL_XFORM_DQS10,
361 EMC_DLL_XFORM_DQS11,
362 EMC_DLL_XFORM_DQS12,
363 EMC_DLL_XFORM_DQS13,
364 EMC_DLL_XFORM_DQS14,
365 EMC_DLL_XFORM_DQS15,
366 EMC_DLL_XFORM_QUSE0,
367 EMC_DLL_XFORM_QUSE1,
368 EMC_DLL_XFORM_QUSE2,
369 EMC_DLL_XFORM_QUSE3,
370 EMC_DLL_XFORM_QUSE4,
371 EMC_DLL_XFORM_QUSE5,
372 EMC_DLL_XFORM_QUSE6,
373 EMC_DLL_XFORM_QUSE7,
374 EMC_DLL_XFORM_ADDR0,
375 EMC_DLL_XFORM_ADDR1,
376 EMC_DLL_XFORM_ADDR2,
377 EMC_DLL_XFORM_ADDR3,
378 EMC_DLL_XFORM_ADDR4,
379 EMC_DLL_XFORM_ADDR5,
380 EMC_DLL_XFORM_QUSE8,
381 EMC_DLL_XFORM_QUSE9,
382 EMC_DLL_XFORM_QUSE10,
383 EMC_DLL_XFORM_QUSE11,
384 EMC_DLL_XFORM_QUSE12,
385 EMC_DLL_XFORM_QUSE13,
386 EMC_DLL_XFORM_QUSE14,
387 EMC_DLL_XFORM_QUSE15,
388 EMC_DLI_TRIM_TXDQS0,
389 EMC_DLI_TRIM_TXDQS1,
390 EMC_DLI_TRIM_TXDQS2,
391 EMC_DLI_TRIM_TXDQS3,
392 EMC_DLI_TRIM_TXDQS4,
393 EMC_DLI_TRIM_TXDQS5,
394 EMC_DLI_TRIM_TXDQS6,
395 EMC_DLI_TRIM_TXDQS7,
396 EMC_DLI_TRIM_TXDQS8,
397 EMC_DLI_TRIM_TXDQS9,
398 EMC_DLI_TRIM_TXDQS10,
399 EMC_DLI_TRIM_TXDQS11,
400 EMC_DLI_TRIM_TXDQS12,
401 EMC_DLI_TRIM_TXDQS13,
402 EMC_DLI_TRIM_TXDQS14,
403 EMC_DLI_TRIM_TXDQS15,
404 EMC_DLL_XFORM_DQ0,
405 EMC_DLL_XFORM_DQ1,
406 EMC_DLL_XFORM_DQ2,
407 EMC_DLL_XFORM_DQ3,
408 EMC_DLL_XFORM_DQ4,
409 EMC_DLL_XFORM_DQ5,
410 EMC_DLL_XFORM_DQ6,
411 EMC_DLL_XFORM_DQ7,
412 EMC_XM2CMDPADCTRL,
413 EMC_XM2CMDPADCTRL4,
414 EMC_XM2CMDPADCTRL5,
415 EMC_XM2DQPADCTRL2,
416 EMC_XM2DQPADCTRL3,
417 EMC_XM2CLKPADCTRL,
418 EMC_XM2CLKPADCTRL2,
419 EMC_XM2COMPPADCTRL,
420 EMC_XM2VTTGENPADCTRL,
421 EMC_XM2VTTGENPADCTRL2,
422 EMC_XM2VTTGENPADCTRL3,
423 EMC_XM2DQSPADCTRL3,
424 EMC_XM2DQSPADCTRL4,
425 EMC_XM2DQSPADCTRL5,
426 EMC_XM2DQSPADCTRL6,
427 EMC_DSR_VTTGEN_DRV,
428 EMC_TXDSRVTTGEN,
429 EMC_FBIO_SPARE,
430 EMC_ZCAL_WAIT_CNT,
431 EMC_MRS_WAIT_CNT2,
432 EMC_CTT,
433 EMC_CTT_DURATION,
434 EMC_CFG_PIPE,
435 EMC_DYN_SELF_REF_CONTROL,
436 EMC_QPOP
437};
438
439struct emc_timing {
440 unsigned long rate;
441
442 u32 emc_burst_data[ARRAY_SIZE(emc_burst_regs)];
443
444 u32 emc_auto_cal_config;
445 u32 emc_auto_cal_config2;
446 u32 emc_auto_cal_config3;
447 u32 emc_auto_cal_interval;
448 u32 emc_bgbias_ctl0;
449 u32 emc_cfg;
450 u32 emc_cfg_2;
451 u32 emc_ctt_term_ctrl;
452 u32 emc_mode_1;
453 u32 emc_mode_2;
454 u32 emc_mode_4;
455 u32 emc_mode_reset;
456 u32 emc_mrs_wait_cnt;
457 u32 emc_sel_dpd_ctrl;
458 u32 emc_xm2dqspadctrl2;
459 u32 emc_zcal_cnt_long;
460 u32 emc_zcal_interval;
461};
462
463struct tegra_emc {
464 struct device *dev;
465
466 struct tegra_mc *mc;
467
468 void __iomem *regs;
469
470 enum emc_dram_type dram_type;
471 unsigned int dram_num;
472
473 struct emc_timing last_timing;
474 struct emc_timing *timings;
475 unsigned int num_timings;
476};
477
478/* Timing change sequence functions */
479
480static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value,
481 unsigned long offset)
482{
483 writel(value, emc->regs + EMC_CCFIFO_DATA);
484 writel(offset, emc->regs + EMC_CCFIFO_ADDR);
485}
486
487static void emc_seq_update_timing(struct tegra_emc *emc)
488{
489 unsigned int i;
490 u32 value;
491
492 writel(1, emc->regs + EMC_TIMING_CONTROL);
493
494 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
495 value = readl(emc->regs + EMC_STATUS);
496 if ((value & EMC_STATUS_TIMING_UPDATE_STALLED) == 0)
497 return;
498 udelay(1);
499 }
500
501 dev_err(emc->dev, "timing update timed out\n");
502}
503
504static void emc_seq_disable_auto_cal(struct tegra_emc *emc)
505{
506 unsigned int i;
507 u32 value;
508
509 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
510
511 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
512 value = readl(emc->regs + EMC_AUTO_CAL_STATUS);
513 if ((value & EMC_AUTO_CAL_STATUS_ACTIVE) == 0)
514 return;
515 udelay(1);
516 }
517
518 dev_err(emc->dev, "auto cal disable timed out\n");
519}
520
521static void emc_seq_wait_clkchange(struct tegra_emc *emc)
522{
523 unsigned int i;
524 u32 value;
525
526 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
527 value = readl(emc->regs + EMC_INTSTATUS);
528 if (value & EMC_INTSTATUS_CLKCHANGE_COMPLETE)
529 return;
530 udelay(1);
531 }
532
533 dev_err(emc->dev, "clock change timed out\n");
534}
535
536static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
537 unsigned long rate)
538{
539 struct emc_timing *timing = NULL;
540 unsigned int i;
541
542 for (i = 0; i < emc->num_timings; i++) {
543 if (emc->timings[i].rate == rate) {
544 timing = &emc->timings[i];
545 break;
546 }
547 }
548
549 if (!timing) {
550 dev_err(emc->dev, "no timing for rate %lu\n", rate);
551 return NULL;
552 }
553
554 return timing;
555}
556
557int tegra_emc_prepare_timing_change(struct tegra_emc *emc,
558 unsigned long rate)
559{
560 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
561 struct emc_timing *last = &emc->last_timing;
562 enum emc_dll_change dll_change;
563 unsigned int pre_wait = 0;
564 u32 val, val2, mask;
565 bool update = false;
566 unsigned int i;
567
568 if (!timing)
569 return -ENOENT;
570
571 if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1))
572 dll_change = DLL_CHANGE_NONE;
573 else if (timing->emc_mode_1 & 0x1)
574 dll_change = DLL_CHANGE_ON;
575 else
576 dll_change = DLL_CHANGE_OFF;
577
578 /* Clear CLKCHANGE_COMPLETE interrupts */
579 writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS);
580
581 /* Disable dynamic self-refresh */
582 val = readl(emc->regs + EMC_CFG);
583 if (val & EMC_CFG_PWR_MASK) {
584 val &= ~EMC_CFG_POWER_FEATURES_MASK;
585 writel(val, emc->regs + EMC_CFG);
586
587 pre_wait = 5;
588 }
589
590 /* Disable SEL_DPD_CTRL for clock change */
591 if (emc->dram_type == DRAM_TYPE_DDR3)
592 mask = EMC_SEL_DPD_CTRL_DDR3_MASK;
593 else
594 mask = EMC_SEL_DPD_CTRL_MASK;
595
596 val = readl(emc->regs + EMC_SEL_DPD_CTRL);
597 if (val & mask) {
598 val &= ~mask;
599 writel(val, emc->regs + EMC_SEL_DPD_CTRL);
600 }
601
602 /* Prepare DQ/DQS for clock change */
603 val = readl(emc->regs + EMC_BGBIAS_CTL0);
604 val2 = last->emc_bgbias_ctl0;
605 if (!(timing->emc_bgbias_ctl0 &
606 EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) &&
607 (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX)) {
608 val2 &= ~EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX;
609 update = true;
610 }
611
612 if ((val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD) ||
613 (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN)) {
614 update = true;
615 }
616
617 if (update) {
618 writel(val2, emc->regs + EMC_BGBIAS_CTL0);
619 if (pre_wait < 5)
620 pre_wait = 5;
621 }
622
623 update = false;
624 val = readl(emc->regs + EMC_XM2DQSPADCTRL2);
625 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE &&
626 !(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) {
627 val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE;
628 update = true;
629 }
630
631 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE &&
632 !(val & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE)) {
633 val |= EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE;
634 update = true;
635 }
636
637 if (update) {
638 writel(val, emc->regs + EMC_XM2DQSPADCTRL2);
639 if (pre_wait < 30)
640 pre_wait = 30;
641 }
642
643 /* Wait to settle */
644 if (pre_wait) {
645 emc_seq_update_timing(emc);
646 udelay(pre_wait);
647 }
648
649 /* Program CTT_TERM control */
650 if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) {
651 emc_seq_disable_auto_cal(emc);
652 writel(timing->emc_ctt_term_ctrl,
653 emc->regs + EMC_CTT_TERM_CTRL);
654 emc_seq_update_timing(emc);
655 }
656
657 /* Program burst shadow registers */
658 for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i)
659 writel(timing->emc_burst_data[i],
660 emc->regs + emc_burst_regs[i]);
661
662 writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2);
663 writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL);
664
665 tegra_mc_write_emem_configuration(emc->mc, timing->rate);
666
667 val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK;
668 emc_ccfifo_writel(emc, val, EMC_CFG);
669
670 /* Program AUTO_CAL_CONFIG */
671 if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2)
672 emc_ccfifo_writel(emc, timing->emc_auto_cal_config2,
673 EMC_AUTO_CAL_CONFIG2);
674
675 if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3)
676 emc_ccfifo_writel(emc, timing->emc_auto_cal_config3,
677 EMC_AUTO_CAL_CONFIG3);
678
679 if (timing->emc_auto_cal_config != last->emc_auto_cal_config) {
680 val = timing->emc_auto_cal_config;
681 val &= EMC_AUTO_CAL_CONFIG_AUTO_CAL_START;
682 emc_ccfifo_writel(emc, val, EMC_AUTO_CAL_CONFIG);
683 }
684
685 /* DDR3: predict MRS long wait count */
686 if (emc->dram_type == DRAM_TYPE_DDR3 &&
687 dll_change == DLL_CHANGE_ON) {
688 u32 cnt = 512;
689
690 if (timing->emc_zcal_interval != 0 &&
691 last->emc_zcal_interval == 0)
692 cnt -= emc->dram_num * 256;
693
694 val = (timing->emc_mrs_wait_cnt
695 & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK)
696 >> EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT;
697 if (cnt < val)
698 cnt = val;
699
700 val = timing->emc_mrs_wait_cnt
701 & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
702 val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
703 & EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
704
705 writel(val, emc->regs + EMC_MRS_WAIT_CNT);
706 }
707
708 val = timing->emc_cfg_2;
709 val &= ~EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR;
710 emc_ccfifo_writel(emc, val, EMC_CFG_2);
711
712 /* DDR3: Turn off DLL and enter self-refresh */
713 if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF)
714 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
715
716 /* Disable refresh controller */
717 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num),
718 EMC_REFCTRL);
719 if (emc->dram_type == DRAM_TYPE_DDR3)
720 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num) |
721 EMC_SELF_REF_CMD_ENABLED,
722 EMC_SELF_REF);
723
724 /* Flow control marker */
725 emc_ccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
726
727 /* DDR3: Exit self-refresh */
728 if (emc->dram_type == DRAM_TYPE_DDR3)
729 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num),
730 EMC_SELF_REF);
731 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num) |
732 EMC_REFCTRL_ENABLE,
733 EMC_REFCTRL);
734
735 /* Set DRAM mode registers */
736 if (emc->dram_type == DRAM_TYPE_DDR3) {
737 if (timing->emc_mode_1 != last->emc_mode_1)
738 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
739 if (timing->emc_mode_2 != last->emc_mode_2)
740 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2);
741
742 if ((timing->emc_mode_reset != last->emc_mode_reset) ||
743 dll_change == DLL_CHANGE_ON) {
744 val = timing->emc_mode_reset;
745 if (dll_change == DLL_CHANGE_ON) {
746 val |= EMC_MODE_SET_DLL_RESET;
747 val |= EMC_MODE_SET_LONG_CNT;
748 } else {
749 val &= ~EMC_MODE_SET_DLL_RESET;
750 }
751 emc_ccfifo_writel(emc, val, EMC_MRS);
752 }
753 } else {
754 if (timing->emc_mode_2 != last->emc_mode_2)
755 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2);
756 if (timing->emc_mode_1 != last->emc_mode_1)
757 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW);
758 if (timing->emc_mode_4 != last->emc_mode_4)
759 emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4);
760 }
761
762 /* Issue ZCAL command if turning ZCAL on */
763 if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) {
764 emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL);
765 if (emc->dram_num > 1)
766 emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV1,
767 EMC_ZQ_CAL);
768 }
769
770 /* Write to RO register to remove stall after change */
771 emc_ccfifo_writel(emc, 0, EMC_CCFIFO_STATUS);
772
773 if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR)
774 emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2);
775
776 /* Disable AUTO_CAL for clock change */
777 emc_seq_disable_auto_cal(emc);
778
779 /* Read register to wait until programming has settled */
780 readl(emc->regs + EMC_INTSTATUS);
781
782 return 0;
783}
784
785void tegra_emc_complete_timing_change(struct tegra_emc *emc,
786 unsigned long rate)
787{
788 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
789 struct emc_timing *last = &emc->last_timing;
790 u32 val;
791
792 if (!timing)
793 return;
794
795 /* Wait until the state machine has settled */
796 emc_seq_wait_clkchange(emc);
797
798 /* Restore AUTO_CAL */
799 if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl)
800 writel(timing->emc_auto_cal_interval,
801 emc->regs + EMC_AUTO_CAL_INTERVAL);
802
803 /* Restore dynamic self-refresh */
804 if (timing->emc_cfg & EMC_CFG_PWR_MASK)
805 writel(timing->emc_cfg, emc->regs + EMC_CFG);
806
807 /* Set ZCAL wait count */
808 writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT);
809
810 /* LPDDR3: Turn off BGBIAS if low frequency */
811 if (emc->dram_type == DRAM_TYPE_LPDDR3 &&
812 timing->emc_bgbias_ctl0 &
813 EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) {
814 val = timing->emc_bgbias_ctl0;
815 val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN;
816 val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD;
817 writel(val, emc->regs + EMC_BGBIAS_CTL0);
818 } else {
819 if (emc->dram_type == DRAM_TYPE_DDR3 &&
820 readl(emc->regs + EMC_BGBIAS_CTL0) !=
821 timing->emc_bgbias_ctl0) {
822 writel(timing->emc_bgbias_ctl0,
823 emc->regs + EMC_BGBIAS_CTL0);
824 }
825
826 writel(timing->emc_auto_cal_interval,
827 emc->regs + EMC_AUTO_CAL_INTERVAL);
828 }
829
830 /* Wait for timing to settle */
831 udelay(2);
832
833 /* Reprogram SEL_DPD_CTRL */
834 writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL);
835 emc_seq_update_timing(emc);
836
837 emc->last_timing = *timing;
838}
839
840/* Initialization and deinitialization */
841
842static void emc_read_current_timing(struct tegra_emc *emc,
843 struct emc_timing *timing)
844{
845 unsigned int i;
846
847 for (i = 0; i < ARRAY_SIZE(emc_burst_regs); ++i)
848 timing->emc_burst_data[i] =
849 readl(emc->regs + emc_burst_regs[i]);
850
851 timing->emc_cfg = readl(emc->regs + EMC_CFG);
852
853 timing->emc_auto_cal_interval = 0;
854 timing->emc_zcal_cnt_long = 0;
855 timing->emc_mode_1 = 0;
856 timing->emc_mode_2 = 0;
857 timing->emc_mode_4 = 0;
858 timing->emc_mode_reset = 0;
859}
860
861static int emc_init(struct tegra_emc *emc)
862{
863 emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5);
864 emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK;
865 emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT;
866
867 emc->dram_num = tegra_mc_get_emem_device_count(emc->mc);
868
869 emc_read_current_timing(emc, &emc->last_timing);
870
871 return 0;
872}
873
874static int load_one_timing_from_dt(struct tegra_emc *emc,
875 struct emc_timing *timing,
876 struct device_node *node)
877{
878 u32 value;
879 int err;
880
881 err = of_property_read_u32(node, "clock-frequency", &value);
882 if (err) {
883 dev_err(emc->dev, "timing %pOFn: failed to read rate: %d\n",
884 node, err);
885 return err;
886 }
887
888 timing->rate = value;
889
890 err = of_property_read_u32_array(node, "nvidia,emc-configuration",
891 timing->emc_burst_data,
892 ARRAY_SIZE(timing->emc_burst_data));
893 if (err) {
894 dev_err(emc->dev,
895 "timing %pOFn: failed to read emc burst data: %d\n",
896 node, err);
897 return err;
898 }
899
900#define EMC_READ_PROP(prop, dtprop) { \
901 err = of_property_read_u32(node, dtprop, &timing->prop); \
902 if (err) { \
903 dev_err(emc->dev, "timing %pOFn: failed to read " #prop ": %d\n", \
904 node, err); \
905 return err; \
906 } \
907}
908
909 EMC_READ_PROP(emc_auto_cal_config, "nvidia,emc-auto-cal-config")
910 EMC_READ_PROP(emc_auto_cal_config2, "nvidia,emc-auto-cal-config2")
911 EMC_READ_PROP(emc_auto_cal_config3, "nvidia,emc-auto-cal-config3")
912 EMC_READ_PROP(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval")
913 EMC_READ_PROP(emc_bgbias_ctl0, "nvidia,emc-bgbias-ctl0")
914 EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg")
915 EMC_READ_PROP(emc_cfg_2, "nvidia,emc-cfg-2")
916 EMC_READ_PROP(emc_ctt_term_ctrl, "nvidia,emc-ctt-term-ctrl")
917 EMC_READ_PROP(emc_mode_1, "nvidia,emc-mode-1")
918 EMC_READ_PROP(emc_mode_2, "nvidia,emc-mode-2")
919 EMC_READ_PROP(emc_mode_4, "nvidia,emc-mode-4")
920 EMC_READ_PROP(emc_mode_reset, "nvidia,emc-mode-reset")
921 EMC_READ_PROP(emc_mrs_wait_cnt, "nvidia,emc-mrs-wait-cnt")
922 EMC_READ_PROP(emc_sel_dpd_ctrl, "nvidia,emc-sel-dpd-ctrl")
923 EMC_READ_PROP(emc_xm2dqspadctrl2, "nvidia,emc-xm2dqspadctrl2")
924 EMC_READ_PROP(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long")
925 EMC_READ_PROP(emc_zcal_interval, "nvidia,emc-zcal-interval")
926
927#undef EMC_READ_PROP
928
929 return 0;
930}
931
932static int cmp_timings(const void *_a, const void *_b)
933{
934 const struct emc_timing *a = _a;
935 const struct emc_timing *b = _b;
936
937 if (a->rate < b->rate)
938 return -1;
939 else if (a->rate == b->rate)
940 return 0;
941 else
942 return 1;
943}
944
945static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
946 struct device_node *node)
947{
948 int child_count = of_get_child_count(node);
949 struct device_node *child;
950 struct emc_timing *timing;
951 unsigned int i = 0;
952 int err;
953
954 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
955 GFP_KERNEL);
956 if (!emc->timings)
957 return -ENOMEM;
958
959 emc->num_timings = child_count;
960
961 for_each_child_of_node(node, child) {
962 timing = &emc->timings[i++];
963
964 err = load_one_timing_from_dt(emc, timing, child);
965 if (err) {
966 of_node_put(child);
967 return err;
968 }
969 }
970
971 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
972 NULL);
973
974 return 0;
975}
976
977static const struct of_device_id tegra_emc_of_match[] = {
978 { .compatible = "nvidia,tegra124-emc" },
979 {}
980};
981
982static struct device_node *
983tegra_emc_find_node_by_ram_code(struct device_node *node, u32 ram_code)
984{
985 struct device_node *np;
986 int err;
987
988 for_each_child_of_node(node, np) {
989 u32 value;
990
991 err = of_property_read_u32(np, "nvidia,ram-code", &value);
992 if (err || (value != ram_code))
993 continue;
994
995 return np;
996 }
997
998 return NULL;
999}
1000
1001/* Debugfs entry */
1002
1003static int emc_debug_rate_get(void *data, u64 *rate)
1004{
1005 struct clk *c = data;
1006
1007 *rate = clk_get_rate(c);
1008
1009 return 0;
1010}
1011
1012static int emc_debug_rate_set(void *data, u64 rate)
1013{
1014 struct clk *c = data;
1015
1016 return clk_set_rate(c, rate);
1017}
1018
1019DEFINE_SIMPLE_ATTRIBUTE(emc_debug_rate_fops, emc_debug_rate_get,
1020 emc_debug_rate_set, "%lld\n");
1021
1022static int emc_debug_supported_rates_show(struct seq_file *s, void *data)
1023{
1024 struct tegra_emc *emc = s->private;
1025 const char *prefix = "";
1026 unsigned int i;
1027
1028 for (i = 0; i < emc->num_timings; i++) {
1029 struct emc_timing *timing = &emc->timings[i];
1030
1031 seq_printf(s, "%s%lu", prefix, timing->rate);
1032
1033 prefix = " ";
1034 }
1035
1036 seq_puts(s, "\n");
1037
1038 return 0;
1039}
1040
1041static int emc_debug_supported_rates_open(struct inode *inode,
1042 struct file *file)
1043{
1044 return single_open(file, emc_debug_supported_rates_show,
1045 inode->i_private);
1046}
1047
1048static const struct file_operations emc_debug_supported_rates_fops = {
1049 .open = emc_debug_supported_rates_open,
1050 .read = seq_read,
1051 .llseek = seq_lseek,
1052 .release = single_release,
1053};
1054
1055static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc)
1056{
1057 struct dentry *root, *file;
1058 struct clk *clk;
1059
1060 root = debugfs_create_dir("emc", NULL);
1061 if (!root) {
1062 dev_err(dev, "failed to create debugfs directory\n");
1063 return;
1064 }
1065
1066 clk = clk_get_sys("tegra-clk-debug", "emc");
1067 if (IS_ERR(clk)) {
1068 dev_err(dev, "failed to get debug clock: %ld\n", PTR_ERR(clk));
1069 return;
1070 }
1071
1072 file = debugfs_create_file("rate", S_IRUGO | S_IWUSR, root, clk,
1073 &emc_debug_rate_fops);
1074 if (!file)
1075 dev_err(dev, "failed to create debugfs entry\n");
1076
1077 file = debugfs_create_file("supported_rates", S_IRUGO, root, emc,
1078 &emc_debug_supported_rates_fops);
1079 if (!file)
1080 dev_err(dev, "failed to create debugfs entry\n");
1081}
1082
1083static int tegra_emc_probe(struct platform_device *pdev)
1084{
1085 struct platform_device *mc;
1086 struct device_node *np;
1087 struct tegra_emc *emc;
1088 struct resource *res;
1089 u32 ram_code;
1090 int err;
1091
1092 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
1093 if (!emc)
1094 return -ENOMEM;
1095
1096 emc->dev = &pdev->dev;
1097
1098 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1099 emc->regs = devm_ioremap_resource(&pdev->dev, res);
1100 if (IS_ERR(emc->regs))
1101 return PTR_ERR(emc->regs);
1102
1103 np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0);
1104 if (!np) {
1105 dev_err(&pdev->dev, "could not get memory controller\n");
1106 return -ENOENT;
1107 }
1108
1109 mc = of_find_device_by_node(np);
1110 of_node_put(np);
1111 if (!mc)
1112 return -ENOENT;
1113
1114 emc->mc = platform_get_drvdata(mc);
1115 if (!emc->mc)
1116 return -EPROBE_DEFER;
1117
1118 ram_code = tegra_read_ram_code();
1119
1120 np = tegra_emc_find_node_by_ram_code(pdev->dev.of_node, ram_code);
1121 if (!np) {
1122 dev_err(&pdev->dev,
1123 "no memory timings for RAM code %u found in DT\n",
1124 ram_code);
1125 return -ENOENT;
1126 }
1127
1128 err = tegra_emc_load_timings_from_dt(emc, np);
1129 of_node_put(np);
1130 if (err)
1131 return err;
1132
1133 if (emc->num_timings == 0) {
1134 dev_err(&pdev->dev,
1135 "no memory timings for RAM code %u registered\n",
1136 ram_code);
1137 return -ENOENT;
1138 }
1139
1140 err = emc_init(emc);
1141 if (err) {
1142 dev_err(&pdev->dev, "EMC initialization failed: %d\n", err);
1143 return err;
1144 }
1145
1146 platform_set_drvdata(pdev, emc);
1147
1148 if (IS_ENABLED(CONFIG_DEBUG_FS))
1149 emc_debugfs_init(&pdev->dev, emc);
1150
1151 return 0;
1152};
1153
1154static struct platform_driver tegra_emc_driver = {
1155 .probe = tegra_emc_probe,
1156 .driver = {
1157 .name = "tegra-emc",
1158 .of_match_table = tegra_emc_of_match,
1159 .suppress_bind_attrs = true,
1160 },
1161};
1162
1163static int tegra_emc_init(void)
1164{
1165 return platform_driver_register(&tegra_emc_driver);
1166}
1167subsys_initcall(tegra_emc_init);