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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 HiSilicon Limited, All Rights Reserved.
4 * Author: Jun Ma <majun258@huawei.com>
5 * Author: Yun Wu <wuyun.wu@huawei.com>
6 */
7
8#include <linux/acpi.h>
9#include <linux/interrupt.h>
10#include <linux/irqchip.h>
11#include <linux/module.h>
12#include <linux/msi.h>
13#include <linux/of_address.h>
14#include <linux/of_irq.h>
15#include <linux/of_platform.h>
16#include <linux/platform_device.h>
17#include <linux/slab.h>
18
19/* Interrupt numbers per mbigen node supported */
20#define IRQS_PER_MBIGEN_NODE 128
21
22/* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */
23#define RESERVED_IRQ_PER_MBIGEN_CHIP 64
24
25/* The maximum IRQ pin number of mbigen chip(start from 0) */
26#define MAXIMUM_IRQ_PIN_NUM 1407
27
28/*
29 * In mbigen vector register
30 * bit[21:12]: event id value
31 * bit[11:0]: device id
32 */
33#define IRQ_EVENT_ID_SHIFT 12
34#define IRQ_EVENT_ID_MASK 0x3ff
35
36/* register range of each mbigen node */
37#define MBIGEN_NODE_OFFSET 0x1000
38
39/* offset of vector register in mbigen node */
40#define REG_MBIGEN_VEC_OFFSET 0x200
41
42/*
43 * offset of clear register in mbigen node
44 * This register is used to clear the status
45 * of interrupt
46 */
47#define REG_MBIGEN_CLEAR_OFFSET 0xa000
48
49/*
50 * offset of interrupt type register
51 * This register is used to configure interrupt
52 * trigger type
53 */
54#define REG_MBIGEN_TYPE_OFFSET 0x0
55
56/**
57 * struct mbigen_device - holds the information of mbigen device.
58 *
59 * @pdev: pointer to the platform device structure of mbigen chip.
60 * @base: mapped address of this mbigen chip.
61 */
62struct mbigen_device {
63 struct platform_device *pdev;
64 void __iomem *base;
65};
66
67static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
68{
69 unsigned int nid, pin;
70
71 hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
72 nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
73 pin = hwirq % IRQS_PER_MBIGEN_NODE;
74
75 return pin * 4 + nid * MBIGEN_NODE_OFFSET
76 + REG_MBIGEN_VEC_OFFSET;
77}
78
79static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
80 u32 *mask, u32 *addr)
81{
82 unsigned int nid, irq_ofst, ofst;
83
84 hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
85 nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
86 irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE;
87
88 *mask = 1 << (irq_ofst % 32);
89 ofst = irq_ofst / 32 * 4;
90
91 *addr = ofst + nid * MBIGEN_NODE_OFFSET
92 + REG_MBIGEN_TYPE_OFFSET;
93}
94
95static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq,
96 u32 *mask, u32 *addr)
97{
98 unsigned int ofst = (hwirq / 32) * 4;
99
100 *mask = 1 << (hwirq % 32);
101 *addr = ofst + REG_MBIGEN_CLEAR_OFFSET;
102}
103
104static void mbigen_eoi_irq(struct irq_data *data)
105{
106 void __iomem *base = data->chip_data;
107 u32 mask, addr;
108
109 get_mbigen_clear_reg(data->hwirq, &mask, &addr);
110
111 writel_relaxed(mask, base + addr);
112
113 irq_chip_eoi_parent(data);
114}
115
116static int mbigen_set_type(struct irq_data *data, unsigned int type)
117{
118 void __iomem *base = data->chip_data;
119 u32 mask, addr, val;
120
121 if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
122 return -EINVAL;
123
124 get_mbigen_type_reg(data->hwirq, &mask, &addr);
125
126 val = readl_relaxed(base + addr);
127
128 if (type == IRQ_TYPE_LEVEL_HIGH)
129 val |= mask;
130 else
131 val &= ~mask;
132
133 writel_relaxed(val, base + addr);
134
135 return 0;
136}
137
138static struct irq_chip mbigen_irq_chip = {
139 .name = "mbigen-v2",
140 .irq_mask = irq_chip_mask_parent,
141 .irq_unmask = irq_chip_unmask_parent,
142 .irq_eoi = mbigen_eoi_irq,
143 .irq_set_type = mbigen_set_type,
144 .irq_set_affinity = irq_chip_set_affinity_parent,
145};
146
147static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
148{
149 struct irq_data *d = irq_get_irq_data(desc->irq);
150 void __iomem *base = d->chip_data;
151 u32 val;
152
153 if (!msg->address_lo && !msg->address_hi)
154 return;
155
156 base += get_mbigen_vec_reg(d->hwirq);
157 val = readl_relaxed(base);
158
159 val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
160 val |= (msg->data << IRQ_EVENT_ID_SHIFT);
161
162 /* The address of doorbell is encoded in mbigen register by default
163 * So,we don't need to program the doorbell address at here
164 */
165 writel_relaxed(val, base);
166}
167
168static int mbigen_domain_translate(struct irq_domain *d,
169 struct irq_fwspec *fwspec,
170 unsigned long *hwirq,
171 unsigned int *type)
172{
173 if (is_of_node(fwspec->fwnode) || is_acpi_device_node(fwspec->fwnode)) {
174 if (fwspec->param_count != 2)
175 return -EINVAL;
176
177 if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) ||
178 (fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP))
179 return -EINVAL;
180 else
181 *hwirq = fwspec->param[0];
182
183 /* If there is no valid irq type, just use the default type */
184 if ((fwspec->param[1] == IRQ_TYPE_EDGE_RISING) ||
185 (fwspec->param[1] == IRQ_TYPE_LEVEL_HIGH))
186 *type = fwspec->param[1];
187 else
188 return -EINVAL;
189
190 return 0;
191 }
192 return -EINVAL;
193}
194
195static int mbigen_irq_domain_alloc(struct irq_domain *domain,
196 unsigned int virq,
197 unsigned int nr_irqs,
198 void *args)
199{
200 struct irq_fwspec *fwspec = args;
201 irq_hw_number_t hwirq;
202 unsigned int type;
203 struct mbigen_device *mgn_chip;
204 int i, err;
205
206 err = mbigen_domain_translate(domain, fwspec, &hwirq, &type);
207 if (err)
208 return err;
209
210 err = platform_msi_device_domain_alloc(domain, virq, nr_irqs);
211 if (err)
212 return err;
213
214 mgn_chip = platform_msi_get_host_data(domain);
215
216 for (i = 0; i < nr_irqs; i++)
217 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
218 &mbigen_irq_chip, mgn_chip->base);
219
220 return 0;
221}
222
223static void mbigen_irq_domain_free(struct irq_domain *domain, unsigned int virq,
224 unsigned int nr_irqs)
225{
226 platform_msi_device_domain_free(domain, virq, nr_irqs);
227}
228
229static const struct irq_domain_ops mbigen_domain_ops = {
230 .translate = mbigen_domain_translate,
231 .alloc = mbigen_irq_domain_alloc,
232 .free = mbigen_irq_domain_free,
233};
234
235static int mbigen_of_create_domain(struct platform_device *pdev,
236 struct mbigen_device *mgn_chip)
237{
238 struct platform_device *child;
239 struct irq_domain *domain;
240 struct device_node *np;
241 u32 num_pins;
242 int ret = 0;
243
244 for_each_child_of_node(pdev->dev.of_node, np) {
245 if (!of_property_read_bool(np, "interrupt-controller"))
246 continue;
247
248 child = of_platform_device_create(np, NULL, NULL);
249 if (!child) {
250 ret = -ENOMEM;
251 break;
252 }
253
254 if (of_property_read_u32(child->dev.of_node, "num-pins",
255 &num_pins) < 0) {
256 dev_err(&pdev->dev, "No num-pins property\n");
257 ret = -EINVAL;
258 break;
259 }
260
261 domain = platform_msi_create_device_domain(&child->dev, num_pins,
262 mbigen_write_msg,
263 &mbigen_domain_ops,
264 mgn_chip);
265 if (!domain) {
266 ret = -ENOMEM;
267 break;
268 }
269 }
270
271 if (ret)
272 of_node_put(np);
273
274 return ret;
275}
276
277#ifdef CONFIG_ACPI
278static const struct acpi_device_id mbigen_acpi_match[] = {
279 { "HISI0152", 0 },
280 {}
281};
282MODULE_DEVICE_TABLE(acpi, mbigen_acpi_match);
283
284static int mbigen_acpi_create_domain(struct platform_device *pdev,
285 struct mbigen_device *mgn_chip)
286{
287 struct irq_domain *domain;
288 u32 num_pins = 0;
289 int ret;
290
291 /*
292 * "num-pins" is the total number of interrupt pins implemented in
293 * this mbigen instance, and mbigen is an interrupt controller
294 * connected to ITS converting wired interrupts into MSI, so we
295 * use "num-pins" to alloc MSI vectors which are needed by client
296 * devices connected to it.
297 *
298 * Here is the DSDT device node used for mbigen in firmware:
299 * Device(MBI0) {
300 * Name(_HID, "HISI0152")
301 * Name(_UID, Zero)
302 * Name(_CRS, ResourceTemplate() {
303 * Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
304 * })
305 *
306 * Name(_DSD, Package () {
307 * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
308 * Package () {
309 * Package () {"num-pins", 378}
310 * }
311 * })
312 * }
313 */
314 ret = device_property_read_u32(&pdev->dev, "num-pins", &num_pins);
315 if (ret || num_pins == 0)
316 return -EINVAL;
317
318 domain = platform_msi_create_device_domain(&pdev->dev, num_pins,
319 mbigen_write_msg,
320 &mbigen_domain_ops,
321 mgn_chip);
322 if (!domain)
323 return -ENOMEM;
324
325 return 0;
326}
327#else
328static inline int mbigen_acpi_create_domain(struct platform_device *pdev,
329 struct mbigen_device *mgn_chip)
330{
331 return -ENODEV;
332}
333#endif
334
335static int mbigen_device_probe(struct platform_device *pdev)
336{
337 struct mbigen_device *mgn_chip;
338 struct resource *res;
339 int err;
340
341 mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
342 if (!mgn_chip)
343 return -ENOMEM;
344
345 mgn_chip->pdev = pdev;
346
347 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
348 if (!res)
349 return -EINVAL;
350
351 mgn_chip->base = devm_ioremap(&pdev->dev, res->start,
352 resource_size(res));
353 if (!mgn_chip->base) {
354 dev_err(&pdev->dev, "failed to ioremap %pR\n", res);
355 return -ENOMEM;
356 }
357
358 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node)
359 err = mbigen_of_create_domain(pdev, mgn_chip);
360 else if (ACPI_COMPANION(&pdev->dev))
361 err = mbigen_acpi_create_domain(pdev, mgn_chip);
362 else
363 err = -EINVAL;
364
365 if (err) {
366 dev_err(&pdev->dev, "Failed to create mbi-gen irqdomain\n");
367 return err;
368 }
369
370 platform_set_drvdata(pdev, mgn_chip);
371 return 0;
372}
373
374static const struct of_device_id mbigen_of_match[] = {
375 { .compatible = "hisilicon,mbigen-v2" },
376 { /* END */ }
377};
378MODULE_DEVICE_TABLE(of, mbigen_of_match);
379
380static struct platform_driver mbigen_platform_driver = {
381 .driver = {
382 .name = "Hisilicon MBIGEN-V2",
383 .of_match_table = mbigen_of_match,
384 .acpi_match_table = ACPI_PTR(mbigen_acpi_match),
385 .suppress_bind_attrs = true,
386 },
387 .probe = mbigen_device_probe,
388};
389
390module_platform_driver(mbigen_platform_driver);
391
392MODULE_AUTHOR("Jun Ma <majun258@huawei.com>");
393MODULE_AUTHOR("Yun Wu <wuyun.wu@huawei.com>");
394MODULE_DESCRIPTION("HiSilicon MBI Generator driver");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 Hisilicon Limited, All Rights Reserved.
4 * Author: Jun Ma <majun258@huawei.com>
5 * Author: Yun Wu <wuyun.wu@huawei.com>
6 */
7
8#include <linux/acpi.h>
9#include <linux/interrupt.h>
10#include <linux/irqchip.h>
11#include <linux/module.h>
12#include <linux/msi.h>
13#include <linux/of_address.h>
14#include <linux/of_irq.h>
15#include <linux/of_platform.h>
16#include <linux/platform_device.h>
17#include <linux/slab.h>
18
19/* Interrupt numbers per mbigen node supported */
20#define IRQS_PER_MBIGEN_NODE 128
21
22/* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */
23#define RESERVED_IRQ_PER_MBIGEN_CHIP 64
24
25/* The maximum IRQ pin number of mbigen chip(start from 0) */
26#define MAXIMUM_IRQ_PIN_NUM 1407
27
28/**
29 * In mbigen vector register
30 * bit[21:12]: event id value
31 * bit[11:0]: device id
32 */
33#define IRQ_EVENT_ID_SHIFT 12
34#define IRQ_EVENT_ID_MASK 0x3ff
35
36/* register range of each mbigen node */
37#define MBIGEN_NODE_OFFSET 0x1000
38
39/* offset of vector register in mbigen node */
40#define REG_MBIGEN_VEC_OFFSET 0x200
41
42/**
43 * offset of clear register in mbigen node
44 * This register is used to clear the status
45 * of interrupt
46 */
47#define REG_MBIGEN_CLEAR_OFFSET 0xa000
48
49/**
50 * offset of interrupt type register
51 * This register is used to configure interrupt
52 * trigger type
53 */
54#define REG_MBIGEN_TYPE_OFFSET 0x0
55
56/**
57 * struct mbigen_device - holds the information of mbigen device.
58 *
59 * @pdev: pointer to the platform device structure of mbigen chip.
60 * @base: mapped address of this mbigen chip.
61 */
62struct mbigen_device {
63 struct platform_device *pdev;
64 void __iomem *base;
65};
66
67static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
68{
69 unsigned int nid, pin;
70
71 hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
72 nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
73 pin = hwirq % IRQS_PER_MBIGEN_NODE;
74
75 return pin * 4 + nid * MBIGEN_NODE_OFFSET
76 + REG_MBIGEN_VEC_OFFSET;
77}
78
79static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
80 u32 *mask, u32 *addr)
81{
82 unsigned int nid, irq_ofst, ofst;
83
84 hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
85 nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
86 irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE;
87
88 *mask = 1 << (irq_ofst % 32);
89 ofst = irq_ofst / 32 * 4;
90
91 *addr = ofst + nid * MBIGEN_NODE_OFFSET
92 + REG_MBIGEN_TYPE_OFFSET;
93}
94
95static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq,
96 u32 *mask, u32 *addr)
97{
98 unsigned int ofst = (hwirq / 32) * 4;
99
100 *mask = 1 << (hwirq % 32);
101 *addr = ofst + REG_MBIGEN_CLEAR_OFFSET;
102}
103
104static void mbigen_eoi_irq(struct irq_data *data)
105{
106 void __iomem *base = data->chip_data;
107 u32 mask, addr;
108
109 get_mbigen_clear_reg(data->hwirq, &mask, &addr);
110
111 writel_relaxed(mask, base + addr);
112
113 irq_chip_eoi_parent(data);
114}
115
116static int mbigen_set_type(struct irq_data *data, unsigned int type)
117{
118 void __iomem *base = data->chip_data;
119 u32 mask, addr, val;
120
121 if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
122 return -EINVAL;
123
124 get_mbigen_type_reg(data->hwirq, &mask, &addr);
125
126 val = readl_relaxed(base + addr);
127
128 if (type == IRQ_TYPE_LEVEL_HIGH)
129 val |= mask;
130 else
131 val &= ~mask;
132
133 writel_relaxed(val, base + addr);
134
135 return 0;
136}
137
138static struct irq_chip mbigen_irq_chip = {
139 .name = "mbigen-v2",
140 .irq_mask = irq_chip_mask_parent,
141 .irq_unmask = irq_chip_unmask_parent,
142 .irq_eoi = mbigen_eoi_irq,
143 .irq_set_type = mbigen_set_type,
144 .irq_set_affinity = irq_chip_set_affinity_parent,
145};
146
147static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
148{
149 struct irq_data *d = irq_get_irq_data(desc->irq);
150 void __iomem *base = d->chip_data;
151 u32 val;
152
153 if (!msg->address_lo && !msg->address_hi)
154 return;
155
156 base += get_mbigen_vec_reg(d->hwirq);
157 val = readl_relaxed(base);
158
159 val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
160 val |= (msg->data << IRQ_EVENT_ID_SHIFT);
161
162 /* The address of doorbell is encoded in mbigen register by default
163 * So,we don't need to program the doorbell address at here
164 */
165 writel_relaxed(val, base);
166}
167
168static int mbigen_domain_translate(struct irq_domain *d,
169 struct irq_fwspec *fwspec,
170 unsigned long *hwirq,
171 unsigned int *type)
172{
173 if (is_of_node(fwspec->fwnode) || is_acpi_device_node(fwspec->fwnode)) {
174 if (fwspec->param_count != 2)
175 return -EINVAL;
176
177 if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) ||
178 (fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP))
179 return -EINVAL;
180 else
181 *hwirq = fwspec->param[0];
182
183 /* If there is no valid irq type, just use the default type */
184 if ((fwspec->param[1] == IRQ_TYPE_EDGE_RISING) ||
185 (fwspec->param[1] == IRQ_TYPE_LEVEL_HIGH))
186 *type = fwspec->param[1];
187 else
188 return -EINVAL;
189
190 return 0;
191 }
192 return -EINVAL;
193}
194
195static int mbigen_irq_domain_alloc(struct irq_domain *domain,
196 unsigned int virq,
197 unsigned int nr_irqs,
198 void *args)
199{
200 struct irq_fwspec *fwspec = args;
201 irq_hw_number_t hwirq;
202 unsigned int type;
203 struct mbigen_device *mgn_chip;
204 int i, err;
205
206 err = mbigen_domain_translate(domain, fwspec, &hwirq, &type);
207 if (err)
208 return err;
209
210 err = platform_msi_domain_alloc(domain, virq, nr_irqs);
211 if (err)
212 return err;
213
214 mgn_chip = platform_msi_get_host_data(domain);
215
216 for (i = 0; i < nr_irqs; i++)
217 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
218 &mbigen_irq_chip, mgn_chip->base);
219
220 return 0;
221}
222
223static const struct irq_domain_ops mbigen_domain_ops = {
224 .translate = mbigen_domain_translate,
225 .alloc = mbigen_irq_domain_alloc,
226 .free = irq_domain_free_irqs_common,
227};
228
229static int mbigen_of_create_domain(struct platform_device *pdev,
230 struct mbigen_device *mgn_chip)
231{
232 struct device *parent;
233 struct platform_device *child;
234 struct irq_domain *domain;
235 struct device_node *np;
236 u32 num_pins;
237
238 for_each_child_of_node(pdev->dev.of_node, np) {
239 if (!of_property_read_bool(np, "interrupt-controller"))
240 continue;
241
242 parent = platform_bus_type.dev_root;
243 child = of_platform_device_create(np, NULL, parent);
244 if (!child) {
245 of_node_put(np);
246 return -ENOMEM;
247 }
248
249 if (of_property_read_u32(child->dev.of_node, "num-pins",
250 &num_pins) < 0) {
251 dev_err(&pdev->dev, "No num-pins property\n");
252 of_node_put(np);
253 return -EINVAL;
254 }
255
256 domain = platform_msi_create_device_domain(&child->dev, num_pins,
257 mbigen_write_msg,
258 &mbigen_domain_ops,
259 mgn_chip);
260 if (!domain) {
261 of_node_put(np);
262 return -ENOMEM;
263 }
264 }
265
266 return 0;
267}
268
269#ifdef CONFIG_ACPI
270static int mbigen_acpi_create_domain(struct platform_device *pdev,
271 struct mbigen_device *mgn_chip)
272{
273 struct irq_domain *domain;
274 u32 num_pins = 0;
275 int ret;
276
277 /*
278 * "num-pins" is the total number of interrupt pins implemented in
279 * this mbigen instance, and mbigen is an interrupt controller
280 * connected to ITS converting wired interrupts into MSI, so we
281 * use "num-pins" to alloc MSI vectors which are needed by client
282 * devices connected to it.
283 *
284 * Here is the DSDT device node used for mbigen in firmware:
285 * Device(MBI0) {
286 * Name(_HID, "HISI0152")
287 * Name(_UID, Zero)
288 * Name(_CRS, ResourceTemplate() {
289 * Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
290 * })
291 *
292 * Name(_DSD, Package () {
293 * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
294 * Package () {
295 * Package () {"num-pins", 378}
296 * }
297 * })
298 * }
299 */
300 ret = device_property_read_u32(&pdev->dev, "num-pins", &num_pins);
301 if (ret || num_pins == 0)
302 return -EINVAL;
303
304 domain = platform_msi_create_device_domain(&pdev->dev, num_pins,
305 mbigen_write_msg,
306 &mbigen_domain_ops,
307 mgn_chip);
308 if (!domain)
309 return -ENOMEM;
310
311 return 0;
312}
313#else
314static inline int mbigen_acpi_create_domain(struct platform_device *pdev,
315 struct mbigen_device *mgn_chip)
316{
317 return -ENODEV;
318}
319#endif
320
321static int mbigen_device_probe(struct platform_device *pdev)
322{
323 struct mbigen_device *mgn_chip;
324 struct resource *res;
325 int err;
326
327 mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
328 if (!mgn_chip)
329 return -ENOMEM;
330
331 mgn_chip->pdev = pdev;
332
333 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
334 if (!res)
335 return -EINVAL;
336
337 mgn_chip->base = devm_ioremap(&pdev->dev, res->start,
338 resource_size(res));
339 if (!mgn_chip->base) {
340 dev_err(&pdev->dev, "failed to ioremap %pR\n", res);
341 return -ENOMEM;
342 }
343
344 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node)
345 err = mbigen_of_create_domain(pdev, mgn_chip);
346 else if (ACPI_COMPANION(&pdev->dev))
347 err = mbigen_acpi_create_domain(pdev, mgn_chip);
348 else
349 err = -EINVAL;
350
351 if (err) {
352 dev_err(&pdev->dev, "Failed to create mbi-gen irqdomain\n");
353 return err;
354 }
355
356 platform_set_drvdata(pdev, mgn_chip);
357 return 0;
358}
359
360static const struct of_device_id mbigen_of_match[] = {
361 { .compatible = "hisilicon,mbigen-v2" },
362 { /* END */ }
363};
364MODULE_DEVICE_TABLE(of, mbigen_of_match);
365
366static const struct acpi_device_id mbigen_acpi_match[] = {
367 { "HISI0152", 0 },
368 {}
369};
370MODULE_DEVICE_TABLE(acpi, mbigen_acpi_match);
371
372static struct platform_driver mbigen_platform_driver = {
373 .driver = {
374 .name = "Hisilicon MBIGEN-V2",
375 .of_match_table = mbigen_of_match,
376 .acpi_match_table = ACPI_PTR(mbigen_acpi_match),
377 },
378 .probe = mbigen_device_probe,
379};
380
381module_platform_driver(mbigen_platform_driver);
382
383MODULE_AUTHOR("Jun Ma <majun258@huawei.com>");
384MODULE_AUTHOR("Yun Wu <wuyun.wu@huawei.com>");
385MODULE_LICENSE("GPL");
386MODULE_DESCRIPTION("Hisilicon MBI Generator driver");