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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Qualcomm SDX55 interconnect driver
4 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
5 *
6 * Copyright (c) 2021, Linaro Ltd.
7 *
8 */
9
10#include <linux/device.h>
11#include <linux/interconnect.h>
12#include <linux/interconnect-provider.h>
13#include <linux/mod_devicetable.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <dt-bindings/interconnect/qcom,sdx55.h>
17
18#include "bcm-voter.h"
19#include "icc-rpmh.h"
20#include "sdx55.h"
21
22static struct qcom_icc_node llcc_mc = {
23 .name = "llcc_mc",
24 .id = SDX55_MASTER_LLCC,
25 .channels = 4,
26 .buswidth = 4,
27 .num_links = 1,
28 .links = { SDX55_SLAVE_EBI_CH0 },
29};
30
31static struct qcom_icc_node acm_tcu = {
32 .name = "acm_tcu",
33 .id = SDX55_MASTER_TCU_0,
34 .channels = 1,
35 .buswidth = 8,
36 .num_links = 3,
37 .links = { SDX55_SLAVE_LLCC,
38 SDX55_SLAVE_MEM_NOC_SNOC,
39 SDX55_SLAVE_MEM_NOC_PCIE_SNOC
40 },
41};
42
43static struct qcom_icc_node qnm_snoc_gc = {
44 .name = "qnm_snoc_gc",
45 .id = SDX55_MASTER_SNOC_GC_MEM_NOC,
46 .channels = 1,
47 .buswidth = 8,
48 .num_links = 1,
49 .links = { SDX55_SLAVE_LLCC },
50};
51
52static struct qcom_icc_node xm_apps_rdwr = {
53 .name = "xm_apps_rdwr",
54 .id = SDX55_MASTER_AMPSS_M0,
55 .channels = 1,
56 .buswidth = 16,
57 .num_links = 3,
58 .links = { SDX55_SLAVE_LLCC,
59 SDX55_SLAVE_MEM_NOC_SNOC,
60 SDX55_SLAVE_MEM_NOC_PCIE_SNOC
61 },
62};
63
64static struct qcom_icc_node qhm_audio = {
65 .name = "qhm_audio",
66 .id = SDX55_MASTER_AUDIO,
67 .channels = 1,
68 .buswidth = 4,
69 .num_links = 1,
70 .links = { SDX55_SLAVE_ANOC_SNOC },
71};
72
73static struct qcom_icc_node qhm_blsp1 = {
74 .name = "qhm_blsp1",
75 .id = SDX55_MASTER_BLSP_1,
76 .channels = 1,
77 .buswidth = 4,
78 .num_links = 1,
79 .links = { SDX55_SLAVE_ANOC_SNOC },
80};
81
82static struct qcom_icc_node qhm_qdss_bam = {
83 .name = "qhm_qdss_bam",
84 .id = SDX55_MASTER_QDSS_BAM,
85 .channels = 1,
86 .buswidth = 4,
87 .num_links = 28,
88 .links = { SDX55_SLAVE_SNOC_CFG,
89 SDX55_SLAVE_EMAC_CFG,
90 SDX55_SLAVE_USB3,
91 SDX55_SLAVE_TLMM,
92 SDX55_SLAVE_SPMI_FETCHER,
93 SDX55_SLAVE_QDSS_CFG,
94 SDX55_SLAVE_PDM,
95 SDX55_SLAVE_SNOC_MEM_NOC_GC,
96 SDX55_SLAVE_TCSR,
97 SDX55_SLAVE_CNOC_DDRSS,
98 SDX55_SLAVE_SPMI_VGI_COEX,
99 SDX55_SLAVE_QPIC,
100 SDX55_SLAVE_OCIMEM,
101 SDX55_SLAVE_IPA_CFG,
102 SDX55_SLAVE_USB3_PHY_CFG,
103 SDX55_SLAVE_AOP,
104 SDX55_SLAVE_BLSP_1,
105 SDX55_SLAVE_SDCC_1,
106 SDX55_SLAVE_CNOC_MSS,
107 SDX55_SLAVE_PCIE_PARF,
108 SDX55_SLAVE_ECC_CFG,
109 SDX55_SLAVE_AUDIO,
110 SDX55_SLAVE_AOSS,
111 SDX55_SLAVE_PRNG,
112 SDX55_SLAVE_CRYPTO_0_CFG,
113 SDX55_SLAVE_TCU,
114 SDX55_SLAVE_CLK_CTL,
115 SDX55_SLAVE_IMEM_CFG
116 },
117};
118
119static struct qcom_icc_node qhm_qpic = {
120 .name = "qhm_qpic",
121 .id = SDX55_MASTER_QPIC,
122 .channels = 1,
123 .buswidth = 4,
124 .num_links = 5,
125 .links = { SDX55_SLAVE_AOSS,
126 SDX55_SLAVE_IPA_CFG,
127 SDX55_SLAVE_ANOC_SNOC,
128 SDX55_SLAVE_AOP,
129 SDX55_SLAVE_AUDIO
130 },
131};
132
133static struct qcom_icc_node qhm_snoc_cfg = {
134 .name = "qhm_snoc_cfg",
135 .id = SDX55_MASTER_SNOC_CFG,
136 .channels = 1,
137 .buswidth = 4,
138 .num_links = 1,
139 .links = { SDX55_SLAVE_SERVICE_SNOC },
140};
141
142static struct qcom_icc_node qhm_spmi_fetcher1 = {
143 .name = "qhm_spmi_fetcher1",
144 .id = SDX55_MASTER_SPMI_FETCHER,
145 .channels = 1,
146 .buswidth = 4,
147 .num_links = 3,
148 .links = { SDX55_SLAVE_AOSS,
149 SDX55_SLAVE_ANOC_SNOC,
150 SDX55_SLAVE_AOP
151 },
152};
153
154static struct qcom_icc_node qnm_aggre_noc = {
155 .name = "qnm_aggre_noc",
156 .id = SDX55_MASTER_ANOC_SNOC,
157 .channels = 1,
158 .buswidth = 8,
159 .num_links = 30,
160 .links = { SDX55_SLAVE_PCIE_0,
161 SDX55_SLAVE_SNOC_CFG,
162 SDX55_SLAVE_SDCC_1,
163 SDX55_SLAVE_TLMM,
164 SDX55_SLAVE_SPMI_FETCHER,
165 SDX55_SLAVE_QDSS_CFG,
166 SDX55_SLAVE_PDM,
167 SDX55_SLAVE_SNOC_MEM_NOC_GC,
168 SDX55_SLAVE_TCSR,
169 SDX55_SLAVE_CNOC_DDRSS,
170 SDX55_SLAVE_SPMI_VGI_COEX,
171 SDX55_SLAVE_QDSS_STM,
172 SDX55_SLAVE_QPIC,
173 SDX55_SLAVE_OCIMEM,
174 SDX55_SLAVE_IPA_CFG,
175 SDX55_SLAVE_USB3_PHY_CFG,
176 SDX55_SLAVE_AOP,
177 SDX55_SLAVE_BLSP_1,
178 SDX55_SLAVE_USB3,
179 SDX55_SLAVE_CNOC_MSS,
180 SDX55_SLAVE_PCIE_PARF,
181 SDX55_SLAVE_ECC_CFG,
182 SDX55_SLAVE_APPSS,
183 SDX55_SLAVE_AUDIO,
184 SDX55_SLAVE_AOSS,
185 SDX55_SLAVE_PRNG,
186 SDX55_SLAVE_CRYPTO_0_CFG,
187 SDX55_SLAVE_TCU,
188 SDX55_SLAVE_CLK_CTL,
189 SDX55_SLAVE_IMEM_CFG
190 },
191};
192
193static struct qcom_icc_node qnm_ipa = {
194 .name = "qnm_ipa",
195 .id = SDX55_MASTER_IPA,
196 .channels = 1,
197 .buswidth = 8,
198 .num_links = 27,
199 .links = { SDX55_SLAVE_SNOC_CFG,
200 SDX55_SLAVE_EMAC_CFG,
201 SDX55_SLAVE_USB3,
202 SDX55_SLAVE_AOSS,
203 SDX55_SLAVE_SPMI_FETCHER,
204 SDX55_SLAVE_QDSS_CFG,
205 SDX55_SLAVE_PDM,
206 SDX55_SLAVE_SNOC_MEM_NOC_GC,
207 SDX55_SLAVE_TCSR,
208 SDX55_SLAVE_CNOC_DDRSS,
209 SDX55_SLAVE_QDSS_STM,
210 SDX55_SLAVE_QPIC,
211 SDX55_SLAVE_OCIMEM,
212 SDX55_SLAVE_IPA_CFG,
213 SDX55_SLAVE_USB3_PHY_CFG,
214 SDX55_SLAVE_AOP,
215 SDX55_SLAVE_BLSP_1,
216 SDX55_SLAVE_SDCC_1,
217 SDX55_SLAVE_CNOC_MSS,
218 SDX55_SLAVE_PCIE_PARF,
219 SDX55_SLAVE_ECC_CFG,
220 SDX55_SLAVE_AUDIO,
221 SDX55_SLAVE_TLMM,
222 SDX55_SLAVE_PRNG,
223 SDX55_SLAVE_CRYPTO_0_CFG,
224 SDX55_SLAVE_CLK_CTL,
225 SDX55_SLAVE_IMEM_CFG
226 },
227};
228
229static struct qcom_icc_node qnm_memnoc = {
230 .name = "qnm_memnoc",
231 .id = SDX55_MASTER_MEM_NOC_SNOC,
232 .channels = 1,
233 .buswidth = 8,
234 .num_links = 29,
235 .links = { SDX55_SLAVE_SNOC_CFG,
236 SDX55_SLAVE_EMAC_CFG,
237 SDX55_SLAVE_USB3,
238 SDX55_SLAVE_TLMM,
239 SDX55_SLAVE_SPMI_FETCHER,
240 SDX55_SLAVE_QDSS_CFG,
241 SDX55_SLAVE_PDM,
242 SDX55_SLAVE_TCSR,
243 SDX55_SLAVE_CNOC_DDRSS,
244 SDX55_SLAVE_SPMI_VGI_COEX,
245 SDX55_SLAVE_QDSS_STM,
246 SDX55_SLAVE_QPIC,
247 SDX55_SLAVE_OCIMEM,
248 SDX55_SLAVE_IPA_CFG,
249 SDX55_SLAVE_USB3_PHY_CFG,
250 SDX55_SLAVE_AOP,
251 SDX55_SLAVE_BLSP_1,
252 SDX55_SLAVE_SDCC_1,
253 SDX55_SLAVE_CNOC_MSS,
254 SDX55_SLAVE_PCIE_PARF,
255 SDX55_SLAVE_ECC_CFG,
256 SDX55_SLAVE_APPSS,
257 SDX55_SLAVE_AUDIO,
258 SDX55_SLAVE_AOSS,
259 SDX55_SLAVE_PRNG,
260 SDX55_SLAVE_CRYPTO_0_CFG,
261 SDX55_SLAVE_TCU,
262 SDX55_SLAVE_CLK_CTL,
263 SDX55_SLAVE_IMEM_CFG
264 },
265};
266
267static struct qcom_icc_node qnm_memnoc_pcie = {
268 .name = "qnm_memnoc_pcie",
269 .id = SDX55_MASTER_MEM_NOC_PCIE_SNOC,
270 .channels = 1,
271 .buswidth = 8,
272 .num_links = 1,
273 .links = { SDX55_SLAVE_PCIE_0 },
274};
275
276static struct qcom_icc_node qxm_crypto = {
277 .name = "qxm_crypto",
278 .id = SDX55_MASTER_CRYPTO_CORE_0,
279 .channels = 1,
280 .buswidth = 8,
281 .num_links = 3,
282 .links = { SDX55_SLAVE_AOSS,
283 SDX55_SLAVE_ANOC_SNOC,
284 SDX55_SLAVE_AOP
285 },
286};
287
288static struct qcom_icc_node xm_emac = {
289 .name = "xm_emac",
290 .id = SDX55_MASTER_EMAC,
291 .channels = 1,
292 .buswidth = 8,
293 .num_links = 1,
294 .links = { SDX55_SLAVE_ANOC_SNOC },
295};
296
297static struct qcom_icc_node xm_ipa2pcie_slv = {
298 .name = "xm_ipa2pcie_slv",
299 .id = SDX55_MASTER_IPA_PCIE,
300 .channels = 1,
301 .buswidth = 8,
302 .num_links = 1,
303 .links = { SDX55_SLAVE_PCIE_0 },
304};
305
306static struct qcom_icc_node xm_pcie = {
307 .name = "xm_pcie",
308 .id = SDX55_MASTER_PCIE,
309 .channels = 1,
310 .buswidth = 8,
311 .num_links = 1,
312 .links = { SDX55_SLAVE_ANOC_SNOC },
313};
314
315static struct qcom_icc_node xm_qdss_etr = {
316 .name = "xm_qdss_etr",
317 .id = SDX55_MASTER_QDSS_ETR,
318 .channels = 1,
319 .buswidth = 8,
320 .num_links = 28,
321 .links = { SDX55_SLAVE_SNOC_CFG,
322 SDX55_SLAVE_EMAC_CFG,
323 SDX55_SLAVE_USB3,
324 SDX55_SLAVE_AOSS,
325 SDX55_SLAVE_SPMI_FETCHER,
326 SDX55_SLAVE_QDSS_CFG,
327 SDX55_SLAVE_PDM,
328 SDX55_SLAVE_SNOC_MEM_NOC_GC,
329 SDX55_SLAVE_TCSR,
330 SDX55_SLAVE_CNOC_DDRSS,
331 SDX55_SLAVE_SPMI_VGI_COEX,
332 SDX55_SLAVE_QPIC,
333 SDX55_SLAVE_OCIMEM,
334 SDX55_SLAVE_IPA_CFG,
335 SDX55_SLAVE_USB3_PHY_CFG,
336 SDX55_SLAVE_AOP,
337 SDX55_SLAVE_BLSP_1,
338 SDX55_SLAVE_SDCC_1,
339 SDX55_SLAVE_CNOC_MSS,
340 SDX55_SLAVE_PCIE_PARF,
341 SDX55_SLAVE_ECC_CFG,
342 SDX55_SLAVE_AUDIO,
343 SDX55_SLAVE_AOSS,
344 SDX55_SLAVE_PRNG,
345 SDX55_SLAVE_CRYPTO_0_CFG,
346 SDX55_SLAVE_TCU,
347 SDX55_SLAVE_CLK_CTL,
348 SDX55_SLAVE_IMEM_CFG
349 },
350};
351
352static struct qcom_icc_node xm_sdc1 = {
353 .name = "xm_sdc1",
354 .id = SDX55_MASTER_SDCC_1,
355 .channels = 1,
356 .buswidth = 8,
357 .num_links = 5,
358 .links = { SDX55_SLAVE_AOSS,
359 SDX55_SLAVE_IPA_CFG,
360 SDX55_SLAVE_ANOC_SNOC,
361 SDX55_SLAVE_AOP,
362 SDX55_SLAVE_AUDIO
363 },
364};
365
366static struct qcom_icc_node xm_usb3 = {
367 .name = "xm_usb3",
368 .id = SDX55_MASTER_USB3,
369 .channels = 1,
370 .buswidth = 8,
371 .num_links = 1,
372 .links = { SDX55_SLAVE_ANOC_SNOC },
373};
374
375static struct qcom_icc_node ebi = {
376 .name = "ebi",
377 .id = SDX55_SLAVE_EBI_CH0,
378 .channels = 1,
379 .buswidth = 4,
380};
381
382static struct qcom_icc_node qns_llcc = {
383 .name = "qns_llcc",
384 .id = SDX55_SLAVE_LLCC,
385 .channels = 1,
386 .buswidth = 16,
387 .num_links = 1,
388 .links = { SDX55_SLAVE_EBI_CH0 },
389};
390
391static struct qcom_icc_node qns_memnoc_snoc = {
392 .name = "qns_memnoc_snoc",
393 .id = SDX55_SLAVE_MEM_NOC_SNOC,
394 .channels = 1,
395 .buswidth = 8,
396 .num_links = 1,
397 .links = { SDX55_MASTER_MEM_NOC_SNOC },
398};
399
400static struct qcom_icc_node qns_sys_pcie = {
401 .name = "qns_sys_pcie",
402 .id = SDX55_SLAVE_MEM_NOC_PCIE_SNOC,
403 .channels = 1,
404 .buswidth = 8,
405 .num_links = 1,
406 .links = { SDX55_MASTER_MEM_NOC_PCIE_SNOC },
407};
408
409static struct qcom_icc_node qhs_aop = {
410 .name = "qhs_aop",
411 .id = SDX55_SLAVE_AOP,
412 .channels = 1,
413 .buswidth = 4,
414};
415
416static struct qcom_icc_node qhs_aoss = {
417 .name = "qhs_aoss",
418 .id = SDX55_SLAVE_AOSS,
419 .channels = 1,
420 .buswidth = 4,
421};
422
423static struct qcom_icc_node qhs_apss = {
424 .name = "qhs_apss",
425 .id = SDX55_SLAVE_APPSS,
426 .channels = 1,
427 .buswidth = 4,
428};
429
430static struct qcom_icc_node qhs_audio = {
431 .name = "qhs_audio",
432 .id = SDX55_SLAVE_AUDIO,
433 .channels = 1,
434 .buswidth = 4,
435};
436
437static struct qcom_icc_node qhs_blsp1 = {
438 .name = "qhs_blsp1",
439 .id = SDX55_SLAVE_BLSP_1,
440 .channels = 1,
441 .buswidth = 4,
442};
443
444static struct qcom_icc_node qhs_clk_ctl = {
445 .name = "qhs_clk_ctl",
446 .id = SDX55_SLAVE_CLK_CTL,
447 .channels = 1,
448 .buswidth = 4,
449};
450
451static struct qcom_icc_node qhs_crypto0_cfg = {
452 .name = "qhs_crypto0_cfg",
453 .id = SDX55_SLAVE_CRYPTO_0_CFG,
454 .channels = 1,
455 .buswidth = 4,
456};
457
458static struct qcom_icc_node qhs_ddrss_cfg = {
459 .name = "qhs_ddrss_cfg",
460 .id = SDX55_SLAVE_CNOC_DDRSS,
461 .channels = 1,
462 .buswidth = 4,
463};
464
465static struct qcom_icc_node qhs_ecc_cfg = {
466 .name = "qhs_ecc_cfg",
467 .id = SDX55_SLAVE_ECC_CFG,
468 .channels = 1,
469 .buswidth = 4,
470};
471
472static struct qcom_icc_node qhs_emac_cfg = {
473 .name = "qhs_emac_cfg",
474 .id = SDX55_SLAVE_EMAC_CFG,
475 .channels = 1,
476 .buswidth = 4,
477};
478
479static struct qcom_icc_node qhs_imem_cfg = {
480 .name = "qhs_imem_cfg",
481 .id = SDX55_SLAVE_IMEM_CFG,
482 .channels = 1,
483 .buswidth = 4,
484};
485
486static struct qcom_icc_node qhs_ipa = {
487 .name = "qhs_ipa",
488 .id = SDX55_SLAVE_IPA_CFG,
489 .channels = 1,
490 .buswidth = 4,
491};
492
493static struct qcom_icc_node qhs_mss_cfg = {
494 .name = "qhs_mss_cfg",
495 .id = SDX55_SLAVE_CNOC_MSS,
496 .channels = 1,
497 .buswidth = 4,
498};
499
500static struct qcom_icc_node qhs_pcie_parf = {
501 .name = "qhs_pcie_parf",
502 .id = SDX55_SLAVE_PCIE_PARF,
503 .channels = 1,
504 .buswidth = 4,
505};
506
507static struct qcom_icc_node qhs_pdm = {
508 .name = "qhs_pdm",
509 .id = SDX55_SLAVE_PDM,
510 .channels = 1,
511 .buswidth = 4,
512};
513
514static struct qcom_icc_node qhs_prng = {
515 .name = "qhs_prng",
516 .id = SDX55_SLAVE_PRNG,
517 .channels = 1,
518 .buswidth = 4,
519};
520
521static struct qcom_icc_node qhs_qdss_cfg = {
522 .name = "qhs_qdss_cfg",
523 .id = SDX55_SLAVE_QDSS_CFG,
524 .channels = 1,
525 .buswidth = 4,
526};
527
528static struct qcom_icc_node qhs_qpic = {
529 .name = "qhs_qpic",
530 .id = SDX55_SLAVE_QPIC,
531 .channels = 1,
532 .buswidth = 4,
533};
534
535static struct qcom_icc_node qhs_sdc1 = {
536 .name = "qhs_sdc1",
537 .id = SDX55_SLAVE_SDCC_1,
538 .channels = 1,
539 .buswidth = 4,
540};
541
542static struct qcom_icc_node qhs_snoc_cfg = {
543 .name = "qhs_snoc_cfg",
544 .id = SDX55_SLAVE_SNOC_CFG,
545 .channels = 1,
546 .buswidth = 4,
547 .num_links = 1,
548 .links = { SDX55_MASTER_SNOC_CFG },
549};
550
551static struct qcom_icc_node qhs_spmi_fetcher = {
552 .name = "qhs_spmi_fetcher",
553 .id = SDX55_SLAVE_SPMI_FETCHER,
554 .channels = 1,
555 .buswidth = 4,
556};
557
558static struct qcom_icc_node qhs_spmi_vgi_coex = {
559 .name = "qhs_spmi_vgi_coex",
560 .id = SDX55_SLAVE_SPMI_VGI_COEX,
561 .channels = 1,
562 .buswidth = 4,
563};
564
565static struct qcom_icc_node qhs_tcsr = {
566 .name = "qhs_tcsr",
567 .id = SDX55_SLAVE_TCSR,
568 .channels = 1,
569 .buswidth = 4,
570};
571
572static struct qcom_icc_node qhs_tlmm = {
573 .name = "qhs_tlmm",
574 .id = SDX55_SLAVE_TLMM,
575 .channels = 1,
576 .buswidth = 4,
577};
578
579static struct qcom_icc_node qhs_usb3 = {
580 .name = "qhs_usb3",
581 .id = SDX55_SLAVE_USB3,
582 .channels = 1,
583 .buswidth = 4,
584};
585
586static struct qcom_icc_node qhs_usb3_phy = {
587 .name = "qhs_usb3_phy",
588 .id = SDX55_SLAVE_USB3_PHY_CFG,
589 .channels = 1,
590 .buswidth = 4,
591};
592
593static struct qcom_icc_node qns_aggre_noc = {
594 .name = "qns_aggre_noc",
595 .id = SDX55_SLAVE_ANOC_SNOC,
596 .channels = 1,
597 .buswidth = 8,
598 .num_links = 1,
599 .links = { SDX55_MASTER_ANOC_SNOC },
600};
601
602static struct qcom_icc_node qns_snoc_memnoc = {
603 .name = "qns_snoc_memnoc",
604 .id = SDX55_SLAVE_SNOC_MEM_NOC_GC,
605 .channels = 1,
606 .buswidth = 8,
607 .num_links = 1,
608 .links = { SDX55_MASTER_SNOC_GC_MEM_NOC },
609};
610
611static struct qcom_icc_node qxs_imem = {
612 .name = "qxs_imem",
613 .id = SDX55_SLAVE_OCIMEM,
614 .channels = 1,
615 .buswidth = 8,
616};
617
618static struct qcom_icc_node srvc_snoc = {
619 .name = "srvc_snoc",
620 .id = SDX55_SLAVE_SERVICE_SNOC,
621 .channels = 1,
622 .buswidth = 4,
623};
624
625static struct qcom_icc_node xs_pcie = {
626 .name = "xs_pcie",
627 .id = SDX55_SLAVE_PCIE_0,
628 .channels = 1,
629 .buswidth = 8,
630};
631
632static struct qcom_icc_node xs_qdss_stm = {
633 .name = "xs_qdss_stm",
634 .id = SDX55_SLAVE_QDSS_STM,
635 .channels = 1,
636 .buswidth = 4,
637};
638
639static struct qcom_icc_node xs_sys_tcu_cfg = {
640 .name = "xs_sys_tcu_cfg",
641 .id = SDX55_SLAVE_TCU,
642 .channels = 1,
643 .buswidth = 8,
644};
645
646static struct qcom_icc_bcm bcm_mc0 = {
647 .name = "MC0",
648 .keepalive = true,
649 .num_nodes = 1,
650 .nodes = { &ebi },
651};
652
653static struct qcom_icc_bcm bcm_sh0 = {
654 .name = "SH0",
655 .keepalive = true,
656 .num_nodes = 1,
657 .nodes = { &qns_llcc },
658};
659
660static struct qcom_icc_bcm bcm_ce0 = {
661 .name = "CE0",
662 .keepalive = false,
663 .num_nodes = 1,
664 .nodes = { &qxm_crypto },
665};
666
667static struct qcom_icc_bcm bcm_pn0 = {
668 .name = "PN0",
669 .keepalive = false,
670 .num_nodes = 1,
671 .nodes = { &qhm_snoc_cfg },
672};
673
674static struct qcom_icc_bcm bcm_sh3 = {
675 .name = "SH3",
676 .keepalive = false,
677 .num_nodes = 1,
678 .nodes = { &xm_apps_rdwr },
679};
680
681static struct qcom_icc_bcm bcm_sh4 = {
682 .name = "SH4",
683 .keepalive = false,
684 .num_nodes = 2,
685 .nodes = { &qns_memnoc_snoc, &qns_sys_pcie },
686};
687
688static struct qcom_icc_bcm bcm_sn0 = {
689 .name = "SN0",
690 .keepalive = true,
691 .num_nodes = 1,
692 .nodes = { &qns_snoc_memnoc },
693};
694
695static struct qcom_icc_bcm bcm_sn1 = {
696 .name = "SN1",
697 .keepalive = false,
698 .num_nodes = 1,
699 .nodes = { &qxs_imem },
700};
701
702static struct qcom_icc_bcm bcm_pn1 = {
703 .name = "PN1",
704 .keepalive = false,
705 .num_nodes = 1,
706 .nodes = { &xm_sdc1 },
707};
708
709static struct qcom_icc_bcm bcm_pn2 = {
710 .name = "PN2",
711 .keepalive = false,
712 .num_nodes = 2,
713 .nodes = { &qhm_audio, &qhm_spmi_fetcher1 },
714};
715
716static struct qcom_icc_bcm bcm_sn3 = {
717 .name = "SN3",
718 .keepalive = false,
719 .num_nodes = 1,
720 .nodes = { &xs_qdss_stm },
721};
722
723static struct qcom_icc_bcm bcm_pn3 = {
724 .name = "PN3",
725 .keepalive = false,
726 .num_nodes = 2,
727 .nodes = { &qhm_blsp1, &qhm_qpic },
728};
729
730static struct qcom_icc_bcm bcm_sn4 = {
731 .name = "SN4",
732 .keepalive = false,
733 .num_nodes = 1,
734 .nodes = { &xs_sys_tcu_cfg },
735};
736
737static struct qcom_icc_bcm bcm_pn5 = {
738 .name = "PN5",
739 .keepalive = false,
740 .num_nodes = 1,
741 .nodes = { &qxm_crypto },
742};
743
744static struct qcom_icc_bcm bcm_sn6 = {
745 .name = "SN6",
746 .keepalive = false,
747 .num_nodes = 1,
748 .nodes = { &xs_pcie },
749};
750
751static struct qcom_icc_bcm bcm_sn7 = {
752 .name = "SN7",
753 .keepalive = false,
754 .num_nodes = 5,
755 .nodes = { &qnm_aggre_noc, &xm_emac, &xm_emac, &xm_usb3, &qns_aggre_noc },
756};
757
758static struct qcom_icc_bcm bcm_sn8 = {
759 .name = "SN8",
760 .keepalive = false,
761 .num_nodes = 2,
762 .nodes = { &qhm_qdss_bam, &xm_qdss_etr },
763};
764
765static struct qcom_icc_bcm bcm_sn9 = {
766 .name = "SN9",
767 .keepalive = false,
768 .num_nodes = 1,
769 .nodes = { &qnm_memnoc },
770};
771
772static struct qcom_icc_bcm bcm_sn10 = {
773 .name = "SN10",
774 .keepalive = false,
775 .num_nodes = 1,
776 .nodes = { &qnm_memnoc_pcie },
777};
778
779static struct qcom_icc_bcm bcm_sn11 = {
780 .name = "SN11",
781 .keepalive = false,
782 .num_nodes = 2,
783 .nodes = { &qnm_ipa, &xm_ipa2pcie_slv },
784};
785
786static struct qcom_icc_bcm * const mc_virt_bcms[] = {
787 &bcm_mc0,
788};
789
790static struct qcom_icc_node * const mc_virt_nodes[] = {
791 [MASTER_LLCC] = &llcc_mc,
792 [SLAVE_EBI_CH0] = &ebi,
793};
794
795static const struct qcom_icc_desc sdx55_mc_virt = {
796 .nodes = mc_virt_nodes,
797 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
798 .bcms = mc_virt_bcms,
799 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
800};
801
802static struct qcom_icc_bcm * const mem_noc_bcms[] = {
803 &bcm_sh0,
804 &bcm_sh3,
805 &bcm_sh4,
806};
807
808static struct qcom_icc_node * const mem_noc_nodes[] = {
809 [MASTER_TCU_0] = &acm_tcu,
810 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
811 [MASTER_AMPSS_M0] = &xm_apps_rdwr,
812 [SLAVE_LLCC] = &qns_llcc,
813 [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc,
814 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie,
815};
816
817static const struct qcom_icc_desc sdx55_mem_noc = {
818 .nodes = mem_noc_nodes,
819 .num_nodes = ARRAY_SIZE(mem_noc_nodes),
820 .bcms = mem_noc_bcms,
821 .num_bcms = ARRAY_SIZE(mem_noc_bcms),
822};
823
824static struct qcom_icc_bcm * const system_noc_bcms[] = {
825 &bcm_ce0,
826 &bcm_pn0,
827 &bcm_pn1,
828 &bcm_pn2,
829 &bcm_pn3,
830 &bcm_pn5,
831 &bcm_sn0,
832 &bcm_sn1,
833 &bcm_sn3,
834 &bcm_sn4,
835 &bcm_sn6,
836 &bcm_sn7,
837 &bcm_sn8,
838 &bcm_sn9,
839 &bcm_sn10,
840 &bcm_sn11,
841};
842
843static struct qcom_icc_node * const system_noc_nodes[] = {
844 [MASTER_AUDIO] = &qhm_audio,
845 [MASTER_BLSP_1] = &qhm_blsp1,
846 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
847 [MASTER_QPIC] = &qhm_qpic,
848 [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
849 [MASTER_SPMI_FETCHER] = &qhm_spmi_fetcher1,
850 [MASTER_ANOC_SNOC] = &qnm_aggre_noc,
851 [MASTER_IPA] = &qnm_ipa,
852 [MASTER_MEM_NOC_SNOC] = &qnm_memnoc,
853 [MASTER_MEM_NOC_PCIE_SNOC] = &qnm_memnoc_pcie,
854 [MASTER_CRYPTO_CORE_0] = &qxm_crypto,
855 [MASTER_EMAC] = &xm_emac,
856 [MASTER_IPA_PCIE] = &xm_ipa2pcie_slv,
857 [MASTER_PCIE] = &xm_pcie,
858 [MASTER_QDSS_ETR] = &xm_qdss_etr,
859 [MASTER_SDCC_1] = &xm_sdc1,
860 [MASTER_USB3] = &xm_usb3,
861 [SLAVE_AOP] = &qhs_aop,
862 [SLAVE_AOSS] = &qhs_aoss,
863 [SLAVE_APPSS] = &qhs_apss,
864 [SLAVE_AUDIO] = &qhs_audio,
865 [SLAVE_BLSP_1] = &qhs_blsp1,
866 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
867 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
868 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
869 [SLAVE_ECC_CFG] = &qhs_ecc_cfg,
870 [SLAVE_EMAC_CFG] = &qhs_emac_cfg,
871 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
872 [SLAVE_IPA_CFG] = &qhs_ipa,
873 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
874 [SLAVE_PCIE_PARF] = &qhs_pcie_parf,
875 [SLAVE_PDM] = &qhs_pdm,
876 [SLAVE_PRNG] = &qhs_prng,
877 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
878 [SLAVE_QPIC] = &qhs_qpic,
879 [SLAVE_SDCC_1] = &qhs_sdc1,
880 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
881 [SLAVE_SPMI_FETCHER] = &qhs_spmi_fetcher,
882 [SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex,
883 [SLAVE_TCSR] = &qhs_tcsr,
884 [SLAVE_TLMM] = &qhs_tlmm,
885 [SLAVE_USB3] = &qhs_usb3,
886 [SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy,
887 [SLAVE_ANOC_SNOC] = &qns_aggre_noc,
888 [SLAVE_SNOC_MEM_NOC_GC] = &qns_snoc_memnoc,
889 [SLAVE_OCIMEM] = &qxs_imem,
890 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
891 [SLAVE_PCIE_0] = &xs_pcie,
892 [SLAVE_QDSS_STM] = &xs_qdss_stm,
893 [SLAVE_TCU] = &xs_sys_tcu_cfg,
894};
895
896static const struct qcom_icc_desc sdx55_system_noc = {
897 .nodes = system_noc_nodes,
898 .num_nodes = ARRAY_SIZE(system_noc_nodes),
899 .bcms = system_noc_bcms,
900 .num_bcms = ARRAY_SIZE(system_noc_bcms),
901};
902
903static const struct of_device_id qnoc_of_match[] = {
904 { .compatible = "qcom,sdx55-mc-virt",
905 .data = &sdx55_mc_virt},
906 { .compatible = "qcom,sdx55-mem-noc",
907 .data = &sdx55_mem_noc},
908 { .compatible = "qcom,sdx55-system-noc",
909 .data = &sdx55_system_noc},
910 { }
911};
912MODULE_DEVICE_TABLE(of, qnoc_of_match);
913
914static struct platform_driver qnoc_driver = {
915 .probe = qcom_icc_rpmh_probe,
916 .remove_new = qcom_icc_rpmh_remove,
917 .driver = {
918 .name = "qnoc-sdx55",
919 .of_match_table = qnoc_of_match,
920 .sync_state = icc_sync_state,
921 },
922};
923module_platform_driver(qnoc_driver);
924
925MODULE_DESCRIPTION("Qualcomm SDX55 NoC driver");
926MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
927MODULE_LICENSE("GPL v2");