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1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef _HNS_ROCE_HW_V2_H
34#define _HNS_ROCE_HW_V2_H
35
36#include <linux/bitops.h>
37
38#define HNS_ROCE_V2_MAX_RC_INL_INN_SZ 32
39#define HNS_ROCE_V2_MTT_ENTRY_SZ 64
40#define HNS_ROCE_V2_AEQE_VEC_NUM 1
41#define HNS_ROCE_V2_ABNORMAL_VEC_NUM 1
42#define HNS_ROCE_V2_MAX_SRQWQE_SEGS 0x1000000
43#define HNS_ROCE_V2_MAX_IDX_SEGS 0x1000000
44#define HNS_ROCE_V2_MAX_XRCD_NUM 0x1000000
45
46#define HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08 10
47
48#define HNS_ROCE_V3_SCCC_SZ 64
49#define HNS_ROCE_V3_GMV_ENTRY_SZ 32
50
51#define HNS_ROCE_V2_EXT_LLM_ENTRY_SZ 8
52#define HNS_ROCE_V2_EXT_LLM_MAX_DEPTH 4096
53
54#define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ PAGE_SIZE
55#define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ PAGE_SIZE
56#define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFF000
57#define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2
58#define HNS_ROCE_INVALID_LKEY 0x0
59#define HNS_ROCE_INVALID_SGE_LENGTH 0x80000000
60#define HNS_ROCE_CMQ_TX_TIMEOUT 30000
61#define HNS_ROCE_V2_RSV_QPS 8
62
63#define HNS_ROCE_V2_HW_RST_TIMEOUT 1000
64#define HNS_ROCE_V2_HW_RST_UNINT_DELAY 100
65
66#define HNS_ROCE_V2_HW_RST_COMPLETION_WAIT 20
67
68#define HNS_ROCE_CONTEXT_HOP_NUM 1
69#define HNS_ROCE_SCCC_HOP_NUM 1
70#define HNS_ROCE_MTT_HOP_NUM 1
71#define HNS_ROCE_CQE_HOP_NUM 1
72#define HNS_ROCE_SRQWQE_HOP_NUM 1
73#define HNS_ROCE_PBL_HOP_NUM 2
74#define HNS_ROCE_IDX_HOP_NUM 1
75#define HNS_ROCE_SQWQE_HOP_NUM 2
76#define HNS_ROCE_EXT_SGE_HOP_NUM 1
77#define HNS_ROCE_RQWQE_HOP_NUM 2
78
79#define HNS_ROCE_V2_EQE_HOP_NUM 2
80#define HNS_ROCE_V3_EQE_HOP_NUM 1
81
82#define HNS_ROCE_BA_PG_SZ_SUPPORTED_256K 6
83#define HNS_ROCE_BA_PG_SZ_SUPPORTED_16K 2
84#define HNS_ROCE_V2_GID_INDEX_NUM 16
85
86#define HNS_ROCE_V2_TABLE_CHUNK_SIZE (1 << 18)
87
88enum {
89 HNS_ROCE_CMD_FLAG_IN = BIT(0),
90 HNS_ROCE_CMD_FLAG_OUT = BIT(1),
91 HNS_ROCE_CMD_FLAG_NEXT = BIT(2),
92 HNS_ROCE_CMD_FLAG_WR = BIT(3),
93 HNS_ROCE_CMD_FLAG_ERR_INTR = BIT(5),
94};
95
96#define HNS_ROCE_CMQ_DESC_NUM_S 3
97
98#define HNS_ROCE_CMQ_SCC_CLR_DONE_CNT 5
99
100#define HNS_ROCE_CONG_SIZE 64
101
102#define check_whether_last_step(hop_num, step_idx) \
103 ((step_idx == 0 && hop_num == HNS_ROCE_HOP_NUM_0) || \
104 (step_idx == 1 && hop_num == 1) || \
105 (step_idx == 2 && hop_num == 2))
106#define HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT 0
107#define HNS_ICL_SWITCH_CMD_ROCEE_SEL BIT(HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT)
108
109#define CMD_CSQ_DESC_NUM 1024
110#define CMD_CRQ_DESC_NUM 1024
111
112/* Free mr used parameters */
113#define HNS_ROCE_FREE_MR_USED_CQE_NUM 128
114#define HNS_ROCE_FREE_MR_USED_QP_NUM 0x8
115#define HNS_ROCE_FREE_MR_USED_PSN 0x0808
116#define HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT 0x7
117#define HNS_ROCE_FREE_MR_USED_QP_TIMEOUT 0x12
118#define HNS_ROCE_FREE_MR_USED_SQWQE_NUM 128
119#define HNS_ROCE_FREE_MR_USED_SQSGE_NUM 0x2
120#define HNS_ROCE_FREE_MR_USED_RQWQE_NUM 128
121#define HNS_ROCE_FREE_MR_USED_RQSGE_NUM 0x2
122#define HNS_ROCE_V2_FREE_MR_TIMEOUT 4500
123
124enum {
125 NO_ARMED = 0x0,
126 REG_NXT_CEQE = 0x2,
127 REG_NXT_SE_CEQE = 0x3
128};
129
130enum {
131 CQE_SIZE_32B = 0x0,
132 CQE_SIZE_64B = 0x1
133};
134
135#define V2_CQ_DB_REQ_NOT_SOL 0
136#define V2_CQ_DB_REQ_NOT 1
137
138#define V2_CQ_STATE_VALID 1
139#define V2_QKEY_VAL 0x80010000
140
141#define GID_LEN_V2 16
142
143enum {
144 HNS_ROCE_V2_WQE_OP_SEND = 0x0,
145 HNS_ROCE_V2_WQE_OP_SEND_WITH_INV = 0x1,
146 HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM = 0x2,
147 HNS_ROCE_V2_WQE_OP_RDMA_WRITE = 0x3,
148 HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM = 0x4,
149 HNS_ROCE_V2_WQE_OP_RDMA_READ = 0x5,
150 HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP = 0x6,
151 HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD = 0x7,
152 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP = 0x8,
153 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD = 0x9,
154 HNS_ROCE_V2_WQE_OP_FAST_REG_PMR = 0xa,
155 HNS_ROCE_V2_WQE_OP_BIND_MW = 0xc,
156 HNS_ROCE_V2_WQE_OP_MASK = 0x1f,
157};
158
159enum {
160 /* rq operations */
161 HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM = 0x0,
162 HNS_ROCE_V2_OPCODE_SEND = 0x1,
163 HNS_ROCE_V2_OPCODE_SEND_WITH_IMM = 0x2,
164 HNS_ROCE_V2_OPCODE_SEND_WITH_INV = 0x3,
165};
166
167enum {
168 HNS_ROCE_V2_SQ_DB,
169 HNS_ROCE_V2_RQ_DB,
170 HNS_ROCE_V2_SRQ_DB,
171 HNS_ROCE_V2_CQ_DB,
172 HNS_ROCE_V2_CQ_DB_NOTIFY
173};
174
175enum {
176 HNS_ROCE_CQE_V2_SUCCESS = 0x00,
177 HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR = 0x01,
178 HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR = 0x02,
179 HNS_ROCE_CQE_V2_LOCAL_PROT_ERR = 0x04,
180 HNS_ROCE_CQE_V2_WR_FLUSH_ERR = 0x05,
181 HNS_ROCE_CQE_V2_MW_BIND_ERR = 0x06,
182 HNS_ROCE_CQE_V2_BAD_RESP_ERR = 0x10,
183 HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR = 0x11,
184 HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR = 0x12,
185 HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR = 0x13,
186 HNS_ROCE_CQE_V2_REMOTE_OP_ERR = 0x14,
187 HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR = 0x15,
188 HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR = 0x16,
189 HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR = 0x22,
190 HNS_ROCE_CQE_V2_GENERAL_ERR = 0x23,
191
192 HNS_ROCE_V2_CQE_STATUS_MASK = 0xff,
193};
194
195/* CMQ command */
196enum hns_roce_opcode_type {
197 HNS_QUERY_FW_VER = 0x0001,
198 HNS_ROCE_OPC_QUERY_HW_VER = 0x8000,
199 HNS_ROCE_OPC_CFG_GLOBAL_PARAM = 0x8001,
200 HNS_ROCE_OPC_ALLOC_PF_RES = 0x8004,
201 HNS_ROCE_OPC_QUERY_COUNTER = 0x8206,
202 HNS_ROCE_OPC_QUERY_PF_RES = 0x8400,
203 HNS_ROCE_OPC_ALLOC_VF_RES = 0x8401,
204 HNS_ROCE_OPC_CFG_EXT_LLM = 0x8403,
205 HNS_ROCE_OPC_QUERY_PF_TIMER_RES = 0x8406,
206 HNS_ROCE_OPC_QUERY_FUNC_INFO = 0x8407,
207 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM = 0x8408,
208 HNS_ROCE_OPC_CFG_ENTRY_SIZE = 0x8409,
209 HNS_ROCE_OPC_QUERY_VF_CAPS_NUM = 0x8410,
210 HNS_ROCE_OPC_CFG_SGID_TB = 0x8500,
211 HNS_ROCE_OPC_CFG_SMAC_TB = 0x8501,
212 HNS_ROCE_OPC_POST_MB = 0x8504,
213 HNS_ROCE_OPC_QUERY_MB_ST = 0x8505,
214 HNS_ROCE_OPC_CFG_BT_ATTR = 0x8506,
215 HNS_ROCE_OPC_FUNC_CLEAR = 0x8508,
216 HNS_ROCE_OPC_CLR_SCCC = 0x8509,
217 HNS_ROCE_OPC_QUERY_SCCC = 0x850a,
218 HNS_ROCE_OPC_RESET_SCCC = 0x850b,
219 HNS_ROCE_OPC_CLEAR_EXTDB_LIST_INFO = 0x850d,
220 HNS_ROCE_OPC_QUERY_VF_RES = 0x850e,
221 HNS_ROCE_OPC_CFG_GMV_TBL = 0x850f,
222 HNS_ROCE_OPC_CFG_GMV_BT = 0x8510,
223 HNS_ROCE_QUERY_RAM_ECC = 0x8513,
224 HNS_SWITCH_PARAMETER_CFG = 0x1033,
225};
226
227enum {
228 TYPE_CRQ,
229 TYPE_CSQ,
230};
231
232enum hns_roce_cmd_return_status {
233 CMD_EXEC_SUCCESS,
234 CMD_NO_AUTH,
235 CMD_NOT_EXIST,
236 CMD_CRQ_FULL,
237 CMD_NEXT_ERR,
238 CMD_NOT_EXEC,
239 CMD_PARA_ERR,
240 CMD_RESULT_ERR,
241 CMD_TIMEOUT,
242 CMD_HILINK_ERR,
243 CMD_INFO_ILLEGAL,
244 CMD_INVALID,
245 CMD_ROH_CHECK_FAIL,
246 CMD_OTHER_ERR = 0xff
247};
248
249struct hns_roce_cmd_errcode {
250 enum hns_roce_cmd_return_status return_status;
251 int errno;
252};
253
254enum hns_roce_sgid_type {
255 GID_TYPE_FLAG_ROCE_V1 = 0,
256 GID_TYPE_FLAG_ROCE_V2_IPV4,
257 GID_TYPE_FLAG_ROCE_V2_IPV6,
258};
259
260struct hns_roce_v2_cq_context {
261 __le32 byte_4_pg_ceqn;
262 __le32 byte_8_cqn;
263 __le32 cqe_cur_blk_addr;
264 __le32 byte_16_hop_addr;
265 __le32 cqe_nxt_blk_addr;
266 __le32 byte_24_pgsz_addr;
267 __le32 byte_28_cq_pi;
268 __le32 byte_32_cq_ci;
269 __le32 cqe_ba;
270 __le32 byte_40_cqe_ba;
271 __le32 byte_44_db_record;
272 __le32 db_record_addr;
273 __le32 byte_52_cqe_cnt;
274 __le32 byte_56_cqe_period_maxcnt;
275 __le32 cqe_report_timer;
276 __le32 byte_64_se_cqe_idx;
277};
278
279#define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM 0x0
280#define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL 0x0
281
282#define CQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_cq_context, h, l)
283
284#define CQC_CQ_ST CQC_FIELD_LOC(1, 0)
285#define CQC_POLL CQC_FIELD_LOC(2, 2)
286#define CQC_SE CQC_FIELD_LOC(3, 3)
287#define CQC_OVER_IGNORE CQC_FIELD_LOC(4, 4)
288#define CQC_ARM_ST CQC_FIELD_LOC(7, 6)
289#define CQC_SHIFT CQC_FIELD_LOC(12, 8)
290#define CQC_CMD_SN CQC_FIELD_LOC(14, 13)
291#define CQC_CEQN CQC_FIELD_LOC(23, 15)
292#define CQC_CQN CQC_FIELD_LOC(55, 32)
293#define CQC_POE_EN CQC_FIELD_LOC(56, 56)
294#define CQC_POE_NUM CQC_FIELD_LOC(58, 57)
295#define CQC_CQE_SIZE CQC_FIELD_LOC(60, 59)
296#define CQC_CQ_CNT_MODE CQC_FIELD_LOC(61, 61)
297#define CQC_STASH CQC_FIELD_LOC(63, 63)
298#define CQC_CQE_CUR_BLK_ADDR_L CQC_FIELD_LOC(95, 64)
299#define CQC_CQE_CUR_BLK_ADDR_H CQC_FIELD_LOC(115, 96)
300#define CQC_POE_QID CQC_FIELD_LOC(125, 116)
301#define CQC_CQE_HOP_NUM CQC_FIELD_LOC(127, 126)
302#define CQC_CQE_NEX_BLK_ADDR_L CQC_FIELD_LOC(159, 128)
303#define CQC_CQE_NEX_BLK_ADDR_H CQC_FIELD_LOC(179, 160)
304#define CQC_CQE_BAR_PG_SZ CQC_FIELD_LOC(187, 184)
305#define CQC_CQE_BUF_PG_SZ CQC_FIELD_LOC(191, 188)
306#define CQC_CQ_PRODUCER_IDX CQC_FIELD_LOC(215, 192)
307#define CQC_CQ_CONSUMER_IDX CQC_FIELD_LOC(247, 224)
308#define CQC_CQE_BA_L CQC_FIELD_LOC(287, 256)
309#define CQC_CQE_BA_H CQC_FIELD_LOC(316, 288)
310#define CQC_POE_QID_H_0 CQC_FIELD_LOC(319, 317)
311#define CQC_DB_RECORD_EN CQC_FIELD_LOC(320, 320)
312#define CQC_CQE_DB_RECORD_ADDR_L CQC_FIELD_LOC(351, 321)
313#define CQC_CQE_DB_RECORD_ADDR_H CQC_FIELD_LOC(383, 352)
314#define CQC_CQE_CNT CQC_FIELD_LOC(407, 384)
315#define CQC_CQ_MAX_CNT CQC_FIELD_LOC(431, 416)
316#define CQC_CQ_PERIOD CQC_FIELD_LOC(447, 432)
317#define CQC_CQE_REPORT_TIMER CQC_FIELD_LOC(471, 448)
318#define CQC_WR_CQE_IDX CQC_FIELD_LOC(479, 472)
319#define CQC_SE_CQE_IDX CQC_FIELD_LOC(503, 480)
320#define CQC_POE_QID_H_1 CQC_FIELD_LOC(511, 511)
321
322struct hns_roce_srq_context {
323 __le32 data[16];
324};
325
326#define SRQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_srq_context, h, l)
327
328#define SRQC_SRQ_ST SRQC_FIELD_LOC(1, 0)
329#define SRQC_WQE_HOP_NUM SRQC_FIELD_LOC(3, 2)
330#define SRQC_SHIFT SRQC_FIELD_LOC(7, 4)
331#define SRQC_SRQN SRQC_FIELD_LOC(31, 8)
332#define SRQC_LIMIT_WL SRQC_FIELD_LOC(47, 32)
333#define SRQC_RSV0 SRQC_FIELD_LOC(63, 48)
334#define SRQC_XRCD SRQC_FIELD_LOC(87, 64)
335#define SRQC_RSV1 SRQC_FIELD_LOC(95, 88)
336#define SRQC_PRODUCER_IDX SRQC_FIELD_LOC(111, 96)
337#define SRQC_CONSUMER_IDX SRQC_FIELD_LOC(127, 112)
338#define SRQC_WQE_BT_BA_L SRQC_FIELD_LOC(159, 128)
339#define SRQC_WQE_BT_BA_H SRQC_FIELD_LOC(188, 160)
340#define SRQC_RSV2 SRQC_FIELD_LOC(190, 189)
341#define SRQC_SRQ_TYPE SRQC_FIELD_LOC(191, 191)
342#define SRQC_PD SRQC_FIELD_LOC(215, 192)
343#define SRQC_RQWS SRQC_FIELD_LOC(219, 216)
344#define SRQC_RSV3 SRQC_FIELD_LOC(223, 220)
345#define SRQC_IDX_BT_BA_L SRQC_FIELD_LOC(255, 224)
346#define SRQC_IDX_BT_BA_H SRQC_FIELD_LOC(284, 256)
347#define SRQC_RSV4 SRQC_FIELD_LOC(287, 285)
348#define SRQC_IDX_CUR_BLK_ADDR_L SRQC_FIELD_LOC(319, 288)
349#define SRQC_IDX_CUR_BLK_ADDR_H SRQC_FIELD_LOC(339, 320)
350#define SRQC_RSV5 SRQC_FIELD_LOC(341, 340)
351#define SRQC_IDX_HOP_NUM SRQC_FIELD_LOC(343, 342)
352#define SRQC_IDX_BA_PG_SZ SRQC_FIELD_LOC(347, 344)
353#define SRQC_IDX_BUF_PG_SZ SRQC_FIELD_LOC(351, 348)
354#define SRQC_IDX_NXT_BLK_ADDR_L SRQC_FIELD_LOC(383, 352)
355#define SRQC_IDX_NXT_BLK_ADDR_H SRQC_FIELD_LOC(403, 384)
356#define SRQC_RSV6 SRQC_FIELD_LOC(415, 404)
357#define SRQC_XRC_CQN SRQC_FIELD_LOC(439, 416)
358#define SRQC_WQE_BA_PG_SZ SRQC_FIELD_LOC(443, 440)
359#define SRQC_WQE_BUF_PG_SZ SRQC_FIELD_LOC(447, 444)
360#define SRQC_DB_RECORD_EN SRQC_FIELD_LOC(448, 448)
361#define SRQC_DB_RECORD_ADDR_L SRQC_FIELD_LOC(479, 449)
362#define SRQC_DB_RECORD_ADDR_H SRQC_FIELD_LOC(511, 480)
363
364enum {
365 V2_MPT_ST_VALID = 0x1,
366 V2_MPT_ST_FREE = 0x2,
367};
368
369enum hns_roce_v2_qp_state {
370 HNS_ROCE_QP_ST_RST,
371 HNS_ROCE_QP_ST_INIT,
372 HNS_ROCE_QP_ST_RTR,
373 HNS_ROCE_QP_ST_RTS,
374 HNS_ROCE_QP_ST_SQD,
375 HNS_ROCE_QP_ST_SQER,
376 HNS_ROCE_QP_ST_ERR,
377 HNS_ROCE_QP_ST_SQ_DRAINING,
378 HNS_ROCE_QP_NUM_ST
379};
380
381struct hns_roce_v2_qp_context_ex {
382 __le32 data[64];
383};
384
385struct hns_roce_v2_qp_context {
386 __le32 byte_4_sqpn_tst;
387 __le32 wqe_sge_ba;
388 __le32 byte_12_sq_hop;
389 __le32 byte_16_buf_ba_pg_sz;
390 __le32 byte_20_smac_sgid_idx;
391 __le32 byte_24_mtu_tc;
392 __le32 byte_28_at_fl;
393 u8 dgid[GID_LEN_V2];
394 __le32 dmac;
395 __le32 byte_52_udpspn_dmac;
396 __le32 byte_56_dqpn_err;
397 __le32 byte_60_qpst_tempid;
398 __le32 qkey_xrcd;
399 __le32 byte_68_rq_db;
400 __le32 rq_db_record_addr;
401 __le32 byte_76_srqn_op_en;
402 __le32 byte_80_rnr_rx_cqn;
403 __le32 byte_84_rq_ci_pi;
404 __le32 rq_cur_blk_addr;
405 __le32 byte_92_srq_info;
406 __le32 byte_96_rx_reqmsn;
407 __le32 rq_nxt_blk_addr;
408 __le32 byte_104_rq_sge;
409 __le32 byte_108_rx_reqepsn;
410 __le32 rq_rnr_timer;
411 __le32 rx_msg_len;
412 __le32 rx_rkey_pkt_info;
413 __le64 rx_va;
414 __le32 byte_132_trrl;
415 __le32 trrl_ba;
416 __le32 byte_140_raq;
417 __le32 byte_144_raq;
418 __le32 byte_148_raq;
419 __le32 byte_152_raq;
420 __le32 byte_156_raq;
421 __le32 byte_160_sq_ci_pi;
422 __le32 sq_cur_blk_addr;
423 __le32 byte_168_irrl_idx;
424 __le32 byte_172_sq_psn;
425 __le32 byte_176_msg_pktn;
426 __le32 sq_cur_sge_blk_addr;
427 __le32 byte_184_irrl_idx;
428 __le32 cur_sge_offset;
429 __le32 byte_192_ext_sge;
430 __le32 byte_196_sq_psn;
431 __le32 byte_200_sq_max;
432 __le32 irrl_ba;
433 __le32 byte_208_irrl;
434 __le32 byte_212_lsn;
435 __le32 sq_timer;
436 __le32 byte_220_retry_psn_msn;
437 __le32 byte_224_retry_msg;
438 __le32 rx_sq_cur_blk_addr;
439 __le32 byte_232_irrl_sge;
440 __le32 irrl_cur_sge_offset;
441 __le32 byte_240_irrl_tail;
442 __le32 byte_244_rnr_rxack;
443 __le32 byte_248_ack_psn;
444 __le32 byte_252_err_txcqn;
445 __le32 byte_256_sqflush_rqcqe;
446
447 struct hns_roce_v2_qp_context_ex ext;
448};
449
450#define QPC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_qp_context, h, l)
451
452#define QPC_TST QPC_FIELD_LOC(2, 0)
453#define QPC_SGE_SHIFT QPC_FIELD_LOC(7, 3)
454#define QPC_CNP_TIMER QPC_FIELD_LOC(31, 8)
455#define QPC_WQE_SGE_BA_L QPC_FIELD_LOC(63, 32)
456#define QPC_WQE_SGE_BA_H QPC_FIELD_LOC(92, 64)
457#define QPC_SQ_HOP_NUM QPC_FIELD_LOC(94, 93)
458#define QPC_CIRE_EN QPC_FIELD_LOC(95, 95)
459#define QPC_WQE_SGE_BA_PG_SZ QPC_FIELD_LOC(99, 96)
460#define QPC_WQE_SGE_BUF_PG_SZ QPC_FIELD_LOC(103, 100)
461#define QPC_PD QPC_FIELD_LOC(127, 104)
462#define QPC_RQ_HOP_NUM QPC_FIELD_LOC(129, 128)
463#define QPC_SGE_HOP_NUM QPC_FIELD_LOC(131, 130)
464#define QPC_RQWS QPC_FIELD_LOC(135, 132)
465#define QPC_SQ_SHIFT QPC_FIELD_LOC(139, 136)
466#define QPC_RQ_SHIFT QPC_FIELD_LOC(143, 140)
467#define QPC_GMV_IDX QPC_FIELD_LOC(159, 144)
468#define QPC_HOPLIMIT QPC_FIELD_LOC(167, 160)
469#define QPC_TC QPC_FIELD_LOC(175, 168)
470#define QPC_VLAN_ID QPC_FIELD_LOC(187, 176)
471#define QPC_MTU QPC_FIELD_LOC(191, 188)
472#define QPC_FL QPC_FIELD_LOC(211, 192)
473#define QPC_SL QPC_FIELD_LOC(215, 212)
474#define QPC_CNP_TX_FLAG QPC_FIELD_LOC(216, 216)
475#define QPC_CE_FLAG QPC_FIELD_LOC(217, 217)
476#define QPC_LBI QPC_FIELD_LOC(218, 218)
477#define QPC_AT QPC_FIELD_LOC(223, 219)
478#define QPC_DGID QPC_FIELD_LOC(351, 224)
479#define QPC_DMAC_L QPC_FIELD_LOC(383, 352)
480#define QPC_DMAC_H QPC_FIELD_LOC(399, 384)
481#define QPC_UDPSPN QPC_FIELD_LOC(415, 400)
482#define QPC_DQPN QPC_FIELD_LOC(439, 416)
483#define QPC_SQ_TX_ERR QPC_FIELD_LOC(440, 440)
484#define QPC_SQ_RX_ERR QPC_FIELD_LOC(441, 441)
485#define QPC_RQ_TX_ERR QPC_FIELD_LOC(442, 442)
486#define QPC_RQ_RX_ERR QPC_FIELD_LOC(443, 443)
487#define QPC_LP_PKTN_INI QPC_FIELD_LOC(447, 444)
488#define QPC_CONG_ALGO_TMPL_ID QPC_FIELD_LOC(455, 448)
489#define QPC_SCC_TOKEN QPC_FIELD_LOC(474, 456)
490#define QPC_SQ_DB_DOING QPC_FIELD_LOC(475, 475)
491#define QPC_RQ_DB_DOING QPC_FIELD_LOC(476, 476)
492#define QPC_QP_ST QPC_FIELD_LOC(479, 477)
493#define QPC_QKEY_XRCD QPC_FIELD_LOC(511, 480)
494#define QPC_RQ_RECORD_EN QPC_FIELD_LOC(512, 512)
495#define QPC_RQ_DB_RECORD_ADDR_L QPC_FIELD_LOC(543, 513)
496#define QPC_RQ_DB_RECORD_ADDR_H QPC_FIELD_LOC(575, 544)
497#define QPC_SRQN QPC_FIELD_LOC(599, 576)
498#define QPC_SRQ_EN QPC_FIELD_LOC(600, 600)
499#define QPC_RRE QPC_FIELD_LOC(601, 601)
500#define QPC_RWE QPC_FIELD_LOC(602, 602)
501#define QPC_ATE QPC_FIELD_LOC(603, 603)
502#define QPC_RQIE QPC_FIELD_LOC(604, 604)
503#define QPC_EXT_ATE QPC_FIELD_LOC(605, 605)
504#define QPC_RQ_VLAN_EN QPC_FIELD_LOC(606, 606)
505#define QPC_RQ_RTY_TX_ERR QPC_FIELD_LOC(607, 607)
506#define QPC_RX_CQN QPC_FIELD_LOC(631, 608)
507#define QPC_XRC_QP_TYPE QPC_FIELD_LOC(632, 632)
508#define QPC_CQEIE QPC_FIELD_LOC(633, 633)
509#define QPC_CQEIS QPC_FIELD_LOC(634, 634)
510#define QPC_MIN_RNR_TIME QPC_FIELD_LOC(639, 635)
511#define QPC_RQ_PRODUCER_IDX QPC_FIELD_LOC(655, 640)
512#define QPC_RQ_CONSUMER_IDX QPC_FIELD_LOC(671, 656)
513#define QPC_RQ_CUR_BLK_ADDR_L QPC_FIELD_LOC(703, 672)
514#define QPC_RQ_CUR_BLK_ADDR_H QPC_FIELD_LOC(723, 704)
515#define QPC_SRQ_INFO QPC_FIELD_LOC(735, 724)
516#define QPC_RX_REQ_MSN QPC_FIELD_LOC(759, 736)
517#define QPC_REDUCE_CODE QPC_FIELD_LOC(766, 760)
518#define QPC_RX_XRC_PKT_CQE_FLG QPC_FIELD_LOC(767, 767)
519#define QPC_RQ_NXT_BLK_ADDR_L QPC_FIELD_LOC(799, 768)
520#define QPC_RQ_NXT_BLK_ADDR_H QPC_FIELD_LOC(819, 800)
521#define QPC_REDUCE_EN QPC_FIELD_LOC(820, 820)
522#define QPC_FLUSH_EN QPC_FIELD_LOC(821, 821)
523#define QPC_AW_EN QPC_FIELD_LOC(822, 822)
524#define QPC_WN_EN QPC_FIELD_LOC(823, 823)
525#define QPC_RQ_CUR_WQE_SGE_NUM QPC_FIELD_LOC(831, 824)
526#define QPC_INV_CREDIT QPC_FIELD_LOC(832, 832)
527#define QPC_LAST_WRITE_TYPE QPC_FIELD_LOC(834, 833)
528#define QPC_RX_REQ_PSN_ERR QPC_FIELD_LOC(835, 835)
529#define QPC_RX_REQ_LAST_OPTYPE QPC_FIELD_LOC(838, 836)
530#define QPC_RX_REQ_RNR QPC_FIELD_LOC(839, 839)
531#define QPC_RX_REQ_EPSN QPC_FIELD_LOC(863, 840)
532#define QPC_RQ_RNR_TIMER QPC_FIELD_LOC(895, 864)
533#define QPC_RX_MSG_LEN QPC_FIELD_LOC(927, 896)
534#define QPC_RX_RKEY_PKT_INFO QPC_FIELD_LOC(959, 928)
535#define QPC_RX_VA QPC_FIELD_LOC(1023, 960)
536#define QPC_TRRL_HEAD_MAX QPC_FIELD_LOC(1031, 1024)
537#define QPC_TRRL_TAIL_MAX QPC_FIELD_LOC(1039, 1032)
538#define QPC_TRRL_BA_L QPC_FIELD_LOC(1055, 1040)
539#define QPC_TRRL_BA_M QPC_FIELD_LOC(1087, 1056)
540#define QPC_TRRL_BA_H QPC_FIELD_LOC(1099, 1088)
541#define QPC_RR_MAX QPC_FIELD_LOC(1102, 1100)
542#define QPC_RQ_RTY_WAIT_DO QPC_FIELD_LOC(1103, 1103)
543#define QPC_RAQ_TRRL_HEAD QPC_FIELD_LOC(1111, 1104)
544#define QPC_RAQ_TRRL_TAIL QPC_FIELD_LOC(1119, 1112)
545#define QPC_RAQ_RTY_INI_PSN QPC_FIELD_LOC(1143, 1120)
546#define QPC_CIRE_SLV_RQ_EN QPC_FIELD_LOC(1144, 1144)
547#define QPC_RAQ_CREDIT QPC_FIELD_LOC(1149, 1145)
548#define QPC_RQ_DB_IN_EXT QPC_FIELD_LOC(1150, 1150)
549#define QPC_RESP_RTY_FLG QPC_FIELD_LOC(1151, 1151)
550#define QPC_RAQ_MSN QPC_FIELD_LOC(1175, 1152)
551#define QPC_RAQ_SYNDROME QPC_FIELD_LOC(1183, 1176)
552#define QPC_RAQ_PSN QPC_FIELD_LOC(1207, 1184)
553#define QPC_RAQ_TRRL_RTY_HEAD QPC_FIELD_LOC(1215, 1208)
554#define QPC_RAQ_USE_PKTN QPC_FIELD_LOC(1239, 1216)
555#define QPC_RQ_SCC_TOKEN QPC_FIELD_LOC(1245, 1240)
556#define QPC_RVD10 QPC_FIELD_LOC(1247, 1246)
557#define QPC_SQ_PRODUCER_IDX QPC_FIELD_LOC(1263, 1248)
558#define QPC_SQ_CONSUMER_IDX QPC_FIELD_LOC(1279, 1264)
559#define QPC_SQ_CUR_BLK_ADDR_L QPC_FIELD_LOC(1311, 1280)
560#define QPC_SQ_CUR_BLK_ADDR_H QPC_FIELD_LOC(1331, 1312)
561#define QPC_MSG_RTY_LP_FLG QPC_FIELD_LOC(1332, 1332)
562#define QPC_SQ_INVLD_FLG QPC_FIELD_LOC(1333, 1333)
563#define QPC_LP_SGEN_INI QPC_FIELD_LOC(1335, 1334)
564#define QPC_SQ_VLAN_EN QPC_FIELD_LOC(1336, 1336)
565#define QPC_POLL_DB_WAIT_DO QPC_FIELD_LOC(1337, 1337)
566#define QPC_SCC_TOKEN_FORBID_SQ_DEQ QPC_FIELD_LOC(1338, 1338)
567#define QPC_WAIT_ACK_TIMEOUT QPC_FIELD_LOC(1339, 1339)
568#define QPC_IRRL_IDX_LSB QPC_FIELD_LOC(1343, 1340)
569#define QPC_ACK_REQ_FREQ QPC_FIELD_LOC(1349, 1344)
570#define QPC_MSG_RNR_FLG QPC_FIELD_LOC(1350, 1350)
571#define QPC_FRE QPC_FIELD_LOC(1351, 1351)
572#define QPC_SQ_CUR_PSN QPC_FIELD_LOC(1375, 1352)
573#define QPC_MSG_USE_PKTN QPC_FIELD_LOC(1399, 1376)
574#define QPC_IRRL_HEAD_PRE QPC_FIELD_LOC(1407, 1400)
575#define QPC_SQ_CUR_SGE_BLK_ADDR_L QPC_FIELD_LOC(1439, 1408)
576#define QPC_SQ_CUR_SGE_BLK_ADDR_H QPC_FIELD_LOC(1459, 1440)
577#define QPC_IRRL_IDX_MSB QPC_FIELD_LOC(1471, 1460)
578#define QPC_CUR_SGE_OFFSET QPC_FIELD_LOC(1503, 1472)
579#define QPC_CUR_SGE_IDX QPC_FIELD_LOC(1527, 1504)
580#define QPC_EXT_SGE_NUM_LEFT QPC_FIELD_LOC(1535, 1528)
581#define QPC_OWNER_MODE QPC_FIELD_LOC(1536, 1536)
582#define QPC_CIRE_SLV_SQ_EN QPC_FIELD_LOC(1537, 1537)
583#define QPC_CIRE_DOING QPC_FIELD_LOC(1538, 1538)
584#define QPC_CIRE_RESULT QPC_FIELD_LOC(1539, 1539)
585#define QPC_OWNER_DB_WAIT_DO QPC_FIELD_LOC(1540, 1540)
586#define QPC_SQ_WQE_INVLD QPC_FIELD_LOC(1541, 1541)
587#define QPC_DCA_MODE QPC_FIELD_LOC(1542, 1542)
588#define QPC_RTY_OWNER_NOCHK QPC_FIELD_LOC(1543, 1543)
589#define QPC_V2_IRRL_HEAD QPC_FIELD_LOC(1543, 1536)
590#define QPC_SQ_MAX_PSN QPC_FIELD_LOC(1567, 1544)
591#define QPC_SQ_MAX_IDX QPC_FIELD_LOC(1583, 1568)
592#define QPC_LCL_OPERATED_CNT QPC_FIELD_LOC(1599, 1584)
593#define QPC_IRRL_BA_L QPC_FIELD_LOC(1631, 1600)
594#define QPC_IRRL_BA_H QPC_FIELD_LOC(1657, 1632)
595#define QPC_PKT_RNR_FLG QPC_FIELD_LOC(1658, 1658)
596#define QPC_PKT_RTY_FLG QPC_FIELD_LOC(1659, 1659)
597#define QPC_RMT_E2E QPC_FIELD_LOC(1660, 1660)
598#define QPC_SR_MAX QPC_FIELD_LOC(1663, 1661)
599#define QPC_LSN QPC_FIELD_LOC(1687, 1664)
600#define QPC_RETRY_NUM_INIT QPC_FIELD_LOC(1690, 1688)
601#define QPC_CHECK_FLG QPC_FIELD_LOC(1692, 1691)
602#define QPC_RETRY_CNT QPC_FIELD_LOC(1695, 1693)
603#define QPC_SQ_TIMER QPC_FIELD_LOC(1727, 1696)
604#define QPC_RETRY_MSG_MSN QPC_FIELD_LOC(1743, 1728)
605#define QPC_RETRY_MSG_PSN_L QPC_FIELD_LOC(1759, 1744)
606#define QPC_RETRY_MSG_PSN_H QPC_FIELD_LOC(1767, 1760)
607#define QPC_RETRY_MSG_FPKT_PSN QPC_FIELD_LOC(1791, 1768)
608#define QPC_RX_SQ_CUR_BLK_ADDR_L QPC_FIELD_LOC(1823, 1792)
609#define QPC_RX_SQ_CUR_BLK_ADDR_H QPC_FIELD_LOC(1843, 1824)
610#define QPC_IRRL_SGE_IDX QPC_FIELD_LOC(1851, 1844)
611#define QPC_LSAN_EN QPC_FIELD_LOC(1852, 1852)
612#define QPC_SO_LP_VLD QPC_FIELD_LOC(1853, 1853)
613#define QPC_FENCE_LP_VLD QPC_FIELD_LOC(1854, 1854)
614#define QPC_IRRL_LP_VLD QPC_FIELD_LOC(1855, 1855)
615#define QPC_IRRL_CUR_SGE_OFFSET QPC_FIELD_LOC(1887, 1856)
616#define QPC_IRRL_TAIL_REAL QPC_FIELD_LOC(1895, 1888)
617#define QPC_IRRL_TAIL_RD QPC_FIELD_LOC(1903, 1896)
618#define QPC_RX_ACK_MSN QPC_FIELD_LOC(1919, 1904)
619#define QPC_RX_ACK_EPSN QPC_FIELD_LOC(1943, 1920)
620#define QPC_RNR_NUM_INIT QPC_FIELD_LOC(1946, 1944)
621#define QPC_RNR_CNT QPC_FIELD_LOC(1949, 1947)
622#define QPC_LCL_OP_FLG QPC_FIELD_LOC(1950, 1950)
623#define QPC_IRRL_RD_FLG QPC_FIELD_LOC(1951, 1951)
624#define QPC_IRRL_PSN QPC_FIELD_LOC(1975, 1952)
625#define QPC_ACK_PSN_ERR QPC_FIELD_LOC(1976, 1976)
626#define QPC_ACK_LAST_OPTYPE QPC_FIELD_LOC(1978, 1977)
627#define QPC_IRRL_PSN_VLD QPC_FIELD_LOC(1979, 1979)
628#define QPC_RNR_RETRY_FLAG QPC_FIELD_LOC(1980, 1980)
629#define QPC_SQ_RTY_TX_ERR QPC_FIELD_LOC(1981, 1981)
630#define QPC_LAST_IND QPC_FIELD_LOC(1982, 1982)
631#define QPC_CQ_ERR_IND QPC_FIELD_LOC(1983, 1983)
632#define QPC_TX_CQN QPC_FIELD_LOC(2007, 1984)
633#define QPC_SIG_TYPE QPC_FIELD_LOC(2008, 2008)
634#define QPC_ERR_TYPE QPC_FIELD_LOC(2015, 2009)
635#define QPC_RQ_CQE_IDX QPC_FIELD_LOC(2031, 2016)
636#define QPC_SQ_FLUSH_IDX QPC_FIELD_LOC(2047, 2032)
637
638#define RETRY_MSG_PSN_SHIFT 16
639
640#define QPCEX_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_qp_context_ex, h, l)
641
642#define QPCEX_CONG_ALG_SEL QPCEX_FIELD_LOC(0, 0)
643#define QPCEX_CONG_ALG_SUB_SEL QPCEX_FIELD_LOC(1, 1)
644#define QPCEX_DIP_CTX_IDX_VLD QPCEX_FIELD_LOC(2, 2)
645#define QPCEX_DIP_CTX_IDX QPCEX_FIELD_LOC(22, 3)
646#define QPCEX_SQ_RQ_NOT_FORBID_EN QPCEX_FIELD_LOC(23, 23)
647#define QPCEX_STASH QPCEX_FIELD_LOC(82, 82)
648
649#define V2_QP_RWE_S 1 /* rdma write enable */
650#define V2_QP_RRE_S 2 /* rdma read enable */
651#define V2_QP_ATE_S 3 /* rdma atomic enable */
652
653struct hns_roce_v2_cqe {
654 __le32 byte_4;
655 union {
656 __le32 rkey;
657 __le32 immtdata;
658 };
659 __le32 byte_12;
660 __le32 byte_16;
661 __le32 byte_cnt;
662 u8 smac[4];
663 __le32 byte_28;
664 __le32 byte_32;
665 __le32 rsv[8];
666};
667
668#define CQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_cqe, h, l)
669
670#define CQE_OPCODE CQE_FIELD_LOC(4, 0)
671#define CQE_RQ_INLINE CQE_FIELD_LOC(5, 5)
672#define CQE_S_R CQE_FIELD_LOC(6, 6)
673#define CQE_OWNER CQE_FIELD_LOC(7, 7)
674#define CQE_STATUS CQE_FIELD_LOC(15, 8)
675#define CQE_WQE_IDX CQE_FIELD_LOC(31, 16)
676#define CQE_RKEY_IMMTDATA CQE_FIELD_LOC(63, 32)
677#define CQE_XRC_SRQN CQE_FIELD_LOC(87, 64)
678#define CQE_RSV0 CQE_FIELD_LOC(95, 88)
679#define CQE_LCL_QPN CQE_FIELD_LOC(119, 96)
680#define CQE_SUB_STATUS CQE_FIELD_LOC(127, 120)
681#define CQE_BYTE_CNT CQE_FIELD_LOC(159, 128)
682#define CQE_SMAC CQE_FIELD_LOC(207, 160)
683#define CQE_PORT_TYPE CQE_FIELD_LOC(209, 208)
684#define CQE_VID CQE_FIELD_LOC(221, 210)
685#define CQE_VID_VLD CQE_FIELD_LOC(222, 222)
686#define CQE_RSV2 CQE_FIELD_LOC(223, 223)
687#define CQE_RMT_QPN CQE_FIELD_LOC(247, 224)
688#define CQE_SL CQE_FIELD_LOC(250, 248)
689#define CQE_PORTN CQE_FIELD_LOC(253, 251)
690#define CQE_GRH CQE_FIELD_LOC(254, 254)
691#define CQE_LPK CQE_FIELD_LOC(255, 255)
692#define CQE_RSV3 CQE_FIELD_LOC(511, 256)
693
694struct hns_roce_v2_mpt_entry {
695 __le32 byte_4_pd_hop_st;
696 __le32 byte_8_mw_cnt_en;
697 __le32 byte_12_mw_pa;
698 __le32 bound_lkey;
699 __le32 len_l;
700 __le32 len_h;
701 __le32 lkey;
702 __le32 va_l;
703 __le32 va_h;
704 __le32 pbl_size;
705 __le32 pbl_ba_l;
706 __le32 byte_48_mode_ba;
707 __le32 pa0_l;
708 __le32 byte_56_pa0_h;
709 __le32 pa1_l;
710 __le32 byte_64_buf_pa1;
711};
712
713#define MPT_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_mpt_entry, h, l)
714
715#define MPT_ST MPT_FIELD_LOC(1, 0)
716#define MPT_PBL_HOP_NUM MPT_FIELD_LOC(3, 2)
717#define MPT_PBL_BA_PG_SZ MPT_FIELD_LOC(7, 4)
718#define MPT_PD MPT_FIELD_LOC(31, 8)
719#define MPT_RA_EN MPT_FIELD_LOC(32, 32)
720#define MPT_R_INV_EN MPT_FIELD_LOC(33, 33)
721#define MPT_L_INV_EN MPT_FIELD_LOC(34, 34)
722#define MPT_BIND_EN MPT_FIELD_LOC(35, 35)
723#define MPT_ATOMIC_EN MPT_FIELD_LOC(36, 36)
724#define MPT_RR_EN MPT_FIELD_LOC(37, 37)
725#define MPT_RW_EN MPT_FIELD_LOC(38, 38)
726#define MPT_LW_EN MPT_FIELD_LOC(39, 39)
727#define MPT_MW_CNT MPT_FIELD_LOC(63, 40)
728#define MPT_FRE MPT_FIELD_LOC(64, 64)
729#define MPT_PA MPT_FIELD_LOC(65, 65)
730#define MPT_ZBVA MPT_FIELD_LOC(66, 66)
731#define MPT_SHARE MPT_FIELD_LOC(67, 67)
732#define MPT_MR_MW MPT_FIELD_LOC(68, 68)
733#define MPT_BPD MPT_FIELD_LOC(69, 69)
734#define MPT_BQP MPT_FIELD_LOC(70, 70)
735#define MPT_INNER_PA_VLD MPT_FIELD_LOC(71, 71)
736#define MPT_MW_BIND_QPN MPT_FIELD_LOC(95, 72)
737#define MPT_BOUND_LKEY MPT_FIELD_LOC(127, 96)
738#define MPT_LEN_L MPT_FIELD_LOC(159, 128)
739#define MPT_LEN_H MPT_FIELD_LOC(191, 160)
740#define MPT_LKEY MPT_FIELD_LOC(223, 192)
741#define MPT_VA MPT_FIELD_LOC(287, 224)
742#define MPT_PBL_SIZE MPT_FIELD_LOC(319, 288)
743#define MPT_PBL_BA_L MPT_FIELD_LOC(351, 320)
744#define MPT_PBL_BA_H MPT_FIELD_LOC(380, 352)
745#define MPT_BLK_MODE MPT_FIELD_LOC(381, 381)
746#define MPT_RSV0 MPT_FIELD_LOC(383, 382)
747#define MPT_PA0_L MPT_FIELD_LOC(415, 384)
748#define MPT_PA0_H MPT_FIELD_LOC(441, 416)
749#define MPT_BOUND_VA MPT_FIELD_LOC(447, 442)
750#define MPT_PA1_L MPT_FIELD_LOC(479, 448)
751#define MPT_PA1_H MPT_FIELD_LOC(505, 480)
752#define MPT_PERSIST_EN MPT_FIELD_LOC(506, 506)
753#define MPT_RSV2 MPT_FIELD_LOC(507, 507)
754#define MPT_PBL_BUF_PG_SZ MPT_FIELD_LOC(511, 508)
755
756#define V2_MPT_BYTE_4_MPT_ST_S 0
757#define V2_MPT_BYTE_4_MPT_ST_M GENMASK(1, 0)
758
759#define V2_MPT_BYTE_4_PBL_HOP_NUM_S 2
760#define V2_MPT_BYTE_4_PBL_HOP_NUM_M GENMASK(3, 2)
761
762#define V2_MPT_BYTE_4_PBL_BA_PG_SZ_S 4
763#define V2_MPT_BYTE_4_PBL_BA_PG_SZ_M GENMASK(7, 4)
764
765#define V2_MPT_BYTE_4_PD_S 8
766#define V2_MPT_BYTE_4_PD_M GENMASK(31, 8)
767
768#define V2_MPT_BYTE_8_RA_EN_S 0
769
770#define V2_MPT_BYTE_8_R_INV_EN_S 1
771
772#define V2_MPT_BYTE_8_L_INV_EN_S 2
773
774#define V2_MPT_BYTE_8_BIND_EN_S 3
775
776#define V2_MPT_BYTE_8_ATOMIC_EN_S 4
777
778#define V2_MPT_BYTE_8_RR_EN_S 5
779
780#define V2_MPT_BYTE_8_RW_EN_S 6
781
782#define V2_MPT_BYTE_8_LW_EN_S 7
783
784#define V2_MPT_BYTE_8_MW_CNT_S 8
785#define V2_MPT_BYTE_8_MW_CNT_M GENMASK(31, 8)
786
787#define V2_MPT_BYTE_12_FRE_S 0
788
789#define V2_MPT_BYTE_12_PA_S 1
790
791#define V2_MPT_BYTE_12_MR_MW_S 4
792
793#define V2_MPT_BYTE_12_BPD_S 5
794
795#define V2_MPT_BYTE_12_BQP_S 6
796
797#define V2_MPT_BYTE_12_INNER_PA_VLD_S 7
798
799#define V2_MPT_BYTE_12_MW_BIND_QPN_S 8
800#define V2_MPT_BYTE_12_MW_BIND_QPN_M GENMASK(31, 8)
801
802#define V2_MPT_BYTE_48_PBL_BA_H_S 0
803#define V2_MPT_BYTE_48_PBL_BA_H_M GENMASK(28, 0)
804
805#define V2_MPT_BYTE_48_BLK_MODE_S 29
806
807#define V2_MPT_BYTE_56_PA0_H_S 0
808#define V2_MPT_BYTE_56_PA0_H_M GENMASK(25, 0)
809
810#define V2_MPT_BYTE_64_PA1_H_S 0
811#define V2_MPT_BYTE_64_PA1_H_M GENMASK(25, 0)
812
813#define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S 28
814#define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28)
815
816struct hns_roce_v2_db {
817 __le32 data[2];
818};
819
820#define DB_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_db, h, l)
821
822#define DB_TAG DB_FIELD_LOC(23, 0)
823#define DB_CMD DB_FIELD_LOC(27, 24)
824#define DB_FLAG DB_FIELD_LOC(31, 31)
825#define DB_PI DB_FIELD_LOC(47, 32)
826#define DB_SL DB_FIELD_LOC(50, 48)
827#define DB_CQ_CI DB_FIELD_LOC(55, 32)
828#define DB_CQ_NOTIFY DB_FIELD_LOC(56, 56)
829#define DB_CQ_CMD_SN DB_FIELD_LOC(58, 57)
830#define EQ_DB_TAG DB_FIELD_LOC(7, 0)
831#define EQ_DB_CMD DB_FIELD_LOC(17, 16)
832#define EQ_DB_CI DB_FIELD_LOC(55, 32)
833
834#define V2_DB_PRODUCER_IDX_S 0
835#define V2_DB_PRODUCER_IDX_M GENMASK(15, 0)
836
837#define V2_CQ_DB_CONS_IDX_S 0
838#define V2_CQ_DB_CONS_IDX_M GENMASK(23, 0)
839
840struct hns_roce_v2_ud_send_wqe {
841 __le32 byte_4;
842 __le32 msg_len;
843 __le32 immtdata;
844 __le32 byte_16;
845 __le32 byte_20;
846 __le32 byte_24;
847 __le32 qkey;
848 __le32 byte_32;
849 __le32 byte_36;
850 __le32 byte_40;
851 u8 dmac[ETH_ALEN];
852 u8 sgid_index;
853 u8 smac_index;
854 u8 dgid[GID_LEN_V2];
855};
856
857#define UD_SEND_WQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_ud_send_wqe, h, l)
858
859#define UD_SEND_WQE_OPCODE UD_SEND_WQE_FIELD_LOC(4, 0)
860#define UD_SEND_WQE_OWNER UD_SEND_WQE_FIELD_LOC(7, 7)
861#define UD_SEND_WQE_CQE UD_SEND_WQE_FIELD_LOC(8, 8)
862#define UD_SEND_WQE_SE UD_SEND_WQE_FIELD_LOC(11, 11)
863#define UD_SEND_WQE_PD UD_SEND_WQE_FIELD_LOC(119, 96)
864#define UD_SEND_WQE_SGE_NUM UD_SEND_WQE_FIELD_LOC(127, 120)
865#define UD_SEND_WQE_MSG_START_SGE_IDX UD_SEND_WQE_FIELD_LOC(151, 128)
866#define UD_SEND_WQE_UDPSPN UD_SEND_WQE_FIELD_LOC(191, 176)
867#define UD_SEND_WQE_DQPN UD_SEND_WQE_FIELD_LOC(247, 224)
868#define UD_SEND_WQE_VLAN UD_SEND_WQE_FIELD_LOC(271, 256)
869#define UD_SEND_WQE_HOPLIMIT UD_SEND_WQE_FIELD_LOC(279, 272)
870#define UD_SEND_WQE_TCLASS UD_SEND_WQE_FIELD_LOC(287, 280)
871#define UD_SEND_WQE_FLOW_LABEL UD_SEND_WQE_FIELD_LOC(307, 288)
872#define UD_SEND_WQE_SL UD_SEND_WQE_FIELD_LOC(311, 308)
873#define UD_SEND_WQE_VLAN_EN UD_SEND_WQE_FIELD_LOC(318, 318)
874#define UD_SEND_WQE_LBI UD_SEND_WQE_FIELD_LOC(319, 319)
875
876struct hns_roce_v2_rc_send_wqe {
877 __le32 byte_4;
878 __le32 msg_len;
879 union {
880 __le32 inv_key;
881 __le32 immtdata;
882 };
883 __le32 byte_16;
884 __le32 byte_20;
885 __le32 rkey;
886 __le64 va;
887};
888
889#define RC_SEND_WQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_v2_rc_send_wqe, h, l)
890
891#define RC_SEND_WQE_OPCODE RC_SEND_WQE_FIELD_LOC(4, 0)
892#define RC_SEND_WQE_DB_SL_L RC_SEND_WQE_FIELD_LOC(6, 5)
893#define RC_SEND_WQE_DB_SL_H RC_SEND_WQE_FIELD_LOC(14, 13)
894#define RC_SEND_WQE_OWNER RC_SEND_WQE_FIELD_LOC(7, 7)
895#define RC_SEND_WQE_CQE RC_SEND_WQE_FIELD_LOC(8, 8)
896#define RC_SEND_WQE_FENCE RC_SEND_WQE_FIELD_LOC(9, 9)
897#define RC_SEND_WQE_SE RC_SEND_WQE_FIELD_LOC(11, 11)
898#define RC_SEND_WQE_INLINE RC_SEND_WQE_FIELD_LOC(12, 12)
899#define RC_SEND_WQE_WQE_INDEX RC_SEND_WQE_FIELD_LOC(30, 15)
900#define RC_SEND_WQE_FLAG RC_SEND_WQE_FIELD_LOC(31, 31)
901#define RC_SEND_WQE_XRC_SRQN RC_SEND_WQE_FIELD_LOC(119, 96)
902#define RC_SEND_WQE_SGE_NUM RC_SEND_WQE_FIELD_LOC(127, 120)
903#define RC_SEND_WQE_MSG_START_SGE_IDX RC_SEND_WQE_FIELD_LOC(151, 128)
904#define RC_SEND_WQE_INL_TYPE RC_SEND_WQE_FIELD_LOC(159, 159)
905
906struct hns_roce_wqe_frmr_seg {
907 __le32 pbl_size;
908 __le32 byte_40;
909};
910
911#define FRMR_WQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_wqe_frmr_seg, h, l)
912
913#define FRMR_PBL_SIZE FRMR_WQE_FIELD_LOC(31, 0)
914#define FRMR_BLOCK_SIZE FRMR_WQE_FIELD_LOC(35, 32)
915#define FRMR_PBL_BUF_PG_SZ FRMR_WQE_FIELD_LOC(39, 36)
916#define FRMR_BLK_MODE FRMR_WQE_FIELD_LOC(40, 40)
917#define FRMR_ZBVA FRMR_WQE_FIELD_LOC(41, 41)
918#define FRMR_BIND_EN FRMR_WQE_FIELD_LOC(42, 42)
919#define FRMR_ATOMIC FRMR_WQE_FIELD_LOC(43, 43)
920#define FRMR_RR FRMR_WQE_FIELD_LOC(44, 44)
921#define FRMR_RW FRMR_WQE_FIELD_LOC(45, 45)
922#define FRMR_LW FRMR_WQE_FIELD_LOC(46, 46)
923
924struct hns_roce_v2_wqe_data_seg {
925 __le32 len;
926 __le32 lkey;
927 __le64 addr;
928};
929
930struct hns_roce_query_version {
931 __le16 rocee_vendor_id;
932 __le16 rocee_hw_version;
933 __le32 rsv[5];
934};
935
936struct hns_roce_query_fw_info {
937 __le32 fw_ver;
938 __le32 rsv[5];
939};
940
941struct hns_roce_func_clear {
942 __le32 rst_funcid_en;
943 __le32 func_done;
944 __le32 rsv[4];
945};
946
947#define FUNC_CLEAR_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_func_clear, h, l)
948
949#define FUNC_CLEAR_RST_FUN_DONE FUNC_CLEAR_FIELD_LOC(32, 32)
950
951/* Each physical function manages up to 248 virtual functions, it takes up to
952 * 100ms for each function to execute clear. If an abnormal reset occurs, it is
953 * executed twice at most, so it takes up to 249 * 2 * 100ms.
954 */
955#define HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS (249 * 2 * 100)
956#define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL 40
957#define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT 20
958
959#define CFG_LLM_A_BA_L CMQ_REQ_FIELD_LOC(31, 0)
960#define CFG_LLM_A_BA_H CMQ_REQ_FIELD_LOC(63, 32)
961#define CFG_LLM_A_DEPTH CMQ_REQ_FIELD_LOC(76, 64)
962#define CFG_LLM_A_PGSZ CMQ_REQ_FIELD_LOC(83, 80)
963#define CFG_LLM_A_INIT_EN CMQ_REQ_FIELD_LOC(84, 84)
964#define CFG_LLM_A_HEAD_BA_L CMQ_REQ_FIELD_LOC(127, 96)
965#define CFG_LLM_A_HEAD_BA_H CMQ_REQ_FIELD_LOC(147, 128)
966#define CFG_LLM_A_HEAD_NXTPTR CMQ_REQ_FIELD_LOC(159, 148)
967#define CFG_LLM_A_HEAD_PTR CMQ_REQ_FIELD_LOC(171, 160)
968#define CFG_LLM_B_TAIL_BA_L CMQ_REQ_FIELD_LOC(31, 0)
969#define CFG_LLM_B_TAIL_BA_H CMQ_REQ_FIELD_LOC(63, 32)
970#define CFG_LLM_B_TAIL_PTR CMQ_REQ_FIELD_LOC(75, 64)
971
972/* Fields of HNS_ROCE_OPC_CFG_GLOBAL_PARAM */
973#define CFG_GLOBAL_PARAM_1US_CYCLES CMQ_REQ_FIELD_LOC(9, 0)
974#define CFG_GLOBAL_PARAM_UDP_PORT CMQ_REQ_FIELD_LOC(31, 16)
975
976/*
977 * Fields of HNS_ROCE_OPC_QUERY_PF_RES, HNS_ROCE_OPC_QUERY_VF_RES
978 * and HNS_ROCE_OPC_ALLOC_VF_RES
979 */
980#define FUNC_RES_A_VF_ID CMQ_REQ_FIELD_LOC(7, 0)
981#define FUNC_RES_A_QPC_BT_IDX CMQ_REQ_FIELD_LOC(42, 32)
982#define FUNC_RES_A_QPC_BT_NUM CMQ_REQ_FIELD_LOC(59, 48)
983#define FUNC_RES_A_SRQC_BT_IDX CMQ_REQ_FIELD_LOC(72, 64)
984#define FUNC_RES_A_SRQC_BT_NUM CMQ_REQ_FIELD_LOC(89, 80)
985#define FUNC_RES_A_CQC_BT_IDX CMQ_REQ_FIELD_LOC(104, 96)
986#define FUNC_RES_A_CQC_BT_NUM CMQ_REQ_FIELD_LOC(121, 112)
987#define FUNC_RES_A_MPT_BT_IDX CMQ_REQ_FIELD_LOC(136, 128)
988#define FUNC_RES_A_MPT_BT_NUM CMQ_REQ_FIELD_LOC(153, 144)
989#define FUNC_RES_A_EQC_BT_IDX CMQ_REQ_FIELD_LOC(168, 160)
990#define FUNC_RES_A_EQC_BT_NUM CMQ_REQ_FIELD_LOC(185, 176)
991#define FUNC_RES_B_SMAC_IDX CMQ_REQ_FIELD_LOC(39, 32)
992#define FUNC_RES_B_SMAC_NUM CMQ_REQ_FIELD_LOC(48, 40)
993#define FUNC_RES_B_SGID_IDX CMQ_REQ_FIELD_LOC(71, 64)
994#define FUNC_RES_B_SGID_NUM CMQ_REQ_FIELD_LOC(80, 72)
995#define FUNC_RES_B_QID_IDX CMQ_REQ_FIELD_LOC(105, 96)
996#define FUNC_RES_B_QID_NUM CMQ_REQ_FIELD_LOC(122, 112)
997#define FUNC_RES_V_QID_NUM CMQ_REQ_FIELD_LOC(115, 112)
998
999#define FUNC_RES_B_SCCC_BT_IDX CMQ_REQ_FIELD_LOC(136, 128)
1000#define FUNC_RES_B_SCCC_BT_NUM CMQ_REQ_FIELD_LOC(145, 137)
1001#define FUNC_RES_B_GMV_BT_IDX CMQ_REQ_FIELD_LOC(167, 160)
1002#define FUNC_RES_B_GMV_BT_NUM CMQ_REQ_FIELD_LOC(176, 168)
1003#define FUNC_RES_V_GMV_BT_NUM CMQ_REQ_FIELD_LOC(184, 176)
1004
1005/* Fields of HNS_ROCE_OPC_QUERY_PF_TIMER_RES */
1006#define PF_TIMER_RES_QPC_ITEM_IDX CMQ_REQ_FIELD_LOC(43, 32)
1007#define PF_TIMER_RES_QPC_ITEM_NUM CMQ_REQ_FIELD_LOC(60, 48)
1008#define PF_TIMER_RES_CQC_ITEM_IDX CMQ_REQ_FIELD_LOC(74, 64)
1009#define PF_TIMER_RES_CQC_ITEM_NUM CMQ_REQ_FIELD_LOC(91, 80)
1010
1011struct hns_roce_vf_switch {
1012 __le32 rocee_sel;
1013 __le32 fun_id;
1014 __le32 cfg;
1015 __le32 resv1;
1016 __le32 resv2;
1017 __le32 resv3;
1018};
1019
1020#define VF_SWITCH_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_vf_switch, h, l)
1021
1022#define VF_SWITCH_VF_ID VF_SWITCH_FIELD_LOC(42, 35)
1023#define VF_SWITCH_ALW_LPBK VF_SWITCH_FIELD_LOC(65, 65)
1024#define VF_SWITCH_ALW_LCL_LPBK VF_SWITCH_FIELD_LOC(66, 66)
1025#define VF_SWITCH_ALW_DST_OVRD VF_SWITCH_FIELD_LOC(67, 67)
1026
1027struct hns_roce_post_mbox {
1028 __le32 in_param_l;
1029 __le32 in_param_h;
1030 __le32 out_param_l;
1031 __le32 out_param_h;
1032 __le32 cmd_tag;
1033 __le32 token_event_en;
1034};
1035
1036struct hns_roce_mbox_status {
1037 __le32 mb_status_hw_run;
1038 __le32 rsv[5];
1039};
1040
1041#define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS 10000
1042
1043#define MB_ST_HW_RUN_M BIT(31)
1044#define MB_ST_COMPLETE_M GENMASK(7, 0)
1045
1046#define MB_ST_COMPLETE_SUCC 1
1047
1048/* Fields of HNS_ROCE_OPC_CFG_BT_ATTR */
1049#define CFG_BT_ATTR_QPC_BA_PGSZ CMQ_REQ_FIELD_LOC(3, 0)
1050#define CFG_BT_ATTR_QPC_BUF_PGSZ CMQ_REQ_FIELD_LOC(7, 4)
1051#define CFG_BT_ATTR_QPC_HOPNUM CMQ_REQ_FIELD_LOC(9, 8)
1052#define CFG_BT_ATTR_SRQC_BA_PGSZ CMQ_REQ_FIELD_LOC(35, 32)
1053#define CFG_BT_ATTR_SRQC_BUF_PGSZ CMQ_REQ_FIELD_LOC(39, 36)
1054#define CFG_BT_ATTR_SRQC_HOPNUM CMQ_REQ_FIELD_LOC(41, 40)
1055#define CFG_BT_ATTR_CQC_BA_PGSZ CMQ_REQ_FIELD_LOC(67, 64)
1056#define CFG_BT_ATTR_CQC_BUF_PGSZ CMQ_REQ_FIELD_LOC(71, 68)
1057#define CFG_BT_ATTR_CQC_HOPNUM CMQ_REQ_FIELD_LOC(73, 72)
1058#define CFG_BT_ATTR_MPT_BA_PGSZ CMQ_REQ_FIELD_LOC(99, 96)
1059#define CFG_BT_ATTR_MPT_BUF_PGSZ CMQ_REQ_FIELD_LOC(103, 100)
1060#define CFG_BT_ATTR_MPT_HOPNUM CMQ_REQ_FIELD_LOC(105, 104)
1061#define CFG_BT_ATTR_SCCC_BA_PGSZ CMQ_REQ_FIELD_LOC(131, 128)
1062#define CFG_BT_ATTR_SCCC_BUF_PGSZ CMQ_REQ_FIELD_LOC(135, 132)
1063#define CFG_BT_ATTR_SCCC_HOPNUM CMQ_REQ_FIELD_LOC(137, 136)
1064
1065/* Fields of HNS_ROCE_OPC_CFG_ENTRY_SIZE */
1066#define CFG_HEM_ENTRY_SIZE_TYPE CMQ_REQ_FIELD_LOC(31, 0)
1067enum {
1068 HNS_ROCE_CFG_QPC_SIZE = BIT(0),
1069 HNS_ROCE_CFG_SCCC_SIZE = BIT(1),
1070};
1071
1072#define CFG_HEM_ENTRY_SIZE_VALUE CMQ_REQ_FIELD_LOC(191, 160)
1073
1074/* Fields of HNS_ROCE_OPC_CFG_GMV_BT */
1075#define CFG_GMV_BT_BA_L CMQ_REQ_FIELD_LOC(31, 0)
1076#define CFG_GMV_BT_BA_H CMQ_REQ_FIELD_LOC(51, 32)
1077#define CFG_GMV_BT_IDX CMQ_REQ_FIELD_LOC(95, 64)
1078
1079/* Fields of HNS_ROCE_QUERY_RAM_ECC */
1080#define QUERY_RAM_ECC_1BIT_ERR CMQ_REQ_FIELD_LOC(31, 0)
1081#define QUERY_RAM_ECC_RES_TYPE CMQ_REQ_FIELD_LOC(63, 32)
1082#define QUERY_RAM_ECC_TAG CMQ_REQ_FIELD_LOC(95, 64)
1083
1084struct hns_roce_cfg_sgid_tb {
1085 __le32 table_idx_rsv;
1086 __le32 vf_sgid_l;
1087 __le32 vf_sgid_ml;
1088 __le32 vf_sgid_mh;
1089 __le32 vf_sgid_h;
1090 __le32 vf_sgid_type_rsv;
1091};
1092
1093#define SGID_TB_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_cfg_sgid_tb, h, l)
1094
1095#define CFG_SGID_TB_TABLE_IDX SGID_TB_FIELD_LOC(7, 0)
1096#define CFG_SGID_TB_VF_SGID_TYPE SGID_TB_FIELD_LOC(161, 160)
1097
1098struct hns_roce_cfg_smac_tb {
1099 __le32 tb_idx_rsv;
1100 __le32 vf_smac_l;
1101 __le32 vf_smac_h_rsv;
1102 __le32 rsv[3];
1103};
1104
1105#define SMAC_TB_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_cfg_smac_tb, h, l)
1106
1107#define CFG_SMAC_TB_IDX SMAC_TB_FIELD_LOC(7, 0)
1108#define CFG_SMAC_TB_VF_SMAC_H SMAC_TB_FIELD_LOC(79, 64)
1109
1110struct hns_roce_cfg_gmv_tb_a {
1111 __le32 vf_sgid_l;
1112 __le32 vf_sgid_ml;
1113 __le32 vf_sgid_mh;
1114 __le32 vf_sgid_h;
1115 __le32 vf_sgid_type_vlan;
1116 __le32 resv;
1117};
1118
1119#define GMV_TB_A_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_cfg_gmv_tb_a, h, l)
1120
1121#define GMV_TB_A_VF_SGID_TYPE GMV_TB_A_FIELD_LOC(129, 128)
1122#define GMV_TB_A_VF_VLAN_EN GMV_TB_A_FIELD_LOC(130, 130)
1123#define GMV_TB_A_VF_VLAN_ID GMV_TB_A_FIELD_LOC(155, 144)
1124
1125struct hns_roce_cfg_gmv_tb_b {
1126 __le32 vf_smac_l;
1127 __le32 vf_smac_h;
1128 __le32 table_idx_rsv;
1129 __le32 resv[3];
1130};
1131
1132#define GMV_TB_B_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_cfg_gmv_tb_b, h, l)
1133
1134#define GMV_TB_B_SMAC_H GMV_TB_B_FIELD_LOC(47, 32)
1135#define GMV_TB_B_SGID_IDX GMV_TB_B_FIELD_LOC(71, 64)
1136
1137#define HNS_ROCE_QUERY_PF_CAPS_CMD_NUM 5
1138struct hns_roce_query_pf_caps_a {
1139 u8 number_ports;
1140 u8 local_ca_ack_delay;
1141 __le16 max_sq_sg;
1142 __le16 max_sq_inline;
1143 __le16 max_rq_sg;
1144 __le32 rsv0;
1145 __le16 num_qpc_timer;
1146 __le16 num_cqc_timer;
1147 __le16 max_srq_sges;
1148 u8 num_aeq_vectors;
1149 u8 num_other_vectors;
1150 u8 max_sq_desc_sz;
1151 u8 max_rq_desc_sz;
1152 u8 rsv1;
1153 u8 cqe_sz;
1154};
1155
1156struct hns_roce_query_pf_caps_b {
1157 u8 mtpt_entry_sz;
1158 u8 irrl_entry_sz;
1159 u8 trrl_entry_sz;
1160 u8 cqc_entry_sz;
1161 u8 srqc_entry_sz;
1162 u8 idx_entry_sz;
1163 u8 sccc_sz;
1164 u8 max_mtu;
1165 __le16 qpc_sz;
1166 __le16 qpc_timer_entry_sz;
1167 __le16 cqc_timer_entry_sz;
1168 u8 min_cqes;
1169 u8 min_wqes;
1170 __le32 page_size_cap;
1171 u8 pkey_table_len;
1172 u8 phy_num_uars;
1173 u8 ctx_hop_num;
1174 u8 pbl_hop_num;
1175};
1176
1177struct hns_roce_query_pf_caps_c {
1178 __le32 cap_flags_num_pds;
1179 __le32 max_gid_num_cqs;
1180 __le32 cq_depth;
1181 __le32 num_mrws;
1182 __le32 ord_num_qps;
1183 __le16 sq_depth;
1184 __le16 rq_depth;
1185};
1186
1187#define PF_CAPS_C_FIELD_LOC(h, l) \
1188 FIELD_LOC(struct hns_roce_query_pf_caps_c, h, l)
1189
1190#define PF_CAPS_C_NUM_PDS PF_CAPS_C_FIELD_LOC(19, 0)
1191#define PF_CAPS_C_CAP_FLAGS PF_CAPS_C_FIELD_LOC(31, 20)
1192#define PF_CAPS_C_NUM_CQS PF_CAPS_C_FIELD_LOC(51, 32)
1193#define PF_CAPS_C_MAX_GID PF_CAPS_C_FIELD_LOC(60, 52)
1194#define PF_CAPS_C_CQ_DEPTH PF_CAPS_C_FIELD_LOC(86, 64)
1195#define PF_CAPS_C_NUM_XRCDS PF_CAPS_C_FIELD_LOC(91, 87)
1196#define PF_CAPS_C_NUM_MRWS PF_CAPS_C_FIELD_LOC(115, 96)
1197#define PF_CAPS_C_NUM_QPS PF_CAPS_C_FIELD_LOC(147, 128)
1198#define PF_CAPS_C_MAX_ORD PF_CAPS_C_FIELD_LOC(155, 148)
1199
1200struct hns_roce_query_pf_caps_d {
1201 __le32 wq_hop_num_max_srqs;
1202 __le16 srq_depth;
1203 __le16 cap_flags_ex;
1204 __le32 num_ceqs_ceq_depth;
1205 __le32 arm_st_aeq_depth;
1206 __le32 num_uars_rsv_pds;
1207 __le32 rsv_uars_rsv_qps;
1208};
1209
1210#define PF_CAPS_D_FIELD_LOC(h, l) \
1211 FIELD_LOC(struct hns_roce_query_pf_caps_d, h, l)
1212
1213#define PF_CAPS_D_NUM_SRQS PF_CAPS_D_FIELD_LOC(19, 0)
1214#define PF_CAPS_D_RQWQE_HOP_NUM PF_CAPS_D_FIELD_LOC(21, 20)
1215#define PF_CAPS_D_EX_SGE_HOP_NUM PF_CAPS_D_FIELD_LOC(23, 22)
1216#define PF_CAPS_D_SQWQE_HOP_NUM PF_CAPS_D_FIELD_LOC(25, 24)
1217#define PF_CAPS_D_CONG_TYPE PF_CAPS_D_FIELD_LOC(29, 26)
1218#define PF_CAPS_D_CEQ_DEPTH PF_CAPS_D_FIELD_LOC(85, 64)
1219#define PF_CAPS_D_NUM_CEQS PF_CAPS_D_FIELD_LOC(95, 86)
1220#define PF_CAPS_D_AEQ_DEPTH PF_CAPS_D_FIELD_LOC(117, 96)
1221#define PF_CAPS_D_AEQ_ARM_ST PF_CAPS_D_FIELD_LOC(119, 118)
1222#define PF_CAPS_D_CEQ_ARM_ST PF_CAPS_D_FIELD_LOC(121, 120)
1223#define PF_CAPS_D_RSV_PDS PF_CAPS_D_FIELD_LOC(147, 128)
1224#define PF_CAPS_D_NUM_UARS PF_CAPS_D_FIELD_LOC(155, 148)
1225#define PF_CAPS_D_RSV_QPS PF_CAPS_D_FIELD_LOC(179, 160)
1226#define PF_CAPS_D_RSV_UARS PF_CAPS_D_FIELD_LOC(187, 180)
1227
1228#define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12
1229
1230struct hns_roce_congestion_algorithm {
1231 u8 alg_sel;
1232 u8 alg_sub_sel;
1233 u8 dip_vld;
1234 u8 wnd_mode_sel;
1235};
1236
1237struct hns_roce_query_pf_caps_e {
1238 __le32 chunk_size_shift_rsv_mrws;
1239 __le32 rsv_cqs;
1240 __le32 rsv_srqs;
1241 __le32 rsv_lkey;
1242 __le16 ceq_max_cnt;
1243 __le16 ceq_period;
1244 __le16 aeq_max_cnt;
1245 __le16 aeq_period;
1246};
1247
1248#define PF_CAPS_E_FIELD_LOC(h, l) \
1249 FIELD_LOC(struct hns_roce_query_pf_caps_e, h, l)
1250
1251#define PF_CAPS_E_RSV_MRWS PF_CAPS_E_FIELD_LOC(19, 0)
1252#define PF_CAPS_E_CHUNK_SIZE_SHIFT PF_CAPS_E_FIELD_LOC(31, 20)
1253#define PF_CAPS_E_RSV_CQS PF_CAPS_E_FIELD_LOC(51, 32)
1254#define PF_CAPS_E_RSV_XRCDS PF_CAPS_E_FIELD_LOC(63, 52)
1255#define PF_CAPS_E_RSV_SRQS PF_CAPS_E_FIELD_LOC(83, 64)
1256#define PF_CAPS_E_RSV_LKEYS PF_CAPS_E_FIELD_LOC(115, 96)
1257
1258struct hns_roce_cmq_req {
1259 __le32 data[6];
1260};
1261
1262#define CMQ_REQ_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_cmq_req, h, l)
1263
1264struct hns_roce_cmq_desc {
1265 __le16 opcode;
1266 __le16 flag;
1267 __le16 retval;
1268 __le16 rsv;
1269 union {
1270 __le32 data[6];
1271 struct {
1272 __le32 own_func_num;
1273 __le32 own_mac_id;
1274 __le32 rsv[4];
1275 } func_info;
1276 };
1277};
1278
1279struct hns_roce_v2_cmq_ring {
1280 dma_addr_t desc_dma_addr;
1281 struct hns_roce_cmq_desc *desc;
1282 u32 head;
1283 u16 buf_size;
1284 u16 desc_num;
1285 u8 flag;
1286 spinlock_t lock; /* command queue lock */
1287};
1288
1289struct hns_roce_v2_cmq {
1290 struct hns_roce_v2_cmq_ring csq;
1291 u16 tx_timeout;
1292};
1293
1294struct hns_roce_link_table {
1295 struct hns_roce_buf_list table;
1296 struct hns_roce_buf *buf;
1297};
1298
1299#define HNS_ROCE_EXT_LLM_ENTRY(addr, id) (((id) << (64 - 12)) | ((addr) >> 12))
1300#define HNS_ROCE_EXT_LLM_MIN_PAGES(que_num) ((que_num) * 4 + 2)
1301
1302struct hns_roce_v2_free_mr {
1303 struct hns_roce_qp *rsv_qp[HNS_ROCE_FREE_MR_USED_QP_NUM];
1304 struct hns_roce_cq *rsv_cq;
1305 struct hns_roce_pd *rsv_pd;
1306 struct mutex mutex;
1307};
1308
1309struct hns_roce_v2_priv {
1310 struct hnae3_handle *handle;
1311 struct hns_roce_v2_cmq cmq;
1312 struct hns_roce_link_table ext_llm;
1313 struct hns_roce_v2_free_mr free_mr;
1314};
1315
1316struct hns_roce_dip {
1317 u8 dgid[GID_LEN_V2];
1318 u32 dip_idx;
1319 struct list_head node; /* all dips are on a list */
1320};
1321
1322struct fmea_ram_ecc {
1323 u32 is_ecc_err;
1324 u32 res_type;
1325 u32 index;
1326};
1327
1328/* only for RNR timeout issue of HIP08 */
1329#define HNS_ROCE_CLOCK_ADJUST 1000
1330#define HNS_ROCE_MAX_CQ_PERIOD 65
1331#define HNS_ROCE_MAX_EQ_PERIOD 65
1332#define HNS_ROCE_RNR_TIMER_10NS 1
1333#define HNS_ROCE_1US_CFG 999
1334#define HNS_ROCE_1NS_CFG 0
1335
1336#define HNS_ROCE_AEQ_DEFAULT_BURST_NUM 0x0
1337#define HNS_ROCE_AEQ_DEFAULT_INTERVAL 0x0
1338#define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x0
1339#define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x0
1340
1341#define HNS_ROCE_V2_EQ_STATE_INVALID 0
1342#define HNS_ROCE_V2_EQ_STATE_VALID 1
1343#define HNS_ROCE_V2_EQ_STATE_OVERFLOW 2
1344#define HNS_ROCE_V2_EQ_STATE_FAILURE 3
1345
1346#define HNS_ROCE_V2_EQ_OVER_IGNORE_0 0
1347#define HNS_ROCE_V2_EQ_OVER_IGNORE_1 1
1348
1349#define HNS_ROCE_V2_EQ_COALESCE_0 0
1350#define HNS_ROCE_V2_EQ_COALESCE_1 1
1351
1352#define HNS_ROCE_V2_EQ_FIRED 0
1353#define HNS_ROCE_V2_EQ_ARMED 1
1354#define HNS_ROCE_V2_EQ_ALWAYS_ARMED 3
1355
1356#define HNS_ROCE_EQ_INIT_EQE_CNT 0
1357#define HNS_ROCE_EQ_INIT_PROD_IDX 0
1358#define HNS_ROCE_EQ_INIT_REPORT_TIMER 0
1359#define HNS_ROCE_EQ_INIT_MSI_IDX 0
1360#define HNS_ROCE_EQ_INIT_CONS_IDX 0
1361#define HNS_ROCE_EQ_INIT_NXT_EQE_BA 0
1362
1363#define HNS_ROCE_V2_COMP_EQE_NUM 0x1000
1364#define HNS_ROCE_V2_ASYNC_EQE_NUM 0x1000
1365
1366#define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S 0
1367
1368#define HNS_ROCE_EQ_DB_CMD_AEQ 0x0
1369#define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED 0x1
1370#define HNS_ROCE_EQ_DB_CMD_CEQ 0x2
1371#define HNS_ROCE_EQ_DB_CMD_CEQ_ARMED 0x3
1372
1373#define EQ_ENABLE 1
1374#define EQ_DISABLE 0
1375
1376#define EQ_REG_OFFSET 0x4
1377
1378#define HNS_ROCE_INT_NAME_LEN 32
1379#define HNS_ROCE_V2_EQN_M GENMASK(23, 0)
1380
1381#define HNS_ROCE_V2_VF_ABN_INT_EN_S 0
1382#define HNS_ROCE_V2_VF_ABN_INT_EN_M GENMASK(0, 0)
1383#define HNS_ROCE_V2_VF_ABN_INT_ST_M GENMASK(2, 0)
1384#define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0)
1385#define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0)
1386
1387struct hns_roce_eq_context {
1388 __le32 data[16];
1389};
1390
1391#define EQC_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_eq_context, h, l)
1392
1393#define EQC_EQ_ST EQC_FIELD_LOC(1, 0)
1394#define EQC_EQE_HOP_NUM EQC_FIELD_LOC(3, 2)
1395#define EQC_OVER_IGNORE EQC_FIELD_LOC(4, 4)
1396#define EQC_COALESCE EQC_FIELD_LOC(5, 5)
1397#define EQC_ARM_ST EQC_FIELD_LOC(7, 6)
1398#define EQC_EQN EQC_FIELD_LOC(15, 8)
1399#define EQC_EQE_CNT EQC_FIELD_LOC(31, 16)
1400#define EQC_EQE_BA_PG_SZ EQC_FIELD_LOC(35, 32)
1401#define EQC_EQE_BUF_PG_SZ EQC_FIELD_LOC(39, 36)
1402#define EQC_EQ_PROD_INDX EQC_FIELD_LOC(63, 40)
1403#define EQC_EQ_MAX_CNT EQC_FIELD_LOC(79, 64)
1404#define EQC_EQ_PERIOD EQC_FIELD_LOC(95, 80)
1405#define EQC_EQE_REPORT_TIMER EQC_FIELD_LOC(127, 96)
1406#define EQC_EQE_BA_L EQC_FIELD_LOC(159, 128)
1407#define EQC_EQE_BA_H EQC_FIELD_LOC(188, 160)
1408#define EQC_SHIFT EQC_FIELD_LOC(199, 192)
1409#define EQC_MSI_INDX EQC_FIELD_LOC(207, 200)
1410#define EQC_CUR_EQE_BA_L EQC_FIELD_LOC(223, 208)
1411#define EQC_CUR_EQE_BA_M EQC_FIELD_LOC(255, 224)
1412#define EQC_CUR_EQE_BA_H EQC_FIELD_LOC(259, 256)
1413#define EQC_EQ_CONS_INDX EQC_FIELD_LOC(287, 264)
1414#define EQC_NEX_EQE_BA_L EQC_FIELD_LOC(319, 288)
1415#define EQC_NEX_EQE_BA_H EQC_FIELD_LOC(339, 320)
1416#define EQC_EQE_SIZE EQC_FIELD_LOC(341, 340)
1417
1418#define MAX_SERVICE_LEVEL 0x7
1419
1420struct hns_roce_wqe_atomic_seg {
1421 __le64 fetchadd_swap_data;
1422 __le64 cmp_data;
1423};
1424
1425struct hns_roce_sccc_clr {
1426 __le32 qpn;
1427 __le32 rsv[5];
1428};
1429
1430struct hns_roce_sccc_clr_done {
1431 __le32 clr_done;
1432 __le32 rsv[5];
1433};
1434
1435int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata);
1436
1437static inline void hns_roce_write64(struct hns_roce_dev *hr_dev, __le32 val[2],
1438 void __iomem *dest)
1439{
1440 struct hns_roce_v2_priv *priv = hr_dev->priv;
1441 struct hnae3_handle *handle = priv->handle;
1442 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1443
1444 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle))
1445 hns_roce_write64_k(val, dest);
1446}
1447
1448#endif
1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef _HNS_ROCE_HW_V2_H
34#define _HNS_ROCE_HW_V2_H
35
36#include <linux/bitops.h>
37
38#define HNS_ROCE_VF_QPC_BT_NUM 256
39#define HNS_ROCE_VF_SCCC_BT_NUM 64
40#define HNS_ROCE_VF_SRQC_BT_NUM 64
41#define HNS_ROCE_VF_CQC_BT_NUM 64
42#define HNS_ROCE_VF_MPT_BT_NUM 64
43#define HNS_ROCE_VF_EQC_NUM 64
44#define HNS_ROCE_VF_SMAC_NUM 32
45#define HNS_ROCE_VF_SGID_NUM 32
46#define HNS_ROCE_VF_SL_NUM 8
47
48#define HNS_ROCE_V2_MAX_QP_NUM 0x100000
49#define HNS_ROCE_V2_MAX_QPC_TIMER_NUM 0x200
50#define HNS_ROCE_V2_MAX_WQE_NUM 0x8000
51#define HNS_ROCE_V2_MAX_SRQ 0x100000
52#define HNS_ROCE_V2_MAX_SRQ_WR 0x8000
53#define HNS_ROCE_V2_MAX_SRQ_SGE 0x100
54#define HNS_ROCE_V2_MAX_CQ_NUM 0x100000
55#define HNS_ROCE_V2_MAX_CQC_TIMER_NUM 0x100
56#define HNS_ROCE_V2_MAX_SRQ_NUM 0x100000
57#define HNS_ROCE_V2_MAX_CQE_NUM 0x400000
58#define HNS_ROCE_V2_MAX_SRQWQE_NUM 0x8000
59#define HNS_ROCE_V2_MAX_RQ_SGE_NUM 0x100
60#define HNS_ROCE_V2_MAX_SQ_SGE_NUM 0xff
61#define HNS_ROCE_V2_MAX_SRQ_SGE_NUM 0x100
62#define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM 0x200000
63#define HNS_ROCE_V2_MAX_SQ_INLINE 0x20
64#define HNS_ROCE_V2_UAR_NUM 256
65#define HNS_ROCE_V2_PHY_UAR_NUM 1
66#define HNS_ROCE_V2_MAX_IRQ_NUM 65
67#define HNS_ROCE_V2_COMP_VEC_NUM 63
68#define HNS_ROCE_V2_AEQE_VEC_NUM 1
69#define HNS_ROCE_V2_ABNORMAL_VEC_NUM 1
70#define HNS_ROCE_V2_MAX_MTPT_NUM 0x100000
71#define HNS_ROCE_V2_MAX_MTT_SEGS 0x1000000
72#define HNS_ROCE_V2_MAX_CQE_SEGS 0x1000000
73#define HNS_ROCE_V2_MAX_SRQWQE_SEGS 0x1000000
74#define HNS_ROCE_V2_MAX_IDX_SEGS 0x1000000
75#define HNS_ROCE_V2_MAX_PD_NUM 0x1000000
76#define HNS_ROCE_V2_MAX_QP_INIT_RDMA 128
77#define HNS_ROCE_V2_MAX_QP_DEST_RDMA 128
78#define HNS_ROCE_V2_MAX_SQ_DESC_SZ 64
79#define HNS_ROCE_V2_MAX_RQ_DESC_SZ 16
80#define HNS_ROCE_V2_MAX_SRQ_DESC_SZ 64
81#define HNS_ROCE_V2_QPC_ENTRY_SZ 256
82#define HNS_ROCE_V2_IRRL_ENTRY_SZ 64
83#define HNS_ROCE_V2_TRRL_ENTRY_SZ 48
84#define HNS_ROCE_V2_CQC_ENTRY_SZ 64
85#define HNS_ROCE_V2_SRQC_ENTRY_SZ 64
86#define HNS_ROCE_V2_MTPT_ENTRY_SZ 64
87#define HNS_ROCE_V2_MTT_ENTRY_SZ 64
88#define HNS_ROCE_V2_CQE_ENTRY_SIZE 32
89#define HNS_ROCE_V2_SCCC_ENTRY_SZ 32
90#define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ 4096
91#define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ 4096
92#define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFFF000
93#define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2
94#define HNS_ROCE_INVALID_LKEY 0x100
95#define HNS_ROCE_CMQ_TX_TIMEOUT 30000
96#define HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE 2
97#define HNS_ROCE_V2_RSV_QPS 8
98
99#define HNS_ROCE_V2_HW_RST_TIMEOUT 1000
100#define HNS_ROCE_V2_HW_RST_UNINT_DELAY 100
101
102#define HNS_ROCE_V2_HW_RST_COMPLETION_WAIT 20
103
104#define HNS_ROCE_CONTEXT_HOP_NUM 1
105#define HNS_ROCE_SCCC_HOP_NUM 1
106#define HNS_ROCE_MTT_HOP_NUM 1
107#define HNS_ROCE_CQE_HOP_NUM 1
108#define HNS_ROCE_SRQWQE_HOP_NUM 1
109#define HNS_ROCE_PBL_HOP_NUM 2
110#define HNS_ROCE_EQE_HOP_NUM 2
111#define HNS_ROCE_IDX_HOP_NUM 1
112
113#define HNS_ROCE_V2_GID_INDEX_NUM 256
114
115#define HNS_ROCE_V2_TABLE_CHUNK_SIZE (1 << 18)
116
117#define HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT 0
118#define HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT 1
119#define HNS_ROCE_CMD_FLAG_NEXT_SHIFT 2
120#define HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT 3
121#define HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT 4
122#define HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT 5
123
124#define HNS_ROCE_CMD_FLAG_IN BIT(HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT)
125#define HNS_ROCE_CMD_FLAG_OUT BIT(HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT)
126#define HNS_ROCE_CMD_FLAG_NEXT BIT(HNS_ROCE_CMD_FLAG_NEXT_SHIFT)
127#define HNS_ROCE_CMD_FLAG_WR BIT(HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT)
128#define HNS_ROCE_CMD_FLAG_NO_INTR BIT(HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT)
129#define HNS_ROCE_CMD_FLAG_ERR_INTR BIT(HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT)
130
131#define HNS_ROCE_CMQ_DESC_NUM_S 3
132
133#define HNS_ROCE_CMQ_SCC_CLR_DONE_CNT 5
134
135#define check_whether_last_step(hop_num, step_idx) \
136 ((step_idx == 0 && hop_num == HNS_ROCE_HOP_NUM_0) || \
137 (step_idx == 1 && hop_num == 1) || \
138 (step_idx == 2 && hop_num == 2))
139#define HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT 0
140#define HNS_ICL_SWITCH_CMD_ROCEE_SEL BIT(HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT)
141
142#define CMD_CSQ_DESC_NUM 1024
143#define CMD_CRQ_DESC_NUM 1024
144
145enum {
146 NO_ARMED = 0x0,
147 REG_NXT_CEQE = 0x2,
148 REG_NXT_SE_CEQE = 0x3
149};
150
151#define V2_CQ_DB_REQ_NOT_SOL 0
152#define V2_CQ_DB_REQ_NOT 1
153
154#define V2_CQ_STATE_VALID 1
155#define V2_QKEY_VAL 0x80010000
156
157#define GID_LEN_V2 16
158
159#define HNS_ROCE_V2_CQE_QPN_MASK 0x3ffff
160
161enum {
162 HNS_ROCE_V2_WQE_OP_SEND = 0x0,
163 HNS_ROCE_V2_WQE_OP_SEND_WITH_INV = 0x1,
164 HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM = 0x2,
165 HNS_ROCE_V2_WQE_OP_RDMA_WRITE = 0x3,
166 HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM = 0x4,
167 HNS_ROCE_V2_WQE_OP_RDMA_READ = 0x5,
168 HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP = 0x6,
169 HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD = 0x7,
170 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP = 0x8,
171 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD = 0x9,
172 HNS_ROCE_V2_WQE_OP_FAST_REG_PMR = 0xa,
173 HNS_ROCE_V2_WQE_OP_LOCAL_INV = 0xb,
174 HNS_ROCE_V2_WQE_OP_BIND_MW_TYPE = 0xc,
175 HNS_ROCE_V2_WQE_OP_MASK = 0x1f,
176};
177
178enum {
179 HNS_ROCE_SQ_OPCODE_SEND = 0x0,
180 HNS_ROCE_SQ_OPCODE_SEND_WITH_INV = 0x1,
181 HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM = 0x2,
182 HNS_ROCE_SQ_OPCODE_RDMA_WRITE = 0x3,
183 HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM = 0x4,
184 HNS_ROCE_SQ_OPCODE_RDMA_READ = 0x5,
185 HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP = 0x6,
186 HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD = 0x7,
187 HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP = 0x8,
188 HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD = 0x9,
189 HNS_ROCE_SQ_OPCODE_FAST_REG_WR = 0xa,
190 HNS_ROCE_SQ_OPCODE_LOCAL_INV = 0xb,
191 HNS_ROCE_SQ_OPCODE_BIND_MW = 0xc,
192};
193
194enum {
195 /* rq operations */
196 HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM = 0x0,
197 HNS_ROCE_V2_OPCODE_SEND = 0x1,
198 HNS_ROCE_V2_OPCODE_SEND_WITH_IMM = 0x2,
199 HNS_ROCE_V2_OPCODE_SEND_WITH_INV = 0x3,
200};
201
202enum {
203 HNS_ROCE_V2_SQ_DB = 0x0,
204 HNS_ROCE_V2_RQ_DB = 0x1,
205 HNS_ROCE_V2_SRQ_DB = 0x2,
206 HNS_ROCE_V2_CQ_DB_PTR = 0x3,
207 HNS_ROCE_V2_CQ_DB_NTR = 0x4,
208};
209
210enum {
211 HNS_ROCE_CQE_V2_SUCCESS = 0x00,
212 HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR = 0x01,
213 HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR = 0x02,
214 HNS_ROCE_CQE_V2_LOCAL_PROT_ERR = 0x04,
215 HNS_ROCE_CQE_V2_WR_FLUSH_ERR = 0x05,
216 HNS_ROCE_CQE_V2_MW_BIND_ERR = 0x06,
217 HNS_ROCE_CQE_V2_BAD_RESP_ERR = 0x10,
218 HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR = 0x11,
219 HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR = 0x12,
220 HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR = 0x13,
221 HNS_ROCE_CQE_V2_REMOTE_OP_ERR = 0x14,
222 HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR = 0x15,
223 HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR = 0x16,
224 HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR = 0x22,
225
226 HNS_ROCE_V2_CQE_STATUS_MASK = 0xff,
227};
228
229/* CMQ command */
230enum hns_roce_opcode_type {
231 HNS_QUERY_FW_VER = 0x0001,
232 HNS_ROCE_OPC_QUERY_HW_VER = 0x8000,
233 HNS_ROCE_OPC_CFG_GLOBAL_PARAM = 0x8001,
234 HNS_ROCE_OPC_ALLOC_PF_RES = 0x8004,
235 HNS_ROCE_OPC_QUERY_PF_RES = 0x8400,
236 HNS_ROCE_OPC_ALLOC_VF_RES = 0x8401,
237 HNS_ROCE_OPC_CFG_EXT_LLM = 0x8403,
238 HNS_ROCE_OPC_CFG_TMOUT_LLM = 0x8404,
239 HNS_ROCE_OPC_QUERY_PF_TIMER_RES = 0x8406,
240 HNS_ROCE_OPC_CFG_SGID_TB = 0x8500,
241 HNS_ROCE_OPC_CFG_SMAC_TB = 0x8501,
242 HNS_ROCE_OPC_POST_MB = 0x8504,
243 HNS_ROCE_OPC_QUERY_MB_ST = 0x8505,
244 HNS_ROCE_OPC_CFG_BT_ATTR = 0x8506,
245 HNS_ROCE_OPC_FUNC_CLEAR = 0x8508,
246 HNS_ROCE_OPC_CLR_SCCC = 0x8509,
247 HNS_ROCE_OPC_QUERY_SCCC = 0x850a,
248 HNS_ROCE_OPC_RESET_SCCC = 0x850b,
249 HNS_SWITCH_PARAMETER_CFG = 0x1033,
250};
251
252enum {
253 TYPE_CRQ,
254 TYPE_CSQ,
255};
256
257enum hns_roce_cmd_return_status {
258 CMD_EXEC_SUCCESS = 0,
259 CMD_NO_AUTH = 1,
260 CMD_NOT_EXEC = 2,
261 CMD_QUEUE_FULL = 3,
262};
263
264enum hns_roce_sgid_type {
265 GID_TYPE_FLAG_ROCE_V1 = 0,
266 GID_TYPE_FLAG_ROCE_V2_IPV4,
267 GID_TYPE_FLAG_ROCE_V2_IPV6,
268};
269
270struct hns_roce_v2_cq_context {
271 __le32 byte_4_pg_ceqn;
272 __le32 byte_8_cqn;
273 __le32 cqe_cur_blk_addr;
274 __le32 byte_16_hop_addr;
275 __le32 cqe_nxt_blk_addr;
276 __le32 byte_24_pgsz_addr;
277 __le32 byte_28_cq_pi;
278 __le32 byte_32_cq_ci;
279 __le32 cqe_ba;
280 __le32 byte_40_cqe_ba;
281 __le32 byte_44_db_record;
282 __le32 db_record_addr;
283 __le32 byte_52_cqe_cnt;
284 __le32 byte_56_cqe_period_maxcnt;
285 __le32 cqe_report_timer;
286 __le32 byte_64_se_cqe_idx;
287};
288#define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM 0x0
289#define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL 0x0
290
291#define V2_CQC_BYTE_4_CQ_ST_S 0
292#define V2_CQC_BYTE_4_CQ_ST_M GENMASK(1, 0)
293
294#define V2_CQC_BYTE_4_POLL_S 2
295
296#define V2_CQC_BYTE_4_SE_S 3
297
298#define V2_CQC_BYTE_4_OVER_IGNORE_S 4
299
300#define V2_CQC_BYTE_4_COALESCE_S 5
301
302#define V2_CQC_BYTE_4_ARM_ST_S 6
303#define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6)
304
305#define V2_CQC_BYTE_4_SHIFT_S 8
306#define V2_CQC_BYTE_4_SHIFT_M GENMASK(12, 8)
307
308#define V2_CQC_BYTE_4_CMD_SN_S 13
309#define V2_CQC_BYTE_4_CMD_SN_M GENMASK(14, 13)
310
311#define V2_CQC_BYTE_4_CEQN_S 15
312#define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15)
313
314#define V2_CQC_BYTE_4_PAGE_OFFSET_S 24
315#define V2_CQC_BYTE_4_PAGE_OFFSET_M GENMASK(31, 24)
316
317#define V2_CQC_BYTE_8_CQN_S 0
318#define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0)
319
320#define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S 0
321#define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M GENMASK(19, 0)
322
323#define V2_CQC_BYTE_16_CQE_HOP_NUM_S 30
324#define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30)
325
326#define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S 0
327#define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M GENMASK(19, 0)
328
329#define V2_CQC_BYTE_24_CQE_BA_PG_SZ_S 24
330#define V2_CQC_BYTE_24_CQE_BA_PG_SZ_M GENMASK(27, 24)
331
332#define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S 28
333#define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M GENMASK(31, 28)
334
335#define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_S 0
336#define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M GENMASK(23, 0)
337
338#define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_S 0
339#define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M GENMASK(23, 0)
340
341#define V2_CQC_BYTE_40_CQE_BA_S 0
342#define V2_CQC_BYTE_40_CQE_BA_M GENMASK(28, 0)
343
344#define V2_CQC_BYTE_44_DB_RECORD_EN_S 0
345
346#define V2_CQC_BYTE_44_DB_RECORD_ADDR_S 1
347#define V2_CQC_BYTE_44_DB_RECORD_ADDR_M GENMASK(31, 1)
348
349#define V2_CQC_BYTE_52_CQE_CNT_S 0
350#define V2_CQC_BYTE_52_CQE_CNT_M GENMASK(23, 0)
351
352#define V2_CQC_BYTE_56_CQ_MAX_CNT_S 0
353#define V2_CQC_BYTE_56_CQ_MAX_CNT_M GENMASK(15, 0)
354
355#define V2_CQC_BYTE_56_CQ_PERIOD_S 16
356#define V2_CQC_BYTE_56_CQ_PERIOD_M GENMASK(31, 16)
357
358#define V2_CQC_BYTE_64_SE_CQE_IDX_S 0
359#define V2_CQC_BYTE_64_SE_CQE_IDX_M GENMASK(23, 0)
360
361struct hns_roce_srq_context {
362 __le32 byte_4_srqn_srqst;
363 __le32 byte_8_limit_wl;
364 __le32 byte_12_xrcd;
365 __le32 byte_16_pi_ci;
366 __le32 wqe_bt_ba;
367 __le32 byte_24_wqe_bt_ba;
368 __le32 byte_28_rqws_pd;
369 __le32 idx_bt_ba;
370 __le32 rsv_idx_bt_ba;
371 __le32 idx_cur_blk_addr;
372 __le32 byte_44_idxbufpgsz_addr;
373 __le32 idx_nxt_blk_addr;
374 __le32 rsv_idxnxtblkaddr;
375 __le32 byte_56_xrc_cqn;
376 __le32 db_record_addr_record_en;
377 __le32 db_record_addr;
378};
379
380#define SRQC_BYTE_4_SRQ_ST_S 0
381#define SRQC_BYTE_4_SRQ_ST_M GENMASK(1, 0)
382
383#define SRQC_BYTE_4_SRQ_WQE_HOP_NUM_S 2
384#define SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M GENMASK(3, 2)
385
386#define SRQC_BYTE_4_SRQ_SHIFT_S 4
387#define SRQC_BYTE_4_SRQ_SHIFT_M GENMASK(7, 4)
388
389#define SRQC_BYTE_4_SRQN_S 8
390#define SRQC_BYTE_4_SRQN_M GENMASK(31, 8)
391
392#define SRQC_BYTE_8_SRQ_LIMIT_WL_S 0
393#define SRQC_BYTE_8_SRQ_LIMIT_WL_M GENMASK(15, 0)
394
395#define SRQC_BYTE_12_SRQ_XRCD_S 0
396#define SRQC_BYTE_12_SRQ_XRCD_M GENMASK(23, 0)
397
398#define SRQC_BYTE_16_SRQ_PRODUCER_IDX_S 0
399#define SRQC_BYTE_16_SRQ_PRODUCER_IDX_M GENMASK(15, 0)
400
401#define SRQC_BYTE_16_SRQ_CONSUMER_IDX_S 0
402#define SRQC_BYTE_16_SRQ_CONSUMER_IDX_M GENMASK(31, 16)
403
404#define SRQC_BYTE_24_SRQ_WQE_BT_BA_S 0
405#define SRQC_BYTE_24_SRQ_WQE_BT_BA_M GENMASK(28, 0)
406
407#define SRQC_BYTE_28_PD_S 0
408#define SRQC_BYTE_28_PD_M GENMASK(23, 0)
409
410#define SRQC_BYTE_28_RQWS_S 24
411#define SRQC_BYTE_28_RQWS_M GENMASK(27, 24)
412
413#define SRQC_BYTE_36_SRQ_IDX_BT_BA_S 0
414#define SRQC_BYTE_36_SRQ_IDX_BT_BA_M GENMASK(28, 0)
415
416#define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S 0
417#define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M GENMASK(19, 0)
418
419#define SRQC_BYTE_44_SRQ_IDX_HOP_NUM_S 22
420#define SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M GENMASK(23, 22)
421
422#define SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S 24
423#define SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M GENMASK(27, 24)
424
425#define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S 28
426#define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M GENMASK(31, 28)
427
428#define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S 0
429#define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M GENMASK(19, 0)
430
431#define SRQC_BYTE_56_SRQ_XRC_CQN_S 0
432#define SRQC_BYTE_56_SRQ_XRC_CQN_M GENMASK(23, 0)
433
434#define SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S 24
435#define SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M GENMASK(27, 24)
436
437#define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_S 28
438#define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M GENMASK(31, 28)
439
440#define SRQC_BYTE_60_SRQ_RECORD_EN_S 0
441
442#define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_S 1
443#define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_M GENMASK(31, 1)
444
445enum{
446 V2_MPT_ST_VALID = 0x1,
447 V2_MPT_ST_FREE = 0x2,
448};
449
450enum hns_roce_v2_qp_state {
451 HNS_ROCE_QP_ST_RST,
452 HNS_ROCE_QP_ST_INIT,
453 HNS_ROCE_QP_ST_RTR,
454 HNS_ROCE_QP_ST_RTS,
455 HNS_ROCE_QP_ST_SQER,
456 HNS_ROCE_QP_ST_SQD,
457 HNS_ROCE_QP_ST_ERR,
458 HNS_ROCE_QP_ST_SQ_DRAINING,
459 HNS_ROCE_QP_NUM_ST
460};
461
462struct hns_roce_v2_qp_context {
463 __le32 byte_4_sqpn_tst;
464 __le32 wqe_sge_ba;
465 __le32 byte_12_sq_hop;
466 __le32 byte_16_buf_ba_pg_sz;
467 __le32 byte_20_smac_sgid_idx;
468 __le32 byte_24_mtu_tc;
469 __le32 byte_28_at_fl;
470 u8 dgid[GID_LEN_V2];
471 __le32 dmac;
472 __le32 byte_52_udpspn_dmac;
473 __le32 byte_56_dqpn_err;
474 __le32 byte_60_qpst_tempid;
475 __le32 qkey_xrcd;
476 __le32 byte_68_rq_db;
477 __le32 rq_db_record_addr;
478 __le32 byte_76_srqn_op_en;
479 __le32 byte_80_rnr_rx_cqn;
480 __le32 byte_84_rq_ci_pi;
481 __le32 rq_cur_blk_addr;
482 __le32 byte_92_srq_info;
483 __le32 byte_96_rx_reqmsn;
484 __le32 rq_nxt_blk_addr;
485 __le32 byte_104_rq_sge;
486 __le32 byte_108_rx_reqepsn;
487 __le32 rq_rnr_timer;
488 __le32 rx_msg_len;
489 __le32 rx_rkey_pkt_info;
490 __le64 rx_va;
491 __le32 byte_132_trrl;
492 __le32 trrl_ba;
493 __le32 byte_140_raq;
494 __le32 byte_144_raq;
495 __le32 byte_148_raq;
496 __le32 byte_152_raq;
497 __le32 byte_156_raq;
498 __le32 byte_160_sq_ci_pi;
499 __le32 sq_cur_blk_addr;
500 __le32 byte_168_irrl_idx;
501 __le32 byte_172_sq_psn;
502 __le32 byte_176_msg_pktn;
503 __le32 sq_cur_sge_blk_addr;
504 __le32 byte_184_irrl_idx;
505 __le32 cur_sge_offset;
506 __le32 byte_192_ext_sge;
507 __le32 byte_196_sq_psn;
508 __le32 byte_200_sq_max;
509 __le32 irrl_ba;
510 __le32 byte_208_irrl;
511 __le32 byte_212_lsn;
512 __le32 sq_timer;
513 __le32 byte_220_retry_psn_msn;
514 __le32 byte_224_retry_msg;
515 __le32 rx_sq_cur_blk_addr;
516 __le32 byte_232_irrl_sge;
517 __le32 irrl_cur_sge_offset;
518 __le32 byte_240_irrl_tail;
519 __le32 byte_244_rnr_rxack;
520 __le32 byte_248_ack_psn;
521 __le32 byte_252_err_txcqn;
522 __le32 byte_256_sqflush_rqcqe;
523};
524
525#define V2_QPC_BYTE_4_TST_S 0
526#define V2_QPC_BYTE_4_TST_M GENMASK(2, 0)
527
528#define V2_QPC_BYTE_4_SGE_SHIFT_S 3
529#define V2_QPC_BYTE_4_SGE_SHIFT_M GENMASK(7, 3)
530
531#define V2_QPC_BYTE_4_SQPN_S 8
532#define V2_QPC_BYTE_4_SQPN_M GENMASK(31, 8)
533
534#define V2_QPC_BYTE_12_WQE_SGE_BA_S 0
535#define V2_QPC_BYTE_12_WQE_SGE_BA_M GENMASK(28, 0)
536
537#define V2_QPC_BYTE_12_SQ_HOP_NUM_S 29
538#define V2_QPC_BYTE_12_SQ_HOP_NUM_M GENMASK(30, 29)
539
540#define V2_QPC_BYTE_12_RSVD_LKEY_EN_S 31
541
542#define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S 0
543#define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M GENMASK(3, 0)
544
545#define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S 4
546#define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M GENMASK(7, 4)
547
548#define V2_QPC_BYTE_16_PD_S 8
549#define V2_QPC_BYTE_16_PD_M GENMASK(31, 8)
550
551#define V2_QPC_BYTE_20_RQ_HOP_NUM_S 0
552#define V2_QPC_BYTE_20_RQ_HOP_NUM_M GENMASK(1, 0)
553
554#define V2_QPC_BYTE_20_SGE_HOP_NUM_S 2
555#define V2_QPC_BYTE_20_SGE_HOP_NUM_M GENMASK(3, 2)
556
557#define V2_QPC_BYTE_20_RQWS_S 4
558#define V2_QPC_BYTE_20_RQWS_M GENMASK(7, 4)
559
560#define V2_QPC_BYTE_20_SQ_SHIFT_S 8
561#define V2_QPC_BYTE_20_SQ_SHIFT_M GENMASK(11, 8)
562
563#define V2_QPC_BYTE_20_RQ_SHIFT_S 12
564#define V2_QPC_BYTE_20_RQ_SHIFT_M GENMASK(15, 12)
565
566#define V2_QPC_BYTE_20_SGID_IDX_S 16
567#define V2_QPC_BYTE_20_SGID_IDX_M GENMASK(23, 16)
568
569#define V2_QPC_BYTE_20_SMAC_IDX_S 24
570#define V2_QPC_BYTE_20_SMAC_IDX_M GENMASK(31, 24)
571
572#define V2_QPC_BYTE_24_HOP_LIMIT_S 0
573#define V2_QPC_BYTE_24_HOP_LIMIT_M GENMASK(7, 0)
574
575#define V2_QPC_BYTE_24_TC_S 8
576#define V2_QPC_BYTE_24_TC_M GENMASK(15, 8)
577
578#define V2_QPC_BYTE_24_VLAN_ID_S 16
579#define V2_QPC_BYTE_24_VLAN_ID_M GENMASK(27, 16)
580
581#define V2_QPC_BYTE_24_MTU_S 28
582#define V2_QPC_BYTE_24_MTU_M GENMASK(31, 28)
583
584#define V2_QPC_BYTE_28_FL_S 0
585#define V2_QPC_BYTE_28_FL_M GENMASK(19, 0)
586
587#define V2_QPC_BYTE_28_SL_S 20
588#define V2_QPC_BYTE_28_SL_M GENMASK(23, 20)
589
590#define V2_QPC_BYTE_28_CNP_TX_FLAG_S 24
591
592#define V2_QPC_BYTE_28_CE_FLAG_S 25
593
594#define V2_QPC_BYTE_28_LBI_S 26
595
596#define V2_QPC_BYTE_28_AT_S 27
597#define V2_QPC_BYTE_28_AT_M GENMASK(31, 27)
598
599#define V2_QPC_BYTE_52_DMAC_S 0
600#define V2_QPC_BYTE_52_DMAC_M GENMASK(15, 0)
601
602#define V2_QPC_BYTE_52_UDPSPN_S 16
603#define V2_QPC_BYTE_52_UDPSPN_M GENMASK(31, 16)
604
605#define V2_QPC_BYTE_56_DQPN_S 0
606#define V2_QPC_BYTE_56_DQPN_M GENMASK(23, 0)
607
608#define V2_QPC_BYTE_56_SQ_TX_ERR_S 24
609#define V2_QPC_BYTE_56_SQ_RX_ERR_S 25
610#define V2_QPC_BYTE_56_RQ_TX_ERR_S 26
611#define V2_QPC_BYTE_56_RQ_RX_ERR_S 27
612
613#define V2_QPC_BYTE_56_LP_PKTN_INI_S 28
614#define V2_QPC_BYTE_56_LP_PKTN_INI_M GENMASK(31, 28)
615
616#define V2_QPC_BYTE_60_TEMPID_S 0
617#define V2_QPC_BYTE_60_TEMPID_M GENMASK(7, 0)
618
619#define V2_QPC_BYTE_60_SCC_TOKEN_S 8
620#define V2_QPC_BYTE_60_SCC_TOKEN_M GENMASK(26, 8)
621
622#define V2_QPC_BYTE_60_SQ_DB_DOING_S 27
623
624#define V2_QPC_BYTE_60_RQ_DB_DOING_S 28
625
626#define V2_QPC_BYTE_60_QP_ST_S 29
627#define V2_QPC_BYTE_60_QP_ST_M GENMASK(31, 29)
628
629#define V2_QPC_BYTE_68_RQ_RECORD_EN_S 0
630
631#define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S 1
632#define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M GENMASK(31, 1)
633
634#define V2_QPC_BYTE_76_SRQN_S 0
635#define V2_QPC_BYTE_76_SRQN_M GENMASK(23, 0)
636
637#define V2_QPC_BYTE_76_SRQ_EN_S 24
638
639#define V2_QPC_BYTE_76_RRE_S 25
640
641#define V2_QPC_BYTE_76_RWE_S 26
642
643#define V2_QPC_BYTE_76_ATE_S 27
644
645#define V2_QPC_BYTE_76_RQIE_S 28
646
647#define V2_QPC_BYTE_76_RQ_VLAN_EN_S 30
648#define V2_QPC_BYTE_80_RX_CQN_S 0
649#define V2_QPC_BYTE_80_RX_CQN_M GENMASK(23, 0)
650
651#define V2_QPC_BYTE_80_MIN_RNR_TIME_S 27
652#define V2_QPC_BYTE_80_MIN_RNR_TIME_M GENMASK(31, 27)
653
654#define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S 0
655#define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M GENMASK(15, 0)
656
657#define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S 16
658#define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M GENMASK(31, 16)
659
660#define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S 0
661#define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M GENMASK(19, 0)
662
663#define V2_QPC_BYTE_92_SRQ_INFO_S 20
664#define V2_QPC_BYTE_92_SRQ_INFO_M GENMASK(31, 20)
665
666#define V2_QPC_BYTE_96_RX_REQ_MSN_S 0
667#define V2_QPC_BYTE_96_RX_REQ_MSN_M GENMASK(23, 0)
668
669#define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S 0
670#define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M GENMASK(19, 0)
671
672#define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S 24
673#define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M GENMASK(31, 24)
674
675#define V2_QPC_BYTE_108_INV_CREDIT_S 0
676
677#define V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S 3
678
679#define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S 4
680#define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M GENMASK(6, 4)
681
682#define V2_QPC_BYTE_108_RX_REQ_RNR_S 7
683
684#define V2_QPC_BYTE_108_RX_REQ_EPSN_S 8
685#define V2_QPC_BYTE_108_RX_REQ_EPSN_M GENMASK(31, 8)
686
687#define V2_QPC_BYTE_132_TRRL_HEAD_MAX_S 0
688#define V2_QPC_BYTE_132_TRRL_HEAD_MAX_M GENMASK(7, 0)
689
690#define V2_QPC_BYTE_132_TRRL_TAIL_MAX_S 8
691#define V2_QPC_BYTE_132_TRRL_TAIL_MAX_M GENMASK(15, 8)
692
693#define V2_QPC_BYTE_132_TRRL_BA_S 16
694#define V2_QPC_BYTE_132_TRRL_BA_M GENMASK(31, 16)
695
696#define V2_QPC_BYTE_140_TRRL_BA_S 0
697#define V2_QPC_BYTE_140_TRRL_BA_M GENMASK(11, 0)
698
699#define V2_QPC_BYTE_140_RR_MAX_S 12
700#define V2_QPC_BYTE_140_RR_MAX_M GENMASK(14, 12)
701
702#define V2_QPC_BYTE_140_RQ_RTY_WAIT_DO_S 15
703
704#define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S 16
705#define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M GENMASK(23, 16)
706
707#define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S 24
708#define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M GENMASK(31, 24)
709
710#define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S 0
711#define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M GENMASK(23, 0)
712
713#define V2_QPC_BYTE_144_RAQ_CREDIT_S 25
714#define V2_QPC_BYTE_144_RAQ_CREDIT_M GENMASK(29, 25)
715
716#define V2_QPC_BYTE_144_RESP_RTY_FLG_S 31
717
718#define V2_QPC_BYTE_148_RQ_MSN_S 0
719#define V2_QPC_BYTE_148_RQ_MSN_M GENMASK(23, 0)
720
721#define V2_QPC_BYTE_148_RAQ_SYNDROME_S 24
722#define V2_QPC_BYTE_148_RAQ_SYNDROME_M GENMASK(31, 24)
723
724#define V2_QPC_BYTE_152_RAQ_PSN_S 0
725#define V2_QPC_BYTE_152_RAQ_PSN_M GENMASK(23, 0)
726
727#define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S 24
728#define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M GENMASK(31, 24)
729
730#define V2_QPC_BYTE_156_RAQ_USE_PKTN_S 0
731#define V2_QPC_BYTE_156_RAQ_USE_PKTN_M GENMASK(23, 0)
732
733#define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S 0
734#define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M GENMASK(15, 0)
735
736#define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S 16
737#define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M GENMASK(31, 16)
738
739#define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S 0
740#define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
741
742#define V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S 20
743
744#define V2_QPC_BYTE_168_SQ_INVLD_FLG_S 21
745
746#define V2_QPC_BYTE_168_LP_SGEN_INI_S 22
747#define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22)
748
749#define V2_QPC_BYTE_168_SQ_VLAN_EN_S 24
750#define V2_QPC_BYTE_168_POLL_DB_WAIT_DO_S 25
751#define V2_QPC_BYTE_168_SCC_TOKEN_FORBID_SQ_DEQ_S 26
752#define V2_QPC_BYTE_168_WAIT_ACK_TIMEOUT_S 27
753#define V2_QPC_BYTE_168_IRRL_IDX_LSB_S 28
754#define V2_QPC_BYTE_168_IRRL_IDX_LSB_M GENMASK(31, 28)
755
756#define V2_QPC_BYTE_172_ACK_REQ_FREQ_S 0
757#define V2_QPC_BYTE_172_ACK_REQ_FREQ_M GENMASK(5, 0)
758
759#define V2_QPC_BYTE_172_MSG_RNR_FLG_S 6
760
761#define V2_QPC_BYTE_172_FRE_S 7
762
763#define V2_QPC_BYTE_172_SQ_CUR_PSN_S 8
764#define V2_QPC_BYTE_172_SQ_CUR_PSN_M GENMASK(31, 8)
765
766#define V2_QPC_BYTE_176_MSG_USE_PKTN_S 0
767#define V2_QPC_BYTE_176_MSG_USE_PKTN_M GENMASK(23, 0)
768
769#define V2_QPC_BYTE_176_IRRL_HEAD_PRE_S 24
770#define V2_QPC_BYTE_176_IRRL_HEAD_PRE_M GENMASK(31, 24)
771
772#define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S 0
773#define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M GENMASK(19, 0)
774
775#define V2_QPC_BYTE_184_IRRL_IDX_MSB_S 20
776#define V2_QPC_BYTE_184_IRRL_IDX_MSB_M GENMASK(31, 20)
777
778#define V2_QPC_BYTE_192_CUR_SGE_IDX_S 0
779#define V2_QPC_BYTE_192_CUR_SGE_IDX_M GENMASK(23, 0)
780
781#define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S 24
782#define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M GENMASK(31, 24)
783
784#define V2_QPC_BYTE_196_IRRL_HEAD_S 0
785#define V2_QPC_BYTE_196_IRRL_HEAD_M GENMASK(7, 0)
786
787#define V2_QPC_BYTE_196_SQ_MAX_PSN_S 8
788#define V2_QPC_BYTE_196_SQ_MAX_PSN_M GENMASK(31, 8)
789
790#define V2_QPC_BYTE_200_SQ_MAX_IDX_S 0
791#define V2_QPC_BYTE_200_SQ_MAX_IDX_M GENMASK(15, 0)
792
793#define V2_QPC_BYTE_200_LCL_OPERATED_CNT_S 16
794#define V2_QPC_BYTE_200_LCL_OPERATED_CNT_M GENMASK(31, 16)
795
796#define V2_QPC_BYTE_208_IRRL_BA_S 0
797#define V2_QPC_BYTE_208_IRRL_BA_M GENMASK(25, 0)
798
799#define V2_QPC_BYTE_208_PKT_RNR_FLG_S 26
800
801#define V2_QPC_BYTE_208_PKT_RTY_FLG_S 27
802
803#define V2_QPC_BYTE_208_RMT_E2E_S 28
804
805#define V2_QPC_BYTE_208_SR_MAX_S 29
806#define V2_QPC_BYTE_208_SR_MAX_M GENMASK(31, 29)
807
808#define V2_QPC_BYTE_212_LSN_S 0
809#define V2_QPC_BYTE_212_LSN_M GENMASK(23, 0)
810
811#define V2_QPC_BYTE_212_RETRY_NUM_INIT_S 24
812#define V2_QPC_BYTE_212_RETRY_NUM_INIT_M GENMASK(26, 24)
813
814#define V2_QPC_BYTE_212_CHECK_FLG_S 27
815#define V2_QPC_BYTE_212_CHECK_FLG_M GENMASK(28, 27)
816
817#define V2_QPC_BYTE_212_RETRY_CNT_S 29
818#define V2_QPC_BYTE_212_RETRY_CNT_M GENMASK(31, 29)
819
820#define V2_QPC_BYTE_220_RETRY_MSG_MSN_S 0
821#define V2_QPC_BYTE_220_RETRY_MSG_MSN_M GENMASK(15, 0)
822
823#define V2_QPC_BYTE_220_RETRY_MSG_PSN_S 16
824#define V2_QPC_BYTE_220_RETRY_MSG_PSN_M GENMASK(31, 16)
825
826#define V2_QPC_BYTE_224_RETRY_MSG_PSN_S 0
827#define V2_QPC_BYTE_224_RETRY_MSG_PSN_M GENMASK(7, 0)
828
829#define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S 8
830#define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M GENMASK(31, 8)
831
832#define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S 0
833#define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M GENMASK(19, 0)
834
835#define V2_QPC_BYTE_232_IRRL_SGE_IDX_S 20
836#define V2_QPC_BYTE_232_IRRL_SGE_IDX_M GENMASK(28, 20)
837
838#define V2_QPC_BYTE_232_SO_LP_VLD_S 29
839#define V2_QPC_BYTE_232_FENCE_LP_VLD_S 30
840#define V2_QPC_BYTE_232_IRRL_LP_VLD_S 31
841
842#define V2_QPC_BYTE_240_IRRL_TAIL_REAL_S 0
843#define V2_QPC_BYTE_240_IRRL_TAIL_REAL_M GENMASK(7, 0)
844
845#define V2_QPC_BYTE_240_IRRL_TAIL_RD_S 8
846#define V2_QPC_BYTE_240_IRRL_TAIL_RD_M GENMASK(15, 8)
847
848#define V2_QPC_BYTE_240_RX_ACK_MSN_S 16
849#define V2_QPC_BYTE_240_RX_ACK_MSN_M GENMASK(31, 16)
850
851#define V2_QPC_BYTE_244_RX_ACK_EPSN_S 0
852#define V2_QPC_BYTE_244_RX_ACK_EPSN_M GENMASK(23, 0)
853
854#define V2_QPC_BYTE_244_RNR_NUM_INIT_S 24
855#define V2_QPC_BYTE_244_RNR_NUM_INIT_M GENMASK(26, 24)
856
857#define V2_QPC_BYTE_244_RNR_CNT_S 27
858#define V2_QPC_BYTE_244_RNR_CNT_M GENMASK(29, 27)
859
860#define V2_QPC_BYTE_244_LCL_OP_FLG_S 30
861#define V2_QPC_BYTE_244_IRRL_RD_FLG_S 31
862
863#define V2_QPC_BYTE_248_IRRL_PSN_S 0
864#define V2_QPC_BYTE_248_IRRL_PSN_M GENMASK(23, 0)
865
866#define V2_QPC_BYTE_248_ACK_PSN_ERR_S 24
867
868#define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S 25
869#define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M GENMASK(26, 25)
870
871#define V2_QPC_BYTE_248_IRRL_PSN_VLD_S 27
872
873#define V2_QPC_BYTE_248_RNR_RETRY_FLAG_S 28
874
875#define V2_QPC_BYTE_248_CQ_ERR_IND_S 31
876
877#define V2_QPC_BYTE_252_TX_CQN_S 0
878#define V2_QPC_BYTE_252_TX_CQN_M GENMASK(23, 0)
879
880#define V2_QPC_BYTE_252_SIG_TYPE_S 24
881
882#define V2_QPC_BYTE_252_ERR_TYPE_S 25
883#define V2_QPC_BYTE_252_ERR_TYPE_M GENMASK(31, 25)
884
885#define V2_QPC_BYTE_256_RQ_CQE_IDX_S 0
886#define V2_QPC_BYTE_256_RQ_CQE_IDX_M GENMASK(15, 0)
887
888#define V2_QPC_BYTE_256_SQ_FLUSH_IDX_S 16
889#define V2_QPC_BYTE_256_SQ_FLUSH_IDX_M GENMASK(31, 16)
890
891#define V2_QP_RWE_S 1 /* rdma write enable */
892#define V2_QP_RRE_S 2 /* rdma read enable */
893#define V2_QP_ATE_S 3 /* rdma atomic enable */
894
895struct hns_roce_v2_cqe {
896 __le32 byte_4;
897 union {
898 __le32 rkey;
899 __le32 immtdata;
900 };
901 __le32 byte_12;
902 __le32 byte_16;
903 __le32 byte_cnt;
904 u8 smac[4];
905 __le32 byte_28;
906 __le32 byte_32;
907};
908
909#define V2_CQE_BYTE_4_OPCODE_S 0
910#define V2_CQE_BYTE_4_OPCODE_M GENMASK(4, 0)
911
912#define V2_CQE_BYTE_4_RQ_INLINE_S 5
913
914#define V2_CQE_BYTE_4_S_R_S 6
915
916#define V2_CQE_BYTE_4_OWNER_S 7
917
918#define V2_CQE_BYTE_4_STATUS_S 8
919#define V2_CQE_BYTE_4_STATUS_M GENMASK(15, 8)
920
921#define V2_CQE_BYTE_4_WQE_INDX_S 16
922#define V2_CQE_BYTE_4_WQE_INDX_M GENMASK(31, 16)
923
924#define V2_CQE_BYTE_12_XRC_SRQN_S 0
925#define V2_CQE_BYTE_12_XRC_SRQN_M GENMASK(23, 0)
926
927#define V2_CQE_BYTE_16_LCL_QPN_S 0
928#define V2_CQE_BYTE_16_LCL_QPN_M GENMASK(23, 0)
929
930#define V2_CQE_BYTE_16_SUB_STATUS_S 24
931#define V2_CQE_BYTE_16_SUB_STATUS_M GENMASK(31, 24)
932
933#define V2_CQE_BYTE_28_SMAC_4_S 0
934#define V2_CQE_BYTE_28_SMAC_4_M GENMASK(7, 0)
935
936#define V2_CQE_BYTE_28_SMAC_5_S 8
937#define V2_CQE_BYTE_28_SMAC_5_M GENMASK(15, 8)
938
939#define V2_CQE_BYTE_28_PORT_TYPE_S 16
940#define V2_CQE_BYTE_28_PORT_TYPE_M GENMASK(17, 16)
941
942#define V2_CQE_BYTE_28_VID_S 18
943#define V2_CQE_BYTE_28_VID_M GENMASK(29, 18)
944
945#define V2_CQE_BYTE_28_VID_VLD_S 30
946
947#define V2_CQE_BYTE_32_RMT_QPN_S 0
948#define V2_CQE_BYTE_32_RMT_QPN_M GENMASK(23, 0)
949
950#define V2_CQE_BYTE_32_SL_S 24
951#define V2_CQE_BYTE_32_SL_M GENMASK(26, 24)
952
953#define V2_CQE_BYTE_32_PORTN_S 27
954#define V2_CQE_BYTE_32_PORTN_M GENMASK(29, 27)
955
956#define V2_CQE_BYTE_32_GRH_S 30
957
958#define V2_CQE_BYTE_32_LPK_S 31
959
960struct hns_roce_v2_mpt_entry {
961 __le32 byte_4_pd_hop_st;
962 __le32 byte_8_mw_cnt_en;
963 __le32 byte_12_mw_pa;
964 __le32 bound_lkey;
965 __le32 len_l;
966 __le32 len_h;
967 __le32 lkey;
968 __le32 va_l;
969 __le32 va_h;
970 __le32 pbl_size;
971 __le32 pbl_ba_l;
972 __le32 byte_48_mode_ba;
973 __le32 pa0_l;
974 __le32 byte_56_pa0_h;
975 __le32 pa1_l;
976 __le32 byte_64_buf_pa1;
977};
978
979#define V2_MPT_BYTE_4_MPT_ST_S 0
980#define V2_MPT_BYTE_4_MPT_ST_M GENMASK(1, 0)
981
982#define V2_MPT_BYTE_4_PBL_HOP_NUM_S 2
983#define V2_MPT_BYTE_4_PBL_HOP_NUM_M GENMASK(3, 2)
984
985#define V2_MPT_BYTE_4_PBL_BA_PG_SZ_S 4
986#define V2_MPT_BYTE_4_PBL_BA_PG_SZ_M GENMASK(7, 4)
987
988#define V2_MPT_BYTE_4_PD_S 8
989#define V2_MPT_BYTE_4_PD_M GENMASK(31, 8)
990
991#define V2_MPT_BYTE_8_RA_EN_S 0
992
993#define V2_MPT_BYTE_8_R_INV_EN_S 1
994
995#define V2_MPT_BYTE_8_L_INV_EN_S 2
996
997#define V2_MPT_BYTE_8_BIND_EN_S 3
998
999#define V2_MPT_BYTE_8_ATOMIC_EN_S 4
1000
1001#define V2_MPT_BYTE_8_RR_EN_S 5
1002
1003#define V2_MPT_BYTE_8_RW_EN_S 6
1004
1005#define V2_MPT_BYTE_8_LW_EN_S 7
1006
1007#define V2_MPT_BYTE_8_MW_CNT_S 8
1008#define V2_MPT_BYTE_8_MW_CNT_M GENMASK(31, 8)
1009
1010#define V2_MPT_BYTE_12_FRE_S 0
1011
1012#define V2_MPT_BYTE_12_PA_S 1
1013
1014#define V2_MPT_BYTE_12_MR_MW_S 4
1015
1016#define V2_MPT_BYTE_12_BPD_S 5
1017
1018#define V2_MPT_BYTE_12_BQP_S 6
1019
1020#define V2_MPT_BYTE_12_INNER_PA_VLD_S 7
1021
1022#define V2_MPT_BYTE_12_MW_BIND_QPN_S 8
1023#define V2_MPT_BYTE_12_MW_BIND_QPN_M GENMASK(31, 8)
1024
1025#define V2_MPT_BYTE_48_PBL_BA_H_S 0
1026#define V2_MPT_BYTE_48_PBL_BA_H_M GENMASK(28, 0)
1027
1028#define V2_MPT_BYTE_48_BLK_MODE_S 29
1029
1030#define V2_MPT_BYTE_56_PA0_H_S 0
1031#define V2_MPT_BYTE_56_PA0_H_M GENMASK(25, 0)
1032
1033#define V2_MPT_BYTE_64_PA1_H_S 0
1034#define V2_MPT_BYTE_64_PA1_H_M GENMASK(25, 0)
1035
1036#define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S 28
1037#define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28)
1038
1039#define V2_DB_BYTE_4_TAG_S 0
1040#define V2_DB_BYTE_4_TAG_M GENMASK(23, 0)
1041
1042#define V2_DB_BYTE_4_CMD_S 24
1043#define V2_DB_BYTE_4_CMD_M GENMASK(27, 24)
1044
1045#define V2_DB_PARAMETER_IDX_S 0
1046#define V2_DB_PARAMETER_IDX_M GENMASK(15, 0)
1047
1048#define V2_DB_PARAMETER_SL_S 16
1049#define V2_DB_PARAMETER_SL_M GENMASK(18, 16)
1050
1051struct hns_roce_v2_cq_db {
1052 __le32 byte_4;
1053 __le32 parameter;
1054};
1055
1056#define V2_CQ_DB_BYTE_4_TAG_S 0
1057#define V2_CQ_DB_BYTE_4_TAG_M GENMASK(23, 0)
1058
1059#define V2_CQ_DB_BYTE_4_CMD_S 24
1060#define V2_CQ_DB_BYTE_4_CMD_M GENMASK(27, 24)
1061
1062#define V2_CQ_DB_PARAMETER_CONS_IDX_S 0
1063#define V2_CQ_DB_PARAMETER_CONS_IDX_M GENMASK(23, 0)
1064
1065#define V2_CQ_DB_PARAMETER_CMD_SN_S 25
1066#define V2_CQ_DB_PARAMETER_CMD_SN_M GENMASK(26, 25)
1067
1068#define V2_CQ_DB_PARAMETER_NOTIFY_S 24
1069
1070struct hns_roce_v2_ud_send_wqe {
1071 __le32 byte_4;
1072 __le32 msg_len;
1073 __le32 immtdata;
1074 __le32 byte_16;
1075 __le32 byte_20;
1076 __le32 byte_24;
1077 __le32 qkey;
1078 __le32 byte_32;
1079 __le32 byte_36;
1080 __le32 byte_40;
1081 __le32 dmac;
1082 __le32 byte_48;
1083 u8 dgid[GID_LEN_V2];
1084
1085};
1086#define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0
1087#define V2_UD_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
1088
1089#define V2_UD_SEND_WQE_BYTE_4_OWNER_S 7
1090
1091#define V2_UD_SEND_WQE_BYTE_4_CQE_S 8
1092
1093#define V2_UD_SEND_WQE_BYTE_4_SE_S 11
1094
1095#define V2_UD_SEND_WQE_BYTE_16_PD_S 0
1096#define V2_UD_SEND_WQE_BYTE_16_PD_M GENMASK(23, 0)
1097
1098#define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S 24
1099#define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
1100
1101#define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
1102#define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
1103
1104#define V2_UD_SEND_WQE_BYTE_24_UDPSPN_S 16
1105#define V2_UD_SEND_WQE_BYTE_24_UDPSPN_M GENMASK(31, 16)
1106
1107#define V2_UD_SEND_WQE_BYTE_32_DQPN_S 0
1108#define V2_UD_SEND_WQE_BYTE_32_DQPN_M GENMASK(23, 0)
1109
1110#define V2_UD_SEND_WQE_BYTE_36_VLAN_S 0
1111#define V2_UD_SEND_WQE_BYTE_36_VLAN_M GENMASK(15, 0)
1112
1113#define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S 16
1114#define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M GENMASK(23, 16)
1115
1116#define V2_UD_SEND_WQE_BYTE_36_TCLASS_S 24
1117#define V2_UD_SEND_WQE_BYTE_36_TCLASS_M GENMASK(31, 24)
1118
1119#define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S 0
1120#define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M GENMASK(19, 0)
1121
1122#define V2_UD_SEND_WQE_BYTE_40_SL_S 20
1123#define V2_UD_SEND_WQE_BYTE_40_SL_M GENMASK(23, 20)
1124
1125#define V2_UD_SEND_WQE_BYTE_40_PORTN_S 24
1126#define V2_UD_SEND_WQE_BYTE_40_PORTN_M GENMASK(26, 24)
1127
1128#define V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S 30
1129
1130#define V2_UD_SEND_WQE_BYTE_40_LBI_S 31
1131
1132#define V2_UD_SEND_WQE_DMAC_0_S 0
1133#define V2_UD_SEND_WQE_DMAC_0_M GENMASK(7, 0)
1134
1135#define V2_UD_SEND_WQE_DMAC_1_S 8
1136#define V2_UD_SEND_WQE_DMAC_1_M GENMASK(15, 8)
1137
1138#define V2_UD_SEND_WQE_DMAC_2_S 16
1139#define V2_UD_SEND_WQE_DMAC_2_M GENMASK(23, 16)
1140
1141#define V2_UD_SEND_WQE_DMAC_3_S 24
1142#define V2_UD_SEND_WQE_DMAC_3_M GENMASK(31, 24)
1143
1144#define V2_UD_SEND_WQE_BYTE_48_DMAC_4_S 0
1145#define V2_UD_SEND_WQE_BYTE_48_DMAC_4_M GENMASK(7, 0)
1146
1147#define V2_UD_SEND_WQE_BYTE_48_DMAC_5_S 8
1148#define V2_UD_SEND_WQE_BYTE_48_DMAC_5_M GENMASK(15, 8)
1149
1150#define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S 16
1151#define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M GENMASK(23, 16)
1152
1153#define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_S 24
1154#define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_M GENMASK(31, 24)
1155
1156struct hns_roce_v2_rc_send_wqe {
1157 __le32 byte_4;
1158 __le32 msg_len;
1159 union {
1160 __le32 inv_key;
1161 __le32 immtdata;
1162 };
1163 __le32 byte_16;
1164 __le32 byte_20;
1165 __le32 rkey;
1166 __le64 va;
1167};
1168
1169#define V2_RC_SEND_WQE_BYTE_4_OPCODE_S 0
1170#define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0)
1171
1172#define V2_RC_SEND_WQE_BYTE_4_OWNER_S 7
1173
1174#define V2_RC_SEND_WQE_BYTE_4_CQE_S 8
1175
1176#define V2_RC_SEND_WQE_BYTE_4_FENCE_S 9
1177
1178#define V2_RC_SEND_WQE_BYTE_4_SO_S 10
1179
1180#define V2_RC_SEND_WQE_BYTE_4_SE_S 11
1181
1182#define V2_RC_SEND_WQE_BYTE_4_INLINE_S 12
1183
1184#define V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S 19
1185
1186#define V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S 20
1187
1188#define V2_RC_FRMR_WQE_BYTE_4_RR_S 21
1189
1190#define V2_RC_FRMR_WQE_BYTE_4_RW_S 22
1191
1192#define V2_RC_FRMR_WQE_BYTE_4_LW_S 23
1193
1194#define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0
1195#define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0)
1196
1197#define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S 24
1198#define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24)
1199
1200#define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0
1201#define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0)
1202
1203struct hns_roce_wqe_frmr_seg {
1204 __le32 pbl_size;
1205 __le32 mode_buf_pg_sz;
1206};
1207
1208#define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S 4
1209#define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M GENMASK(7, 4)
1210
1211#define V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S 8
1212
1213struct hns_roce_v2_wqe_data_seg {
1214 __le32 len;
1215 __le32 lkey;
1216 __le64 addr;
1217};
1218
1219struct hns_roce_v2_db {
1220 __le32 byte_4;
1221 __le32 parameter;
1222};
1223
1224struct hns_roce_query_version {
1225 __le16 rocee_vendor_id;
1226 __le16 rocee_hw_version;
1227 __le32 rsv[5];
1228};
1229
1230struct hns_roce_query_fw_info {
1231 __le32 fw_ver;
1232 __le32 rsv[5];
1233};
1234
1235struct hns_roce_func_clear {
1236 __le32 rst_funcid_en;
1237 __le32 func_done;
1238 __le32 rsv[4];
1239};
1240
1241#define FUNC_CLEAR_RST_FUN_DONE_S 0
1242/* Each physical function manages up to 248 virtual functionsï¼›
1243 * it takes up to 100ms for each function to execute clearï¼›
1244 * if an abnormal reset occurs, it is executed twice at most;
1245 * so it takes up to 249 * 2 * 100ms.
1246 */
1247#define HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS (249 * 2 * 100)
1248#define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL 40
1249#define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT 20
1250
1251struct hns_roce_cfg_llm_a {
1252 __le32 base_addr_l;
1253 __le32 base_addr_h;
1254 __le32 depth_pgsz_init_en;
1255 __le32 head_ba_l;
1256 __le32 head_ba_h_nxtptr;
1257 __le32 head_ptr;
1258};
1259
1260#define CFG_LLM_QUE_DEPTH_S 0
1261#define CFG_LLM_QUE_DEPTH_M GENMASK(12, 0)
1262
1263#define CFG_LLM_QUE_PGSZ_S 16
1264#define CFG_LLM_QUE_PGSZ_M GENMASK(19, 16)
1265
1266#define CFG_LLM_INIT_EN_S 20
1267#define CFG_LLM_INIT_EN_M GENMASK(20, 20)
1268
1269#define CFG_LLM_HEAD_PTR_S 0
1270#define CFG_LLM_HEAD_PTR_M GENMASK(11, 0)
1271
1272struct hns_roce_cfg_llm_b {
1273 __le32 tail_ba_l;
1274 __le32 tail_ba_h;
1275 __le32 tail_ptr;
1276 __le32 rsv[3];
1277};
1278
1279#define CFG_LLM_TAIL_BA_H_S 0
1280#define CFG_LLM_TAIL_BA_H_M GENMASK(19, 0)
1281
1282#define CFG_LLM_TAIL_PTR_S 0
1283#define CFG_LLM_TAIL_PTR_M GENMASK(11, 0)
1284
1285struct hns_roce_cfg_global_param {
1286 __le32 time_cfg_udp_port;
1287 __le32 rsv[5];
1288};
1289
1290#define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S 0
1291#define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M GENMASK(9, 0)
1292
1293#define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S 16
1294#define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M GENMASK(31, 16)
1295
1296struct hns_roce_pf_res_a {
1297 __le32 rsv;
1298 __le32 qpc_bt_idx_num;
1299 __le32 srqc_bt_idx_num;
1300 __le32 cqc_bt_idx_num;
1301 __le32 mpt_bt_idx_num;
1302 __le32 eqc_bt_idx_num;
1303};
1304
1305#define PF_RES_DATA_1_PF_QPC_BT_IDX_S 0
1306#define PF_RES_DATA_1_PF_QPC_BT_IDX_M GENMASK(10, 0)
1307
1308#define PF_RES_DATA_1_PF_QPC_BT_NUM_S 16
1309#define PF_RES_DATA_1_PF_QPC_BT_NUM_M GENMASK(27, 16)
1310
1311#define PF_RES_DATA_2_PF_SRQC_BT_IDX_S 0
1312#define PF_RES_DATA_2_PF_SRQC_BT_IDX_M GENMASK(8, 0)
1313
1314#define PF_RES_DATA_2_PF_SRQC_BT_NUM_S 16
1315#define PF_RES_DATA_2_PF_SRQC_BT_NUM_M GENMASK(25, 16)
1316
1317#define PF_RES_DATA_3_PF_CQC_BT_IDX_S 0
1318#define PF_RES_DATA_3_PF_CQC_BT_IDX_M GENMASK(8, 0)
1319
1320#define PF_RES_DATA_3_PF_CQC_BT_NUM_S 16
1321#define PF_RES_DATA_3_PF_CQC_BT_NUM_M GENMASK(25, 16)
1322
1323#define PF_RES_DATA_4_PF_MPT_BT_IDX_S 0
1324#define PF_RES_DATA_4_PF_MPT_BT_IDX_M GENMASK(8, 0)
1325
1326#define PF_RES_DATA_4_PF_MPT_BT_NUM_S 16
1327#define PF_RES_DATA_4_PF_MPT_BT_NUM_M GENMASK(25, 16)
1328
1329#define PF_RES_DATA_5_PF_EQC_BT_IDX_S 0
1330#define PF_RES_DATA_5_PF_EQC_BT_IDX_M GENMASK(8, 0)
1331
1332#define PF_RES_DATA_5_PF_EQC_BT_NUM_S 16
1333#define PF_RES_DATA_5_PF_EQC_BT_NUM_M GENMASK(25, 16)
1334
1335struct hns_roce_pf_res_b {
1336 __le32 rsv0;
1337 __le32 smac_idx_num;
1338 __le32 sgid_idx_num;
1339 __le32 qid_idx_sl_num;
1340 __le32 sccc_bt_idx_num;
1341 __le32 rsv;
1342};
1343
1344#define PF_RES_DATA_1_PF_SMAC_IDX_S 0
1345#define PF_RES_DATA_1_PF_SMAC_IDX_M GENMASK(7, 0)
1346
1347#define PF_RES_DATA_1_PF_SMAC_NUM_S 8
1348#define PF_RES_DATA_1_PF_SMAC_NUM_M GENMASK(16, 8)
1349
1350#define PF_RES_DATA_2_PF_SGID_IDX_S 0
1351#define PF_RES_DATA_2_PF_SGID_IDX_M GENMASK(7, 0)
1352
1353#define PF_RES_DATA_2_PF_SGID_NUM_S 8
1354#define PF_RES_DATA_2_PF_SGID_NUM_M GENMASK(16, 8)
1355
1356#define PF_RES_DATA_3_PF_QID_IDX_S 0
1357#define PF_RES_DATA_3_PF_QID_IDX_M GENMASK(9, 0)
1358
1359#define PF_RES_DATA_3_PF_SL_NUM_S 16
1360#define PF_RES_DATA_3_PF_SL_NUM_M GENMASK(26, 16)
1361
1362#define PF_RES_DATA_4_PF_SCCC_BT_IDX_S 0
1363#define PF_RES_DATA_4_PF_SCCC_BT_IDX_M GENMASK(8, 0)
1364
1365#define PF_RES_DATA_4_PF_SCCC_BT_NUM_S 9
1366#define PF_RES_DATA_4_PF_SCCC_BT_NUM_M GENMASK(17, 9)
1367
1368struct hns_roce_pf_timer_res_a {
1369 __le32 rsv0;
1370 __le32 qpc_timer_bt_idx_num;
1371 __le32 cqc_timer_bt_idx_num;
1372 __le32 rsv[3];
1373};
1374
1375#define PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_S 0
1376#define PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_M GENMASK(11, 0)
1377
1378#define PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S 16
1379#define PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M GENMASK(28, 16)
1380
1381#define PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_S 0
1382#define PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_M GENMASK(10, 0)
1383
1384#define PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S 16
1385#define PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M GENMASK(27, 16)
1386
1387struct hns_roce_vf_res_a {
1388 __le32 vf_id;
1389 __le32 vf_qpc_bt_idx_num;
1390 __le32 vf_srqc_bt_idx_num;
1391 __le32 vf_cqc_bt_idx_num;
1392 __le32 vf_mpt_bt_idx_num;
1393 __le32 vf_eqc_bt_idx_num;
1394};
1395
1396#define VF_RES_A_DATA_1_VF_QPC_BT_IDX_S 0
1397#define VF_RES_A_DATA_1_VF_QPC_BT_IDX_M GENMASK(10, 0)
1398
1399#define VF_RES_A_DATA_1_VF_QPC_BT_NUM_S 16
1400#define VF_RES_A_DATA_1_VF_QPC_BT_NUM_M GENMASK(27, 16)
1401
1402#define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S 0
1403#define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M GENMASK(8, 0)
1404
1405#define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S 16
1406#define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M GENMASK(25, 16)
1407
1408#define VF_RES_A_DATA_3_VF_CQC_BT_IDX_S 0
1409#define VF_RES_A_DATA_3_VF_CQC_BT_IDX_M GENMASK(8, 0)
1410
1411#define VF_RES_A_DATA_3_VF_CQC_BT_NUM_S 16
1412#define VF_RES_A_DATA_3_VF_CQC_BT_NUM_M GENMASK(25, 16)
1413
1414#define VF_RES_A_DATA_4_VF_MPT_BT_IDX_S 0
1415#define VF_RES_A_DATA_4_VF_MPT_BT_IDX_M GENMASK(8, 0)
1416
1417#define VF_RES_A_DATA_4_VF_MPT_BT_NUM_S 16
1418#define VF_RES_A_DATA_4_VF_MPT_BT_NUM_M GENMASK(25, 16)
1419
1420#define VF_RES_A_DATA_5_VF_EQC_IDX_S 0
1421#define VF_RES_A_DATA_5_VF_EQC_IDX_M GENMASK(8, 0)
1422
1423#define VF_RES_A_DATA_5_VF_EQC_NUM_S 16
1424#define VF_RES_A_DATA_5_VF_EQC_NUM_M GENMASK(25, 16)
1425
1426struct hns_roce_vf_res_b {
1427 __le32 rsv0;
1428 __le32 vf_smac_idx_num;
1429 __le32 vf_sgid_idx_num;
1430 __le32 vf_qid_idx_sl_num;
1431 __le32 vf_sccc_idx_num;
1432 __le32 rsv1;
1433};
1434
1435#define VF_RES_B_DATA_0_VF_ID_S 0
1436#define VF_RES_B_DATA_0_VF_ID_M GENMASK(7, 0)
1437
1438#define VF_RES_B_DATA_1_VF_SMAC_IDX_S 0
1439#define VF_RES_B_DATA_1_VF_SMAC_IDX_M GENMASK(7, 0)
1440
1441#define VF_RES_B_DATA_1_VF_SMAC_NUM_S 8
1442#define VF_RES_B_DATA_1_VF_SMAC_NUM_M GENMASK(16, 8)
1443
1444#define VF_RES_B_DATA_2_VF_SGID_IDX_S 0
1445#define VF_RES_B_DATA_2_VF_SGID_IDX_M GENMASK(7, 0)
1446
1447#define VF_RES_B_DATA_2_VF_SGID_NUM_S 8
1448#define VF_RES_B_DATA_2_VF_SGID_NUM_M GENMASK(16, 8)
1449
1450#define VF_RES_B_DATA_3_VF_QID_IDX_S 0
1451#define VF_RES_B_DATA_3_VF_QID_IDX_M GENMASK(9, 0)
1452
1453#define VF_RES_B_DATA_3_VF_SL_NUM_S 16
1454#define VF_RES_B_DATA_3_VF_SL_NUM_M GENMASK(19, 16)
1455
1456#define VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S 0
1457#define VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M GENMASK(8, 0)
1458
1459#define VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S 9
1460#define VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M GENMASK(17, 9)
1461
1462struct hns_roce_vf_switch {
1463 __le32 rocee_sel;
1464 __le32 fun_id;
1465 __le32 cfg;
1466 __le32 resv1;
1467 __le32 resv2;
1468 __le32 resv3;
1469};
1470
1471#define VF_SWITCH_DATA_FUN_ID_VF_ID_S 3
1472#define VF_SWITCH_DATA_FUN_ID_VF_ID_M GENMASK(10, 3)
1473
1474#define VF_SWITCH_DATA_CFG_ALW_LPBK_S 1
1475#define VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S 2
1476#define VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S 3
1477
1478struct hns_roce_post_mbox {
1479 __le32 in_param_l;
1480 __le32 in_param_h;
1481 __le32 out_param_l;
1482 __le32 out_param_h;
1483 __le32 cmd_tag;
1484 __le32 token_event_en;
1485};
1486
1487struct hns_roce_mbox_status {
1488 __le32 mb_status_hw_run;
1489 __le32 rsv[5];
1490};
1491
1492struct hns_roce_cfg_bt_attr {
1493 __le32 vf_qpc_cfg;
1494 __le32 vf_srqc_cfg;
1495 __le32 vf_cqc_cfg;
1496 __le32 vf_mpt_cfg;
1497 __le32 vf_sccc_cfg;
1498 __le32 rsv;
1499};
1500
1501#define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S 0
1502#define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M GENMASK(3, 0)
1503
1504#define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S 4
1505#define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M GENMASK(7, 4)
1506
1507#define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S 8
1508#define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M GENMASK(9, 8)
1509
1510#define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S 0
1511#define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M GENMASK(3, 0)
1512
1513#define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S 4
1514#define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M GENMASK(7, 4)
1515
1516#define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S 8
1517#define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M GENMASK(9, 8)
1518
1519#define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S 0
1520#define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M GENMASK(3, 0)
1521
1522#define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S 4
1523#define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M GENMASK(7, 4)
1524
1525#define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S 8
1526#define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M GENMASK(9, 8)
1527
1528#define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S 0
1529#define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M GENMASK(3, 0)
1530
1531#define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S 4
1532#define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M GENMASK(7, 4)
1533
1534#define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S 8
1535#define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M GENMASK(9, 8)
1536
1537#define CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S 0
1538#define CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M GENMASK(3, 0)
1539
1540#define CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S 4
1541#define CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M GENMASK(7, 4)
1542
1543#define CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S 8
1544#define CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M GENMASK(9, 8)
1545
1546struct hns_roce_cfg_sgid_tb {
1547 __le32 table_idx_rsv;
1548 __le32 vf_sgid_l;
1549 __le32 vf_sgid_ml;
1550 __le32 vf_sgid_mh;
1551 __le32 vf_sgid_h;
1552 __le32 vf_sgid_type_rsv;
1553};
1554#define CFG_SGID_TB_TABLE_IDX_S 0
1555#define CFG_SGID_TB_TABLE_IDX_M GENMASK(7, 0)
1556
1557#define CFG_SGID_TB_VF_SGID_TYPE_S 0
1558#define CFG_SGID_TB_VF_SGID_TYPE_M GENMASK(1, 0)
1559
1560struct hns_roce_cfg_smac_tb {
1561 __le32 tb_idx_rsv;
1562 __le32 vf_smac_l;
1563 __le32 vf_smac_h_rsv;
1564 __le32 rsv[3];
1565};
1566#define CFG_SMAC_TB_IDX_S 0
1567#define CFG_SMAC_TB_IDX_M GENMASK(7, 0)
1568
1569#define CFG_SMAC_TB_VF_SMAC_H_S 0
1570#define CFG_SMAC_TB_VF_SMAC_H_M GENMASK(15, 0)
1571
1572struct hns_roce_cmq_desc {
1573 __le16 opcode;
1574 __le16 flag;
1575 __le16 retval;
1576 __le16 rsv;
1577 __le32 data[6];
1578};
1579
1580#define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS 10000
1581
1582#define HNS_ROCE_HW_RUN_BIT_SHIFT 31
1583#define HNS_ROCE_HW_MB_STATUS_MASK 0xFF
1584
1585struct hns_roce_v2_cmq_ring {
1586 dma_addr_t desc_dma_addr;
1587 struct hns_roce_cmq_desc *desc;
1588 u32 head;
1589 u32 tail;
1590
1591 u16 buf_size;
1592 u16 desc_num;
1593 int next_to_use;
1594 int next_to_clean;
1595 u8 flag;
1596 spinlock_t lock; /* command queue lock */
1597};
1598
1599struct hns_roce_v2_cmq {
1600 struct hns_roce_v2_cmq_ring csq;
1601 struct hns_roce_v2_cmq_ring crq;
1602 u16 tx_timeout;
1603 u16 last_status;
1604};
1605
1606enum hns_roce_link_table_type {
1607 TSQ_LINK_TABLE,
1608 TPQ_LINK_TABLE,
1609};
1610
1611struct hns_roce_link_table {
1612 struct hns_roce_buf_list table;
1613 struct hns_roce_buf_list *pg_list;
1614 u32 npages;
1615 u32 pg_sz;
1616};
1617
1618struct hns_roce_link_table_entry {
1619 u32 blk_ba0;
1620 u32 blk_ba1_nxt_ptr;
1621};
1622#define HNS_ROCE_LINK_TABLE_BA1_S 0
1623#define HNS_ROCE_LINK_TABLE_BA1_M GENMASK(19, 0)
1624
1625#define HNS_ROCE_LINK_TABLE_NXT_PTR_S 20
1626#define HNS_ROCE_LINK_TABLE_NXT_PTR_M GENMASK(31, 20)
1627
1628struct hns_roce_v2_priv {
1629 struct hnae3_handle *handle;
1630 struct hns_roce_v2_cmq cmq;
1631 struct hns_roce_link_table tsq;
1632 struct hns_roce_link_table tpq;
1633};
1634
1635struct hns_roce_eq_context {
1636 __le32 byte_4;
1637 __le32 byte_8;
1638 __le32 byte_12;
1639 __le32 eqe_report_timer;
1640 __le32 eqe_ba0;
1641 __le32 eqe_ba1;
1642 __le32 byte_28;
1643 __le32 byte_32;
1644 __le32 byte_36;
1645 __le32 nxt_eqe_ba0;
1646 __le32 nxt_eqe_ba1;
1647 __le32 rsv[5];
1648};
1649
1650#define HNS_ROCE_AEQ_DEFAULT_BURST_NUM 0x0
1651#define HNS_ROCE_AEQ_DEFAULT_INTERVAL 0x0
1652#define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x0
1653#define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x0
1654
1655#define HNS_ROCE_V2_EQ_STATE_INVALID 0
1656#define HNS_ROCE_V2_EQ_STATE_VALID 1
1657#define HNS_ROCE_V2_EQ_STATE_OVERFLOW 2
1658#define HNS_ROCE_V2_EQ_STATE_FAILURE 3
1659
1660#define HNS_ROCE_V2_EQ_OVER_IGNORE_0 0
1661#define HNS_ROCE_V2_EQ_OVER_IGNORE_1 1
1662
1663#define HNS_ROCE_V2_EQ_COALESCE_0 0
1664#define HNS_ROCE_V2_EQ_COALESCE_1 1
1665
1666#define HNS_ROCE_V2_EQ_FIRED 0
1667#define HNS_ROCE_V2_EQ_ARMED 1
1668#define HNS_ROCE_V2_EQ_ALWAYS_ARMED 3
1669
1670#define HNS_ROCE_EQ_INIT_EQE_CNT 0
1671#define HNS_ROCE_EQ_INIT_PROD_IDX 0
1672#define HNS_ROCE_EQ_INIT_REPORT_TIMER 0
1673#define HNS_ROCE_EQ_INIT_MSI_IDX 0
1674#define HNS_ROCE_EQ_INIT_CONS_IDX 0
1675#define HNS_ROCE_EQ_INIT_NXT_EQE_BA 0
1676
1677#define HNS_ROCE_V2_CEQ_CEQE_OWNER_S 31
1678#define HNS_ROCE_V2_AEQ_AEQE_OWNER_S 31
1679
1680#define HNS_ROCE_V2_COMP_EQE_NUM 0x1000
1681#define HNS_ROCE_V2_ASYNC_EQE_NUM 0x1000
1682
1683#define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S 0
1684#define HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S 1
1685#define HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S 2
1686
1687#define HNS_ROCE_EQ_DB_CMD_AEQ 0x0
1688#define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED 0x1
1689#define HNS_ROCE_EQ_DB_CMD_CEQ 0x2
1690#define HNS_ROCE_EQ_DB_CMD_CEQ_ARMED 0x3
1691
1692#define EQ_ENABLE 1
1693#define EQ_DISABLE 0
1694
1695#define EQ_REG_OFFSET 0x4
1696
1697#define HNS_ROCE_INT_NAME_LEN 32
1698#define HNS_ROCE_V2_EQN_M GENMASK(23, 0)
1699
1700#define HNS_ROCE_V2_CONS_IDX_M GENMASK(23, 0)
1701
1702#define HNS_ROCE_V2_VF_ABN_INT_EN_S 0
1703#define HNS_ROCE_V2_VF_ABN_INT_EN_M GENMASK(0, 0)
1704#define HNS_ROCE_V2_VF_ABN_INT_ST_M GENMASK(2, 0)
1705#define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0)
1706#define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0)
1707
1708/* WORD0 */
1709#define HNS_ROCE_EQC_EQ_ST_S 0
1710#define HNS_ROCE_EQC_EQ_ST_M GENMASK(1, 0)
1711
1712#define HNS_ROCE_EQC_HOP_NUM_S 2
1713#define HNS_ROCE_EQC_HOP_NUM_M GENMASK(3, 2)
1714
1715#define HNS_ROCE_EQC_OVER_IGNORE_S 4
1716#define HNS_ROCE_EQC_OVER_IGNORE_M GENMASK(4, 4)
1717
1718#define HNS_ROCE_EQC_COALESCE_S 5
1719#define HNS_ROCE_EQC_COALESCE_M GENMASK(5, 5)
1720
1721#define HNS_ROCE_EQC_ARM_ST_S 6
1722#define HNS_ROCE_EQC_ARM_ST_M GENMASK(7, 6)
1723
1724#define HNS_ROCE_EQC_EQN_S 8
1725#define HNS_ROCE_EQC_EQN_M GENMASK(15, 8)
1726
1727#define HNS_ROCE_EQC_EQE_CNT_S 16
1728#define HNS_ROCE_EQC_EQE_CNT_M GENMASK(31, 16)
1729
1730/* WORD1 */
1731#define HNS_ROCE_EQC_BA_PG_SZ_S 0
1732#define HNS_ROCE_EQC_BA_PG_SZ_M GENMASK(3, 0)
1733
1734#define HNS_ROCE_EQC_BUF_PG_SZ_S 4
1735#define HNS_ROCE_EQC_BUF_PG_SZ_M GENMASK(7, 4)
1736
1737#define HNS_ROCE_EQC_PROD_INDX_S 8
1738#define HNS_ROCE_EQC_PROD_INDX_M GENMASK(31, 8)
1739
1740/* WORD2 */
1741#define HNS_ROCE_EQC_MAX_CNT_S 0
1742#define HNS_ROCE_EQC_MAX_CNT_M GENMASK(15, 0)
1743
1744#define HNS_ROCE_EQC_PERIOD_S 16
1745#define HNS_ROCE_EQC_PERIOD_M GENMASK(31, 16)
1746
1747/* WORD3 */
1748#define HNS_ROCE_EQC_REPORT_TIMER_S 0
1749#define HNS_ROCE_EQC_REPORT_TIMER_M GENMASK(31, 0)
1750
1751/* WORD4 */
1752#define HNS_ROCE_EQC_EQE_BA_L_S 0
1753#define HNS_ROCE_EQC_EQE_BA_L_M GENMASK(31, 0)
1754
1755/* WORD5 */
1756#define HNS_ROCE_EQC_EQE_BA_H_S 0
1757#define HNS_ROCE_EQC_EQE_BA_H_M GENMASK(28, 0)
1758
1759/* WORD6 */
1760#define HNS_ROCE_EQC_SHIFT_S 0
1761#define HNS_ROCE_EQC_SHIFT_M GENMASK(7, 0)
1762
1763#define HNS_ROCE_EQC_MSI_INDX_S 8
1764#define HNS_ROCE_EQC_MSI_INDX_M GENMASK(15, 8)
1765
1766#define HNS_ROCE_EQC_CUR_EQE_BA_L_S 16
1767#define HNS_ROCE_EQC_CUR_EQE_BA_L_M GENMASK(31, 16)
1768
1769/* WORD7 */
1770#define HNS_ROCE_EQC_CUR_EQE_BA_M_S 0
1771#define HNS_ROCE_EQC_CUR_EQE_BA_M_M GENMASK(31, 0)
1772
1773/* WORD8 */
1774#define HNS_ROCE_EQC_CUR_EQE_BA_H_S 0
1775#define HNS_ROCE_EQC_CUR_EQE_BA_H_M GENMASK(3, 0)
1776
1777#define HNS_ROCE_EQC_CONS_INDX_S 8
1778#define HNS_ROCE_EQC_CONS_INDX_M GENMASK(31, 8)
1779
1780/* WORD9 */
1781#define HNS_ROCE_EQC_NXT_EQE_BA_L_S 0
1782#define HNS_ROCE_EQC_NXT_EQE_BA_L_M GENMASK(31, 0)
1783
1784/* WORD10 */
1785#define HNS_ROCE_EQC_NXT_EQE_BA_H_S 0
1786#define HNS_ROCE_EQC_NXT_EQE_BA_H_M GENMASK(19, 0)
1787
1788#define HNS_ROCE_V2_CEQE_COMP_CQN_S 0
1789#define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0)
1790
1791#define HNS_ROCE_V2_AEQE_EVENT_TYPE_S 0
1792#define HNS_ROCE_V2_AEQE_EVENT_TYPE_M GENMASK(7, 0)
1793
1794#define HNS_ROCE_V2_AEQE_SUB_TYPE_S 8
1795#define HNS_ROCE_V2_AEQE_SUB_TYPE_M GENMASK(15, 8)
1796
1797#define HNS_ROCE_V2_EQ_DB_CMD_S 16
1798#define HNS_ROCE_V2_EQ_DB_CMD_M GENMASK(17, 16)
1799
1800#define HNS_ROCE_V2_EQ_DB_TAG_S 0
1801#define HNS_ROCE_V2_EQ_DB_TAG_M GENMASK(7, 0)
1802
1803#define HNS_ROCE_V2_EQ_DB_PARA_S 0
1804#define HNS_ROCE_V2_EQ_DB_PARA_M GENMASK(23, 0)
1805
1806#define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S 0
1807#define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0)
1808
1809struct hns_roce_wqe_atomic_seg {
1810 __le64 fetchadd_swap_data;
1811 __le64 cmp_data;
1812};
1813
1814struct hns_roce_sccc_clr {
1815 __le32 qpn;
1816 __le32 rsv[5];
1817};
1818
1819struct hns_roce_sccc_clr_done {
1820 __le32 clr_done;
1821 __le32 rsv[5];
1822};
1823
1824int hns_roce_v2_query_cqc_info(struct hns_roce_dev *hr_dev, u32 cqn,
1825 int *buffer);
1826
1827static inline void hns_roce_write64(struct hns_roce_dev *hr_dev, __le32 val[2],
1828 void __iomem *dest)
1829{
1830 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
1831 struct hnae3_handle *handle = priv->handle;
1832 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1833
1834 if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle))
1835 hns_roce_write64_k(val, dest);
1836}
1837
1838#endif