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1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/*
3 * Copyright(c) 2015 - 2020 Intel Corporation.
4 */
5
6#ifndef _COMMON_H
7#define _COMMON_H
8
9#include <rdma/hfi/hfi1_user.h>
10
11/*
12 * This file contains defines, structures, etc. that are used
13 * to communicate between kernel and user code.
14 */
15
16/* version of protocol header (known to chip also). In the long run,
17 * we should be able to generate and accept a range of version numbers;
18 * for now we only accept one, and it's compiled in.
19 */
20#define IPS_PROTO_VERSION 2
21
22/*
23 * These are compile time constants that you may want to enable or disable
24 * if you are trying to debug problems with code or performance.
25 * HFI1_VERBOSE_TRACING define as 1 if you want additional tracing in
26 * fast path code
27 * HFI1_TRACE_REGWRITES define as 1 if you want register writes to be
28 * traced in fast path code
29 * _HFI1_TRACING define as 0 if you want to remove all tracing in a
30 * compilation unit
31 */
32
33/* driver/hw feature set bitmask */
34#define HFI1_CAP_USER_SHIFT 24
35#define HFI1_CAP_MASK ((1UL << HFI1_CAP_USER_SHIFT) - 1)
36/* locked flag - if set, only HFI1_CAP_WRITABLE_MASK bits can be set */
37#define HFI1_CAP_LOCKED_SHIFT 63
38#define HFI1_CAP_LOCKED_MASK 0x1ULL
39#define HFI1_CAP_LOCKED_SMASK (HFI1_CAP_LOCKED_MASK << HFI1_CAP_LOCKED_SHIFT)
40/* extra bits used between kernel and user processes */
41#define HFI1_CAP_MISC_SHIFT (HFI1_CAP_USER_SHIFT * 2)
42#define HFI1_CAP_MISC_MASK ((1ULL << (HFI1_CAP_LOCKED_SHIFT - \
43 HFI1_CAP_MISC_SHIFT)) - 1)
44
45#define HFI1_CAP_KSET(cap) ({ hfi1_cap_mask |= HFI1_CAP_##cap; hfi1_cap_mask; })
46#define HFI1_CAP_KCLEAR(cap) \
47 ({ \
48 hfi1_cap_mask &= ~HFI1_CAP_##cap; \
49 hfi1_cap_mask; \
50 })
51#define HFI1_CAP_USET(cap) \
52 ({ \
53 hfi1_cap_mask |= (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
54 hfi1_cap_mask; \
55 })
56#define HFI1_CAP_UCLEAR(cap) \
57 ({ \
58 hfi1_cap_mask &= ~(HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
59 hfi1_cap_mask; \
60 })
61#define HFI1_CAP_SET(cap) \
62 ({ \
63 hfi1_cap_mask |= (HFI1_CAP_##cap | (HFI1_CAP_##cap << \
64 HFI1_CAP_USER_SHIFT)); \
65 hfi1_cap_mask; \
66 })
67#define HFI1_CAP_CLEAR(cap) \
68 ({ \
69 hfi1_cap_mask &= ~(HFI1_CAP_##cap | \
70 (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT)); \
71 hfi1_cap_mask; \
72 })
73#define HFI1_CAP_LOCK() \
74 ({ hfi1_cap_mask |= HFI1_CAP_LOCKED_SMASK; hfi1_cap_mask; })
75#define HFI1_CAP_LOCKED() (!!(hfi1_cap_mask & HFI1_CAP_LOCKED_SMASK))
76/*
77 * The set of capability bits that can be changed after initial load
78 * This set is the same for kernel and user contexts. However, for
79 * user contexts, the set can be further filtered by using the
80 * HFI1_CAP_RESERVED_MASK bits.
81 */
82#define HFI1_CAP_WRITABLE_MASK (HFI1_CAP_SDMA_AHG | \
83 HFI1_CAP_HDRSUPP | \
84 HFI1_CAP_MULTI_PKT_EGR | \
85 HFI1_CAP_NODROP_RHQ_FULL | \
86 HFI1_CAP_NODROP_EGR_FULL | \
87 HFI1_CAP_ALLOW_PERM_JKEY | \
88 HFI1_CAP_STATIC_RATE_CTRL | \
89 HFI1_CAP_PRINT_UNIMPL | \
90 HFI1_CAP_TID_UNMAP | \
91 HFI1_CAP_OPFN)
92/*
93 * A set of capability bits that are "global" and are not allowed to be
94 * set in the user bitmask.
95 */
96#define HFI1_CAP_RESERVED_MASK ((HFI1_CAP_SDMA | \
97 HFI1_CAP_USE_SDMA_HEAD | \
98 HFI1_CAP_EXTENDED_PSN | \
99 HFI1_CAP_PRINT_UNIMPL | \
100 HFI1_CAP_NO_INTEGRITY | \
101 HFI1_CAP_PKEY_CHECK | \
102 HFI1_CAP_TID_RDMA | \
103 HFI1_CAP_OPFN | \
104 HFI1_CAP_AIP) << \
105 HFI1_CAP_USER_SHIFT)
106/*
107 * Set of capabilities that need to be enabled for kernel context in
108 * order to be allowed for user contexts, as well.
109 */
110#define HFI1_CAP_MUST_HAVE_KERN (HFI1_CAP_STATIC_RATE_CTRL)
111/* Default enabled capabilities (both kernel and user) */
112#define HFI1_CAP_MASK_DEFAULT (HFI1_CAP_HDRSUPP | \
113 HFI1_CAP_NODROP_RHQ_FULL | \
114 HFI1_CAP_NODROP_EGR_FULL | \
115 HFI1_CAP_SDMA | \
116 HFI1_CAP_PRINT_UNIMPL | \
117 HFI1_CAP_STATIC_RATE_CTRL | \
118 HFI1_CAP_PKEY_CHECK | \
119 HFI1_CAP_MULTI_PKT_EGR | \
120 HFI1_CAP_EXTENDED_PSN | \
121 HFI1_CAP_AIP | \
122 ((HFI1_CAP_HDRSUPP | \
123 HFI1_CAP_MULTI_PKT_EGR | \
124 HFI1_CAP_STATIC_RATE_CTRL | \
125 HFI1_CAP_PKEY_CHECK | \
126 HFI1_CAP_EARLY_CREDIT_RETURN) << \
127 HFI1_CAP_USER_SHIFT))
128/*
129 * A bitmask of kernel/global capabilities that should be communicated
130 * to user level processes.
131 */
132#define HFI1_CAP_K2U (HFI1_CAP_SDMA | \
133 HFI1_CAP_EXTENDED_PSN | \
134 HFI1_CAP_PKEY_CHECK | \
135 HFI1_CAP_NO_INTEGRITY)
136
137#define HFI1_USER_SWVERSION ((HFI1_USER_SWMAJOR << HFI1_SWMAJOR_SHIFT) | \
138 HFI1_USER_SWMINOR)
139
140/*
141 * The next set of defines are for packet headers, and chip register
142 * and memory bits that are visible to and/or used by user-mode software.
143 */
144
145/*
146 * Receive Header Flags
147 */
148#define RHF_PKT_LEN_SHIFT 0
149#define RHF_PKT_LEN_MASK 0xfffull
150#define RHF_PKT_LEN_SMASK (RHF_PKT_LEN_MASK << RHF_PKT_LEN_SHIFT)
151
152#define RHF_RCV_TYPE_SHIFT 12
153#define RHF_RCV_TYPE_MASK 0x7ull
154#define RHF_RCV_TYPE_SMASK (RHF_RCV_TYPE_MASK << RHF_RCV_TYPE_SHIFT)
155
156#define RHF_USE_EGR_BFR_SHIFT 15
157#define RHF_USE_EGR_BFR_MASK 0x1ull
158#define RHF_USE_EGR_BFR_SMASK (RHF_USE_EGR_BFR_MASK << RHF_USE_EGR_BFR_SHIFT)
159
160#define RHF_EGR_INDEX_SHIFT 16
161#define RHF_EGR_INDEX_MASK 0x7ffull
162#define RHF_EGR_INDEX_SMASK (RHF_EGR_INDEX_MASK << RHF_EGR_INDEX_SHIFT)
163
164#define RHF_DC_INFO_SHIFT 27
165#define RHF_DC_INFO_MASK 0x1ull
166#define RHF_DC_INFO_SMASK (RHF_DC_INFO_MASK << RHF_DC_INFO_SHIFT)
167
168#define RHF_RCV_SEQ_SHIFT 28
169#define RHF_RCV_SEQ_MASK 0xfull
170#define RHF_RCV_SEQ_SMASK (RHF_RCV_SEQ_MASK << RHF_RCV_SEQ_SHIFT)
171
172#define RHF_EGR_OFFSET_SHIFT 32
173#define RHF_EGR_OFFSET_MASK 0xfffull
174#define RHF_EGR_OFFSET_SMASK (RHF_EGR_OFFSET_MASK << RHF_EGR_OFFSET_SHIFT)
175#define RHF_HDRQ_OFFSET_SHIFT 44
176#define RHF_HDRQ_OFFSET_MASK 0x1ffull
177#define RHF_HDRQ_OFFSET_SMASK (RHF_HDRQ_OFFSET_MASK << RHF_HDRQ_OFFSET_SHIFT)
178#define RHF_K_HDR_LEN_ERR (0x1ull << 53)
179#define RHF_DC_UNC_ERR (0x1ull << 54)
180#define RHF_DC_ERR (0x1ull << 55)
181#define RHF_RCV_TYPE_ERR_SHIFT 56
182#define RHF_RCV_TYPE_ERR_MASK 0x7ul
183#define RHF_RCV_TYPE_ERR_SMASK (RHF_RCV_TYPE_ERR_MASK << RHF_RCV_TYPE_ERR_SHIFT)
184#define RHF_TID_ERR (0x1ull << 59)
185#define RHF_LEN_ERR (0x1ull << 60)
186#define RHF_ECC_ERR (0x1ull << 61)
187#define RHF_RESERVED (0x1ull << 62)
188#define RHF_ICRC_ERR (0x1ull << 63)
189
190#define RHF_ERROR_SMASK 0xffe0000000000000ull /* bits 63:53 */
191
192/* RHF receive types */
193#define RHF_RCV_TYPE_EXPECTED 0
194#define RHF_RCV_TYPE_EAGER 1
195#define RHF_RCV_TYPE_IB 2 /* normal IB, IB Raw, or IPv6 */
196#define RHF_RCV_TYPE_ERROR 3
197#define RHF_RCV_TYPE_BYPASS 4
198#define RHF_RCV_TYPE_INVALID5 5
199#define RHF_RCV_TYPE_INVALID6 6
200#define RHF_RCV_TYPE_INVALID7 7
201
202/* RHF receive type error - expected packet errors */
203#define RHF_RTE_EXPECTED_FLOW_SEQ_ERR 0x2
204#define RHF_RTE_EXPECTED_FLOW_GEN_ERR 0x4
205
206/* RHF receive type error - eager packet errors */
207#define RHF_RTE_EAGER_NO_ERR 0x0
208
209/* RHF receive type error - IB packet errors */
210#define RHF_RTE_IB_NO_ERR 0x0
211
212/* RHF receive type error - error packet errors */
213#define RHF_RTE_ERROR_NO_ERR 0x0
214#define RHF_RTE_ERROR_OP_CODE_ERR 0x1
215#define RHF_RTE_ERROR_KHDR_MIN_LEN_ERR 0x2
216#define RHF_RTE_ERROR_KHDR_HCRC_ERR 0x3
217#define RHF_RTE_ERROR_KHDR_KVER_ERR 0x4
218#define RHF_RTE_ERROR_CONTEXT_ERR 0x5
219#define RHF_RTE_ERROR_KHDR_TID_ERR 0x6
220
221/* RHF receive type error - bypass packet errors */
222#define RHF_RTE_BYPASS_NO_ERR 0x0
223
224/* MAX RcvSEQ */
225#define RHF_MAX_SEQ 13
226
227/* IB - LRH header constants */
228#define HFI1_LRH_GRH 0x0003 /* 1. word of IB LRH - next header: GRH */
229#define HFI1_LRH_BTH 0x0002 /* 1. word of IB LRH - next header: BTH */
230
231/* misc. */
232#define SC15_PACKET 0xF
233#define SIZE_OF_CRC 1
234#define SIZE_OF_LT 1
235#define MAX_16B_PADDING 12 /* CRC = 4, LT = 1, Pad = 0 to 7 bytes */
236
237#define LIM_MGMT_P_KEY 0x7FFF
238#define FULL_MGMT_P_KEY 0xFFFF
239
240#define DEFAULT_P_KEY LIM_MGMT_P_KEY
241
242#define HFI1_PSM_IOC_BASE_SEQ 0x0
243
244/* Number of BTH.PSN bits used for sequence number in expected rcvs */
245#define HFI1_KDETH_BTH_SEQ_SHIFT 11
246#define HFI1_KDETH_BTH_SEQ_MASK (BIT(HFI1_KDETH_BTH_SEQ_SHIFT) - 1)
247
248static inline __u64 rhf_to_cpu(const __le32 *rbuf)
249{
250 return __le64_to_cpu(*((__le64 *)rbuf));
251}
252
253static inline u64 rhf_err_flags(u64 rhf)
254{
255 return rhf & RHF_ERROR_SMASK;
256}
257
258static inline u32 rhf_rcv_type(u64 rhf)
259{
260 return (rhf >> RHF_RCV_TYPE_SHIFT) & RHF_RCV_TYPE_MASK;
261}
262
263static inline u32 rhf_rcv_type_err(u64 rhf)
264{
265 return (rhf >> RHF_RCV_TYPE_ERR_SHIFT) & RHF_RCV_TYPE_ERR_MASK;
266}
267
268/* return size is in bytes, not DWORDs */
269static inline u32 rhf_pkt_len(u64 rhf)
270{
271 return ((rhf & RHF_PKT_LEN_SMASK) >> RHF_PKT_LEN_SHIFT) << 2;
272}
273
274static inline u32 rhf_egr_index(u64 rhf)
275{
276 return (rhf >> RHF_EGR_INDEX_SHIFT) & RHF_EGR_INDEX_MASK;
277}
278
279static inline u32 rhf_rcv_seq(u64 rhf)
280{
281 return (rhf >> RHF_RCV_SEQ_SHIFT) & RHF_RCV_SEQ_MASK;
282}
283
284/* returned offset is in DWORDS */
285static inline u32 rhf_hdrq_offset(u64 rhf)
286{
287 return (rhf >> RHF_HDRQ_OFFSET_SHIFT) & RHF_HDRQ_OFFSET_MASK;
288}
289
290static inline u64 rhf_use_egr_bfr(u64 rhf)
291{
292 return rhf & RHF_USE_EGR_BFR_SMASK;
293}
294
295static inline u64 rhf_dc_info(u64 rhf)
296{
297 return rhf & RHF_DC_INFO_SMASK;
298}
299
300static inline u32 rhf_egr_buf_offset(u64 rhf)
301{
302 return (rhf >> RHF_EGR_OFFSET_SHIFT) & RHF_EGR_OFFSET_MASK;
303}
304#endif /* _COMMON_H */
1/*
2 * Copyright(c) 2015 - 2018 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47
48#ifndef _COMMON_H
49#define _COMMON_H
50
51#include <rdma/hfi/hfi1_user.h>
52
53/*
54 * This file contains defines, structures, etc. that are used
55 * to communicate between kernel and user code.
56 */
57
58/* version of protocol header (known to chip also). In the long run,
59 * we should be able to generate and accept a range of version numbers;
60 * for now we only accept one, and it's compiled in.
61 */
62#define IPS_PROTO_VERSION 2
63
64/*
65 * These are compile time constants that you may want to enable or disable
66 * if you are trying to debug problems with code or performance.
67 * HFI1_VERBOSE_TRACING define as 1 if you want additional tracing in
68 * fast path code
69 * HFI1_TRACE_REGWRITES define as 1 if you want register writes to be
70 * traced in fast path code
71 * _HFI1_TRACING define as 0 if you want to remove all tracing in a
72 * compilation unit
73 */
74
75/*
76 * If a packet's QP[23:16] bits match this value, then it is
77 * a PSM packet and the hardware will expect a KDETH header
78 * following the BTH.
79 */
80#define DEFAULT_KDETH_QP 0x80
81
82/* driver/hw feature set bitmask */
83#define HFI1_CAP_USER_SHIFT 24
84#define HFI1_CAP_MASK ((1UL << HFI1_CAP_USER_SHIFT) - 1)
85/* locked flag - if set, only HFI1_CAP_WRITABLE_MASK bits can be set */
86#define HFI1_CAP_LOCKED_SHIFT 63
87#define HFI1_CAP_LOCKED_MASK 0x1ULL
88#define HFI1_CAP_LOCKED_SMASK (HFI1_CAP_LOCKED_MASK << HFI1_CAP_LOCKED_SHIFT)
89/* extra bits used between kernel and user processes */
90#define HFI1_CAP_MISC_SHIFT (HFI1_CAP_USER_SHIFT * 2)
91#define HFI1_CAP_MISC_MASK ((1ULL << (HFI1_CAP_LOCKED_SHIFT - \
92 HFI1_CAP_MISC_SHIFT)) - 1)
93
94#define HFI1_CAP_KSET(cap) ({ hfi1_cap_mask |= HFI1_CAP_##cap; hfi1_cap_mask; })
95#define HFI1_CAP_KCLEAR(cap) \
96 ({ \
97 hfi1_cap_mask &= ~HFI1_CAP_##cap; \
98 hfi1_cap_mask; \
99 })
100#define HFI1_CAP_USET(cap) \
101 ({ \
102 hfi1_cap_mask |= (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
103 hfi1_cap_mask; \
104 })
105#define HFI1_CAP_UCLEAR(cap) \
106 ({ \
107 hfi1_cap_mask &= ~(HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
108 hfi1_cap_mask; \
109 })
110#define HFI1_CAP_SET(cap) \
111 ({ \
112 hfi1_cap_mask |= (HFI1_CAP_##cap | (HFI1_CAP_##cap << \
113 HFI1_CAP_USER_SHIFT)); \
114 hfi1_cap_mask; \
115 })
116#define HFI1_CAP_CLEAR(cap) \
117 ({ \
118 hfi1_cap_mask &= ~(HFI1_CAP_##cap | \
119 (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT)); \
120 hfi1_cap_mask; \
121 })
122#define HFI1_CAP_LOCK() \
123 ({ hfi1_cap_mask |= HFI1_CAP_LOCKED_SMASK; hfi1_cap_mask; })
124#define HFI1_CAP_LOCKED() (!!(hfi1_cap_mask & HFI1_CAP_LOCKED_SMASK))
125/*
126 * The set of capability bits that can be changed after initial load
127 * This set is the same for kernel and user contexts. However, for
128 * user contexts, the set can be further filtered by using the
129 * HFI1_CAP_RESERVED_MASK bits.
130 */
131#define HFI1_CAP_WRITABLE_MASK (HFI1_CAP_SDMA_AHG | \
132 HFI1_CAP_HDRSUPP | \
133 HFI1_CAP_MULTI_PKT_EGR | \
134 HFI1_CAP_NODROP_RHQ_FULL | \
135 HFI1_CAP_NODROP_EGR_FULL | \
136 HFI1_CAP_ALLOW_PERM_JKEY | \
137 HFI1_CAP_STATIC_RATE_CTRL | \
138 HFI1_CAP_PRINT_UNIMPL | \
139 HFI1_CAP_TID_UNMAP | \
140 HFI1_CAP_OPFN)
141/*
142 * A set of capability bits that are "global" and are not allowed to be
143 * set in the user bitmask.
144 */
145#define HFI1_CAP_RESERVED_MASK ((HFI1_CAP_SDMA | \
146 HFI1_CAP_USE_SDMA_HEAD | \
147 HFI1_CAP_EXTENDED_PSN | \
148 HFI1_CAP_PRINT_UNIMPL | \
149 HFI1_CAP_NO_INTEGRITY | \
150 HFI1_CAP_PKEY_CHECK | \
151 HFI1_CAP_TID_RDMA | \
152 HFI1_CAP_OPFN) << \
153 HFI1_CAP_USER_SHIFT)
154/*
155 * Set of capabilities that need to be enabled for kernel context in
156 * order to be allowed for user contexts, as well.
157 */
158#define HFI1_CAP_MUST_HAVE_KERN (HFI1_CAP_STATIC_RATE_CTRL)
159/* Default enabled capabilities (both kernel and user) */
160#define HFI1_CAP_MASK_DEFAULT (HFI1_CAP_HDRSUPP | \
161 HFI1_CAP_NODROP_RHQ_FULL | \
162 HFI1_CAP_NODROP_EGR_FULL | \
163 HFI1_CAP_SDMA | \
164 HFI1_CAP_PRINT_UNIMPL | \
165 HFI1_CAP_STATIC_RATE_CTRL | \
166 HFI1_CAP_PKEY_CHECK | \
167 HFI1_CAP_MULTI_PKT_EGR | \
168 HFI1_CAP_EXTENDED_PSN | \
169 ((HFI1_CAP_HDRSUPP | \
170 HFI1_CAP_MULTI_PKT_EGR | \
171 HFI1_CAP_STATIC_RATE_CTRL | \
172 HFI1_CAP_PKEY_CHECK | \
173 HFI1_CAP_EARLY_CREDIT_RETURN) << \
174 HFI1_CAP_USER_SHIFT))
175/*
176 * A bitmask of kernel/global capabilities that should be communicated
177 * to user level processes.
178 */
179#define HFI1_CAP_K2U (HFI1_CAP_SDMA | \
180 HFI1_CAP_EXTENDED_PSN | \
181 HFI1_CAP_PKEY_CHECK | \
182 HFI1_CAP_NO_INTEGRITY)
183
184#define HFI1_USER_SWVERSION ((HFI1_USER_SWMAJOR << HFI1_SWMAJOR_SHIFT) | \
185 HFI1_USER_SWMINOR)
186
187#ifndef HFI1_KERN_TYPE
188#define HFI1_KERN_TYPE 0
189#endif
190
191/*
192 * Similarly, this is the kernel version going back to the user. It's
193 * slightly different, in that we want to tell if the driver was built as
194 * part of a Intel release, or from the driver from openfabrics.org,
195 * kernel.org, or a standard distribution, for support reasons.
196 * The high bit is 0 for non-Intel and 1 for Intel-built/supplied.
197 *
198 * It's returned by the driver to the user code during initialization in the
199 * spi_sw_version field of hfi1_base_info, so the user code can in turn
200 * check for compatibility with the kernel.
201*/
202#define HFI1_KERN_SWVERSION ((HFI1_KERN_TYPE << 31) | HFI1_USER_SWVERSION)
203
204/*
205 * Define the driver version number. This is something that refers only
206 * to the driver itself, not the software interfaces it supports.
207 */
208#ifndef HFI1_DRIVER_VERSION_BASE
209#define HFI1_DRIVER_VERSION_BASE "0.9-294"
210#endif
211
212/* create the final driver version string */
213#ifdef HFI1_IDSTR
214#define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE " " HFI1_IDSTR
215#else
216#define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE
217#endif
218
219/*
220 * Diagnostics can send a packet by writing the following
221 * struct to the diag packet special file.
222 *
223 * This allows a custom PBC qword, so that special modes and deliberate
224 * changes to CRCs can be used.
225 */
226#define _DIAG_PKT_VERS 1
227struct diag_pkt {
228 __u16 version; /* structure version */
229 __u16 unit; /* which device */
230 __u16 sw_index; /* send sw index to use */
231 __u16 len; /* data length, in bytes */
232 __u16 port; /* port number */
233 __u16 unused;
234 __u32 flags; /* call flags */
235 __u64 data; /* user data pointer */
236 __u64 pbc; /* PBC for the packet */
237};
238
239/* diag_pkt flags */
240#define F_DIAGPKT_WAIT 0x1 /* wait until packet is sent */
241
242/*
243 * The next set of defines are for packet headers, and chip register
244 * and memory bits that are visible to and/or used by user-mode software.
245 */
246
247/*
248 * Receive Header Flags
249 */
250#define RHF_PKT_LEN_SHIFT 0
251#define RHF_PKT_LEN_MASK 0xfffull
252#define RHF_PKT_LEN_SMASK (RHF_PKT_LEN_MASK << RHF_PKT_LEN_SHIFT)
253
254#define RHF_RCV_TYPE_SHIFT 12
255#define RHF_RCV_TYPE_MASK 0x7ull
256#define RHF_RCV_TYPE_SMASK (RHF_RCV_TYPE_MASK << RHF_RCV_TYPE_SHIFT)
257
258#define RHF_USE_EGR_BFR_SHIFT 15
259#define RHF_USE_EGR_BFR_MASK 0x1ull
260#define RHF_USE_EGR_BFR_SMASK (RHF_USE_EGR_BFR_MASK << RHF_USE_EGR_BFR_SHIFT)
261
262#define RHF_EGR_INDEX_SHIFT 16
263#define RHF_EGR_INDEX_MASK 0x7ffull
264#define RHF_EGR_INDEX_SMASK (RHF_EGR_INDEX_MASK << RHF_EGR_INDEX_SHIFT)
265
266#define RHF_DC_INFO_SHIFT 27
267#define RHF_DC_INFO_MASK 0x1ull
268#define RHF_DC_INFO_SMASK (RHF_DC_INFO_MASK << RHF_DC_INFO_SHIFT)
269
270#define RHF_RCV_SEQ_SHIFT 28
271#define RHF_RCV_SEQ_MASK 0xfull
272#define RHF_RCV_SEQ_SMASK (RHF_RCV_SEQ_MASK << RHF_RCV_SEQ_SHIFT)
273
274#define RHF_EGR_OFFSET_SHIFT 32
275#define RHF_EGR_OFFSET_MASK 0xfffull
276#define RHF_EGR_OFFSET_SMASK (RHF_EGR_OFFSET_MASK << RHF_EGR_OFFSET_SHIFT)
277#define RHF_HDRQ_OFFSET_SHIFT 44
278#define RHF_HDRQ_OFFSET_MASK 0x1ffull
279#define RHF_HDRQ_OFFSET_SMASK (RHF_HDRQ_OFFSET_MASK << RHF_HDRQ_OFFSET_SHIFT)
280#define RHF_K_HDR_LEN_ERR (0x1ull << 53)
281#define RHF_DC_UNC_ERR (0x1ull << 54)
282#define RHF_DC_ERR (0x1ull << 55)
283#define RHF_RCV_TYPE_ERR_SHIFT 56
284#define RHF_RCV_TYPE_ERR_MASK 0x7ul
285#define RHF_RCV_TYPE_ERR_SMASK (RHF_RCV_TYPE_ERR_MASK << RHF_RCV_TYPE_ERR_SHIFT)
286#define RHF_TID_ERR (0x1ull << 59)
287#define RHF_LEN_ERR (0x1ull << 60)
288#define RHF_ECC_ERR (0x1ull << 61)
289#define RHF_RESERVED (0x1ull << 62)
290#define RHF_ICRC_ERR (0x1ull << 63)
291
292#define RHF_ERROR_SMASK 0xffe0000000000000ull /* bits 63:53 */
293
294/* RHF receive types */
295#define RHF_RCV_TYPE_EXPECTED 0
296#define RHF_RCV_TYPE_EAGER 1
297#define RHF_RCV_TYPE_IB 2 /* normal IB, IB Raw, or IPv6 */
298#define RHF_RCV_TYPE_ERROR 3
299#define RHF_RCV_TYPE_BYPASS 4
300#define RHF_RCV_TYPE_INVALID5 5
301#define RHF_RCV_TYPE_INVALID6 6
302#define RHF_RCV_TYPE_INVALID7 7
303
304/* RHF receive type error - expected packet errors */
305#define RHF_RTE_EXPECTED_FLOW_SEQ_ERR 0x2
306#define RHF_RTE_EXPECTED_FLOW_GEN_ERR 0x4
307
308/* RHF receive type error - eager packet errors */
309#define RHF_RTE_EAGER_NO_ERR 0x0
310
311/* RHF receive type error - IB packet errors */
312#define RHF_RTE_IB_NO_ERR 0x0
313
314/* RHF receive type error - error packet errors */
315#define RHF_RTE_ERROR_NO_ERR 0x0
316#define RHF_RTE_ERROR_OP_CODE_ERR 0x1
317#define RHF_RTE_ERROR_KHDR_MIN_LEN_ERR 0x2
318#define RHF_RTE_ERROR_KHDR_HCRC_ERR 0x3
319#define RHF_RTE_ERROR_KHDR_KVER_ERR 0x4
320#define RHF_RTE_ERROR_CONTEXT_ERR 0x5
321#define RHF_RTE_ERROR_KHDR_TID_ERR 0x6
322
323/* RHF receive type error - bypass packet errors */
324#define RHF_RTE_BYPASS_NO_ERR 0x0
325
326/* IB - LRH header constants */
327#define HFI1_LRH_GRH 0x0003 /* 1. word of IB LRH - next header: GRH */
328#define HFI1_LRH_BTH 0x0002 /* 1. word of IB LRH - next header: BTH */
329
330/* misc. */
331#define SC15_PACKET 0xF
332#define SIZE_OF_CRC 1
333#define SIZE_OF_LT 1
334#define MAX_16B_PADDING 12 /* CRC = 4, LT = 1, Pad = 0 to 7 bytes */
335
336#define LIM_MGMT_P_KEY 0x7FFF
337#define FULL_MGMT_P_KEY 0xFFFF
338
339#define DEFAULT_P_KEY LIM_MGMT_P_KEY
340
341#define HFI1_PSM_IOC_BASE_SEQ 0x0
342
343/* Number of BTH.PSN bits used for sequence number in expected rcvs */
344#define HFI1_KDETH_BTH_SEQ_SHIFT 11
345#define HFI1_KDETH_BTH_SEQ_MASK (BIT(HFI1_KDETH_BTH_SEQ_SHIFT) - 1)
346
347static inline __u64 rhf_to_cpu(const __le32 *rbuf)
348{
349 return __le64_to_cpu(*((__le64 *)rbuf));
350}
351
352static inline u64 rhf_err_flags(u64 rhf)
353{
354 return rhf & RHF_ERROR_SMASK;
355}
356
357static inline u32 rhf_rcv_type(u64 rhf)
358{
359 return (rhf >> RHF_RCV_TYPE_SHIFT) & RHF_RCV_TYPE_MASK;
360}
361
362static inline u32 rhf_rcv_type_err(u64 rhf)
363{
364 return (rhf >> RHF_RCV_TYPE_ERR_SHIFT) & RHF_RCV_TYPE_ERR_MASK;
365}
366
367/* return size is in bytes, not DWORDs */
368static inline u32 rhf_pkt_len(u64 rhf)
369{
370 return ((rhf & RHF_PKT_LEN_SMASK) >> RHF_PKT_LEN_SHIFT) << 2;
371}
372
373static inline u32 rhf_egr_index(u64 rhf)
374{
375 return (rhf >> RHF_EGR_INDEX_SHIFT) & RHF_EGR_INDEX_MASK;
376}
377
378static inline u32 rhf_rcv_seq(u64 rhf)
379{
380 return (rhf >> RHF_RCV_SEQ_SHIFT) & RHF_RCV_SEQ_MASK;
381}
382
383/* returned offset is in DWORDS */
384static inline u32 rhf_hdrq_offset(u64 rhf)
385{
386 return (rhf >> RHF_HDRQ_OFFSET_SHIFT) & RHF_HDRQ_OFFSET_MASK;
387}
388
389static inline u64 rhf_use_egr_bfr(u64 rhf)
390{
391 return rhf & RHF_USE_EGR_BFR_SMASK;
392}
393
394static inline u64 rhf_dc_info(u64 rhf)
395{
396 return rhf & RHF_DC_INFO_SMASK;
397}
398
399static inline u32 rhf_egr_buf_offset(u64 rhf)
400{
401 return (rhf >> RHF_EGR_OFFSET_SHIFT) & RHF_EGR_OFFSET_MASK;
402}
403#endif /* _COMMON_H */