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1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Dave Airlie
30 */
31#include <linux/seq_file.h>
32#include <linux/atomic.h>
33#include <linux/wait.h>
34#include <linux/kref.h>
35#include <linux/slab.h>
36#include <linux/firmware.h>
37#include <linux/pm_runtime.h>
38
39#include <drm/drm_drv.h>
40#include "amdgpu.h"
41#include "amdgpu_trace.h"
42#include "amdgpu_reset.h"
43
44/*
45 * Fences mark an event in the GPUs pipeline and are used
46 * for GPU/CPU synchronization. When the fence is written,
47 * it is expected that all buffers associated with that fence
48 * are no longer in use by the associated ring on the GPU and
49 * that the relevant GPU caches have been flushed.
50 */
51
52struct amdgpu_fence {
53 struct dma_fence base;
54
55 /* RB, DMA, etc. */
56 struct amdgpu_ring *ring;
57 ktime_t start_timestamp;
58};
59
60static struct kmem_cache *amdgpu_fence_slab;
61
62int amdgpu_fence_slab_init(void)
63{
64 amdgpu_fence_slab = kmem_cache_create(
65 "amdgpu_fence", sizeof(struct amdgpu_fence), 0,
66 SLAB_HWCACHE_ALIGN, NULL);
67 if (!amdgpu_fence_slab)
68 return -ENOMEM;
69 return 0;
70}
71
72void amdgpu_fence_slab_fini(void)
73{
74 rcu_barrier();
75 kmem_cache_destroy(amdgpu_fence_slab);
76}
77/*
78 * Cast helper
79 */
80static const struct dma_fence_ops amdgpu_fence_ops;
81static const struct dma_fence_ops amdgpu_job_fence_ops;
82static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f)
83{
84 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
85
86 if (__f->base.ops == &amdgpu_fence_ops ||
87 __f->base.ops == &amdgpu_job_fence_ops)
88 return __f;
89
90 return NULL;
91}
92
93/**
94 * amdgpu_fence_write - write a fence value
95 *
96 * @ring: ring the fence is associated with
97 * @seq: sequence number to write
98 *
99 * Writes a fence value to memory (all asics).
100 */
101static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
102{
103 struct amdgpu_fence_driver *drv = &ring->fence_drv;
104
105 if (drv->cpu_addr)
106 *drv->cpu_addr = cpu_to_le32(seq);
107}
108
109/**
110 * amdgpu_fence_read - read a fence value
111 *
112 * @ring: ring the fence is associated with
113 *
114 * Reads a fence value from memory (all asics).
115 * Returns the value of the fence read from memory.
116 */
117static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
118{
119 struct amdgpu_fence_driver *drv = &ring->fence_drv;
120 u32 seq = 0;
121
122 if (drv->cpu_addr)
123 seq = le32_to_cpu(*drv->cpu_addr);
124 else
125 seq = atomic_read(&drv->last_seq);
126
127 return seq;
128}
129
130/**
131 * amdgpu_fence_emit - emit a fence on the requested ring
132 *
133 * @ring: ring the fence is associated with
134 * @f: resulting fence object
135 * @job: job the fence is embedded in
136 * @flags: flags to pass into the subordinate .emit_fence() call
137 *
138 * Emits a fence command on the requested ring (all asics).
139 * Returns 0 on success, -ENOMEM on failure.
140 */
141int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, struct amdgpu_job *job,
142 unsigned int flags)
143{
144 struct amdgpu_device *adev = ring->adev;
145 struct dma_fence *fence;
146 struct amdgpu_fence *am_fence;
147 struct dma_fence __rcu **ptr;
148 uint32_t seq;
149 int r;
150
151 if (job == NULL) {
152 /* create a sperate hw fence */
153 am_fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_ATOMIC);
154 if (am_fence == NULL)
155 return -ENOMEM;
156 fence = &am_fence->base;
157 am_fence->ring = ring;
158 } else {
159 /* take use of job-embedded fence */
160 fence = &job->hw_fence;
161 }
162
163 seq = ++ring->fence_drv.sync_seq;
164 if (job && job->job_run_counter) {
165 /* reinit seq for resubmitted jobs */
166 fence->seqno = seq;
167 /* TO be inline with external fence creation and other drivers */
168 dma_fence_get(fence);
169 } else {
170 if (job) {
171 dma_fence_init(fence, &amdgpu_job_fence_ops,
172 &ring->fence_drv.lock,
173 adev->fence_context + ring->idx, seq);
174 /* Against remove in amdgpu_job_{free, free_cb} */
175 dma_fence_get(fence);
176 } else {
177 dma_fence_init(fence, &amdgpu_fence_ops,
178 &ring->fence_drv.lock,
179 adev->fence_context + ring->idx, seq);
180 }
181 }
182
183 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
184 seq, flags | AMDGPU_FENCE_FLAG_INT);
185 pm_runtime_get_noresume(adev_to_drm(adev)->dev);
186 trace_amdgpu_runpm_reference_dumps(1, __func__);
187 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
188 if (unlikely(rcu_dereference_protected(*ptr, 1))) {
189 struct dma_fence *old;
190
191 rcu_read_lock();
192 old = dma_fence_get_rcu_safe(ptr);
193 rcu_read_unlock();
194
195 if (old) {
196 r = dma_fence_wait(old, false);
197 dma_fence_put(old);
198 if (r)
199 return r;
200 }
201 }
202
203 to_amdgpu_fence(fence)->start_timestamp = ktime_get();
204
205 /* This function can't be called concurrently anyway, otherwise
206 * emitting the fence would mess up the hardware ring buffer.
207 */
208 rcu_assign_pointer(*ptr, dma_fence_get(fence));
209
210 *f = fence;
211
212 return 0;
213}
214
215/**
216 * amdgpu_fence_emit_polling - emit a fence on the requeste ring
217 *
218 * @ring: ring the fence is associated with
219 * @s: resulting sequence number
220 * @timeout: the timeout for waiting in usecs
221 *
222 * Emits a fence command on the requested ring (all asics).
223 * Used For polling fence.
224 * Returns 0 on success, -ENOMEM on failure.
225 */
226int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
227 uint32_t timeout)
228{
229 uint32_t seq;
230 signed long r;
231
232 if (!s)
233 return -EINVAL;
234
235 seq = ++ring->fence_drv.sync_seq;
236 r = amdgpu_fence_wait_polling(ring,
237 seq - ring->fence_drv.num_fences_mask,
238 timeout);
239 if (r < 1)
240 return -ETIMEDOUT;
241
242 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
243 seq, 0);
244
245 *s = seq;
246
247 return 0;
248}
249
250/**
251 * amdgpu_fence_schedule_fallback - schedule fallback check
252 *
253 * @ring: pointer to struct amdgpu_ring
254 *
255 * Start a timer as fallback to our interrupts.
256 */
257static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
258{
259 mod_timer(&ring->fence_drv.fallback_timer,
260 jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT);
261}
262
263/**
264 * amdgpu_fence_process - check for fence activity
265 *
266 * @ring: pointer to struct amdgpu_ring
267 *
268 * Checks the current fence value and calculates the last
269 * signalled fence value. Wakes the fence queue if the
270 * sequence number has increased.
271 *
272 * Returns true if fence was processed
273 */
274bool amdgpu_fence_process(struct amdgpu_ring *ring)
275{
276 struct amdgpu_fence_driver *drv = &ring->fence_drv;
277 struct amdgpu_device *adev = ring->adev;
278 uint32_t seq, last_seq;
279
280 do {
281 last_seq = atomic_read(&ring->fence_drv.last_seq);
282 seq = amdgpu_fence_read(ring);
283
284 } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
285
286 if (del_timer(&ring->fence_drv.fallback_timer) &&
287 seq != ring->fence_drv.sync_seq)
288 amdgpu_fence_schedule_fallback(ring);
289
290 if (unlikely(seq == last_seq))
291 return false;
292
293 last_seq &= drv->num_fences_mask;
294 seq &= drv->num_fences_mask;
295
296 do {
297 struct dma_fence *fence, **ptr;
298
299 ++last_seq;
300 last_seq &= drv->num_fences_mask;
301 ptr = &drv->fences[last_seq];
302
303 /* There is always exactly one thread signaling this fence slot */
304 fence = rcu_dereference_protected(*ptr, 1);
305 RCU_INIT_POINTER(*ptr, NULL);
306
307 if (!fence)
308 continue;
309
310 dma_fence_signal(fence);
311 dma_fence_put(fence);
312 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
313 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
314 trace_amdgpu_runpm_reference_dumps(0, __func__);
315 } while (last_seq != seq);
316
317 return true;
318}
319
320/**
321 * amdgpu_fence_fallback - fallback for hardware interrupts
322 *
323 * @t: timer context used to obtain the pointer to ring structure
324 *
325 * Checks for fence activity.
326 */
327static void amdgpu_fence_fallback(struct timer_list *t)
328{
329 struct amdgpu_ring *ring = from_timer(ring, t,
330 fence_drv.fallback_timer);
331
332 if (amdgpu_fence_process(ring))
333 DRM_WARN("Fence fallback timer expired on ring %s\n", ring->name);
334}
335
336/**
337 * amdgpu_fence_wait_empty - wait for all fences to signal
338 *
339 * @ring: ring index the fence is associated with
340 *
341 * Wait for all fences on the requested ring to signal (all asics).
342 * Returns 0 if the fences have passed, error for all other cases.
343 */
344int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
345{
346 uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq);
347 struct dma_fence *fence, **ptr;
348 int r;
349
350 if (!seq)
351 return 0;
352
353 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
354 rcu_read_lock();
355 fence = rcu_dereference(*ptr);
356 if (!fence || !dma_fence_get_rcu(fence)) {
357 rcu_read_unlock();
358 return 0;
359 }
360 rcu_read_unlock();
361
362 r = dma_fence_wait(fence, false);
363 dma_fence_put(fence);
364 return r;
365}
366
367/**
368 * amdgpu_fence_wait_polling - busy wait for givn sequence number
369 *
370 * @ring: ring index the fence is associated with
371 * @wait_seq: sequence number to wait
372 * @timeout: the timeout for waiting in usecs
373 *
374 * Wait for all fences on the requested ring to signal (all asics).
375 * Returns left time if no timeout, 0 or minus if timeout.
376 */
377signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
378 uint32_t wait_seq,
379 signed long timeout)
380{
381
382 while ((int32_t)(wait_seq - amdgpu_fence_read(ring)) > 0 && timeout > 0) {
383 udelay(2);
384 timeout -= 2;
385 }
386 return timeout > 0 ? timeout : 0;
387}
388/**
389 * amdgpu_fence_count_emitted - get the count of emitted fences
390 *
391 * @ring: ring the fence is associated with
392 *
393 * Get the number of fences emitted on the requested ring (all asics).
394 * Returns the number of emitted fences on the ring. Used by the
395 * dynpm code to ring track activity.
396 */
397unsigned int amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
398{
399 uint64_t emitted;
400
401 /* We are not protected by ring lock when reading the last sequence
402 * but it's ok to report slightly wrong fence count here.
403 */
404 emitted = 0x100000000ull;
405 emitted -= atomic_read(&ring->fence_drv.last_seq);
406 emitted += READ_ONCE(ring->fence_drv.sync_seq);
407 return lower_32_bits(emitted);
408}
409
410/**
411 * amdgpu_fence_last_unsignaled_time_us - the time fence emitted until now
412 * @ring: ring the fence is associated with
413 *
414 * Find the earliest fence unsignaled until now, calculate the time delta
415 * between the time fence emitted and now.
416 */
417u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring)
418{
419 struct amdgpu_fence_driver *drv = &ring->fence_drv;
420 struct dma_fence *fence;
421 uint32_t last_seq, sync_seq;
422
423 last_seq = atomic_read(&ring->fence_drv.last_seq);
424 sync_seq = READ_ONCE(ring->fence_drv.sync_seq);
425 if (last_seq == sync_seq)
426 return 0;
427
428 ++last_seq;
429 last_seq &= drv->num_fences_mask;
430 fence = drv->fences[last_seq];
431 if (!fence)
432 return 0;
433
434 return ktime_us_delta(ktime_get(),
435 to_amdgpu_fence(fence)->start_timestamp);
436}
437
438/**
439 * amdgpu_fence_update_start_timestamp - update the timestamp of the fence
440 * @ring: ring the fence is associated with
441 * @seq: the fence seq number to update.
442 * @timestamp: the start timestamp to update.
443 *
444 * The function called at the time the fence and related ib is about to
445 * resubmit to gpu in MCBP scenario. Thus we do not consider race condition
446 * with amdgpu_fence_process to modify the same fence.
447 */
448void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq, ktime_t timestamp)
449{
450 struct amdgpu_fence_driver *drv = &ring->fence_drv;
451 struct dma_fence *fence;
452
453 seq &= drv->num_fences_mask;
454 fence = drv->fences[seq];
455 if (!fence)
456 return;
457
458 to_amdgpu_fence(fence)->start_timestamp = timestamp;
459}
460
461/**
462 * amdgpu_fence_driver_start_ring - make the fence driver
463 * ready for use on the requested ring.
464 *
465 * @ring: ring to start the fence driver on
466 * @irq_src: interrupt source to use for this ring
467 * @irq_type: interrupt type to use for this ring
468 *
469 * Make the fence driver ready for processing (all asics).
470 * Not all asics have all rings, so each asic will only
471 * start the fence driver on the rings it has.
472 * Returns 0 for success, errors for failure.
473 */
474int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
475 struct amdgpu_irq_src *irq_src,
476 unsigned int irq_type)
477{
478 struct amdgpu_device *adev = ring->adev;
479 uint64_t index;
480
481 if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) {
482 ring->fence_drv.cpu_addr = ring->fence_cpu_addr;
483 ring->fence_drv.gpu_addr = ring->fence_gpu_addr;
484 } else {
485 /* put fence directly behind firmware */
486 index = ALIGN(adev->uvd.fw->size, 8);
487 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index;
488 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;
489 }
490 amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
491
492 ring->fence_drv.irq_src = irq_src;
493 ring->fence_drv.irq_type = irq_type;
494 ring->fence_drv.initialized = true;
495
496 DRM_DEV_DEBUG(adev->dev, "fence driver on ring %s use gpu addr 0x%016llx\n",
497 ring->name, ring->fence_drv.gpu_addr);
498 return 0;
499}
500
501/**
502 * amdgpu_fence_driver_init_ring - init the fence driver
503 * for the requested ring.
504 *
505 * @ring: ring to init the fence driver on
506 *
507 * Init the fence driver for the requested ring (all asics).
508 * Helper function for amdgpu_fence_driver_init().
509 */
510int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
511{
512 struct amdgpu_device *adev = ring->adev;
513
514 if (!adev)
515 return -EINVAL;
516
517 if (!is_power_of_2(ring->num_hw_submission))
518 return -EINVAL;
519
520 ring->fence_drv.cpu_addr = NULL;
521 ring->fence_drv.gpu_addr = 0;
522 ring->fence_drv.sync_seq = 0;
523 atomic_set(&ring->fence_drv.last_seq, 0);
524 ring->fence_drv.initialized = false;
525
526 timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0);
527
528 ring->fence_drv.num_fences_mask = ring->num_hw_submission * 2 - 1;
529 spin_lock_init(&ring->fence_drv.lock);
530 ring->fence_drv.fences = kcalloc(ring->num_hw_submission * 2, sizeof(void *),
531 GFP_KERNEL);
532
533 if (!ring->fence_drv.fences)
534 return -ENOMEM;
535
536 return 0;
537}
538
539/**
540 * amdgpu_fence_driver_sw_init - init the fence driver
541 * for all possible rings.
542 *
543 * @adev: amdgpu device pointer
544 *
545 * Init the fence driver for all possible rings (all asics).
546 * Not all asics have all rings, so each asic will only
547 * start the fence driver on the rings it has using
548 * amdgpu_fence_driver_start_ring().
549 * Returns 0 for success.
550 */
551int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev)
552{
553 return 0;
554}
555
556/**
557 * amdgpu_fence_need_ring_interrupt_restore - helper function to check whether
558 * fence driver interrupts need to be restored.
559 *
560 * @ring: ring that to be checked
561 *
562 * Interrupts for rings that belong to GFX IP don't need to be restored
563 * when the target power state is s0ix.
564 *
565 * Return true if need to restore interrupts, false otherwise.
566 */
567static bool amdgpu_fence_need_ring_interrupt_restore(struct amdgpu_ring *ring)
568{
569 struct amdgpu_device *adev = ring->adev;
570 bool is_gfx_power_domain = false;
571
572 switch (ring->funcs->type) {
573 case AMDGPU_RING_TYPE_SDMA:
574 /* SDMA 5.x+ is part of GFX power domain so it's covered by GFXOFF */
575 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >=
576 IP_VERSION(5, 0, 0))
577 is_gfx_power_domain = true;
578 break;
579 case AMDGPU_RING_TYPE_GFX:
580 case AMDGPU_RING_TYPE_COMPUTE:
581 case AMDGPU_RING_TYPE_KIQ:
582 case AMDGPU_RING_TYPE_MES:
583 is_gfx_power_domain = true;
584 break;
585 default:
586 break;
587 }
588
589 return !(adev->in_s0ix && is_gfx_power_domain);
590}
591
592/**
593 * amdgpu_fence_driver_hw_fini - tear down the fence driver
594 * for all possible rings.
595 *
596 * @adev: amdgpu device pointer
597 *
598 * Tear down the fence driver for all possible rings (all asics).
599 */
600void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev)
601{
602 int i, r;
603
604 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
605 struct amdgpu_ring *ring = adev->rings[i];
606
607 if (!ring || !ring->fence_drv.initialized)
608 continue;
609
610 /* You can't wait for HW to signal if it's gone */
611 if (!drm_dev_is_unplugged(adev_to_drm(adev)))
612 r = amdgpu_fence_wait_empty(ring);
613 else
614 r = -ENODEV;
615 /* no need to trigger GPU reset as we are unloading */
616 if (r)
617 amdgpu_fence_driver_force_completion(ring);
618
619 if (!drm_dev_is_unplugged(adev_to_drm(adev)) &&
620 ring->fence_drv.irq_src &&
621 amdgpu_fence_need_ring_interrupt_restore(ring))
622 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
623 ring->fence_drv.irq_type);
624
625 del_timer_sync(&ring->fence_drv.fallback_timer);
626 }
627}
628
629/* Will either stop and flush handlers for amdgpu interrupt or reanble it */
630void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop)
631{
632 int i;
633
634 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
635 struct amdgpu_ring *ring = adev->rings[i];
636
637 if (!ring || !ring->fence_drv.initialized || !ring->fence_drv.irq_src)
638 continue;
639
640 if (stop)
641 disable_irq(adev->irq.irq);
642 else
643 enable_irq(adev->irq.irq);
644 }
645}
646
647void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev)
648{
649 unsigned int i, j;
650
651 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
652 struct amdgpu_ring *ring = adev->rings[i];
653
654 if (!ring || !ring->fence_drv.initialized)
655 continue;
656
657 /*
658 * Notice we check for sched.ops since there's some
659 * override on the meaning of sched.ready by amdgpu.
660 * The natural check would be sched.ready, which is
661 * set as drm_sched_init() finishes...
662 */
663 if (ring->sched.ops)
664 drm_sched_fini(&ring->sched);
665
666 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
667 dma_fence_put(ring->fence_drv.fences[j]);
668 kfree(ring->fence_drv.fences);
669 ring->fence_drv.fences = NULL;
670 ring->fence_drv.initialized = false;
671 }
672}
673
674/**
675 * amdgpu_fence_driver_hw_init - enable the fence driver
676 * for all possible rings.
677 *
678 * @adev: amdgpu device pointer
679 *
680 * Enable the fence driver for all possible rings (all asics).
681 * Not all asics have all rings, so each asic will only
682 * start the fence driver on the rings it has using
683 * amdgpu_fence_driver_start_ring().
684 * Returns 0 for success.
685 */
686void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev)
687{
688 int i;
689
690 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
691 struct amdgpu_ring *ring = adev->rings[i];
692
693 if (!ring || !ring->fence_drv.initialized)
694 continue;
695
696 /* enable the interrupt */
697 if (ring->fence_drv.irq_src &&
698 amdgpu_fence_need_ring_interrupt_restore(ring))
699 amdgpu_irq_get(adev, ring->fence_drv.irq_src,
700 ring->fence_drv.irq_type);
701 }
702}
703
704/**
705 * amdgpu_fence_driver_clear_job_fences - clear job embedded fences of ring
706 *
707 * @ring: fence of the ring to be cleared
708 *
709 */
710void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring)
711{
712 int i;
713 struct dma_fence *old, **ptr;
714
715 for (i = 0; i <= ring->fence_drv.num_fences_mask; i++) {
716 ptr = &ring->fence_drv.fences[i];
717 old = rcu_dereference_protected(*ptr, 1);
718 if (old && old->ops == &amdgpu_job_fence_ops) {
719 struct amdgpu_job *job;
720
721 /* For non-scheduler bad job, i.e. failed ib test, we need to signal
722 * it right here or we won't be able to track them in fence_drv
723 * and they will remain unsignaled during sa_bo free.
724 */
725 job = container_of(old, struct amdgpu_job, hw_fence);
726 if (!job->base.s_fence && !dma_fence_is_signaled(old))
727 dma_fence_signal(old);
728 RCU_INIT_POINTER(*ptr, NULL);
729 dma_fence_put(old);
730 }
731 }
732}
733
734/**
735 * amdgpu_fence_driver_set_error - set error code on fences
736 * @ring: the ring which contains the fences
737 * @error: the error code to set
738 *
739 * Set an error code to all the fences pending on the ring.
740 */
741void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error)
742{
743 struct amdgpu_fence_driver *drv = &ring->fence_drv;
744 unsigned long flags;
745
746 spin_lock_irqsave(&drv->lock, flags);
747 for (unsigned int i = 0; i <= drv->num_fences_mask; ++i) {
748 struct dma_fence *fence;
749
750 fence = rcu_dereference_protected(drv->fences[i],
751 lockdep_is_held(&drv->lock));
752 if (fence && !dma_fence_is_signaled_locked(fence))
753 dma_fence_set_error(fence, error);
754 }
755 spin_unlock_irqrestore(&drv->lock, flags);
756}
757
758/**
759 * amdgpu_fence_driver_force_completion - force signal latest fence of ring
760 *
761 * @ring: fence of the ring to signal
762 *
763 */
764void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
765{
766 amdgpu_fence_driver_set_error(ring, -ECANCELED);
767 amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
768 amdgpu_fence_process(ring);
769}
770
771/*
772 * Common fence implementation
773 */
774
775static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence)
776{
777 return "amdgpu";
778}
779
780static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)
781{
782 return (const char *)to_amdgpu_fence(f)->ring->name;
783}
784
785static const char *amdgpu_job_fence_get_timeline_name(struct dma_fence *f)
786{
787 struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
788
789 return (const char *)to_amdgpu_ring(job->base.sched)->name;
790}
791
792/**
793 * amdgpu_fence_enable_signaling - enable signalling on fence
794 * @f: fence
795 *
796 * This function is called with fence_queue lock held, and adds a callback
797 * to fence_queue that checks if this fence is signaled, and if so it
798 * signals the fence and removes itself.
799 */
800static bool amdgpu_fence_enable_signaling(struct dma_fence *f)
801{
802 if (!timer_pending(&to_amdgpu_fence(f)->ring->fence_drv.fallback_timer))
803 amdgpu_fence_schedule_fallback(to_amdgpu_fence(f)->ring);
804
805 return true;
806}
807
808/**
809 * amdgpu_job_fence_enable_signaling - enable signalling on job fence
810 * @f: fence
811 *
812 * This is the simliar function with amdgpu_fence_enable_signaling above, it
813 * only handles the job embedded fence.
814 */
815static bool amdgpu_job_fence_enable_signaling(struct dma_fence *f)
816{
817 struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
818
819 if (!timer_pending(&to_amdgpu_ring(job->base.sched)->fence_drv.fallback_timer))
820 amdgpu_fence_schedule_fallback(to_amdgpu_ring(job->base.sched));
821
822 return true;
823}
824
825/**
826 * amdgpu_fence_free - free up the fence memory
827 *
828 * @rcu: RCU callback head
829 *
830 * Free up the fence memory after the RCU grace period.
831 */
832static void amdgpu_fence_free(struct rcu_head *rcu)
833{
834 struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
835
836 /* free fence_slab if it's separated fence*/
837 kmem_cache_free(amdgpu_fence_slab, to_amdgpu_fence(f));
838}
839
840/**
841 * amdgpu_job_fence_free - free up the job with embedded fence
842 *
843 * @rcu: RCU callback head
844 *
845 * Free up the job with embedded fence after the RCU grace period.
846 */
847static void amdgpu_job_fence_free(struct rcu_head *rcu)
848{
849 struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
850
851 /* free job if fence has a parent job */
852 kfree(container_of(f, struct amdgpu_job, hw_fence));
853}
854
855/**
856 * amdgpu_fence_release - callback that fence can be freed
857 *
858 * @f: fence
859 *
860 * This function is called when the reference count becomes zero.
861 * It just RCU schedules freeing up the fence.
862 */
863static void amdgpu_fence_release(struct dma_fence *f)
864{
865 call_rcu(&f->rcu, amdgpu_fence_free);
866}
867
868/**
869 * amdgpu_job_fence_release - callback that job embedded fence can be freed
870 *
871 * @f: fence
872 *
873 * This is the simliar function with amdgpu_fence_release above, it
874 * only handles the job embedded fence.
875 */
876static void amdgpu_job_fence_release(struct dma_fence *f)
877{
878 call_rcu(&f->rcu, amdgpu_job_fence_free);
879}
880
881static const struct dma_fence_ops amdgpu_fence_ops = {
882 .get_driver_name = amdgpu_fence_get_driver_name,
883 .get_timeline_name = amdgpu_fence_get_timeline_name,
884 .enable_signaling = amdgpu_fence_enable_signaling,
885 .release = amdgpu_fence_release,
886};
887
888static const struct dma_fence_ops amdgpu_job_fence_ops = {
889 .get_driver_name = amdgpu_fence_get_driver_name,
890 .get_timeline_name = amdgpu_job_fence_get_timeline_name,
891 .enable_signaling = amdgpu_job_fence_enable_signaling,
892 .release = amdgpu_job_fence_release,
893};
894
895/*
896 * Fence debugfs
897 */
898#if defined(CONFIG_DEBUG_FS)
899static int amdgpu_debugfs_fence_info_show(struct seq_file *m, void *unused)
900{
901 struct amdgpu_device *adev = m->private;
902 int i;
903
904 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
905 struct amdgpu_ring *ring = adev->rings[i];
906
907 if (!ring || !ring->fence_drv.initialized)
908 continue;
909
910 amdgpu_fence_process(ring);
911
912 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
913 seq_printf(m, "Last signaled fence 0x%08x\n",
914 atomic_read(&ring->fence_drv.last_seq));
915 seq_printf(m, "Last emitted 0x%08x\n",
916 ring->fence_drv.sync_seq);
917
918 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX ||
919 ring->funcs->type == AMDGPU_RING_TYPE_SDMA) {
920 seq_printf(m, "Last signaled trailing fence 0x%08x\n",
921 le32_to_cpu(*ring->trail_fence_cpu_addr));
922 seq_printf(m, "Last emitted 0x%08x\n",
923 ring->trail_seq);
924 }
925
926 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
927 continue;
928
929 /* set in CP_VMID_PREEMPT and preemption occurred */
930 seq_printf(m, "Last preempted 0x%08x\n",
931 le32_to_cpu(*(ring->fence_drv.cpu_addr + 2)));
932 /* set in CP_VMID_RESET and reset occurred */
933 seq_printf(m, "Last reset 0x%08x\n",
934 le32_to_cpu(*(ring->fence_drv.cpu_addr + 4)));
935 /* Both preemption and reset occurred */
936 seq_printf(m, "Last both 0x%08x\n",
937 le32_to_cpu(*(ring->fence_drv.cpu_addr + 6)));
938 }
939 return 0;
940}
941
942/*
943 * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover
944 *
945 * Manually trigger a gpu reset at the next fence wait.
946 */
947static int gpu_recover_get(void *data, u64 *val)
948{
949 struct amdgpu_device *adev = (struct amdgpu_device *)data;
950 struct drm_device *dev = adev_to_drm(adev);
951 int r;
952
953 r = pm_runtime_get_sync(dev->dev);
954 if (r < 0) {
955 pm_runtime_put_autosuspend(dev->dev);
956 return 0;
957 }
958
959 if (amdgpu_reset_domain_schedule(adev->reset_domain, &adev->reset_work))
960 flush_work(&adev->reset_work);
961
962 *val = atomic_read(&adev->reset_domain->reset_res);
963
964 pm_runtime_mark_last_busy(dev->dev);
965 pm_runtime_put_autosuspend(dev->dev);
966
967 return 0;
968}
969
970DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_fence_info);
971DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gpu_recover_fops, gpu_recover_get, NULL,
972 "%lld\n");
973
974static void amdgpu_debugfs_reset_work(struct work_struct *work)
975{
976 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
977 reset_work);
978
979 struct amdgpu_reset_context reset_context;
980
981 memset(&reset_context, 0, sizeof(reset_context));
982
983 reset_context.method = AMD_RESET_METHOD_NONE;
984 reset_context.reset_req_dev = adev;
985 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
986
987 amdgpu_device_gpu_recover(adev, NULL, &reset_context);
988}
989
990#endif
991
992void amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
993{
994#if defined(CONFIG_DEBUG_FS)
995 struct drm_minor *minor = adev_to_drm(adev)->primary;
996 struct dentry *root = minor->debugfs_root;
997
998 debugfs_create_file("amdgpu_fence_info", 0444, root, adev,
999 &amdgpu_debugfs_fence_info_fops);
1000
1001 if (!amdgpu_sriov_vf(adev)) {
1002
1003 INIT_WORK(&adev->reset_work, amdgpu_debugfs_reset_work);
1004 debugfs_create_file("amdgpu_gpu_recover", 0444, root, adev,
1005 &amdgpu_debugfs_gpu_recover_fops);
1006 }
1007#endif
1008}
1009
1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Dave Airlie
30 */
31#include <linux/seq_file.h>
32#include <linux/atomic.h>
33#include <linux/wait.h>
34#include <linux/kref.h>
35#include <linux/slab.h>
36#include <linux/firmware.h>
37
38#include <drm/drm_debugfs.h>
39
40#include "amdgpu.h"
41#include "amdgpu_trace.h"
42
43/*
44 * Fences
45 * Fences mark an event in the GPUs pipeline and are used
46 * for GPU/CPU synchronization. When the fence is written,
47 * it is expected that all buffers associated with that fence
48 * are no longer in use by the associated ring on the GPU and
49 * that the the relevant GPU caches have been flushed.
50 */
51
52struct amdgpu_fence {
53 struct dma_fence base;
54
55 /* RB, DMA, etc. */
56 struct amdgpu_ring *ring;
57};
58
59static struct kmem_cache *amdgpu_fence_slab;
60
61int amdgpu_fence_slab_init(void)
62{
63 amdgpu_fence_slab = kmem_cache_create(
64 "amdgpu_fence", sizeof(struct amdgpu_fence), 0,
65 SLAB_HWCACHE_ALIGN, NULL);
66 if (!amdgpu_fence_slab)
67 return -ENOMEM;
68 return 0;
69}
70
71void amdgpu_fence_slab_fini(void)
72{
73 rcu_barrier();
74 kmem_cache_destroy(amdgpu_fence_slab);
75}
76/*
77 * Cast helper
78 */
79static const struct dma_fence_ops amdgpu_fence_ops;
80static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f)
81{
82 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
83
84 if (__f->base.ops == &amdgpu_fence_ops)
85 return __f;
86
87 return NULL;
88}
89
90/**
91 * amdgpu_fence_write - write a fence value
92 *
93 * @ring: ring the fence is associated with
94 * @seq: sequence number to write
95 *
96 * Writes a fence value to memory (all asics).
97 */
98static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
99{
100 struct amdgpu_fence_driver *drv = &ring->fence_drv;
101
102 if (drv->cpu_addr)
103 *drv->cpu_addr = cpu_to_le32(seq);
104}
105
106/**
107 * amdgpu_fence_read - read a fence value
108 *
109 * @ring: ring the fence is associated with
110 *
111 * Reads a fence value from memory (all asics).
112 * Returns the value of the fence read from memory.
113 */
114static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
115{
116 struct amdgpu_fence_driver *drv = &ring->fence_drv;
117 u32 seq = 0;
118
119 if (drv->cpu_addr)
120 seq = le32_to_cpu(*drv->cpu_addr);
121 else
122 seq = atomic_read(&drv->last_seq);
123
124 return seq;
125}
126
127/**
128 * amdgpu_fence_emit - emit a fence on the requested ring
129 *
130 * @ring: ring the fence is associated with
131 * @f: resulting fence object
132 *
133 * Emits a fence command on the requested ring (all asics).
134 * Returns 0 on success, -ENOMEM on failure.
135 */
136int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f,
137 unsigned flags)
138{
139 struct amdgpu_device *adev = ring->adev;
140 struct amdgpu_fence *fence;
141 struct dma_fence __rcu **ptr;
142 uint32_t seq;
143 int r;
144
145 fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
146 if (fence == NULL)
147 return -ENOMEM;
148
149 seq = ++ring->fence_drv.sync_seq;
150 fence->ring = ring;
151 dma_fence_init(&fence->base, &amdgpu_fence_ops,
152 &ring->fence_drv.lock,
153 adev->fence_context + ring->idx,
154 seq);
155 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
156 seq, flags | AMDGPU_FENCE_FLAG_INT);
157
158 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
159 if (unlikely(rcu_dereference_protected(*ptr, 1))) {
160 struct dma_fence *old;
161
162 rcu_read_lock();
163 old = dma_fence_get_rcu_safe(ptr);
164 rcu_read_unlock();
165
166 if (old) {
167 r = dma_fence_wait(old, false);
168 dma_fence_put(old);
169 if (r)
170 return r;
171 }
172 }
173
174 /* This function can't be called concurrently anyway, otherwise
175 * emitting the fence would mess up the hardware ring buffer.
176 */
177 rcu_assign_pointer(*ptr, dma_fence_get(&fence->base));
178
179 *f = &fence->base;
180
181 return 0;
182}
183
184/**
185 * amdgpu_fence_emit_polling - emit a fence on the requeste ring
186 *
187 * @ring: ring the fence is associated with
188 * @s: resulting sequence number
189 *
190 * Emits a fence command on the requested ring (all asics).
191 * Used For polling fence.
192 * Returns 0 on success, -ENOMEM on failure.
193 */
194int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s)
195{
196 uint32_t seq;
197
198 if (!s)
199 return -EINVAL;
200
201 seq = ++ring->fence_drv.sync_seq;
202 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
203 seq, 0);
204
205 *s = seq;
206
207 return 0;
208}
209
210/**
211 * amdgpu_fence_schedule_fallback - schedule fallback check
212 *
213 * @ring: pointer to struct amdgpu_ring
214 *
215 * Start a timer as fallback to our interrupts.
216 */
217static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
218{
219 mod_timer(&ring->fence_drv.fallback_timer,
220 jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT);
221}
222
223/**
224 * amdgpu_fence_process - check for fence activity
225 *
226 * @ring: pointer to struct amdgpu_ring
227 *
228 * Checks the current fence value and calculates the last
229 * signalled fence value. Wakes the fence queue if the
230 * sequence number has increased.
231 *
232 * Returns true if fence was processed
233 */
234bool amdgpu_fence_process(struct amdgpu_ring *ring)
235{
236 struct amdgpu_fence_driver *drv = &ring->fence_drv;
237 uint32_t seq, last_seq;
238 int r;
239
240 do {
241 last_seq = atomic_read(&ring->fence_drv.last_seq);
242 seq = amdgpu_fence_read(ring);
243
244 } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
245
246 if (del_timer(&ring->fence_drv.fallback_timer) &&
247 seq != ring->fence_drv.sync_seq)
248 amdgpu_fence_schedule_fallback(ring);
249
250 if (unlikely(seq == last_seq))
251 return false;
252
253 last_seq &= drv->num_fences_mask;
254 seq &= drv->num_fences_mask;
255
256 do {
257 struct dma_fence *fence, **ptr;
258
259 ++last_seq;
260 last_seq &= drv->num_fences_mask;
261 ptr = &drv->fences[last_seq];
262
263 /* There is always exactly one thread signaling this fence slot */
264 fence = rcu_dereference_protected(*ptr, 1);
265 RCU_INIT_POINTER(*ptr, NULL);
266
267 if (!fence)
268 continue;
269
270 r = dma_fence_signal(fence);
271 if (!r)
272 DMA_FENCE_TRACE(fence, "signaled from irq context\n");
273 else
274 BUG();
275
276 dma_fence_put(fence);
277 } while (last_seq != seq);
278
279 return true;
280}
281
282/**
283 * amdgpu_fence_fallback - fallback for hardware interrupts
284 *
285 * @work: delayed work item
286 *
287 * Checks for fence activity.
288 */
289static void amdgpu_fence_fallback(struct timer_list *t)
290{
291 struct amdgpu_ring *ring = from_timer(ring, t,
292 fence_drv.fallback_timer);
293
294 if (amdgpu_fence_process(ring))
295 DRM_WARN("Fence fallback timer expired on ring %s\n", ring->name);
296}
297
298/**
299 * amdgpu_fence_wait_empty - wait for all fences to signal
300 *
301 * @adev: amdgpu device pointer
302 * @ring: ring index the fence is associated with
303 *
304 * Wait for all fences on the requested ring to signal (all asics).
305 * Returns 0 if the fences have passed, error for all other cases.
306 */
307int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
308{
309 uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq);
310 struct dma_fence *fence, **ptr;
311 int r;
312
313 if (!seq)
314 return 0;
315
316 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
317 rcu_read_lock();
318 fence = rcu_dereference(*ptr);
319 if (!fence || !dma_fence_get_rcu(fence)) {
320 rcu_read_unlock();
321 return 0;
322 }
323 rcu_read_unlock();
324
325 r = dma_fence_wait(fence, false);
326 dma_fence_put(fence);
327 return r;
328}
329
330/**
331 * amdgpu_fence_wait_polling - busy wait for givn sequence number
332 *
333 * @ring: ring index the fence is associated with
334 * @wait_seq: sequence number to wait
335 * @timeout: the timeout for waiting in usecs
336 *
337 * Wait for all fences on the requested ring to signal (all asics).
338 * Returns left time if no timeout, 0 or minus if timeout.
339 */
340signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
341 uint32_t wait_seq,
342 signed long timeout)
343{
344 uint32_t seq;
345
346 do {
347 seq = amdgpu_fence_read(ring);
348 udelay(5);
349 timeout -= 5;
350 } while ((int32_t)(wait_seq - seq) > 0 && timeout > 0);
351
352 return timeout > 0 ? timeout : 0;
353}
354/**
355 * amdgpu_fence_count_emitted - get the count of emitted fences
356 *
357 * @ring: ring the fence is associated with
358 *
359 * Get the number of fences emitted on the requested ring (all asics).
360 * Returns the number of emitted fences on the ring. Used by the
361 * dynpm code to ring track activity.
362 */
363unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
364{
365 uint64_t emitted;
366
367 /* We are not protected by ring lock when reading the last sequence
368 * but it's ok to report slightly wrong fence count here.
369 */
370 amdgpu_fence_process(ring);
371 emitted = 0x100000000ull;
372 emitted -= atomic_read(&ring->fence_drv.last_seq);
373 emitted += READ_ONCE(ring->fence_drv.sync_seq);
374 return lower_32_bits(emitted);
375}
376
377/**
378 * amdgpu_fence_driver_start_ring - make the fence driver
379 * ready for use on the requested ring.
380 *
381 * @ring: ring to start the fence driver on
382 * @irq_src: interrupt source to use for this ring
383 * @irq_type: interrupt type to use for this ring
384 *
385 * Make the fence driver ready for processing (all asics).
386 * Not all asics have all rings, so each asic will only
387 * start the fence driver on the rings it has.
388 * Returns 0 for success, errors for failure.
389 */
390int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
391 struct amdgpu_irq_src *irq_src,
392 unsigned irq_type)
393{
394 struct amdgpu_device *adev = ring->adev;
395 uint64_t index;
396
397 if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) {
398 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
399 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
400 } else {
401 /* put fence directly behind firmware */
402 index = ALIGN(adev->uvd.fw->size, 8);
403 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index;
404 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;
405 }
406 amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
407 amdgpu_irq_get(adev, irq_src, irq_type);
408
409 ring->fence_drv.irq_src = irq_src;
410 ring->fence_drv.irq_type = irq_type;
411 ring->fence_drv.initialized = true;
412
413 DRM_DEV_DEBUG(adev->dev, "fence driver on ring %s use gpu addr "
414 "0x%016llx, cpu addr 0x%p\n", ring->name,
415 ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
416 return 0;
417}
418
419/**
420 * amdgpu_fence_driver_init_ring - init the fence driver
421 * for the requested ring.
422 *
423 * @ring: ring to init the fence driver on
424 * @num_hw_submission: number of entries on the hardware queue
425 *
426 * Init the fence driver for the requested ring (all asics).
427 * Helper function for amdgpu_fence_driver_init().
428 */
429int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
430 unsigned num_hw_submission)
431{
432 struct amdgpu_device *adev = ring->adev;
433 long timeout;
434 int r;
435
436 if (!adev)
437 return -EINVAL;
438
439 /* Check that num_hw_submission is a power of two */
440 if ((num_hw_submission & (num_hw_submission - 1)) != 0)
441 return -EINVAL;
442
443 ring->fence_drv.cpu_addr = NULL;
444 ring->fence_drv.gpu_addr = 0;
445 ring->fence_drv.sync_seq = 0;
446 atomic_set(&ring->fence_drv.last_seq, 0);
447 ring->fence_drv.initialized = false;
448
449 timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0);
450
451 ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1;
452 spin_lock_init(&ring->fence_drv.lock);
453 ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *),
454 GFP_KERNEL);
455 if (!ring->fence_drv.fences)
456 return -ENOMEM;
457
458 /* No need to setup the GPU scheduler for KIQ ring */
459 if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
460 switch (ring->funcs->type) {
461 case AMDGPU_RING_TYPE_GFX:
462 timeout = adev->gfx_timeout;
463 break;
464 case AMDGPU_RING_TYPE_COMPUTE:
465 /*
466 * For non-sriov case, no timeout enforce
467 * on compute ring by default. Unless user
468 * specifies a timeout for compute ring.
469 *
470 * For sriov case, always use the timeout
471 * as gfx ring
472 */
473 if (!amdgpu_sriov_vf(ring->adev))
474 timeout = adev->compute_timeout;
475 else
476 timeout = adev->gfx_timeout;
477 break;
478 case AMDGPU_RING_TYPE_SDMA:
479 timeout = adev->sdma_timeout;
480 break;
481 default:
482 timeout = adev->video_timeout;
483 break;
484 }
485
486 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
487 num_hw_submission, amdgpu_job_hang_limit,
488 timeout, ring->name);
489 if (r) {
490 DRM_ERROR("Failed to create scheduler on ring %s.\n",
491 ring->name);
492 return r;
493 }
494 }
495
496 return 0;
497}
498
499/**
500 * amdgpu_fence_driver_init - init the fence driver
501 * for all possible rings.
502 *
503 * @adev: amdgpu device pointer
504 *
505 * Init the fence driver for all possible rings (all asics).
506 * Not all asics have all rings, so each asic will only
507 * start the fence driver on the rings it has using
508 * amdgpu_fence_driver_start_ring().
509 * Returns 0 for success.
510 */
511int amdgpu_fence_driver_init(struct amdgpu_device *adev)
512{
513 if (amdgpu_debugfs_fence_init(adev))
514 dev_err(adev->dev, "fence debugfs file creation failed\n");
515
516 return 0;
517}
518
519/**
520 * amdgpu_fence_driver_fini - tear down the fence driver
521 * for all possible rings.
522 *
523 * @adev: amdgpu device pointer
524 *
525 * Tear down the fence driver for all possible rings (all asics).
526 */
527void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
528{
529 unsigned i, j;
530 int r;
531
532 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
533 struct amdgpu_ring *ring = adev->rings[i];
534
535 if (!ring || !ring->fence_drv.initialized)
536 continue;
537 r = amdgpu_fence_wait_empty(ring);
538 if (r) {
539 /* no need to trigger GPU reset as we are unloading */
540 amdgpu_fence_driver_force_completion(ring);
541 }
542 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
543 ring->fence_drv.irq_type);
544 drm_sched_fini(&ring->sched);
545 del_timer_sync(&ring->fence_drv.fallback_timer);
546 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
547 dma_fence_put(ring->fence_drv.fences[j]);
548 kfree(ring->fence_drv.fences);
549 ring->fence_drv.fences = NULL;
550 ring->fence_drv.initialized = false;
551 }
552}
553
554/**
555 * amdgpu_fence_driver_suspend - suspend the fence driver
556 * for all possible rings.
557 *
558 * @adev: amdgpu device pointer
559 *
560 * Suspend the fence driver for all possible rings (all asics).
561 */
562void amdgpu_fence_driver_suspend(struct amdgpu_device *adev)
563{
564 int i, r;
565
566 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
567 struct amdgpu_ring *ring = adev->rings[i];
568 if (!ring || !ring->fence_drv.initialized)
569 continue;
570
571 /* wait for gpu to finish processing current batch */
572 r = amdgpu_fence_wait_empty(ring);
573 if (r) {
574 /* delay GPU reset to resume */
575 amdgpu_fence_driver_force_completion(ring);
576 }
577
578 /* disable the interrupt */
579 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
580 ring->fence_drv.irq_type);
581 }
582}
583
584/**
585 * amdgpu_fence_driver_resume - resume the fence driver
586 * for all possible rings.
587 *
588 * @adev: amdgpu device pointer
589 *
590 * Resume the fence driver for all possible rings (all asics).
591 * Not all asics have all rings, so each asic will only
592 * start the fence driver on the rings it has using
593 * amdgpu_fence_driver_start_ring().
594 * Returns 0 for success.
595 */
596void amdgpu_fence_driver_resume(struct amdgpu_device *adev)
597{
598 int i;
599
600 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
601 struct amdgpu_ring *ring = adev->rings[i];
602 if (!ring || !ring->fence_drv.initialized)
603 continue;
604
605 /* enable the interrupt */
606 amdgpu_irq_get(adev, ring->fence_drv.irq_src,
607 ring->fence_drv.irq_type);
608 }
609}
610
611/**
612 * amdgpu_fence_driver_force_completion - force signal latest fence of ring
613 *
614 * @ring: fence of the ring to signal
615 *
616 */
617void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
618{
619 amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
620 amdgpu_fence_process(ring);
621}
622
623/*
624 * Common fence implementation
625 */
626
627static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence)
628{
629 return "amdgpu";
630}
631
632static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)
633{
634 struct amdgpu_fence *fence = to_amdgpu_fence(f);
635 return (const char *)fence->ring->name;
636}
637
638/**
639 * amdgpu_fence_enable_signaling - enable signalling on fence
640 * @fence: fence
641 *
642 * This function is called with fence_queue lock held, and adds a callback
643 * to fence_queue that checks if this fence is signaled, and if so it
644 * signals the fence and removes itself.
645 */
646static bool amdgpu_fence_enable_signaling(struct dma_fence *f)
647{
648 struct amdgpu_fence *fence = to_amdgpu_fence(f);
649 struct amdgpu_ring *ring = fence->ring;
650
651 if (!timer_pending(&ring->fence_drv.fallback_timer))
652 amdgpu_fence_schedule_fallback(ring);
653
654 DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
655
656 return true;
657}
658
659/**
660 * amdgpu_fence_free - free up the fence memory
661 *
662 * @rcu: RCU callback head
663 *
664 * Free up the fence memory after the RCU grace period.
665 */
666static void amdgpu_fence_free(struct rcu_head *rcu)
667{
668 struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
669 struct amdgpu_fence *fence = to_amdgpu_fence(f);
670 kmem_cache_free(amdgpu_fence_slab, fence);
671}
672
673/**
674 * amdgpu_fence_release - callback that fence can be freed
675 *
676 * @fence: fence
677 *
678 * This function is called when the reference count becomes zero.
679 * It just RCU schedules freeing up the fence.
680 */
681static void amdgpu_fence_release(struct dma_fence *f)
682{
683 call_rcu(&f->rcu, amdgpu_fence_free);
684}
685
686static const struct dma_fence_ops amdgpu_fence_ops = {
687 .get_driver_name = amdgpu_fence_get_driver_name,
688 .get_timeline_name = amdgpu_fence_get_timeline_name,
689 .enable_signaling = amdgpu_fence_enable_signaling,
690 .release = amdgpu_fence_release,
691};
692
693/*
694 * Fence debugfs
695 */
696#if defined(CONFIG_DEBUG_FS)
697static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
698{
699 struct drm_info_node *node = (struct drm_info_node *)m->private;
700 struct drm_device *dev = node->minor->dev;
701 struct amdgpu_device *adev = dev->dev_private;
702 int i;
703
704 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
705 struct amdgpu_ring *ring = adev->rings[i];
706 if (!ring || !ring->fence_drv.initialized)
707 continue;
708
709 amdgpu_fence_process(ring);
710
711 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
712 seq_printf(m, "Last signaled fence 0x%08x\n",
713 atomic_read(&ring->fence_drv.last_seq));
714 seq_printf(m, "Last emitted 0x%08x\n",
715 ring->fence_drv.sync_seq);
716
717 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX ||
718 ring->funcs->type == AMDGPU_RING_TYPE_SDMA) {
719 seq_printf(m, "Last signaled trailing fence 0x%08x\n",
720 le32_to_cpu(*ring->trail_fence_cpu_addr));
721 seq_printf(m, "Last emitted 0x%08x\n",
722 ring->trail_seq);
723 }
724
725 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
726 continue;
727
728 /* set in CP_VMID_PREEMPT and preemption occurred */
729 seq_printf(m, "Last preempted 0x%08x\n",
730 le32_to_cpu(*(ring->fence_drv.cpu_addr + 2)));
731 /* set in CP_VMID_RESET and reset occurred */
732 seq_printf(m, "Last reset 0x%08x\n",
733 le32_to_cpu(*(ring->fence_drv.cpu_addr + 4)));
734 /* Both preemption and reset occurred */
735 seq_printf(m, "Last both 0x%08x\n",
736 le32_to_cpu(*(ring->fence_drv.cpu_addr + 6)));
737 }
738 return 0;
739}
740
741/**
742 * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover
743 *
744 * Manually trigger a gpu reset at the next fence wait.
745 */
746static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data)
747{
748 struct drm_info_node *node = (struct drm_info_node *) m->private;
749 struct drm_device *dev = node->minor->dev;
750 struct amdgpu_device *adev = dev->dev_private;
751
752 seq_printf(m, "gpu recover\n");
753 amdgpu_device_gpu_recover(adev, NULL);
754
755 return 0;
756}
757
758static const struct drm_info_list amdgpu_debugfs_fence_list[] = {
759 {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
760 {"amdgpu_gpu_recover", &amdgpu_debugfs_gpu_recover, 0, NULL}
761};
762
763static const struct drm_info_list amdgpu_debugfs_fence_list_sriov[] = {
764 {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
765};
766#endif
767
768int amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
769{
770#if defined(CONFIG_DEBUG_FS)
771 if (amdgpu_sriov_vf(adev))
772 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list_sriov, 1);
773 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2);
774#else
775 return 0;
776#endif
777}
778