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1// SPDX-License-Identifier: GPL-2.0
2// Copyright 2014-2015 Freescale
3// Copyright 2018 NXP
4
5/*
6 * Driver for NXP Layerscape Queue Direct Memory Access Controller
7 *
8 * Author:
9 * Wen He <wen.he_1@nxp.com>
10 * Jiaheng Fan <jiaheng.fan@nxp.com>
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/delay.h>
16#include <linux/of.h>
17#include <linux/of_dma.h>
18#include <linux/dma-mapping.h>
19#include <linux/platform_device.h>
20
21#include "virt-dma.h"
22#include "fsldma.h"
23
24/* Register related definition */
25#define FSL_QDMA_DMR 0x0
26#define FSL_QDMA_DSR 0x4
27#define FSL_QDMA_DEIER 0xe00
28#define FSL_QDMA_DEDR 0xe04
29#define FSL_QDMA_DECFDW0R 0xe10
30#define FSL_QDMA_DECFDW1R 0xe14
31#define FSL_QDMA_DECFDW2R 0xe18
32#define FSL_QDMA_DECFDW3R 0xe1c
33#define FSL_QDMA_DECFQIDR 0xe30
34#define FSL_QDMA_DECBR 0xe34
35
36#define FSL_QDMA_BCQMR(x) (0xc0 + 0x100 * (x))
37#define FSL_QDMA_BCQSR(x) (0xc4 + 0x100 * (x))
38#define FSL_QDMA_BCQEDPA_SADDR(x) (0xc8 + 0x100 * (x))
39#define FSL_QDMA_BCQDPA_SADDR(x) (0xcc + 0x100 * (x))
40#define FSL_QDMA_BCQEEPA_SADDR(x) (0xd0 + 0x100 * (x))
41#define FSL_QDMA_BCQEPA_SADDR(x) (0xd4 + 0x100 * (x))
42#define FSL_QDMA_BCQIER(x) (0xe0 + 0x100 * (x))
43#define FSL_QDMA_BCQIDR(x) (0xe4 + 0x100 * (x))
44
45#define FSL_QDMA_SQDPAR 0x80c
46#define FSL_QDMA_SQEPAR 0x814
47#define FSL_QDMA_BSQMR 0x800
48#define FSL_QDMA_BSQSR 0x804
49#define FSL_QDMA_BSQICR 0x828
50#define FSL_QDMA_CQMR 0xa00
51#define FSL_QDMA_CQDSCR1 0xa08
52#define FSL_QDMA_CQDSCR2 0xa0c
53#define FSL_QDMA_CQIER 0xa10
54#define FSL_QDMA_CQEDR 0xa14
55#define FSL_QDMA_SQCCMR 0xa20
56
57/* Registers for bit and genmask */
58#define FSL_QDMA_CQIDR_SQT BIT(15)
59#define QDMA_CCDF_FORMAT BIT(29)
60#define QDMA_CCDF_SER BIT(30)
61#define QDMA_SG_FIN BIT(30)
62#define QDMA_SG_LEN_MASK GENMASK(29, 0)
63#define QDMA_CCDF_MASK GENMASK(28, 20)
64
65#define FSL_QDMA_DEDR_CLEAR GENMASK(31, 0)
66#define FSL_QDMA_BCQIDR_CLEAR GENMASK(31, 0)
67#define FSL_QDMA_DEIER_CLEAR GENMASK(31, 0)
68
69#define FSL_QDMA_BCQIER_CQTIE BIT(15)
70#define FSL_QDMA_BCQIER_CQPEIE BIT(23)
71#define FSL_QDMA_BSQICR_ICEN BIT(31)
72
73#define FSL_QDMA_BSQICR_ICST(x) ((x) << 16)
74#define FSL_QDMA_CQIER_MEIE BIT(31)
75#define FSL_QDMA_CQIER_TEIE BIT(0)
76#define FSL_QDMA_SQCCMR_ENTER_WM BIT(21)
77
78#define FSL_QDMA_BCQMR_EN BIT(31)
79#define FSL_QDMA_BCQMR_EI BIT(30)
80#define FSL_QDMA_BCQMR_CD_THLD(x) ((x) << 20)
81#define FSL_QDMA_BCQMR_CQ_SIZE(x) ((x) << 16)
82
83#define FSL_QDMA_BCQSR_QF BIT(16)
84#define FSL_QDMA_BCQSR_XOFF BIT(0)
85
86#define FSL_QDMA_BSQMR_EN BIT(31)
87#define FSL_QDMA_BSQMR_DI BIT(30)
88#define FSL_QDMA_BSQMR_CQ_SIZE(x) ((x) << 16)
89
90#define FSL_QDMA_BSQSR_QE BIT(17)
91
92#define FSL_QDMA_DMR_DQD BIT(30)
93#define FSL_QDMA_DSR_DB BIT(31)
94
95/* Size related definition */
96#define FSL_QDMA_QUEUE_MAX 8
97#define FSL_QDMA_COMMAND_BUFFER_SIZE 64
98#define FSL_QDMA_DESCRIPTOR_BUFFER_SIZE 32
99#define FSL_QDMA_CIRCULAR_DESC_SIZE_MIN 64
100#define FSL_QDMA_CIRCULAR_DESC_SIZE_MAX 16384
101#define FSL_QDMA_QUEUE_NUM_MAX 8
102
103/* Field definition for CMD */
104#define FSL_QDMA_CMD_RWTTYPE 0x4
105#define FSL_QDMA_CMD_LWC 0x2
106#define FSL_QDMA_CMD_RWTTYPE_OFFSET 28
107#define FSL_QDMA_CMD_NS_OFFSET 27
108#define FSL_QDMA_CMD_DQOS_OFFSET 24
109#define FSL_QDMA_CMD_WTHROTL_OFFSET 20
110#define FSL_QDMA_CMD_DSEN_OFFSET 19
111#define FSL_QDMA_CMD_LWC_OFFSET 16
112#define FSL_QDMA_CMD_PF BIT(17)
113
114/* Field definition for Descriptor status */
115#define QDMA_CCDF_STATUS_RTE BIT(5)
116#define QDMA_CCDF_STATUS_WTE BIT(4)
117#define QDMA_CCDF_STATUS_CDE BIT(2)
118#define QDMA_CCDF_STATUS_SDE BIT(1)
119#define QDMA_CCDF_STATUS_DDE BIT(0)
120#define QDMA_CCDF_STATUS_MASK (QDMA_CCDF_STATUS_RTE | \
121 QDMA_CCDF_STATUS_WTE | \
122 QDMA_CCDF_STATUS_CDE | \
123 QDMA_CCDF_STATUS_SDE | \
124 QDMA_CCDF_STATUS_DDE)
125
126/* Field definition for Descriptor offset */
127#define QDMA_CCDF_OFFSET 20
128#define QDMA_SDDF_CMD(x) (((u64)(x)) << 32)
129
130/* Field definition for safe loop count*/
131#define FSL_QDMA_HALT_COUNT 1500
132#define FSL_QDMA_MAX_SIZE 16385
133#define FSL_QDMA_COMP_TIMEOUT 1000
134#define FSL_COMMAND_QUEUE_OVERFLLOW 10
135
136#define FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma_engine, x) \
137 (((fsl_qdma_engine)->block_offset) * (x))
138
139/**
140 * struct fsl_qdma_format - This is the struct holding describing compound
141 * descriptor format with qDMA.
142 * @status: Command status and enqueue status notification.
143 * @cfg: Frame offset and frame format.
144 * @addr_lo: Holding the compound descriptor of the lower
145 * 32-bits address in memory 40-bit address.
146 * @addr_hi: Same as above member, but point high 8-bits in
147 * memory 40-bit address.
148 * @__reserved1: Reserved field.
149 * @cfg8b_w1: Compound descriptor command queue origin produced
150 * by qDMA and dynamic debug field.
151 * @data: Pointer to the memory 40-bit address, describes DMA
152 * source information and DMA destination information.
153 */
154struct fsl_qdma_format {
155 __le32 status;
156 __le32 cfg;
157 union {
158 struct {
159 __le32 addr_lo;
160 u8 addr_hi;
161 u8 __reserved1[2];
162 u8 cfg8b_w1;
163 } __packed;
164 struct {
165 __le32 __reserved2;
166 __le32 cmd;
167 } __packed;
168 __le64 data;
169 };
170} __packed;
171
172/* qDMA status notification pre information */
173struct fsl_pre_status {
174 u64 addr;
175 u8 queue;
176};
177
178static DEFINE_PER_CPU(struct fsl_pre_status, pre);
179
180struct fsl_qdma_chan {
181 struct virt_dma_chan vchan;
182 struct virt_dma_desc vdesc;
183 enum dma_status status;
184 struct fsl_qdma_engine *qdma;
185 struct fsl_qdma_queue *queue;
186};
187
188struct fsl_qdma_queue {
189 struct fsl_qdma_format *virt_head;
190 struct fsl_qdma_format *virt_tail;
191 struct list_head comp_used;
192 struct list_head comp_free;
193 struct dma_pool *comp_pool;
194 struct dma_pool *desc_pool;
195 spinlock_t queue_lock;
196 dma_addr_t bus_addr;
197 u32 n_cq;
198 u32 id;
199 struct fsl_qdma_format *cq;
200 void __iomem *block_base;
201};
202
203struct fsl_qdma_comp {
204 dma_addr_t bus_addr;
205 dma_addr_t desc_bus_addr;
206 struct fsl_qdma_format *virt_addr;
207 struct fsl_qdma_format *desc_virt_addr;
208 struct fsl_qdma_chan *qchan;
209 struct virt_dma_desc vdesc;
210 struct list_head list;
211};
212
213struct fsl_qdma_engine {
214 struct dma_device dma_dev;
215 void __iomem *ctrl_base;
216 void __iomem *status_base;
217 void __iomem *block_base;
218 u32 n_chans;
219 u32 n_queues;
220 struct mutex fsl_qdma_mutex;
221 int error_irq;
222 int *queue_irq;
223 u32 feature;
224 struct fsl_qdma_queue *queue;
225 struct fsl_qdma_queue **status;
226 struct fsl_qdma_chan *chans;
227 int block_number;
228 int block_offset;
229 int irq_base;
230 int desc_allocated;
231
232};
233
234static inline u64
235qdma_ccdf_addr_get64(const struct fsl_qdma_format *ccdf)
236{
237 return le64_to_cpu(ccdf->data) & (U64_MAX >> 24);
238}
239
240static inline void
241qdma_desc_addr_set64(struct fsl_qdma_format *ccdf, u64 addr)
242{
243 ccdf->addr_hi = upper_32_bits(addr);
244 ccdf->addr_lo = cpu_to_le32(lower_32_bits(addr));
245}
246
247static inline u8
248qdma_ccdf_get_queue(const struct fsl_qdma_format *ccdf)
249{
250 return ccdf->cfg8b_w1 & U8_MAX;
251}
252
253static inline int
254qdma_ccdf_get_offset(const struct fsl_qdma_format *ccdf)
255{
256 return (le32_to_cpu(ccdf->cfg) & QDMA_CCDF_MASK) >> QDMA_CCDF_OFFSET;
257}
258
259static inline void
260qdma_ccdf_set_format(struct fsl_qdma_format *ccdf, int offset)
261{
262 ccdf->cfg = cpu_to_le32(QDMA_CCDF_FORMAT |
263 (offset << QDMA_CCDF_OFFSET));
264}
265
266static inline int
267qdma_ccdf_get_status(const struct fsl_qdma_format *ccdf)
268{
269 return (le32_to_cpu(ccdf->status) & QDMA_CCDF_STATUS_MASK);
270}
271
272static inline void
273qdma_ccdf_set_ser(struct fsl_qdma_format *ccdf, int status)
274{
275 ccdf->status = cpu_to_le32(QDMA_CCDF_SER | status);
276}
277
278static inline void qdma_csgf_set_len(struct fsl_qdma_format *csgf, int len)
279{
280 csgf->cfg = cpu_to_le32(len & QDMA_SG_LEN_MASK);
281}
282
283static inline void qdma_csgf_set_f(struct fsl_qdma_format *csgf, int len)
284{
285 csgf->cfg = cpu_to_le32(QDMA_SG_FIN | (len & QDMA_SG_LEN_MASK));
286}
287
288static u32 qdma_readl(struct fsl_qdma_engine *qdma, void __iomem *addr)
289{
290 return FSL_DMA_IN(qdma, addr, 32);
291}
292
293static void qdma_writel(struct fsl_qdma_engine *qdma, u32 val,
294 void __iomem *addr)
295{
296 FSL_DMA_OUT(qdma, addr, val, 32);
297}
298
299static struct fsl_qdma_chan *to_fsl_qdma_chan(struct dma_chan *chan)
300{
301 return container_of(chan, struct fsl_qdma_chan, vchan.chan);
302}
303
304static struct fsl_qdma_comp *to_fsl_qdma_comp(struct virt_dma_desc *vd)
305{
306 return container_of(vd, struct fsl_qdma_comp, vdesc);
307}
308
309static void fsl_qdma_free_chan_resources(struct dma_chan *chan)
310{
311 struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
312 struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
313 struct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma;
314 struct fsl_qdma_comp *comp_temp, *_comp_temp;
315 unsigned long flags;
316 LIST_HEAD(head);
317
318 spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
319 vchan_get_all_descriptors(&fsl_chan->vchan, &head);
320 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
321
322 vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
323
324 if (!fsl_queue->comp_pool && !fsl_queue->desc_pool)
325 return;
326
327 list_for_each_entry_safe(comp_temp, _comp_temp,
328 &fsl_queue->comp_used, list) {
329 dma_pool_free(fsl_queue->comp_pool,
330 comp_temp->virt_addr,
331 comp_temp->bus_addr);
332 dma_pool_free(fsl_queue->desc_pool,
333 comp_temp->desc_virt_addr,
334 comp_temp->desc_bus_addr);
335 list_del(&comp_temp->list);
336 kfree(comp_temp);
337 }
338
339 list_for_each_entry_safe(comp_temp, _comp_temp,
340 &fsl_queue->comp_free, list) {
341 dma_pool_free(fsl_queue->comp_pool,
342 comp_temp->virt_addr,
343 comp_temp->bus_addr);
344 dma_pool_free(fsl_queue->desc_pool,
345 comp_temp->desc_virt_addr,
346 comp_temp->desc_bus_addr);
347 list_del(&comp_temp->list);
348 kfree(comp_temp);
349 }
350
351 dma_pool_destroy(fsl_queue->comp_pool);
352 dma_pool_destroy(fsl_queue->desc_pool);
353
354 fsl_qdma->desc_allocated--;
355 fsl_queue->comp_pool = NULL;
356 fsl_queue->desc_pool = NULL;
357}
358
359static void fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp *fsl_comp,
360 dma_addr_t dst, dma_addr_t src, u32 len)
361{
362 struct fsl_qdma_format *sdf, *ddf;
363 struct fsl_qdma_format *ccdf, *csgf_desc, *csgf_src, *csgf_dest;
364
365 ccdf = fsl_comp->virt_addr;
366 csgf_desc = fsl_comp->virt_addr + 1;
367 csgf_src = fsl_comp->virt_addr + 2;
368 csgf_dest = fsl_comp->virt_addr + 3;
369 sdf = fsl_comp->desc_virt_addr;
370 ddf = fsl_comp->desc_virt_addr + 1;
371
372 memset(fsl_comp->virt_addr, 0, FSL_QDMA_COMMAND_BUFFER_SIZE);
373 memset(fsl_comp->desc_virt_addr, 0, FSL_QDMA_DESCRIPTOR_BUFFER_SIZE);
374 /* Head Command Descriptor(Frame Descriptor) */
375 qdma_desc_addr_set64(ccdf, fsl_comp->bus_addr + 16);
376 qdma_ccdf_set_format(ccdf, qdma_ccdf_get_offset(ccdf));
377 qdma_ccdf_set_ser(ccdf, qdma_ccdf_get_status(ccdf));
378 /* Status notification is enqueued to status queue. */
379 /* Compound Command Descriptor(Frame List Table) */
380 qdma_desc_addr_set64(csgf_desc, fsl_comp->desc_bus_addr);
381 /* It must be 32 as Compound S/G Descriptor */
382 qdma_csgf_set_len(csgf_desc, 32);
383 qdma_desc_addr_set64(csgf_src, src);
384 qdma_csgf_set_len(csgf_src, len);
385 qdma_desc_addr_set64(csgf_dest, dst);
386 qdma_csgf_set_len(csgf_dest, len);
387 /* This entry is the last entry. */
388 qdma_csgf_set_f(csgf_dest, len);
389 /* Descriptor Buffer */
390 sdf->cmd = cpu_to_le32((FSL_QDMA_CMD_RWTTYPE << FSL_QDMA_CMD_RWTTYPE_OFFSET) |
391 FSL_QDMA_CMD_PF);
392
393 ddf->cmd = cpu_to_le32((FSL_QDMA_CMD_RWTTYPE << FSL_QDMA_CMD_RWTTYPE_OFFSET) |
394 (FSL_QDMA_CMD_LWC << FSL_QDMA_CMD_LWC_OFFSET));
395}
396
397/*
398 * Pre-request full command descriptor for enqueue.
399 */
400static int fsl_qdma_pre_request_enqueue_desc(struct fsl_qdma_queue *queue)
401{
402 int i;
403 struct fsl_qdma_comp *comp_temp, *_comp_temp;
404
405 for (i = 0; i < queue->n_cq + FSL_COMMAND_QUEUE_OVERFLLOW; i++) {
406 comp_temp = kzalloc(sizeof(*comp_temp), GFP_KERNEL);
407 if (!comp_temp)
408 goto err_alloc;
409 comp_temp->virt_addr =
410 dma_pool_alloc(queue->comp_pool, GFP_KERNEL,
411 &comp_temp->bus_addr);
412 if (!comp_temp->virt_addr)
413 goto err_dma_alloc;
414
415 comp_temp->desc_virt_addr =
416 dma_pool_alloc(queue->desc_pool, GFP_KERNEL,
417 &comp_temp->desc_bus_addr);
418 if (!comp_temp->desc_virt_addr)
419 goto err_desc_dma_alloc;
420
421 list_add_tail(&comp_temp->list, &queue->comp_free);
422 }
423
424 return 0;
425
426err_desc_dma_alloc:
427 dma_pool_free(queue->comp_pool, comp_temp->virt_addr,
428 comp_temp->bus_addr);
429
430err_dma_alloc:
431 kfree(comp_temp);
432
433err_alloc:
434 list_for_each_entry_safe(comp_temp, _comp_temp,
435 &queue->comp_free, list) {
436 if (comp_temp->virt_addr)
437 dma_pool_free(queue->comp_pool,
438 comp_temp->virt_addr,
439 comp_temp->bus_addr);
440 if (comp_temp->desc_virt_addr)
441 dma_pool_free(queue->desc_pool,
442 comp_temp->desc_virt_addr,
443 comp_temp->desc_bus_addr);
444
445 list_del(&comp_temp->list);
446 kfree(comp_temp);
447 }
448
449 return -ENOMEM;
450}
451
452/*
453 * Request a command descriptor for enqueue.
454 */
455static struct fsl_qdma_comp
456*fsl_qdma_request_enqueue_desc(struct fsl_qdma_chan *fsl_chan)
457{
458 unsigned long flags;
459 struct fsl_qdma_comp *comp_temp;
460 int timeout = FSL_QDMA_COMP_TIMEOUT;
461 struct fsl_qdma_queue *queue = fsl_chan->queue;
462
463 while (timeout--) {
464 spin_lock_irqsave(&queue->queue_lock, flags);
465 if (!list_empty(&queue->comp_free)) {
466 comp_temp = list_first_entry(&queue->comp_free,
467 struct fsl_qdma_comp,
468 list);
469 list_del(&comp_temp->list);
470
471 spin_unlock_irqrestore(&queue->queue_lock, flags);
472 comp_temp->qchan = fsl_chan;
473 return comp_temp;
474 }
475 spin_unlock_irqrestore(&queue->queue_lock, flags);
476 udelay(1);
477 }
478
479 return NULL;
480}
481
482static struct fsl_qdma_queue
483*fsl_qdma_alloc_queue_resources(struct platform_device *pdev,
484 struct fsl_qdma_engine *fsl_qdma)
485{
486 int ret, len, i, j;
487 int queue_num, block_number;
488 unsigned int queue_size[FSL_QDMA_QUEUE_MAX];
489 struct fsl_qdma_queue *queue_head, *queue_temp;
490
491 queue_num = fsl_qdma->n_queues;
492 block_number = fsl_qdma->block_number;
493
494 if (queue_num > FSL_QDMA_QUEUE_MAX)
495 queue_num = FSL_QDMA_QUEUE_MAX;
496 len = sizeof(*queue_head) * queue_num * block_number;
497 queue_head = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
498 if (!queue_head)
499 return NULL;
500
501 ret = device_property_read_u32_array(&pdev->dev, "queue-sizes",
502 queue_size, queue_num);
503 if (ret) {
504 dev_err(&pdev->dev, "Can't get queue-sizes.\n");
505 return NULL;
506 }
507 for (j = 0; j < block_number; j++) {
508 for (i = 0; i < queue_num; i++) {
509 if (queue_size[i] > FSL_QDMA_CIRCULAR_DESC_SIZE_MAX ||
510 queue_size[i] < FSL_QDMA_CIRCULAR_DESC_SIZE_MIN) {
511 dev_err(&pdev->dev,
512 "Get wrong queue-sizes.\n");
513 return NULL;
514 }
515 queue_temp = queue_head + i + (j * queue_num);
516
517 queue_temp->cq =
518 dmam_alloc_coherent(&pdev->dev,
519 sizeof(struct fsl_qdma_format) *
520 queue_size[i],
521 &queue_temp->bus_addr,
522 GFP_KERNEL);
523 if (!queue_temp->cq)
524 return NULL;
525 queue_temp->block_base = fsl_qdma->block_base +
526 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
527 queue_temp->n_cq = queue_size[i];
528 queue_temp->id = i;
529 queue_temp->virt_head = queue_temp->cq;
530 queue_temp->virt_tail = queue_temp->cq;
531 /*
532 * List for queue command buffer
533 */
534 INIT_LIST_HEAD(&queue_temp->comp_used);
535 spin_lock_init(&queue_temp->queue_lock);
536 }
537 }
538 return queue_head;
539}
540
541static struct fsl_qdma_queue
542*fsl_qdma_prep_status_queue(struct platform_device *pdev)
543{
544 int ret;
545 unsigned int status_size;
546 struct fsl_qdma_queue *status_head;
547 struct device_node *np = pdev->dev.of_node;
548
549 ret = of_property_read_u32(np, "status-sizes", &status_size);
550 if (ret) {
551 dev_err(&pdev->dev, "Can't get status-sizes.\n");
552 return NULL;
553 }
554 if (status_size > FSL_QDMA_CIRCULAR_DESC_SIZE_MAX ||
555 status_size < FSL_QDMA_CIRCULAR_DESC_SIZE_MIN) {
556 dev_err(&pdev->dev, "Get wrong status_size.\n");
557 return NULL;
558 }
559 status_head = devm_kzalloc(&pdev->dev,
560 sizeof(*status_head), GFP_KERNEL);
561 if (!status_head)
562 return NULL;
563
564 /*
565 * Buffer for queue command
566 */
567 status_head->cq = dmam_alloc_coherent(&pdev->dev,
568 sizeof(struct fsl_qdma_format) *
569 status_size,
570 &status_head->bus_addr,
571 GFP_KERNEL);
572 if (!status_head->cq)
573 return NULL;
574
575 status_head->n_cq = status_size;
576 status_head->virt_head = status_head->cq;
577 status_head->virt_tail = status_head->cq;
578 status_head->comp_pool = NULL;
579
580 return status_head;
581}
582
583static int fsl_qdma_halt(struct fsl_qdma_engine *fsl_qdma)
584{
585 u32 reg;
586 int i, j, count = FSL_QDMA_HALT_COUNT;
587 void __iomem *block, *ctrl = fsl_qdma->ctrl_base;
588
589 /* Disable the command queue and wait for idle state. */
590 reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR);
591 reg |= FSL_QDMA_DMR_DQD;
592 qdma_writel(fsl_qdma, reg, ctrl + FSL_QDMA_DMR);
593 for (j = 0; j < fsl_qdma->block_number; j++) {
594 block = fsl_qdma->block_base +
595 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
596 for (i = 0; i < FSL_QDMA_QUEUE_NUM_MAX; i++)
597 qdma_writel(fsl_qdma, 0, block + FSL_QDMA_BCQMR(i));
598 }
599 while (1) {
600 reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DSR);
601 if (!(reg & FSL_QDMA_DSR_DB))
602 break;
603 if (count-- < 0)
604 return -EBUSY;
605 udelay(100);
606 }
607
608 for (j = 0; j < fsl_qdma->block_number; j++) {
609 block = fsl_qdma->block_base +
610 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
611
612 /* Disable status queue. */
613 qdma_writel(fsl_qdma, 0, block + FSL_QDMA_BSQMR);
614
615 /*
616 * clear the command queue interrupt detect register for
617 * all queues.
618 */
619 qdma_writel(fsl_qdma, FSL_QDMA_BCQIDR_CLEAR,
620 block + FSL_QDMA_BCQIDR(0));
621 }
622
623 return 0;
624}
625
626static int
627fsl_qdma_queue_transfer_complete(struct fsl_qdma_engine *fsl_qdma,
628 __iomem void *block,
629 int id)
630{
631 bool duplicate;
632 u32 reg, i, count;
633 u8 completion_status;
634 struct fsl_qdma_queue *temp_queue;
635 struct fsl_qdma_format *status_addr;
636 struct fsl_qdma_comp *fsl_comp = NULL;
637 struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;
638 struct fsl_qdma_queue *fsl_status = fsl_qdma->status[id];
639
640 count = FSL_QDMA_MAX_SIZE;
641
642 while (count--) {
643 duplicate = 0;
644 reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQSR);
645 if (reg & FSL_QDMA_BSQSR_QE)
646 return 0;
647
648 status_addr = fsl_status->virt_head;
649
650 if (qdma_ccdf_get_queue(status_addr) ==
651 __this_cpu_read(pre.queue) &&
652 qdma_ccdf_addr_get64(status_addr) ==
653 __this_cpu_read(pre.addr))
654 duplicate = 1;
655 i = qdma_ccdf_get_queue(status_addr) +
656 id * fsl_qdma->n_queues;
657 __this_cpu_write(pre.addr, qdma_ccdf_addr_get64(status_addr));
658 __this_cpu_write(pre.queue, qdma_ccdf_get_queue(status_addr));
659 temp_queue = fsl_queue + i;
660
661 spin_lock(&temp_queue->queue_lock);
662 if (list_empty(&temp_queue->comp_used)) {
663 if (!duplicate) {
664 spin_unlock(&temp_queue->queue_lock);
665 return -EAGAIN;
666 }
667 } else {
668 fsl_comp = list_first_entry(&temp_queue->comp_used,
669 struct fsl_qdma_comp, list);
670 if (fsl_comp->bus_addr + 16 !=
671 __this_cpu_read(pre.addr)) {
672 if (!duplicate) {
673 spin_unlock(&temp_queue->queue_lock);
674 return -EAGAIN;
675 }
676 }
677 }
678
679 if (duplicate) {
680 reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQMR);
681 reg |= FSL_QDMA_BSQMR_DI;
682 qdma_desc_addr_set64(status_addr, 0x0);
683 fsl_status->virt_head++;
684 if (fsl_status->virt_head == fsl_status->cq
685 + fsl_status->n_cq)
686 fsl_status->virt_head = fsl_status->cq;
687 qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BSQMR);
688 spin_unlock(&temp_queue->queue_lock);
689 continue;
690 }
691 list_del(&fsl_comp->list);
692
693 completion_status = qdma_ccdf_get_status(status_addr);
694
695 reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQMR);
696 reg |= FSL_QDMA_BSQMR_DI;
697 qdma_desc_addr_set64(status_addr, 0x0);
698 fsl_status->virt_head++;
699 if (fsl_status->virt_head == fsl_status->cq + fsl_status->n_cq)
700 fsl_status->virt_head = fsl_status->cq;
701 qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BSQMR);
702 spin_unlock(&temp_queue->queue_lock);
703
704 /* The completion_status is evaluated here
705 * (outside of spin lock)
706 */
707 if (completion_status) {
708 /* A completion error occurred! */
709 if (completion_status & QDMA_CCDF_STATUS_WTE) {
710 /* Write transaction error */
711 fsl_comp->vdesc.tx_result.result =
712 DMA_TRANS_WRITE_FAILED;
713 } else if (completion_status & QDMA_CCDF_STATUS_RTE) {
714 /* Read transaction error */
715 fsl_comp->vdesc.tx_result.result =
716 DMA_TRANS_READ_FAILED;
717 } else {
718 /* Command/source/destination
719 * description error
720 */
721 fsl_comp->vdesc.tx_result.result =
722 DMA_TRANS_ABORTED;
723 dev_err(fsl_qdma->dma_dev.dev,
724 "DMA status descriptor error %x\n",
725 completion_status);
726 }
727 }
728
729 spin_lock(&fsl_comp->qchan->vchan.lock);
730 vchan_cookie_complete(&fsl_comp->vdesc);
731 fsl_comp->qchan->status = DMA_COMPLETE;
732 spin_unlock(&fsl_comp->qchan->vchan.lock);
733 }
734
735 return 0;
736}
737
738static irqreturn_t fsl_qdma_error_handler(int irq, void *dev_id)
739{
740 unsigned int intr;
741 struct fsl_qdma_engine *fsl_qdma = dev_id;
742 void __iomem *status = fsl_qdma->status_base;
743 unsigned int decfdw0r;
744 unsigned int decfdw1r;
745 unsigned int decfdw2r;
746 unsigned int decfdw3r;
747
748 intr = qdma_readl(fsl_qdma, status + FSL_QDMA_DEDR);
749
750 if (intr) {
751 decfdw0r = qdma_readl(fsl_qdma, status + FSL_QDMA_DECFDW0R);
752 decfdw1r = qdma_readl(fsl_qdma, status + FSL_QDMA_DECFDW1R);
753 decfdw2r = qdma_readl(fsl_qdma, status + FSL_QDMA_DECFDW2R);
754 decfdw3r = qdma_readl(fsl_qdma, status + FSL_QDMA_DECFDW3R);
755 dev_err(fsl_qdma->dma_dev.dev,
756 "DMA transaction error! (%x: %x-%x-%x-%x)\n",
757 intr, decfdw0r, decfdw1r, decfdw2r, decfdw3r);
758 }
759
760 qdma_writel(fsl_qdma, FSL_QDMA_DEDR_CLEAR, status + FSL_QDMA_DEDR);
761 return IRQ_HANDLED;
762}
763
764static irqreturn_t fsl_qdma_queue_handler(int irq, void *dev_id)
765{
766 int id;
767 unsigned int intr, reg;
768 struct fsl_qdma_engine *fsl_qdma = dev_id;
769 void __iomem *block, *ctrl = fsl_qdma->ctrl_base;
770
771 id = irq - fsl_qdma->irq_base;
772 if (id < 0 && id > fsl_qdma->block_number) {
773 dev_err(fsl_qdma->dma_dev.dev,
774 "irq %d is wrong irq_base is %d\n",
775 irq, fsl_qdma->irq_base);
776 }
777
778 block = fsl_qdma->block_base +
779 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, id);
780
781 intr = qdma_readl(fsl_qdma, block + FSL_QDMA_BCQIDR(0));
782
783 if ((intr & FSL_QDMA_CQIDR_SQT) != 0)
784 intr = fsl_qdma_queue_transfer_complete(fsl_qdma, block, id);
785
786 if (intr != 0) {
787 reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR);
788 reg |= FSL_QDMA_DMR_DQD;
789 qdma_writel(fsl_qdma, reg, ctrl + FSL_QDMA_DMR);
790 qdma_writel(fsl_qdma, 0, block + FSL_QDMA_BCQIER(0));
791 dev_err(fsl_qdma->dma_dev.dev, "QDMA: status err!\n");
792 }
793
794 /* Clear all detected events and interrupts. */
795 qdma_writel(fsl_qdma, FSL_QDMA_BCQIDR_CLEAR,
796 block + FSL_QDMA_BCQIDR(0));
797
798 return IRQ_HANDLED;
799}
800
801static int
802fsl_qdma_irq_init(struct platform_device *pdev,
803 struct fsl_qdma_engine *fsl_qdma)
804{
805 int i;
806 int cpu;
807 int ret;
808 char irq_name[32];
809
810 fsl_qdma->error_irq =
811 platform_get_irq_byname(pdev, "qdma-error");
812 if (fsl_qdma->error_irq < 0)
813 return fsl_qdma->error_irq;
814
815 ret = devm_request_irq(&pdev->dev, fsl_qdma->error_irq,
816 fsl_qdma_error_handler, 0,
817 "qDMA error", fsl_qdma);
818 if (ret) {
819 dev_err(&pdev->dev, "Can't register qDMA controller IRQ.\n");
820 return ret;
821 }
822
823 for (i = 0; i < fsl_qdma->block_number; i++) {
824 sprintf(irq_name, "qdma-queue%d", i);
825 fsl_qdma->queue_irq[i] =
826 platform_get_irq_byname(pdev, irq_name);
827
828 if (fsl_qdma->queue_irq[i] < 0)
829 return fsl_qdma->queue_irq[i];
830
831 ret = devm_request_irq(&pdev->dev,
832 fsl_qdma->queue_irq[i],
833 fsl_qdma_queue_handler,
834 0,
835 "qDMA queue",
836 fsl_qdma);
837 if (ret) {
838 dev_err(&pdev->dev,
839 "Can't register qDMA queue IRQ.\n");
840 return ret;
841 }
842
843 cpu = i % num_online_cpus();
844 ret = irq_set_affinity_hint(fsl_qdma->queue_irq[i],
845 get_cpu_mask(cpu));
846 if (ret) {
847 dev_err(&pdev->dev,
848 "Can't set cpu %d affinity to IRQ %d.\n",
849 cpu,
850 fsl_qdma->queue_irq[i]);
851 return ret;
852 }
853 }
854
855 return 0;
856}
857
858static void fsl_qdma_irq_exit(struct platform_device *pdev,
859 struct fsl_qdma_engine *fsl_qdma)
860{
861 int i;
862
863 devm_free_irq(&pdev->dev, fsl_qdma->error_irq, fsl_qdma);
864 for (i = 0; i < fsl_qdma->block_number; i++)
865 devm_free_irq(&pdev->dev, fsl_qdma->queue_irq[i], fsl_qdma);
866}
867
868static int fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)
869{
870 u32 reg;
871 int i, j, ret;
872 struct fsl_qdma_queue *temp;
873 void __iomem *status = fsl_qdma->status_base;
874 void __iomem *block, *ctrl = fsl_qdma->ctrl_base;
875 struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;
876
877 /* Try to halt the qDMA engine first. */
878 ret = fsl_qdma_halt(fsl_qdma);
879 if (ret) {
880 dev_err(fsl_qdma->dma_dev.dev, "DMA halt failed!");
881 return ret;
882 }
883
884 for (i = 0; i < fsl_qdma->block_number; i++) {
885 /*
886 * Clear the command queue interrupt detect register for
887 * all queues.
888 */
889
890 block = fsl_qdma->block_base +
891 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, i);
892 qdma_writel(fsl_qdma, FSL_QDMA_BCQIDR_CLEAR,
893 block + FSL_QDMA_BCQIDR(0));
894 }
895
896 for (j = 0; j < fsl_qdma->block_number; j++) {
897 block = fsl_qdma->block_base +
898 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
899 for (i = 0; i < fsl_qdma->n_queues; i++) {
900 temp = fsl_queue + i + (j * fsl_qdma->n_queues);
901 /*
902 * Initialize Command Queue registers to
903 * point to the first
904 * command descriptor in memory.
905 * Dequeue Pointer Address Registers
906 * Enqueue Pointer Address Registers
907 */
908
909 qdma_writel(fsl_qdma, temp->bus_addr,
910 block + FSL_QDMA_BCQDPA_SADDR(i));
911 qdma_writel(fsl_qdma, temp->bus_addr,
912 block + FSL_QDMA_BCQEPA_SADDR(i));
913
914 /* Initialize the queue mode. */
915 reg = FSL_QDMA_BCQMR_EN;
916 reg |= FSL_QDMA_BCQMR_CD_THLD(ilog2(temp->n_cq) - 4);
917 reg |= FSL_QDMA_BCQMR_CQ_SIZE(ilog2(temp->n_cq) - 6);
918 qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BCQMR(i));
919 }
920
921 /*
922 * Workaround for erratum: ERR010812.
923 * We must enable XOFF to avoid the enqueue rejection occurs.
924 * Setting SQCCMR ENTER_WM to 0x20.
925 */
926
927 qdma_writel(fsl_qdma, FSL_QDMA_SQCCMR_ENTER_WM,
928 block + FSL_QDMA_SQCCMR);
929
930 /*
931 * Initialize status queue registers to point to the first
932 * command descriptor in memory.
933 * Dequeue Pointer Address Registers
934 * Enqueue Pointer Address Registers
935 */
936
937 qdma_writel(fsl_qdma, fsl_qdma->status[j]->bus_addr,
938 block + FSL_QDMA_SQEPAR);
939 qdma_writel(fsl_qdma, fsl_qdma->status[j]->bus_addr,
940 block + FSL_QDMA_SQDPAR);
941 /* Initialize status queue interrupt. */
942 qdma_writel(fsl_qdma, FSL_QDMA_BCQIER_CQTIE,
943 block + FSL_QDMA_BCQIER(0));
944 qdma_writel(fsl_qdma, FSL_QDMA_BSQICR_ICEN |
945 FSL_QDMA_BSQICR_ICST(5) | 0x8000,
946 block + FSL_QDMA_BSQICR);
947 qdma_writel(fsl_qdma, FSL_QDMA_CQIER_MEIE |
948 FSL_QDMA_CQIER_TEIE,
949 block + FSL_QDMA_CQIER);
950
951 /* Initialize the status queue mode. */
952 reg = FSL_QDMA_BSQMR_EN;
953 reg |= FSL_QDMA_BSQMR_CQ_SIZE(ilog2
954 (fsl_qdma->status[j]->n_cq) - 6);
955
956 qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BSQMR);
957 reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQMR);
958 }
959
960 /* Initialize controller interrupt register. */
961 qdma_writel(fsl_qdma, FSL_QDMA_DEDR_CLEAR, status + FSL_QDMA_DEDR);
962 qdma_writel(fsl_qdma, FSL_QDMA_DEIER_CLEAR, status + FSL_QDMA_DEIER);
963
964 reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR);
965 reg &= ~FSL_QDMA_DMR_DQD;
966 qdma_writel(fsl_qdma, reg, ctrl + FSL_QDMA_DMR);
967
968 return 0;
969}
970
971static struct dma_async_tx_descriptor *
972fsl_qdma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst,
973 dma_addr_t src, size_t len, unsigned long flags)
974{
975 struct fsl_qdma_comp *fsl_comp;
976 struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
977
978 fsl_comp = fsl_qdma_request_enqueue_desc(fsl_chan);
979
980 if (!fsl_comp)
981 return NULL;
982
983 fsl_qdma_comp_fill_memcpy(fsl_comp, dst, src, len);
984
985 return vchan_tx_prep(&fsl_chan->vchan, &fsl_comp->vdesc, flags);
986}
987
988static void fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan)
989{
990 u32 reg;
991 struct virt_dma_desc *vdesc;
992 struct fsl_qdma_comp *fsl_comp;
993 struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
994 void __iomem *block = fsl_queue->block_base;
995
996 reg = qdma_readl(fsl_chan->qdma, block + FSL_QDMA_BCQSR(fsl_queue->id));
997 if (reg & (FSL_QDMA_BCQSR_QF | FSL_QDMA_BCQSR_XOFF))
998 return;
999 vdesc = vchan_next_desc(&fsl_chan->vchan);
1000 if (!vdesc)
1001 return;
1002 list_del(&vdesc->node);
1003 fsl_comp = to_fsl_qdma_comp(vdesc);
1004
1005 memcpy(fsl_queue->virt_head++,
1006 fsl_comp->virt_addr, sizeof(struct fsl_qdma_format));
1007 if (fsl_queue->virt_head == fsl_queue->cq + fsl_queue->n_cq)
1008 fsl_queue->virt_head = fsl_queue->cq;
1009
1010 list_add_tail(&fsl_comp->list, &fsl_queue->comp_used);
1011 barrier();
1012 reg = qdma_readl(fsl_chan->qdma, block + FSL_QDMA_BCQMR(fsl_queue->id));
1013 reg |= FSL_QDMA_BCQMR_EI;
1014 qdma_writel(fsl_chan->qdma, reg, block + FSL_QDMA_BCQMR(fsl_queue->id));
1015 fsl_chan->status = DMA_IN_PROGRESS;
1016}
1017
1018static void fsl_qdma_free_desc(struct virt_dma_desc *vdesc)
1019{
1020 unsigned long flags;
1021 struct fsl_qdma_comp *fsl_comp;
1022 struct fsl_qdma_queue *fsl_queue;
1023
1024 fsl_comp = to_fsl_qdma_comp(vdesc);
1025 fsl_queue = fsl_comp->qchan->queue;
1026
1027 spin_lock_irqsave(&fsl_queue->queue_lock, flags);
1028 list_add_tail(&fsl_comp->list, &fsl_queue->comp_free);
1029 spin_unlock_irqrestore(&fsl_queue->queue_lock, flags);
1030}
1031
1032static void fsl_qdma_issue_pending(struct dma_chan *chan)
1033{
1034 unsigned long flags;
1035 struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
1036 struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
1037
1038 spin_lock_irqsave(&fsl_queue->queue_lock, flags);
1039 spin_lock(&fsl_chan->vchan.lock);
1040 if (vchan_issue_pending(&fsl_chan->vchan))
1041 fsl_qdma_enqueue_desc(fsl_chan);
1042 spin_unlock(&fsl_chan->vchan.lock);
1043 spin_unlock_irqrestore(&fsl_queue->queue_lock, flags);
1044}
1045
1046static void fsl_qdma_synchronize(struct dma_chan *chan)
1047{
1048 struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
1049
1050 vchan_synchronize(&fsl_chan->vchan);
1051}
1052
1053static int fsl_qdma_terminate_all(struct dma_chan *chan)
1054{
1055 LIST_HEAD(head);
1056 unsigned long flags;
1057 struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
1058
1059 spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
1060 vchan_get_all_descriptors(&fsl_chan->vchan, &head);
1061 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
1062 vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
1063 return 0;
1064}
1065
1066static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan)
1067{
1068 int ret;
1069 struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
1070 struct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma;
1071 struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
1072
1073 if (fsl_queue->comp_pool && fsl_queue->desc_pool)
1074 return fsl_qdma->desc_allocated;
1075
1076 INIT_LIST_HEAD(&fsl_queue->comp_free);
1077
1078 /*
1079 * The dma pool for queue command buffer
1080 */
1081 fsl_queue->comp_pool =
1082 dma_pool_create("comp_pool",
1083 chan->device->dev,
1084 FSL_QDMA_COMMAND_BUFFER_SIZE,
1085 64, 0);
1086 if (!fsl_queue->comp_pool)
1087 return -ENOMEM;
1088
1089 /*
1090 * The dma pool for Descriptor(SD/DD) buffer
1091 */
1092 fsl_queue->desc_pool =
1093 dma_pool_create("desc_pool",
1094 chan->device->dev,
1095 FSL_QDMA_DESCRIPTOR_BUFFER_SIZE,
1096 32, 0);
1097 if (!fsl_queue->desc_pool)
1098 goto err_desc_pool;
1099
1100 ret = fsl_qdma_pre_request_enqueue_desc(fsl_queue);
1101 if (ret) {
1102 dev_err(chan->device->dev,
1103 "failed to alloc dma buffer for S/G descriptor\n");
1104 goto err_mem;
1105 }
1106
1107 fsl_qdma->desc_allocated++;
1108 return fsl_qdma->desc_allocated;
1109
1110err_mem:
1111 dma_pool_destroy(fsl_queue->desc_pool);
1112err_desc_pool:
1113 dma_pool_destroy(fsl_queue->comp_pool);
1114 return -ENOMEM;
1115}
1116
1117static int fsl_qdma_probe(struct platform_device *pdev)
1118{
1119 int ret, i;
1120 int blk_num, blk_off;
1121 u32 len, chans, queues;
1122 struct fsl_qdma_chan *fsl_chan;
1123 struct fsl_qdma_engine *fsl_qdma;
1124 struct device_node *np = pdev->dev.of_node;
1125
1126 ret = of_property_read_u32(np, "dma-channels", &chans);
1127 if (ret) {
1128 dev_err(&pdev->dev, "Can't get dma-channels.\n");
1129 return ret;
1130 }
1131
1132 ret = of_property_read_u32(np, "block-offset", &blk_off);
1133 if (ret) {
1134 dev_err(&pdev->dev, "Can't get block-offset.\n");
1135 return ret;
1136 }
1137
1138 ret = of_property_read_u32(np, "block-number", &blk_num);
1139 if (ret) {
1140 dev_err(&pdev->dev, "Can't get block-number.\n");
1141 return ret;
1142 }
1143
1144 blk_num = min_t(int, blk_num, num_online_cpus());
1145
1146 len = sizeof(*fsl_qdma);
1147 fsl_qdma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1148 if (!fsl_qdma)
1149 return -ENOMEM;
1150
1151 len = sizeof(*fsl_chan) * chans;
1152 fsl_qdma->chans = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1153 if (!fsl_qdma->chans)
1154 return -ENOMEM;
1155
1156 len = sizeof(struct fsl_qdma_queue *) * blk_num;
1157 fsl_qdma->status = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1158 if (!fsl_qdma->status)
1159 return -ENOMEM;
1160
1161 len = sizeof(int) * blk_num;
1162 fsl_qdma->queue_irq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1163 if (!fsl_qdma->queue_irq)
1164 return -ENOMEM;
1165
1166 ret = of_property_read_u32(np, "fsl,dma-queues", &queues);
1167 if (ret) {
1168 dev_err(&pdev->dev, "Can't get queues.\n");
1169 return ret;
1170 }
1171
1172 fsl_qdma->desc_allocated = 0;
1173 fsl_qdma->n_chans = chans;
1174 fsl_qdma->n_queues = queues;
1175 fsl_qdma->block_number = blk_num;
1176 fsl_qdma->block_offset = blk_off;
1177
1178 mutex_init(&fsl_qdma->fsl_qdma_mutex);
1179
1180 for (i = 0; i < fsl_qdma->block_number; i++) {
1181 fsl_qdma->status[i] = fsl_qdma_prep_status_queue(pdev);
1182 if (!fsl_qdma->status[i])
1183 return -ENOMEM;
1184 }
1185 fsl_qdma->ctrl_base = devm_platform_ioremap_resource(pdev, 0);
1186 if (IS_ERR(fsl_qdma->ctrl_base))
1187 return PTR_ERR(fsl_qdma->ctrl_base);
1188
1189 fsl_qdma->status_base = devm_platform_ioremap_resource(pdev, 1);
1190 if (IS_ERR(fsl_qdma->status_base))
1191 return PTR_ERR(fsl_qdma->status_base);
1192
1193 fsl_qdma->block_base = devm_platform_ioremap_resource(pdev, 2);
1194 if (IS_ERR(fsl_qdma->block_base))
1195 return PTR_ERR(fsl_qdma->block_base);
1196 fsl_qdma->queue = fsl_qdma_alloc_queue_resources(pdev, fsl_qdma);
1197 if (!fsl_qdma->queue)
1198 return -ENOMEM;
1199
1200 fsl_qdma->irq_base = platform_get_irq_byname(pdev, "qdma-queue0");
1201 if (fsl_qdma->irq_base < 0)
1202 return fsl_qdma->irq_base;
1203
1204 fsl_qdma->feature = of_property_read_bool(np, "big-endian");
1205 INIT_LIST_HEAD(&fsl_qdma->dma_dev.channels);
1206
1207 for (i = 0; i < fsl_qdma->n_chans; i++) {
1208 struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i];
1209
1210 fsl_chan->qdma = fsl_qdma;
1211 fsl_chan->queue = fsl_qdma->queue + i % (fsl_qdma->n_queues *
1212 fsl_qdma->block_number);
1213 fsl_chan->vchan.desc_free = fsl_qdma_free_desc;
1214 vchan_init(&fsl_chan->vchan, &fsl_qdma->dma_dev);
1215 }
1216
1217 dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
1218
1219 fsl_qdma->dma_dev.dev = &pdev->dev;
1220 fsl_qdma->dma_dev.device_free_chan_resources =
1221 fsl_qdma_free_chan_resources;
1222 fsl_qdma->dma_dev.device_alloc_chan_resources =
1223 fsl_qdma_alloc_chan_resources;
1224 fsl_qdma->dma_dev.device_tx_status = dma_cookie_status;
1225 fsl_qdma->dma_dev.device_prep_dma_memcpy = fsl_qdma_prep_memcpy;
1226 fsl_qdma->dma_dev.device_issue_pending = fsl_qdma_issue_pending;
1227 fsl_qdma->dma_dev.device_synchronize = fsl_qdma_synchronize;
1228 fsl_qdma->dma_dev.device_terminate_all = fsl_qdma_terminate_all;
1229
1230 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(40));
1231 if (ret) {
1232 dev_err(&pdev->dev, "dma_set_mask failure.\n");
1233 return ret;
1234 }
1235
1236 platform_set_drvdata(pdev, fsl_qdma);
1237
1238 ret = fsl_qdma_reg_init(fsl_qdma);
1239 if (ret) {
1240 dev_err(&pdev->dev, "Can't Initialize the qDMA engine.\n");
1241 return ret;
1242 }
1243
1244 ret = fsl_qdma_irq_init(pdev, fsl_qdma);
1245 if (ret)
1246 return ret;
1247
1248 ret = dma_async_device_register(&fsl_qdma->dma_dev);
1249 if (ret) {
1250 dev_err(&pdev->dev, "Can't register NXP Layerscape qDMA engine.\n");
1251 return ret;
1252 }
1253
1254 return 0;
1255}
1256
1257static void fsl_qdma_cleanup_vchan(struct dma_device *dmadev)
1258{
1259 struct fsl_qdma_chan *chan, *_chan;
1260
1261 list_for_each_entry_safe(chan, _chan,
1262 &dmadev->channels, vchan.chan.device_node) {
1263 list_del(&chan->vchan.chan.device_node);
1264 tasklet_kill(&chan->vchan.task);
1265 }
1266}
1267
1268static void fsl_qdma_remove(struct platform_device *pdev)
1269{
1270 struct device_node *np = pdev->dev.of_node;
1271 struct fsl_qdma_engine *fsl_qdma = platform_get_drvdata(pdev);
1272
1273 fsl_qdma_irq_exit(pdev, fsl_qdma);
1274 fsl_qdma_cleanup_vchan(&fsl_qdma->dma_dev);
1275 of_dma_controller_free(np);
1276 dma_async_device_unregister(&fsl_qdma->dma_dev);
1277}
1278
1279static const struct of_device_id fsl_qdma_dt_ids[] = {
1280 { .compatible = "fsl,ls1021a-qdma", },
1281 { /* sentinel */ }
1282};
1283MODULE_DEVICE_TABLE(of, fsl_qdma_dt_ids);
1284
1285static struct platform_driver fsl_qdma_driver = {
1286 .driver = {
1287 .name = "fsl-qdma",
1288 .of_match_table = fsl_qdma_dt_ids,
1289 },
1290 .probe = fsl_qdma_probe,
1291 .remove_new = fsl_qdma_remove,
1292};
1293
1294module_platform_driver(fsl_qdma_driver);
1295
1296MODULE_ALIAS("platform:fsl-qdma");
1297MODULE_LICENSE("GPL v2");
1298MODULE_DESCRIPTION("NXP Layerscape qDMA engine driver");
1// SPDX-License-Identifier: GPL-2.0
2// Copyright 2014-2015 Freescale
3// Copyright 2018 NXP
4
5/*
6 * Driver for NXP Layerscape Queue Direct Memory Access Controller
7 *
8 * Author:
9 * Wen He <wen.he_1@nxp.com>
10 * Jiaheng Fan <jiaheng.fan@nxp.com>
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/delay.h>
16#include <linux/of_irq.h>
17#include <linux/of_platform.h>
18#include <linux/of_dma.h>
19#include <linux/dma-mapping.h>
20
21#include "virt-dma.h"
22#include "fsldma.h"
23
24/* Register related definition */
25#define FSL_QDMA_DMR 0x0
26#define FSL_QDMA_DSR 0x4
27#define FSL_QDMA_DEIER 0xe00
28#define FSL_QDMA_DEDR 0xe04
29#define FSL_QDMA_DECFDW0R 0xe10
30#define FSL_QDMA_DECFDW1R 0xe14
31#define FSL_QDMA_DECFDW2R 0xe18
32#define FSL_QDMA_DECFDW3R 0xe1c
33#define FSL_QDMA_DECFQIDR 0xe30
34#define FSL_QDMA_DECBR 0xe34
35
36#define FSL_QDMA_BCQMR(x) (0xc0 + 0x100 * (x))
37#define FSL_QDMA_BCQSR(x) (0xc4 + 0x100 * (x))
38#define FSL_QDMA_BCQEDPA_SADDR(x) (0xc8 + 0x100 * (x))
39#define FSL_QDMA_BCQDPA_SADDR(x) (0xcc + 0x100 * (x))
40#define FSL_QDMA_BCQEEPA_SADDR(x) (0xd0 + 0x100 * (x))
41#define FSL_QDMA_BCQEPA_SADDR(x) (0xd4 + 0x100 * (x))
42#define FSL_QDMA_BCQIER(x) (0xe0 + 0x100 * (x))
43#define FSL_QDMA_BCQIDR(x) (0xe4 + 0x100 * (x))
44
45#define FSL_QDMA_SQDPAR 0x80c
46#define FSL_QDMA_SQEPAR 0x814
47#define FSL_QDMA_BSQMR 0x800
48#define FSL_QDMA_BSQSR 0x804
49#define FSL_QDMA_BSQICR 0x828
50#define FSL_QDMA_CQMR 0xa00
51#define FSL_QDMA_CQDSCR1 0xa08
52#define FSL_QDMA_CQDSCR2 0xa0c
53#define FSL_QDMA_CQIER 0xa10
54#define FSL_QDMA_CQEDR 0xa14
55#define FSL_QDMA_SQCCMR 0xa20
56
57/* Registers for bit and genmask */
58#define FSL_QDMA_CQIDR_SQT BIT(15)
59#define QDMA_CCDF_FOTMAT BIT(29)
60#define QDMA_CCDF_SER BIT(30)
61#define QDMA_SG_FIN BIT(30)
62#define QDMA_SG_LEN_MASK GENMASK(29, 0)
63#define QDMA_CCDF_MASK GENMASK(28, 20)
64
65#define FSL_QDMA_DEDR_CLEAR GENMASK(31, 0)
66#define FSL_QDMA_BCQIDR_CLEAR GENMASK(31, 0)
67#define FSL_QDMA_DEIER_CLEAR GENMASK(31, 0)
68
69#define FSL_QDMA_BCQIER_CQTIE BIT(15)
70#define FSL_QDMA_BCQIER_CQPEIE BIT(23)
71#define FSL_QDMA_BSQICR_ICEN BIT(31)
72
73#define FSL_QDMA_BSQICR_ICST(x) ((x) << 16)
74#define FSL_QDMA_CQIER_MEIE BIT(31)
75#define FSL_QDMA_CQIER_TEIE BIT(0)
76#define FSL_QDMA_SQCCMR_ENTER_WM BIT(21)
77
78#define FSL_QDMA_BCQMR_EN BIT(31)
79#define FSL_QDMA_BCQMR_EI BIT(30)
80#define FSL_QDMA_BCQMR_CD_THLD(x) ((x) << 20)
81#define FSL_QDMA_BCQMR_CQ_SIZE(x) ((x) << 16)
82
83#define FSL_QDMA_BCQSR_QF BIT(16)
84#define FSL_QDMA_BCQSR_XOFF BIT(0)
85
86#define FSL_QDMA_BSQMR_EN BIT(31)
87#define FSL_QDMA_BSQMR_DI BIT(30)
88#define FSL_QDMA_BSQMR_CQ_SIZE(x) ((x) << 16)
89
90#define FSL_QDMA_BSQSR_QE BIT(17)
91
92#define FSL_QDMA_DMR_DQD BIT(30)
93#define FSL_QDMA_DSR_DB BIT(31)
94
95/* Size related definition */
96#define FSL_QDMA_QUEUE_MAX 8
97#define FSL_QDMA_COMMAND_BUFFER_SIZE 64
98#define FSL_QDMA_DESCRIPTOR_BUFFER_SIZE 32
99#define FSL_QDMA_CIRCULAR_DESC_SIZE_MIN 64
100#define FSL_QDMA_CIRCULAR_DESC_SIZE_MAX 16384
101#define FSL_QDMA_QUEUE_NUM_MAX 8
102
103/* Field definition for CMD */
104#define FSL_QDMA_CMD_RWTTYPE 0x4
105#define FSL_QDMA_CMD_LWC 0x2
106#define FSL_QDMA_CMD_RWTTYPE_OFFSET 28
107#define FSL_QDMA_CMD_NS_OFFSET 27
108#define FSL_QDMA_CMD_DQOS_OFFSET 24
109#define FSL_QDMA_CMD_WTHROTL_OFFSET 20
110#define FSL_QDMA_CMD_DSEN_OFFSET 19
111#define FSL_QDMA_CMD_LWC_OFFSET 16
112
113/* Field definition for Descriptor offset */
114#define QDMA_CCDF_STATUS 20
115#define QDMA_CCDF_OFFSET 20
116#define QDMA_SDDF_CMD(x) (((u64)(x)) << 32)
117
118/* Field definition for safe loop count*/
119#define FSL_QDMA_HALT_COUNT 1500
120#define FSL_QDMA_MAX_SIZE 16385
121#define FSL_QDMA_COMP_TIMEOUT 1000
122#define FSL_COMMAND_QUEUE_OVERFLLOW 10
123
124#define FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma_engine, x) \
125 (((fsl_qdma_engine)->block_offset) * (x))
126
127/**
128 * struct fsl_qdma_format - This is the struct holding describing compound
129 * descriptor format with qDMA.
130 * @status: Command status and enqueue status notification.
131 * @cfg: Frame offset and frame format.
132 * @addr_lo: Holding the compound descriptor of the lower
133 * 32-bits address in memory 40-bit address.
134 * @addr_hi: Same as above member, but point high 8-bits in
135 * memory 40-bit address.
136 * @__reserved1: Reserved field.
137 * @cfg8b_w1: Compound descriptor command queue origin produced
138 * by qDMA and dynamic debug field.
139 * @data Pointer to the memory 40-bit address, describes DMA
140 * source information and DMA destination information.
141 */
142struct fsl_qdma_format {
143 __le32 status;
144 __le32 cfg;
145 union {
146 struct {
147 __le32 addr_lo;
148 u8 addr_hi;
149 u8 __reserved1[2];
150 u8 cfg8b_w1;
151 } __packed;
152 __le64 data;
153 };
154} __packed;
155
156/* qDMA status notification pre information */
157struct fsl_pre_status {
158 u64 addr;
159 u8 queue;
160};
161
162static DEFINE_PER_CPU(struct fsl_pre_status, pre);
163
164struct fsl_qdma_chan {
165 struct virt_dma_chan vchan;
166 struct virt_dma_desc vdesc;
167 enum dma_status status;
168 struct fsl_qdma_engine *qdma;
169 struct fsl_qdma_queue *queue;
170};
171
172struct fsl_qdma_queue {
173 struct fsl_qdma_format *virt_head;
174 struct fsl_qdma_format *virt_tail;
175 struct list_head comp_used;
176 struct list_head comp_free;
177 struct dma_pool *comp_pool;
178 struct dma_pool *desc_pool;
179 spinlock_t queue_lock;
180 dma_addr_t bus_addr;
181 u32 n_cq;
182 u32 id;
183 struct fsl_qdma_format *cq;
184 void __iomem *block_base;
185};
186
187struct fsl_qdma_comp {
188 dma_addr_t bus_addr;
189 dma_addr_t desc_bus_addr;
190 struct fsl_qdma_format *virt_addr;
191 struct fsl_qdma_format *desc_virt_addr;
192 struct fsl_qdma_chan *qchan;
193 struct virt_dma_desc vdesc;
194 struct list_head list;
195};
196
197struct fsl_qdma_engine {
198 struct dma_device dma_dev;
199 void __iomem *ctrl_base;
200 void __iomem *status_base;
201 void __iomem *block_base;
202 u32 n_chans;
203 u32 n_queues;
204 struct mutex fsl_qdma_mutex;
205 int error_irq;
206 int *queue_irq;
207 u32 feature;
208 struct fsl_qdma_queue *queue;
209 struct fsl_qdma_queue **status;
210 struct fsl_qdma_chan *chans;
211 int block_number;
212 int block_offset;
213 int irq_base;
214 int desc_allocated;
215
216};
217
218static inline u64
219qdma_ccdf_addr_get64(const struct fsl_qdma_format *ccdf)
220{
221 return le64_to_cpu(ccdf->data) & (U64_MAX >> 24);
222}
223
224static inline void
225qdma_desc_addr_set64(struct fsl_qdma_format *ccdf, u64 addr)
226{
227 ccdf->addr_hi = upper_32_bits(addr);
228 ccdf->addr_lo = cpu_to_le32(lower_32_bits(addr));
229}
230
231static inline u8
232qdma_ccdf_get_queue(const struct fsl_qdma_format *ccdf)
233{
234 return ccdf->cfg8b_w1 & U8_MAX;
235}
236
237static inline int
238qdma_ccdf_get_offset(const struct fsl_qdma_format *ccdf)
239{
240 return (le32_to_cpu(ccdf->cfg) & QDMA_CCDF_MASK) >> QDMA_CCDF_OFFSET;
241}
242
243static inline void
244qdma_ccdf_set_format(struct fsl_qdma_format *ccdf, int offset)
245{
246 ccdf->cfg = cpu_to_le32(QDMA_CCDF_FOTMAT | offset);
247}
248
249static inline int
250qdma_ccdf_get_status(const struct fsl_qdma_format *ccdf)
251{
252 return (le32_to_cpu(ccdf->status) & QDMA_CCDF_MASK) >> QDMA_CCDF_STATUS;
253}
254
255static inline void
256qdma_ccdf_set_ser(struct fsl_qdma_format *ccdf, int status)
257{
258 ccdf->status = cpu_to_le32(QDMA_CCDF_SER | status);
259}
260
261static inline void qdma_csgf_set_len(struct fsl_qdma_format *csgf, int len)
262{
263 csgf->cfg = cpu_to_le32(len & QDMA_SG_LEN_MASK);
264}
265
266static inline void qdma_csgf_set_f(struct fsl_qdma_format *csgf, int len)
267{
268 csgf->cfg = cpu_to_le32(QDMA_SG_FIN | (len & QDMA_SG_LEN_MASK));
269}
270
271static u32 qdma_readl(struct fsl_qdma_engine *qdma, void __iomem *addr)
272{
273 return FSL_DMA_IN(qdma, addr, 32);
274}
275
276static void qdma_writel(struct fsl_qdma_engine *qdma, u32 val,
277 void __iomem *addr)
278{
279 FSL_DMA_OUT(qdma, addr, val, 32);
280}
281
282static struct fsl_qdma_chan *to_fsl_qdma_chan(struct dma_chan *chan)
283{
284 return container_of(chan, struct fsl_qdma_chan, vchan.chan);
285}
286
287static struct fsl_qdma_comp *to_fsl_qdma_comp(struct virt_dma_desc *vd)
288{
289 return container_of(vd, struct fsl_qdma_comp, vdesc);
290}
291
292static void fsl_qdma_free_chan_resources(struct dma_chan *chan)
293{
294 struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
295 struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
296 struct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma;
297 struct fsl_qdma_comp *comp_temp, *_comp_temp;
298 unsigned long flags;
299 LIST_HEAD(head);
300
301 spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
302 vchan_get_all_descriptors(&fsl_chan->vchan, &head);
303 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
304
305 vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
306
307 if (!fsl_queue->comp_pool && !fsl_queue->comp_pool)
308 return;
309
310 list_for_each_entry_safe(comp_temp, _comp_temp,
311 &fsl_queue->comp_used, list) {
312 dma_pool_free(fsl_queue->comp_pool,
313 comp_temp->virt_addr,
314 comp_temp->bus_addr);
315 dma_pool_free(fsl_queue->desc_pool,
316 comp_temp->desc_virt_addr,
317 comp_temp->desc_bus_addr);
318 list_del(&comp_temp->list);
319 kfree(comp_temp);
320 }
321
322 list_for_each_entry_safe(comp_temp, _comp_temp,
323 &fsl_queue->comp_free, list) {
324 dma_pool_free(fsl_queue->comp_pool,
325 comp_temp->virt_addr,
326 comp_temp->bus_addr);
327 dma_pool_free(fsl_queue->desc_pool,
328 comp_temp->desc_virt_addr,
329 comp_temp->desc_bus_addr);
330 list_del(&comp_temp->list);
331 kfree(comp_temp);
332 }
333
334 dma_pool_destroy(fsl_queue->comp_pool);
335 dma_pool_destroy(fsl_queue->desc_pool);
336
337 fsl_qdma->desc_allocated--;
338 fsl_queue->comp_pool = NULL;
339 fsl_queue->desc_pool = NULL;
340}
341
342static void fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp *fsl_comp,
343 dma_addr_t dst, dma_addr_t src, u32 len)
344{
345 u32 cmd;
346 struct fsl_qdma_format *sdf, *ddf;
347 struct fsl_qdma_format *ccdf, *csgf_desc, *csgf_src, *csgf_dest;
348
349 ccdf = fsl_comp->virt_addr;
350 csgf_desc = fsl_comp->virt_addr + 1;
351 csgf_src = fsl_comp->virt_addr + 2;
352 csgf_dest = fsl_comp->virt_addr + 3;
353 sdf = fsl_comp->desc_virt_addr;
354 ddf = fsl_comp->desc_virt_addr + 1;
355
356 memset(fsl_comp->virt_addr, 0, FSL_QDMA_COMMAND_BUFFER_SIZE);
357 memset(fsl_comp->desc_virt_addr, 0, FSL_QDMA_DESCRIPTOR_BUFFER_SIZE);
358 /* Head Command Descriptor(Frame Descriptor) */
359 qdma_desc_addr_set64(ccdf, fsl_comp->bus_addr + 16);
360 qdma_ccdf_set_format(ccdf, qdma_ccdf_get_offset(ccdf));
361 qdma_ccdf_set_ser(ccdf, qdma_ccdf_get_status(ccdf));
362 /* Status notification is enqueued to status queue. */
363 /* Compound Command Descriptor(Frame List Table) */
364 qdma_desc_addr_set64(csgf_desc, fsl_comp->desc_bus_addr);
365 /* It must be 32 as Compound S/G Descriptor */
366 qdma_csgf_set_len(csgf_desc, 32);
367 qdma_desc_addr_set64(csgf_src, src);
368 qdma_csgf_set_len(csgf_src, len);
369 qdma_desc_addr_set64(csgf_dest, dst);
370 qdma_csgf_set_len(csgf_dest, len);
371 /* This entry is the last entry. */
372 qdma_csgf_set_f(csgf_dest, len);
373 /* Descriptor Buffer */
374 cmd = cpu_to_le32(FSL_QDMA_CMD_RWTTYPE <<
375 FSL_QDMA_CMD_RWTTYPE_OFFSET);
376 sdf->data = QDMA_SDDF_CMD(cmd);
377
378 cmd = cpu_to_le32(FSL_QDMA_CMD_RWTTYPE <<
379 FSL_QDMA_CMD_RWTTYPE_OFFSET);
380 cmd |= cpu_to_le32(FSL_QDMA_CMD_LWC << FSL_QDMA_CMD_LWC_OFFSET);
381 ddf->data = QDMA_SDDF_CMD(cmd);
382}
383
384/*
385 * Pre-request full command descriptor for enqueue.
386 */
387static int fsl_qdma_pre_request_enqueue_desc(struct fsl_qdma_queue *queue)
388{
389 int i;
390 struct fsl_qdma_comp *comp_temp, *_comp_temp;
391
392 for (i = 0; i < queue->n_cq + FSL_COMMAND_QUEUE_OVERFLLOW; i++) {
393 comp_temp = kzalloc(sizeof(*comp_temp), GFP_KERNEL);
394 if (!comp_temp)
395 goto err_alloc;
396 comp_temp->virt_addr =
397 dma_pool_alloc(queue->comp_pool, GFP_KERNEL,
398 &comp_temp->bus_addr);
399 if (!comp_temp->virt_addr)
400 goto err_dma_alloc;
401
402 comp_temp->desc_virt_addr =
403 dma_pool_alloc(queue->desc_pool, GFP_KERNEL,
404 &comp_temp->desc_bus_addr);
405 if (!comp_temp->desc_virt_addr)
406 goto err_desc_dma_alloc;
407
408 list_add_tail(&comp_temp->list, &queue->comp_free);
409 }
410
411 return 0;
412
413err_desc_dma_alloc:
414 dma_pool_free(queue->comp_pool, comp_temp->virt_addr,
415 comp_temp->bus_addr);
416
417err_dma_alloc:
418 kfree(comp_temp);
419
420err_alloc:
421 list_for_each_entry_safe(comp_temp, _comp_temp,
422 &queue->comp_free, list) {
423 if (comp_temp->virt_addr)
424 dma_pool_free(queue->comp_pool,
425 comp_temp->virt_addr,
426 comp_temp->bus_addr);
427 if (comp_temp->desc_virt_addr)
428 dma_pool_free(queue->desc_pool,
429 comp_temp->desc_virt_addr,
430 comp_temp->desc_bus_addr);
431
432 list_del(&comp_temp->list);
433 kfree(comp_temp);
434 }
435
436 return -ENOMEM;
437}
438
439/*
440 * Request a command descriptor for enqueue.
441 */
442static struct fsl_qdma_comp
443*fsl_qdma_request_enqueue_desc(struct fsl_qdma_chan *fsl_chan)
444{
445 unsigned long flags;
446 struct fsl_qdma_comp *comp_temp;
447 int timeout = FSL_QDMA_COMP_TIMEOUT;
448 struct fsl_qdma_queue *queue = fsl_chan->queue;
449
450 while (timeout--) {
451 spin_lock_irqsave(&queue->queue_lock, flags);
452 if (!list_empty(&queue->comp_free)) {
453 comp_temp = list_first_entry(&queue->comp_free,
454 struct fsl_qdma_comp,
455 list);
456 list_del(&comp_temp->list);
457
458 spin_unlock_irqrestore(&queue->queue_lock, flags);
459 comp_temp->qchan = fsl_chan;
460 return comp_temp;
461 }
462 spin_unlock_irqrestore(&queue->queue_lock, flags);
463 udelay(1);
464 }
465
466 return NULL;
467}
468
469static struct fsl_qdma_queue
470*fsl_qdma_alloc_queue_resources(struct platform_device *pdev,
471 struct fsl_qdma_engine *fsl_qdma)
472{
473 int ret, len, i, j;
474 int queue_num, block_number;
475 unsigned int queue_size[FSL_QDMA_QUEUE_MAX];
476 struct fsl_qdma_queue *queue_head, *queue_temp;
477
478 queue_num = fsl_qdma->n_queues;
479 block_number = fsl_qdma->block_number;
480
481 if (queue_num > FSL_QDMA_QUEUE_MAX)
482 queue_num = FSL_QDMA_QUEUE_MAX;
483 len = sizeof(*queue_head) * queue_num * block_number;
484 queue_head = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
485 if (!queue_head)
486 return NULL;
487
488 ret = device_property_read_u32_array(&pdev->dev, "queue-sizes",
489 queue_size, queue_num);
490 if (ret) {
491 dev_err(&pdev->dev, "Can't get queue-sizes.\n");
492 return NULL;
493 }
494 for (j = 0; j < block_number; j++) {
495 for (i = 0; i < queue_num; i++) {
496 if (queue_size[i] > FSL_QDMA_CIRCULAR_DESC_SIZE_MAX ||
497 queue_size[i] < FSL_QDMA_CIRCULAR_DESC_SIZE_MIN) {
498 dev_err(&pdev->dev,
499 "Get wrong queue-sizes.\n");
500 return NULL;
501 }
502 queue_temp = queue_head + i + (j * queue_num);
503
504 queue_temp->cq =
505 dma_alloc_coherent(&pdev->dev,
506 sizeof(struct fsl_qdma_format) *
507 queue_size[i],
508 &queue_temp->bus_addr,
509 GFP_KERNEL);
510 if (!queue_temp->cq)
511 return NULL;
512 queue_temp->block_base = fsl_qdma->block_base +
513 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
514 queue_temp->n_cq = queue_size[i];
515 queue_temp->id = i;
516 queue_temp->virt_head = queue_temp->cq;
517 queue_temp->virt_tail = queue_temp->cq;
518 /*
519 * List for queue command buffer
520 */
521 INIT_LIST_HEAD(&queue_temp->comp_used);
522 spin_lock_init(&queue_temp->queue_lock);
523 }
524 }
525 return queue_head;
526}
527
528static struct fsl_qdma_queue
529*fsl_qdma_prep_status_queue(struct platform_device *pdev)
530{
531 int ret;
532 unsigned int status_size;
533 struct fsl_qdma_queue *status_head;
534 struct device_node *np = pdev->dev.of_node;
535
536 ret = of_property_read_u32(np, "status-sizes", &status_size);
537 if (ret) {
538 dev_err(&pdev->dev, "Can't get status-sizes.\n");
539 return NULL;
540 }
541 if (status_size > FSL_QDMA_CIRCULAR_DESC_SIZE_MAX ||
542 status_size < FSL_QDMA_CIRCULAR_DESC_SIZE_MIN) {
543 dev_err(&pdev->dev, "Get wrong status_size.\n");
544 return NULL;
545 }
546 status_head = devm_kzalloc(&pdev->dev,
547 sizeof(*status_head), GFP_KERNEL);
548 if (!status_head)
549 return NULL;
550
551 /*
552 * Buffer for queue command
553 */
554 status_head->cq = dma_alloc_coherent(&pdev->dev,
555 sizeof(struct fsl_qdma_format) *
556 status_size,
557 &status_head->bus_addr,
558 GFP_KERNEL);
559 if (!status_head->cq) {
560 devm_kfree(&pdev->dev, status_head);
561 return NULL;
562 }
563 status_head->n_cq = status_size;
564 status_head->virt_head = status_head->cq;
565 status_head->virt_tail = status_head->cq;
566 status_head->comp_pool = NULL;
567
568 return status_head;
569}
570
571static int fsl_qdma_halt(struct fsl_qdma_engine *fsl_qdma)
572{
573 u32 reg;
574 int i, j, count = FSL_QDMA_HALT_COUNT;
575 void __iomem *block, *ctrl = fsl_qdma->ctrl_base;
576
577 /* Disable the command queue and wait for idle state. */
578 reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR);
579 reg |= FSL_QDMA_DMR_DQD;
580 qdma_writel(fsl_qdma, reg, ctrl + FSL_QDMA_DMR);
581 for (j = 0; j < fsl_qdma->block_number; j++) {
582 block = fsl_qdma->block_base +
583 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
584 for (i = 0; i < FSL_QDMA_QUEUE_NUM_MAX; i++)
585 qdma_writel(fsl_qdma, 0, block + FSL_QDMA_BCQMR(i));
586 }
587 while (1) {
588 reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DSR);
589 if (!(reg & FSL_QDMA_DSR_DB))
590 break;
591 if (count-- < 0)
592 return -EBUSY;
593 udelay(100);
594 }
595
596 for (j = 0; j < fsl_qdma->block_number; j++) {
597 block = fsl_qdma->block_base +
598 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
599
600 /* Disable status queue. */
601 qdma_writel(fsl_qdma, 0, block + FSL_QDMA_BSQMR);
602
603 /*
604 * clear the command queue interrupt detect register for
605 * all queues.
606 */
607 qdma_writel(fsl_qdma, FSL_QDMA_BCQIDR_CLEAR,
608 block + FSL_QDMA_BCQIDR(0));
609 }
610
611 return 0;
612}
613
614static int
615fsl_qdma_queue_transfer_complete(struct fsl_qdma_engine *fsl_qdma,
616 void *block,
617 int id)
618{
619 bool duplicate;
620 u32 reg, i, count;
621 struct fsl_qdma_queue *temp_queue;
622 struct fsl_qdma_format *status_addr;
623 struct fsl_qdma_comp *fsl_comp = NULL;
624 struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;
625 struct fsl_qdma_queue *fsl_status = fsl_qdma->status[id];
626
627 count = FSL_QDMA_MAX_SIZE;
628
629 while (count--) {
630 duplicate = 0;
631 reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQSR);
632 if (reg & FSL_QDMA_BSQSR_QE)
633 return 0;
634
635 status_addr = fsl_status->virt_head;
636
637 if (qdma_ccdf_get_queue(status_addr) ==
638 __this_cpu_read(pre.queue) &&
639 qdma_ccdf_addr_get64(status_addr) ==
640 __this_cpu_read(pre.addr))
641 duplicate = 1;
642 i = qdma_ccdf_get_queue(status_addr) +
643 id * fsl_qdma->n_queues;
644 __this_cpu_write(pre.addr, qdma_ccdf_addr_get64(status_addr));
645 __this_cpu_write(pre.queue, qdma_ccdf_get_queue(status_addr));
646 temp_queue = fsl_queue + i;
647
648 spin_lock(&temp_queue->queue_lock);
649 if (list_empty(&temp_queue->comp_used)) {
650 if (!duplicate) {
651 spin_unlock(&temp_queue->queue_lock);
652 return -EAGAIN;
653 }
654 } else {
655 fsl_comp = list_first_entry(&temp_queue->comp_used,
656 struct fsl_qdma_comp, list);
657 if (fsl_comp->bus_addr + 16 !=
658 __this_cpu_read(pre.addr)) {
659 if (!duplicate) {
660 spin_unlock(&temp_queue->queue_lock);
661 return -EAGAIN;
662 }
663 }
664 }
665
666 if (duplicate) {
667 reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQMR);
668 reg |= FSL_QDMA_BSQMR_DI;
669 qdma_desc_addr_set64(status_addr, 0x0);
670 fsl_status->virt_head++;
671 if (fsl_status->virt_head == fsl_status->cq
672 + fsl_status->n_cq)
673 fsl_status->virt_head = fsl_status->cq;
674 qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BSQMR);
675 spin_unlock(&temp_queue->queue_lock);
676 continue;
677 }
678 list_del(&fsl_comp->list);
679
680 reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQMR);
681 reg |= FSL_QDMA_BSQMR_DI;
682 qdma_desc_addr_set64(status_addr, 0x0);
683 fsl_status->virt_head++;
684 if (fsl_status->virt_head == fsl_status->cq + fsl_status->n_cq)
685 fsl_status->virt_head = fsl_status->cq;
686 qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BSQMR);
687 spin_unlock(&temp_queue->queue_lock);
688
689 spin_lock(&fsl_comp->qchan->vchan.lock);
690 vchan_cookie_complete(&fsl_comp->vdesc);
691 fsl_comp->qchan->status = DMA_COMPLETE;
692 spin_unlock(&fsl_comp->qchan->vchan.lock);
693 }
694
695 return 0;
696}
697
698static irqreturn_t fsl_qdma_error_handler(int irq, void *dev_id)
699{
700 unsigned int intr;
701 struct fsl_qdma_engine *fsl_qdma = dev_id;
702 void __iomem *status = fsl_qdma->status_base;
703
704 intr = qdma_readl(fsl_qdma, status + FSL_QDMA_DEDR);
705
706 if (intr)
707 dev_err(fsl_qdma->dma_dev.dev, "DMA transaction error!\n");
708
709 qdma_writel(fsl_qdma, FSL_QDMA_DEDR_CLEAR, status + FSL_QDMA_DEDR);
710 return IRQ_HANDLED;
711}
712
713static irqreturn_t fsl_qdma_queue_handler(int irq, void *dev_id)
714{
715 int id;
716 unsigned int intr, reg;
717 struct fsl_qdma_engine *fsl_qdma = dev_id;
718 void __iomem *block, *ctrl = fsl_qdma->ctrl_base;
719
720 id = irq - fsl_qdma->irq_base;
721 if (id < 0 && id > fsl_qdma->block_number) {
722 dev_err(fsl_qdma->dma_dev.dev,
723 "irq %d is wrong irq_base is %d\n",
724 irq, fsl_qdma->irq_base);
725 }
726
727 block = fsl_qdma->block_base +
728 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, id);
729
730 intr = qdma_readl(fsl_qdma, block + FSL_QDMA_BCQIDR(0));
731
732 if ((intr & FSL_QDMA_CQIDR_SQT) != 0)
733 intr = fsl_qdma_queue_transfer_complete(fsl_qdma, block, id);
734
735 if (intr != 0) {
736 reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR);
737 reg |= FSL_QDMA_DMR_DQD;
738 qdma_writel(fsl_qdma, reg, ctrl + FSL_QDMA_DMR);
739 qdma_writel(fsl_qdma, 0, block + FSL_QDMA_BCQIER(0));
740 dev_err(fsl_qdma->dma_dev.dev, "QDMA: status err!\n");
741 }
742
743 /* Clear all detected events and interrupts. */
744 qdma_writel(fsl_qdma, FSL_QDMA_BCQIDR_CLEAR,
745 block + FSL_QDMA_BCQIDR(0));
746
747 return IRQ_HANDLED;
748}
749
750static int
751fsl_qdma_irq_init(struct platform_device *pdev,
752 struct fsl_qdma_engine *fsl_qdma)
753{
754 int i;
755 int cpu;
756 int ret;
757 char irq_name[20];
758
759 fsl_qdma->error_irq =
760 platform_get_irq_byname(pdev, "qdma-error");
761 if (fsl_qdma->error_irq < 0)
762 return fsl_qdma->error_irq;
763
764 ret = devm_request_irq(&pdev->dev, fsl_qdma->error_irq,
765 fsl_qdma_error_handler, 0,
766 "qDMA error", fsl_qdma);
767 if (ret) {
768 dev_err(&pdev->dev, "Can't register qDMA controller IRQ.\n");
769 return ret;
770 }
771
772 for (i = 0; i < fsl_qdma->block_number; i++) {
773 sprintf(irq_name, "qdma-queue%d", i);
774 fsl_qdma->queue_irq[i] =
775 platform_get_irq_byname(pdev, irq_name);
776
777 if (fsl_qdma->queue_irq[i] < 0)
778 return fsl_qdma->queue_irq[i];
779
780 ret = devm_request_irq(&pdev->dev,
781 fsl_qdma->queue_irq[i],
782 fsl_qdma_queue_handler,
783 0,
784 "qDMA queue",
785 fsl_qdma);
786 if (ret) {
787 dev_err(&pdev->dev,
788 "Can't register qDMA queue IRQ.\n");
789 return ret;
790 }
791
792 cpu = i % num_online_cpus();
793 ret = irq_set_affinity_hint(fsl_qdma->queue_irq[i],
794 get_cpu_mask(cpu));
795 if (ret) {
796 dev_err(&pdev->dev,
797 "Can't set cpu %d affinity to IRQ %d.\n",
798 cpu,
799 fsl_qdma->queue_irq[i]);
800 return ret;
801 }
802 }
803
804 return 0;
805}
806
807static void fsl_qdma_irq_exit(struct platform_device *pdev,
808 struct fsl_qdma_engine *fsl_qdma)
809{
810 int i;
811
812 devm_free_irq(&pdev->dev, fsl_qdma->error_irq, fsl_qdma);
813 for (i = 0; i < fsl_qdma->block_number; i++)
814 devm_free_irq(&pdev->dev, fsl_qdma->queue_irq[i], fsl_qdma);
815}
816
817static int fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)
818{
819 u32 reg;
820 int i, j, ret;
821 struct fsl_qdma_queue *temp;
822 void __iomem *status = fsl_qdma->status_base;
823 void __iomem *block, *ctrl = fsl_qdma->ctrl_base;
824 struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;
825
826 /* Try to halt the qDMA engine first. */
827 ret = fsl_qdma_halt(fsl_qdma);
828 if (ret) {
829 dev_err(fsl_qdma->dma_dev.dev, "DMA halt failed!");
830 return ret;
831 }
832
833 for (i = 0; i < fsl_qdma->block_number; i++) {
834 /*
835 * Clear the command queue interrupt detect register for
836 * all queues.
837 */
838
839 block = fsl_qdma->block_base +
840 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, i);
841 qdma_writel(fsl_qdma, FSL_QDMA_BCQIDR_CLEAR,
842 block + FSL_QDMA_BCQIDR(0));
843 }
844
845 for (j = 0; j < fsl_qdma->block_number; j++) {
846 block = fsl_qdma->block_base +
847 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
848 for (i = 0; i < fsl_qdma->n_queues; i++) {
849 temp = fsl_queue + i + (j * fsl_qdma->n_queues);
850 /*
851 * Initialize Command Queue registers to
852 * point to the first
853 * command descriptor in memory.
854 * Dequeue Pointer Address Registers
855 * Enqueue Pointer Address Registers
856 */
857
858 qdma_writel(fsl_qdma, temp->bus_addr,
859 block + FSL_QDMA_BCQDPA_SADDR(i));
860 qdma_writel(fsl_qdma, temp->bus_addr,
861 block + FSL_QDMA_BCQEPA_SADDR(i));
862
863 /* Initialize the queue mode. */
864 reg = FSL_QDMA_BCQMR_EN;
865 reg |= FSL_QDMA_BCQMR_CD_THLD(ilog2(temp->n_cq) - 4);
866 reg |= FSL_QDMA_BCQMR_CQ_SIZE(ilog2(temp->n_cq) - 6);
867 qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BCQMR(i));
868 }
869
870 /*
871 * Workaround for erratum: ERR010812.
872 * We must enable XOFF to avoid the enqueue rejection occurs.
873 * Setting SQCCMR ENTER_WM to 0x20.
874 */
875
876 qdma_writel(fsl_qdma, FSL_QDMA_SQCCMR_ENTER_WM,
877 block + FSL_QDMA_SQCCMR);
878
879 /*
880 * Initialize status queue registers to point to the first
881 * command descriptor in memory.
882 * Dequeue Pointer Address Registers
883 * Enqueue Pointer Address Registers
884 */
885
886 qdma_writel(fsl_qdma, fsl_qdma->status[j]->bus_addr,
887 block + FSL_QDMA_SQEPAR);
888 qdma_writel(fsl_qdma, fsl_qdma->status[j]->bus_addr,
889 block + FSL_QDMA_SQDPAR);
890 /* Initialize status queue interrupt. */
891 qdma_writel(fsl_qdma, FSL_QDMA_BCQIER_CQTIE,
892 block + FSL_QDMA_BCQIER(0));
893 qdma_writel(fsl_qdma, FSL_QDMA_BSQICR_ICEN |
894 FSL_QDMA_BSQICR_ICST(5) | 0x8000,
895 block + FSL_QDMA_BSQICR);
896 qdma_writel(fsl_qdma, FSL_QDMA_CQIER_MEIE |
897 FSL_QDMA_CQIER_TEIE,
898 block + FSL_QDMA_CQIER);
899
900 /* Initialize the status queue mode. */
901 reg = FSL_QDMA_BSQMR_EN;
902 reg |= FSL_QDMA_BSQMR_CQ_SIZE(ilog2
903 (fsl_qdma->status[j]->n_cq) - 6);
904
905 qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BSQMR);
906 reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQMR);
907 }
908
909 /* Initialize controller interrupt register. */
910 qdma_writel(fsl_qdma, FSL_QDMA_DEDR_CLEAR, status + FSL_QDMA_DEDR);
911 qdma_writel(fsl_qdma, FSL_QDMA_DEIER_CLEAR, status + FSL_QDMA_DEIER);
912
913 reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR);
914 reg &= ~FSL_QDMA_DMR_DQD;
915 qdma_writel(fsl_qdma, reg, ctrl + FSL_QDMA_DMR);
916
917 return 0;
918}
919
920static struct dma_async_tx_descriptor *
921fsl_qdma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst,
922 dma_addr_t src, size_t len, unsigned long flags)
923{
924 struct fsl_qdma_comp *fsl_comp;
925 struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
926
927 fsl_comp = fsl_qdma_request_enqueue_desc(fsl_chan);
928
929 if (!fsl_comp)
930 return NULL;
931
932 fsl_qdma_comp_fill_memcpy(fsl_comp, dst, src, len);
933
934 return vchan_tx_prep(&fsl_chan->vchan, &fsl_comp->vdesc, flags);
935}
936
937static void fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan)
938{
939 u32 reg;
940 struct virt_dma_desc *vdesc;
941 struct fsl_qdma_comp *fsl_comp;
942 struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
943 void __iomem *block = fsl_queue->block_base;
944
945 reg = qdma_readl(fsl_chan->qdma, block + FSL_QDMA_BCQSR(fsl_queue->id));
946 if (reg & (FSL_QDMA_BCQSR_QF | FSL_QDMA_BCQSR_XOFF))
947 return;
948 vdesc = vchan_next_desc(&fsl_chan->vchan);
949 if (!vdesc)
950 return;
951 list_del(&vdesc->node);
952 fsl_comp = to_fsl_qdma_comp(vdesc);
953
954 memcpy(fsl_queue->virt_head++,
955 fsl_comp->virt_addr, sizeof(struct fsl_qdma_format));
956 if (fsl_queue->virt_head == fsl_queue->cq + fsl_queue->n_cq)
957 fsl_queue->virt_head = fsl_queue->cq;
958
959 list_add_tail(&fsl_comp->list, &fsl_queue->comp_used);
960 barrier();
961 reg = qdma_readl(fsl_chan->qdma, block + FSL_QDMA_BCQMR(fsl_queue->id));
962 reg |= FSL_QDMA_BCQMR_EI;
963 qdma_writel(fsl_chan->qdma, reg, block + FSL_QDMA_BCQMR(fsl_queue->id));
964 fsl_chan->status = DMA_IN_PROGRESS;
965}
966
967static void fsl_qdma_free_desc(struct virt_dma_desc *vdesc)
968{
969 unsigned long flags;
970 struct fsl_qdma_comp *fsl_comp;
971 struct fsl_qdma_queue *fsl_queue;
972
973 fsl_comp = to_fsl_qdma_comp(vdesc);
974 fsl_queue = fsl_comp->qchan->queue;
975
976 spin_lock_irqsave(&fsl_queue->queue_lock, flags);
977 list_add_tail(&fsl_comp->list, &fsl_queue->comp_free);
978 spin_unlock_irqrestore(&fsl_queue->queue_lock, flags);
979}
980
981static void fsl_qdma_issue_pending(struct dma_chan *chan)
982{
983 unsigned long flags;
984 struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
985 struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
986
987 spin_lock_irqsave(&fsl_queue->queue_lock, flags);
988 spin_lock(&fsl_chan->vchan.lock);
989 if (vchan_issue_pending(&fsl_chan->vchan))
990 fsl_qdma_enqueue_desc(fsl_chan);
991 spin_unlock(&fsl_chan->vchan.lock);
992 spin_unlock_irqrestore(&fsl_queue->queue_lock, flags);
993}
994
995static void fsl_qdma_synchronize(struct dma_chan *chan)
996{
997 struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
998
999 vchan_synchronize(&fsl_chan->vchan);
1000}
1001
1002static int fsl_qdma_terminate_all(struct dma_chan *chan)
1003{
1004 LIST_HEAD(head);
1005 unsigned long flags;
1006 struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
1007
1008 spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
1009 vchan_get_all_descriptors(&fsl_chan->vchan, &head);
1010 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
1011 vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
1012 return 0;
1013}
1014
1015static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan)
1016{
1017 int ret;
1018 struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
1019 struct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma;
1020 struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
1021
1022 if (fsl_queue->comp_pool && fsl_queue->desc_pool)
1023 return fsl_qdma->desc_allocated;
1024
1025 INIT_LIST_HEAD(&fsl_queue->comp_free);
1026
1027 /*
1028 * The dma pool for queue command buffer
1029 */
1030 fsl_queue->comp_pool =
1031 dma_pool_create("comp_pool",
1032 chan->device->dev,
1033 FSL_QDMA_COMMAND_BUFFER_SIZE,
1034 64, 0);
1035 if (!fsl_queue->comp_pool)
1036 return -ENOMEM;
1037
1038 /*
1039 * The dma pool for Descriptor(SD/DD) buffer
1040 */
1041 fsl_queue->desc_pool =
1042 dma_pool_create("desc_pool",
1043 chan->device->dev,
1044 FSL_QDMA_DESCRIPTOR_BUFFER_SIZE,
1045 32, 0);
1046 if (!fsl_queue->desc_pool)
1047 goto err_desc_pool;
1048
1049 ret = fsl_qdma_pre_request_enqueue_desc(fsl_queue);
1050 if (ret) {
1051 dev_err(chan->device->dev,
1052 "failed to alloc dma buffer for S/G descriptor\n");
1053 goto err_mem;
1054 }
1055
1056 fsl_qdma->desc_allocated++;
1057 return fsl_qdma->desc_allocated;
1058
1059err_mem:
1060 dma_pool_destroy(fsl_queue->desc_pool);
1061err_desc_pool:
1062 dma_pool_destroy(fsl_queue->comp_pool);
1063 return -ENOMEM;
1064}
1065
1066static int fsl_qdma_probe(struct platform_device *pdev)
1067{
1068 int ret, i;
1069 int blk_num, blk_off;
1070 u32 len, chans, queues;
1071 struct resource *res;
1072 struct fsl_qdma_chan *fsl_chan;
1073 struct fsl_qdma_engine *fsl_qdma;
1074 struct device_node *np = pdev->dev.of_node;
1075
1076 ret = of_property_read_u32(np, "dma-channels", &chans);
1077 if (ret) {
1078 dev_err(&pdev->dev, "Can't get dma-channels.\n");
1079 return ret;
1080 }
1081
1082 ret = of_property_read_u32(np, "block-offset", &blk_off);
1083 if (ret) {
1084 dev_err(&pdev->dev, "Can't get block-offset.\n");
1085 return ret;
1086 }
1087
1088 ret = of_property_read_u32(np, "block-number", &blk_num);
1089 if (ret) {
1090 dev_err(&pdev->dev, "Can't get block-number.\n");
1091 return ret;
1092 }
1093
1094 blk_num = min_t(int, blk_num, num_online_cpus());
1095
1096 len = sizeof(*fsl_qdma);
1097 fsl_qdma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1098 if (!fsl_qdma)
1099 return -ENOMEM;
1100
1101 len = sizeof(*fsl_chan) * chans;
1102 fsl_qdma->chans = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1103 if (!fsl_qdma->chans)
1104 return -ENOMEM;
1105
1106 len = sizeof(struct fsl_qdma_queue *) * blk_num;
1107 fsl_qdma->status = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1108 if (!fsl_qdma->status)
1109 return -ENOMEM;
1110
1111 len = sizeof(int) * blk_num;
1112 fsl_qdma->queue_irq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1113 if (!fsl_qdma->queue_irq)
1114 return -ENOMEM;
1115
1116 ret = of_property_read_u32(np, "fsl,dma-queues", &queues);
1117 if (ret) {
1118 dev_err(&pdev->dev, "Can't get queues.\n");
1119 return ret;
1120 }
1121
1122 fsl_qdma->desc_allocated = 0;
1123 fsl_qdma->n_chans = chans;
1124 fsl_qdma->n_queues = queues;
1125 fsl_qdma->block_number = blk_num;
1126 fsl_qdma->block_offset = blk_off;
1127
1128 mutex_init(&fsl_qdma->fsl_qdma_mutex);
1129
1130 for (i = 0; i < fsl_qdma->block_number; i++) {
1131 fsl_qdma->status[i] = fsl_qdma_prep_status_queue(pdev);
1132 if (!fsl_qdma->status[i])
1133 return -ENOMEM;
1134 }
1135 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1136 fsl_qdma->ctrl_base = devm_ioremap_resource(&pdev->dev, res);
1137 if (IS_ERR(fsl_qdma->ctrl_base))
1138 return PTR_ERR(fsl_qdma->ctrl_base);
1139
1140 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1141 fsl_qdma->status_base = devm_ioremap_resource(&pdev->dev, res);
1142 if (IS_ERR(fsl_qdma->status_base))
1143 return PTR_ERR(fsl_qdma->status_base);
1144
1145 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1146 fsl_qdma->block_base = devm_ioremap_resource(&pdev->dev, res);
1147 if (IS_ERR(fsl_qdma->block_base))
1148 return PTR_ERR(fsl_qdma->block_base);
1149 fsl_qdma->queue = fsl_qdma_alloc_queue_resources(pdev, fsl_qdma);
1150 if (!fsl_qdma->queue)
1151 return -ENOMEM;
1152
1153 ret = fsl_qdma_irq_init(pdev, fsl_qdma);
1154 if (ret)
1155 return ret;
1156
1157 fsl_qdma->irq_base = platform_get_irq_byname(pdev, "qdma-queue0");
1158 fsl_qdma->feature = of_property_read_bool(np, "big-endian");
1159 INIT_LIST_HEAD(&fsl_qdma->dma_dev.channels);
1160
1161 for (i = 0; i < fsl_qdma->n_chans; i++) {
1162 struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i];
1163
1164 fsl_chan->qdma = fsl_qdma;
1165 fsl_chan->queue = fsl_qdma->queue + i % (fsl_qdma->n_queues *
1166 fsl_qdma->block_number);
1167 fsl_chan->vchan.desc_free = fsl_qdma_free_desc;
1168 vchan_init(&fsl_chan->vchan, &fsl_qdma->dma_dev);
1169 }
1170
1171 dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
1172
1173 fsl_qdma->dma_dev.dev = &pdev->dev;
1174 fsl_qdma->dma_dev.device_free_chan_resources =
1175 fsl_qdma_free_chan_resources;
1176 fsl_qdma->dma_dev.device_alloc_chan_resources =
1177 fsl_qdma_alloc_chan_resources;
1178 fsl_qdma->dma_dev.device_tx_status = dma_cookie_status;
1179 fsl_qdma->dma_dev.device_prep_dma_memcpy = fsl_qdma_prep_memcpy;
1180 fsl_qdma->dma_dev.device_issue_pending = fsl_qdma_issue_pending;
1181 fsl_qdma->dma_dev.device_synchronize = fsl_qdma_synchronize;
1182 fsl_qdma->dma_dev.device_terminate_all = fsl_qdma_terminate_all;
1183
1184 dma_set_mask(&pdev->dev, DMA_BIT_MASK(40));
1185
1186 platform_set_drvdata(pdev, fsl_qdma);
1187
1188 ret = dma_async_device_register(&fsl_qdma->dma_dev);
1189 if (ret) {
1190 dev_err(&pdev->dev,
1191 "Can't register NXP Layerscape qDMA engine.\n");
1192 return ret;
1193 }
1194
1195 ret = fsl_qdma_reg_init(fsl_qdma);
1196 if (ret) {
1197 dev_err(&pdev->dev, "Can't Initialize the qDMA engine.\n");
1198 return ret;
1199 }
1200
1201 return 0;
1202}
1203
1204static void fsl_qdma_cleanup_vchan(struct dma_device *dmadev)
1205{
1206 struct fsl_qdma_chan *chan, *_chan;
1207
1208 list_for_each_entry_safe(chan, _chan,
1209 &dmadev->channels, vchan.chan.device_node) {
1210 list_del(&chan->vchan.chan.device_node);
1211 tasklet_kill(&chan->vchan.task);
1212 }
1213}
1214
1215static int fsl_qdma_remove(struct platform_device *pdev)
1216{
1217 int i;
1218 struct fsl_qdma_queue *status;
1219 struct device_node *np = pdev->dev.of_node;
1220 struct fsl_qdma_engine *fsl_qdma = platform_get_drvdata(pdev);
1221
1222 fsl_qdma_irq_exit(pdev, fsl_qdma);
1223 fsl_qdma_cleanup_vchan(&fsl_qdma->dma_dev);
1224 of_dma_controller_free(np);
1225 dma_async_device_unregister(&fsl_qdma->dma_dev);
1226
1227 for (i = 0; i < fsl_qdma->block_number; i++) {
1228 status = fsl_qdma->status[i];
1229 dma_free_coherent(&pdev->dev, sizeof(struct fsl_qdma_format) *
1230 status->n_cq, status->cq, status->bus_addr);
1231 }
1232 return 0;
1233}
1234
1235static const struct of_device_id fsl_qdma_dt_ids[] = {
1236 { .compatible = "fsl,ls1021a-qdma", },
1237 { /* sentinel */ }
1238};
1239MODULE_DEVICE_TABLE(of, fsl_qdma_dt_ids);
1240
1241static struct platform_driver fsl_qdma_driver = {
1242 .driver = {
1243 .name = "fsl-qdma",
1244 .of_match_table = fsl_qdma_dt_ids,
1245 },
1246 .probe = fsl_qdma_probe,
1247 .remove = fsl_qdma_remove,
1248};
1249
1250module_platform_driver(fsl_qdma_driver);
1251
1252MODULE_ALIAS("platform:fsl-qdma");
1253MODULE_LICENSE("GPL v2");
1254MODULE_DESCRIPTION("NXP Layerscape qDMA engine driver");