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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * IXP4 timer driver
4 * Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
5 *
6 * Based on arch/arm/mach-ixp4xx/common.c
7 * Copyright 2002 (C) Intel Corporation
8 * Copyright 2003-2004 (C) MontaVista, Software, Inc.
9 * Copyright (C) Deepak Saxena <dsaxena@plexity.net>
10 */
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/clockchips.h>
14#include <linux/clocksource.h>
15#include <linux/sched_clock.h>
16#include <linux/slab.h>
17#include <linux/bitops.h>
18#include <linux/delay.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
21#include <linux/platform_device.h>
22
23/*
24 * Constants to make it easy to access Timer Control/Status registers
25 */
26#define IXP4XX_OSTS_OFFSET 0x00 /* Continuous Timestamp */
27#define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
28#define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
29#define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
30#define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
31#define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
32
33/*
34 * Timer register values and bit definitions
35 */
36#define IXP4XX_OST_ENABLE 0x00000001
37#define IXP4XX_OST_ONE_SHOT 0x00000002
38/* Low order bits of reload value ignored */
39#define IXP4XX_OST_RELOAD_MASK 0x00000003
40#define IXP4XX_OST_DISABLED 0x00000000
41#define IXP4XX_OSST_TIMER_1_PEND 0x00000001
42#define IXP4XX_OSST_TIMER_2_PEND 0x00000002
43#define IXP4XX_OSST_TIMER_TS_PEND 0x00000004
44/* Remaining registers are for the watchdog and defined in the watchdog driver */
45
46struct ixp4xx_timer {
47 void __iomem *base;
48 u32 latch;
49 struct clock_event_device clkevt;
50#ifdef CONFIG_ARM
51 struct delay_timer delay_timer;
52#endif
53};
54
55/*
56 * A local singleton used by sched_clock and delay timer reads, which are
57 * fast and stateless
58 */
59static struct ixp4xx_timer *local_ixp4xx_timer;
60
61static inline struct ixp4xx_timer *
62to_ixp4xx_timer(struct clock_event_device *evt)
63{
64 return container_of(evt, struct ixp4xx_timer, clkevt);
65}
66
67static unsigned long ixp4xx_read_timer(void)
68{
69 return __raw_readl(local_ixp4xx_timer->base + IXP4XX_OSTS_OFFSET);
70}
71
72static u64 notrace ixp4xx_read_sched_clock(void)
73{
74 return ixp4xx_read_timer();
75}
76
77static u64 ixp4xx_clocksource_read(struct clocksource *c)
78{
79 return ixp4xx_read_timer();
80}
81
82static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
83{
84 struct ixp4xx_timer *tmr = dev_id;
85 struct clock_event_device *evt = &tmr->clkevt;
86
87 /* Clear Pending Interrupt */
88 __raw_writel(IXP4XX_OSST_TIMER_1_PEND,
89 tmr->base + IXP4XX_OSST_OFFSET);
90
91 evt->event_handler(evt);
92
93 return IRQ_HANDLED;
94}
95
96static int ixp4xx_set_next_event(unsigned long cycles,
97 struct clock_event_device *evt)
98{
99 struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
100 u32 val;
101
102 val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
103 /* Keep enable/oneshot bits */
104 val &= IXP4XX_OST_RELOAD_MASK;
105 __raw_writel((cycles & ~IXP4XX_OST_RELOAD_MASK) | val,
106 tmr->base + IXP4XX_OSRT1_OFFSET);
107
108 return 0;
109}
110
111static int ixp4xx_shutdown(struct clock_event_device *evt)
112{
113 struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
114 u32 val;
115
116 val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
117 val &= ~IXP4XX_OST_ENABLE;
118 __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
119
120 return 0;
121}
122
123static int ixp4xx_set_oneshot(struct clock_event_device *evt)
124{
125 struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
126
127 __raw_writel(IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT,
128 tmr->base + IXP4XX_OSRT1_OFFSET);
129
130 return 0;
131}
132
133static int ixp4xx_set_periodic(struct clock_event_device *evt)
134{
135 struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
136 u32 val;
137
138 val = tmr->latch & ~IXP4XX_OST_RELOAD_MASK;
139 val |= IXP4XX_OST_ENABLE;
140 __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
141
142 return 0;
143}
144
145static int ixp4xx_resume(struct clock_event_device *evt)
146{
147 struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
148 u32 val;
149
150 val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
151 val |= IXP4XX_OST_ENABLE;
152 __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
153
154 return 0;
155}
156
157/*
158 * IXP4xx timer tick
159 * We use OS timer1 on the CPU for the timer tick and the timestamp
160 * counter as a source of real clock ticks to account for missed jiffies.
161 */
162static __init int ixp4xx_timer_register(void __iomem *base,
163 int timer_irq,
164 unsigned int timer_freq)
165{
166 struct ixp4xx_timer *tmr;
167 int ret;
168
169 tmr = kzalloc(sizeof(*tmr), GFP_KERNEL);
170 if (!tmr)
171 return -ENOMEM;
172 tmr->base = base;
173
174 /*
175 * The timer register doesn't allow to specify the two least
176 * significant bits of the timeout value and assumes them being zero.
177 * So make sure the latch is the best value with the two least
178 * significant bits unset.
179 */
180 tmr->latch = DIV_ROUND_CLOSEST(timer_freq,
181 (IXP4XX_OST_RELOAD_MASK + 1) * HZ)
182 * (IXP4XX_OST_RELOAD_MASK + 1);
183
184 local_ixp4xx_timer = tmr;
185
186 /* Reset/disable counter */
187 __raw_writel(0, tmr->base + IXP4XX_OSRT1_OFFSET);
188
189 /* Clear any pending interrupt on timer 1 */
190 __raw_writel(IXP4XX_OSST_TIMER_1_PEND,
191 tmr->base + IXP4XX_OSST_OFFSET);
192
193 /* Reset time-stamp counter */
194 __raw_writel(0, tmr->base + IXP4XX_OSTS_OFFSET);
195
196 clocksource_mmio_init(NULL, "OSTS", timer_freq, 200, 32,
197 ixp4xx_clocksource_read);
198
199 tmr->clkevt.name = "ixp4xx timer1";
200 tmr->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
201 tmr->clkevt.rating = 200;
202 tmr->clkevt.set_state_shutdown = ixp4xx_shutdown;
203 tmr->clkevt.set_state_periodic = ixp4xx_set_periodic;
204 tmr->clkevt.set_state_oneshot = ixp4xx_set_oneshot;
205 tmr->clkevt.tick_resume = ixp4xx_resume;
206 tmr->clkevt.set_next_event = ixp4xx_set_next_event;
207 tmr->clkevt.cpumask = cpumask_of(0);
208 tmr->clkevt.irq = timer_irq;
209 ret = request_irq(timer_irq, ixp4xx_timer_interrupt,
210 IRQF_TIMER, "IXP4XX-TIMER1", tmr);
211 if (ret) {
212 pr_crit("no timer IRQ\n");
213 return -ENODEV;
214 }
215 clockevents_config_and_register(&tmr->clkevt, timer_freq,
216 0xf, 0xfffffffe);
217
218 sched_clock_register(ixp4xx_read_sched_clock, 32, timer_freq);
219
220#ifdef CONFIG_ARM
221 /* Also use this timer for delays */
222 tmr->delay_timer.read_current_timer = ixp4xx_read_timer;
223 tmr->delay_timer.freq = timer_freq;
224 register_current_timer_delay(&tmr->delay_timer);
225#endif
226
227 return 0;
228}
229
230static struct platform_device ixp4xx_watchdog_device = {
231 .name = "ixp4xx-watchdog",
232 .id = -1,
233};
234
235/*
236 * This probe gets called after the timer is already up and running. The main
237 * function on this platform is to spawn the watchdog device as a child.
238 */
239static int ixp4xx_timer_probe(struct platform_device *pdev)
240{
241 struct device *dev = &pdev->dev;
242
243 /* Pass the base address as platform data and nothing else */
244 ixp4xx_watchdog_device.dev.platform_data = local_ixp4xx_timer->base;
245 ixp4xx_watchdog_device.dev.parent = dev;
246 return platform_device_register(&ixp4xx_watchdog_device);
247}
248
249static const struct of_device_id ixp4xx_timer_dt_id[] = {
250 { .compatible = "intel,ixp4xx-timer", },
251 { /* sentinel */ },
252};
253
254static struct platform_driver ixp4xx_timer_driver = {
255 .probe = ixp4xx_timer_probe,
256 .driver = {
257 .name = "ixp4xx-timer",
258 .of_match_table = ixp4xx_timer_dt_id,
259 .suppress_bind_attrs = true,
260 },
261};
262builtin_platform_driver(ixp4xx_timer_driver);
263
264static __init int ixp4xx_of_timer_init(struct device_node *np)
265{
266 void __iomem *base;
267 int irq;
268 int ret;
269
270 base = of_iomap(np, 0);
271 if (!base) {
272 pr_crit("IXP4xx: can't remap timer\n");
273 return -ENODEV;
274 }
275
276 irq = irq_of_parse_and_map(np, 0);
277 if (irq <= 0) {
278 pr_err("Can't parse IRQ\n");
279 ret = -EINVAL;
280 goto out_unmap;
281 }
282
283 /* TODO: get some fixed clocks into the device tree */
284 ret = ixp4xx_timer_register(base, irq, 66666000);
285 if (ret)
286 goto out_unmap;
287 return 0;
288
289out_unmap:
290 iounmap(base);
291 return ret;
292}
293TIMER_OF_DECLARE(ixp4xx, "intel,ixp4xx-timer", ixp4xx_of_timer_init);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * IXP4 timer driver
4 * Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
5 *
6 * Based on arch/arm/mach-ixp4xx/common.c
7 * Copyright 2002 (C) Intel Corporation
8 * Copyright 2003-2004 (C) MontaVista, Software, Inc.
9 * Copyright (C) Deepak Saxena <dsaxena@plexity.net>
10 */
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/clockchips.h>
14#include <linux/clocksource.h>
15#include <linux/sched_clock.h>
16#include <linux/slab.h>
17#include <linux/bitops.h>
18#include <linux/delay.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
21/* Goes away with OF conversion */
22#include <linux/platform_data/timer-ixp4xx.h>
23
24/*
25 * Constants to make it easy to access Timer Control/Status registers
26 */
27#define IXP4XX_OSTS_OFFSET 0x00 /* Continuous Timestamp */
28#define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
29#define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
30#define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
31#define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
32#define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */
33#define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */
34#define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */
35#define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
36
37/*
38 * Timer register values and bit definitions
39 */
40#define IXP4XX_OST_ENABLE 0x00000001
41#define IXP4XX_OST_ONE_SHOT 0x00000002
42/* Low order bits of reload value ignored */
43#define IXP4XX_OST_RELOAD_MASK 0x00000003
44#define IXP4XX_OST_DISABLED 0x00000000
45#define IXP4XX_OSST_TIMER_1_PEND 0x00000001
46#define IXP4XX_OSST_TIMER_2_PEND 0x00000002
47#define IXP4XX_OSST_TIMER_TS_PEND 0x00000004
48#define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008
49#define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
50
51#define IXP4XX_WDT_KEY 0x0000482E
52#define IXP4XX_WDT_RESET_ENABLE 0x00000001
53#define IXP4XX_WDT_IRQ_ENABLE 0x00000002
54#define IXP4XX_WDT_COUNT_ENABLE 0x00000004
55
56struct ixp4xx_timer {
57 void __iomem *base;
58 unsigned int tick_rate;
59 u32 latch;
60 struct clock_event_device clkevt;
61#ifdef CONFIG_ARM
62 struct delay_timer delay_timer;
63#endif
64};
65
66/*
67 * A local singleton used by sched_clock and delay timer reads, which are
68 * fast and stateless
69 */
70static struct ixp4xx_timer *local_ixp4xx_timer;
71
72static inline struct ixp4xx_timer *
73to_ixp4xx_timer(struct clock_event_device *evt)
74{
75 return container_of(evt, struct ixp4xx_timer, clkevt);
76}
77
78static unsigned long ixp4xx_read_timer(void)
79{
80 return __raw_readl(local_ixp4xx_timer->base + IXP4XX_OSTS_OFFSET);
81}
82
83static u64 notrace ixp4xx_read_sched_clock(void)
84{
85 return ixp4xx_read_timer();
86}
87
88static u64 ixp4xx_clocksource_read(struct clocksource *c)
89{
90 return ixp4xx_read_timer();
91}
92
93static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
94{
95 struct ixp4xx_timer *tmr = dev_id;
96 struct clock_event_device *evt = &tmr->clkevt;
97
98 /* Clear Pending Interrupt */
99 __raw_writel(IXP4XX_OSST_TIMER_1_PEND,
100 tmr->base + IXP4XX_OSST_OFFSET);
101
102 evt->event_handler(evt);
103
104 return IRQ_HANDLED;
105}
106
107static int ixp4xx_set_next_event(unsigned long cycles,
108 struct clock_event_device *evt)
109{
110 struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
111 u32 val;
112
113 val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
114 /* Keep enable/oneshot bits */
115 val &= IXP4XX_OST_RELOAD_MASK;
116 __raw_writel((cycles & ~IXP4XX_OST_RELOAD_MASK) | val,
117 tmr->base + IXP4XX_OSRT1_OFFSET);
118
119 return 0;
120}
121
122static int ixp4xx_shutdown(struct clock_event_device *evt)
123{
124 struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
125 u32 val;
126
127 val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
128 val &= ~IXP4XX_OST_ENABLE;
129 __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
130
131 return 0;
132}
133
134static int ixp4xx_set_oneshot(struct clock_event_device *evt)
135{
136 struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
137
138 __raw_writel(IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT,
139 tmr->base + IXP4XX_OSRT1_OFFSET);
140
141 return 0;
142}
143
144static int ixp4xx_set_periodic(struct clock_event_device *evt)
145{
146 struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
147 u32 val;
148
149 val = tmr->latch & ~IXP4XX_OST_RELOAD_MASK;
150 val |= IXP4XX_OST_ENABLE;
151 __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
152
153 return 0;
154}
155
156static int ixp4xx_resume(struct clock_event_device *evt)
157{
158 struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
159 u32 val;
160
161 val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
162 val |= IXP4XX_OST_ENABLE;
163 __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
164
165 return 0;
166}
167
168/*
169 * IXP4xx timer tick
170 * We use OS timer1 on the CPU for the timer tick and the timestamp
171 * counter as a source of real clock ticks to account for missed jiffies.
172 */
173static __init int ixp4xx_timer_register(void __iomem *base,
174 int timer_irq,
175 unsigned int timer_freq)
176{
177 struct ixp4xx_timer *tmr;
178 int ret;
179
180 tmr = kzalloc(sizeof(*tmr), GFP_KERNEL);
181 if (!tmr)
182 return -ENOMEM;
183 tmr->base = base;
184 tmr->tick_rate = timer_freq;
185
186 /*
187 * The timer register doesn't allow to specify the two least
188 * significant bits of the timeout value and assumes them being zero.
189 * So make sure the latch is the best value with the two least
190 * significant bits unset.
191 */
192 tmr->latch = DIV_ROUND_CLOSEST(timer_freq,
193 (IXP4XX_OST_RELOAD_MASK + 1) * HZ)
194 * (IXP4XX_OST_RELOAD_MASK + 1);
195
196 local_ixp4xx_timer = tmr;
197
198 /* Reset/disable counter */
199 __raw_writel(0, tmr->base + IXP4XX_OSRT1_OFFSET);
200
201 /* Clear any pending interrupt on timer 1 */
202 __raw_writel(IXP4XX_OSST_TIMER_1_PEND,
203 tmr->base + IXP4XX_OSST_OFFSET);
204
205 /* Reset time-stamp counter */
206 __raw_writel(0, tmr->base + IXP4XX_OSTS_OFFSET);
207
208 clocksource_mmio_init(NULL, "OSTS", timer_freq, 200, 32,
209 ixp4xx_clocksource_read);
210
211 tmr->clkevt.name = "ixp4xx timer1";
212 tmr->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
213 tmr->clkevt.rating = 200;
214 tmr->clkevt.set_state_shutdown = ixp4xx_shutdown;
215 tmr->clkevt.set_state_periodic = ixp4xx_set_periodic;
216 tmr->clkevt.set_state_oneshot = ixp4xx_set_oneshot;
217 tmr->clkevt.tick_resume = ixp4xx_resume;
218 tmr->clkevt.set_next_event = ixp4xx_set_next_event;
219 tmr->clkevt.cpumask = cpumask_of(0);
220 tmr->clkevt.irq = timer_irq;
221 ret = request_irq(timer_irq, ixp4xx_timer_interrupt,
222 IRQF_TIMER, "IXP4XX-TIMER1", tmr);
223 if (ret) {
224 pr_crit("no timer IRQ\n");
225 return -ENODEV;
226 }
227 clockevents_config_and_register(&tmr->clkevt, timer_freq,
228 0xf, 0xfffffffe);
229
230 sched_clock_register(ixp4xx_read_sched_clock, 32, timer_freq);
231
232#ifdef CONFIG_ARM
233 /* Also use this timer for delays */
234 tmr->delay_timer.read_current_timer = ixp4xx_read_timer;
235 tmr->delay_timer.freq = timer_freq;
236 register_current_timer_delay(&tmr->delay_timer);
237#endif
238
239 return 0;
240}
241
242/**
243 * ixp4xx_timer_setup() - Timer setup function to be called from boardfiles
244 * @timerbase: physical base of timer block
245 * @timer_irq: Linux IRQ number for the timer
246 * @timer_freq: Fixed frequency of the timer
247 */
248void __init ixp4xx_timer_setup(resource_size_t timerbase,
249 int timer_irq,
250 unsigned int timer_freq)
251{
252 void __iomem *base;
253
254 base = ioremap(timerbase, 0x100);
255 if (!base) {
256 pr_crit("IXP4xx: can't remap timer\n");
257 return;
258 }
259 ixp4xx_timer_register(base, timer_irq, timer_freq);
260}
261EXPORT_SYMBOL_GPL(ixp4xx_timer_setup);
262
263#ifdef CONFIG_OF
264static __init int ixp4xx_of_timer_init(struct device_node *np)
265{
266 void __iomem *base;
267 int irq;
268 int ret;
269
270 base = of_iomap(np, 0);
271 if (!base) {
272 pr_crit("IXP4xx: can't remap timer\n");
273 return -ENODEV;
274 }
275
276 irq = irq_of_parse_and_map(np, 0);
277 if (irq <= 0) {
278 pr_err("Can't parse IRQ\n");
279 ret = -EINVAL;
280 goto out_unmap;
281 }
282
283 /* TODO: get some fixed clocks into the device tree */
284 ret = ixp4xx_timer_register(base, irq, 66666000);
285 if (ret)
286 goto out_unmap;
287 return 0;
288
289out_unmap:
290 iounmap(base);
291 return ret;
292}
293TIMER_OF_DECLARE(ixp4xx, "intel,ixp4xx-timer", ixp4xx_of_timer_init);
294#endif