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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2013 - 2014 Texas Instruments Incorporated - https://www.ti.com
4 *
5 * Authors:
6 * Jyri Sarha <jsarha@ti.com>
7 * Sergej Sawazki <ce3a@gmx.de>
8 *
9 * Gpio controlled clock implementation
10 */
11
12#include <linux/clk-provider.h>
13#include <linux/export.h>
14#include <linux/slab.h>
15#include <linux/gpio/consumer.h>
16#include <linux/err.h>
17#include <linux/device.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20
21/**
22 * DOC: basic gpio gated clock which can be enabled and disabled
23 * with gpio output
24 * Traits of this clock:
25 * prepare - clk_(un)prepare only ensures parent is (un)prepared
26 * enable - clk_enable and clk_disable are functional & control gpio
27 * rate - inherits rate from parent. No clk_set_rate support
28 * parent - fixed parent. No clk_set_parent support
29 */
30
31/**
32 * struct clk_gpio - gpio gated clock
33 *
34 * @hw: handle between common and hardware-specific interfaces
35 * @gpiod: gpio descriptor
36 *
37 * Clock with a gpio control for enabling and disabling the parent clock
38 * or switching between two parents by asserting or deasserting the gpio.
39 *
40 * Implements .enable, .disable and .is_enabled or
41 * .get_parent, .set_parent and .determine_rate depending on which clk_ops
42 * is used.
43 */
44struct clk_gpio {
45 struct clk_hw hw;
46 struct gpio_desc *gpiod;
47};
48
49#define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
50
51static int clk_gpio_gate_enable(struct clk_hw *hw)
52{
53 struct clk_gpio *clk = to_clk_gpio(hw);
54
55 gpiod_set_value(clk->gpiod, 1);
56
57 return 0;
58}
59
60static void clk_gpio_gate_disable(struct clk_hw *hw)
61{
62 struct clk_gpio *clk = to_clk_gpio(hw);
63
64 gpiod_set_value(clk->gpiod, 0);
65}
66
67static int clk_gpio_gate_is_enabled(struct clk_hw *hw)
68{
69 struct clk_gpio *clk = to_clk_gpio(hw);
70
71 return gpiod_get_value(clk->gpiod);
72}
73
74static const struct clk_ops clk_gpio_gate_ops = {
75 .enable = clk_gpio_gate_enable,
76 .disable = clk_gpio_gate_disable,
77 .is_enabled = clk_gpio_gate_is_enabled,
78};
79
80static int clk_sleeping_gpio_gate_prepare(struct clk_hw *hw)
81{
82 struct clk_gpio *clk = to_clk_gpio(hw);
83
84 gpiod_set_value_cansleep(clk->gpiod, 1);
85
86 return 0;
87}
88
89static void clk_sleeping_gpio_gate_unprepare(struct clk_hw *hw)
90{
91 struct clk_gpio *clk = to_clk_gpio(hw);
92
93 gpiod_set_value_cansleep(clk->gpiod, 0);
94}
95
96static int clk_sleeping_gpio_gate_is_prepared(struct clk_hw *hw)
97{
98 struct clk_gpio *clk = to_clk_gpio(hw);
99
100 return gpiod_get_value_cansleep(clk->gpiod);
101}
102
103static const struct clk_ops clk_sleeping_gpio_gate_ops = {
104 .prepare = clk_sleeping_gpio_gate_prepare,
105 .unprepare = clk_sleeping_gpio_gate_unprepare,
106 .is_prepared = clk_sleeping_gpio_gate_is_prepared,
107};
108
109/**
110 * DOC: basic clock multiplexer which can be controlled with a gpio output
111 * Traits of this clock:
112 * prepare - clk_prepare only ensures that parents are prepared
113 * rate - rate is only affected by parent switching. No clk_set_rate support
114 * parent - parent is adjustable through clk_set_parent
115 */
116
117static u8 clk_gpio_mux_get_parent(struct clk_hw *hw)
118{
119 struct clk_gpio *clk = to_clk_gpio(hw);
120
121 return gpiod_get_value_cansleep(clk->gpiod);
122}
123
124static int clk_gpio_mux_set_parent(struct clk_hw *hw, u8 index)
125{
126 struct clk_gpio *clk = to_clk_gpio(hw);
127
128 gpiod_set_value_cansleep(clk->gpiod, index);
129
130 return 0;
131}
132
133static const struct clk_ops clk_gpio_mux_ops = {
134 .get_parent = clk_gpio_mux_get_parent,
135 .set_parent = clk_gpio_mux_set_parent,
136 .determine_rate = __clk_mux_determine_rate,
137};
138
139static struct clk_hw *clk_register_gpio(struct device *dev, u8 num_parents,
140 struct gpio_desc *gpiod,
141 const struct clk_ops *clk_gpio_ops)
142{
143 struct clk_gpio *clk_gpio;
144 struct clk_hw *hw;
145 struct clk_init_data init = {};
146 int err;
147 const struct clk_parent_data gpio_parent_data[] = {
148 { .index = 0 },
149 { .index = 1 },
150 };
151
152 clk_gpio = devm_kzalloc(dev, sizeof(*clk_gpio), GFP_KERNEL);
153 if (!clk_gpio)
154 return ERR_PTR(-ENOMEM);
155
156 init.name = dev->of_node->name;
157 init.ops = clk_gpio_ops;
158 init.parent_data = gpio_parent_data;
159 init.num_parents = num_parents;
160 init.flags = CLK_SET_RATE_PARENT;
161
162 clk_gpio->gpiod = gpiod;
163 clk_gpio->hw.init = &init;
164
165 hw = &clk_gpio->hw;
166 err = devm_clk_hw_register(dev, hw);
167 if (err)
168 return ERR_PTR(err);
169
170 return hw;
171}
172
173static struct clk_hw *clk_hw_register_gpio_gate(struct device *dev,
174 int num_parents,
175 struct gpio_desc *gpiod)
176{
177 const struct clk_ops *ops;
178
179 if (gpiod_cansleep(gpiod))
180 ops = &clk_sleeping_gpio_gate_ops;
181 else
182 ops = &clk_gpio_gate_ops;
183
184 return clk_register_gpio(dev, num_parents, gpiod, ops);
185}
186
187static struct clk_hw *clk_hw_register_gpio_mux(struct device *dev,
188 struct gpio_desc *gpiod)
189{
190 return clk_register_gpio(dev, 2, gpiod, &clk_gpio_mux_ops);
191}
192
193static int gpio_clk_driver_probe(struct platform_device *pdev)
194{
195 struct device *dev = &pdev->dev;
196 struct device_node *node = dev->of_node;
197 const char *gpio_name;
198 unsigned int num_parents;
199 struct gpio_desc *gpiod;
200 struct clk_hw *hw;
201 bool is_mux;
202 int ret;
203
204 is_mux = of_device_is_compatible(node, "gpio-mux-clock");
205
206 num_parents = of_clk_get_parent_count(node);
207 if (is_mux && num_parents != 2) {
208 dev_err(dev, "mux-clock must have 2 parents\n");
209 return -EINVAL;
210 }
211
212 gpio_name = is_mux ? "select" : "enable";
213 gpiod = devm_gpiod_get(dev, gpio_name, GPIOD_OUT_LOW);
214 if (IS_ERR(gpiod)) {
215 ret = PTR_ERR(gpiod);
216 if (ret == -EPROBE_DEFER)
217 pr_debug("%pOFn: %s: GPIOs not yet available, retry later\n",
218 node, __func__);
219 else
220 pr_err("%pOFn: %s: Can't get '%s' named GPIO property\n",
221 node, __func__,
222 gpio_name);
223 return ret;
224 }
225
226 if (is_mux)
227 hw = clk_hw_register_gpio_mux(dev, gpiod);
228 else
229 hw = clk_hw_register_gpio_gate(dev, num_parents, gpiod);
230 if (IS_ERR(hw))
231 return PTR_ERR(hw);
232
233 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
234}
235
236static const struct of_device_id gpio_clk_match_table[] = {
237 { .compatible = "gpio-mux-clock" },
238 { .compatible = "gpio-gate-clock" },
239 { }
240};
241
242static struct platform_driver gpio_clk_driver = {
243 .probe = gpio_clk_driver_probe,
244 .driver = {
245 .name = "gpio-clk",
246 .of_match_table = gpio_clk_match_table,
247 },
248};
249builtin_platform_driver(gpio_clk_driver);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2013 - 2014 Texas Instruments Incorporated - http://www.ti.com
4 *
5 * Authors:
6 * Jyri Sarha <jsarha@ti.com>
7 * Sergej Sawazki <ce3a@gmx.de>
8 *
9 * Gpio controlled clock implementation
10 */
11
12#include <linux/clk-provider.h>
13#include <linux/export.h>
14#include <linux/slab.h>
15#include <linux/gpio/consumer.h>
16#include <linux/err.h>
17#include <linux/device.h>
18#include <linux/platform_device.h>
19#include <linux/of_device.h>
20
21/**
22 * DOC: basic gpio gated clock which can be enabled and disabled
23 * with gpio output
24 * Traits of this clock:
25 * prepare - clk_(un)prepare only ensures parent is (un)prepared
26 * enable - clk_enable and clk_disable are functional & control gpio
27 * rate - inherits rate from parent. No clk_set_rate support
28 * parent - fixed parent. No clk_set_parent support
29 */
30
31static int clk_gpio_gate_enable(struct clk_hw *hw)
32{
33 struct clk_gpio *clk = to_clk_gpio(hw);
34
35 gpiod_set_value(clk->gpiod, 1);
36
37 return 0;
38}
39
40static void clk_gpio_gate_disable(struct clk_hw *hw)
41{
42 struct clk_gpio *clk = to_clk_gpio(hw);
43
44 gpiod_set_value(clk->gpiod, 0);
45}
46
47static int clk_gpio_gate_is_enabled(struct clk_hw *hw)
48{
49 struct clk_gpio *clk = to_clk_gpio(hw);
50
51 return gpiod_get_value(clk->gpiod);
52}
53
54const struct clk_ops clk_gpio_gate_ops = {
55 .enable = clk_gpio_gate_enable,
56 .disable = clk_gpio_gate_disable,
57 .is_enabled = clk_gpio_gate_is_enabled,
58};
59EXPORT_SYMBOL_GPL(clk_gpio_gate_ops);
60
61static int clk_sleeping_gpio_gate_prepare(struct clk_hw *hw)
62{
63 struct clk_gpio *clk = to_clk_gpio(hw);
64
65 gpiod_set_value_cansleep(clk->gpiod, 1);
66
67 return 0;
68}
69
70static void clk_sleeping_gpio_gate_unprepare(struct clk_hw *hw)
71{
72 struct clk_gpio *clk = to_clk_gpio(hw);
73
74 gpiod_set_value_cansleep(clk->gpiod, 0);
75}
76
77static int clk_sleeping_gpio_gate_is_prepared(struct clk_hw *hw)
78{
79 struct clk_gpio *clk = to_clk_gpio(hw);
80
81 return gpiod_get_value_cansleep(clk->gpiod);
82}
83
84static const struct clk_ops clk_sleeping_gpio_gate_ops = {
85 .prepare = clk_sleeping_gpio_gate_prepare,
86 .unprepare = clk_sleeping_gpio_gate_unprepare,
87 .is_prepared = clk_sleeping_gpio_gate_is_prepared,
88};
89
90/**
91 * DOC: basic clock multiplexer which can be controlled with a gpio output
92 * Traits of this clock:
93 * prepare - clk_prepare only ensures that parents are prepared
94 * rate - rate is only affected by parent switching. No clk_set_rate support
95 * parent - parent is adjustable through clk_set_parent
96 */
97
98static u8 clk_gpio_mux_get_parent(struct clk_hw *hw)
99{
100 struct clk_gpio *clk = to_clk_gpio(hw);
101
102 return gpiod_get_value_cansleep(clk->gpiod);
103}
104
105static int clk_gpio_mux_set_parent(struct clk_hw *hw, u8 index)
106{
107 struct clk_gpio *clk = to_clk_gpio(hw);
108
109 gpiod_set_value_cansleep(clk->gpiod, index);
110
111 return 0;
112}
113
114const struct clk_ops clk_gpio_mux_ops = {
115 .get_parent = clk_gpio_mux_get_parent,
116 .set_parent = clk_gpio_mux_set_parent,
117 .determine_rate = __clk_mux_determine_rate,
118};
119EXPORT_SYMBOL_GPL(clk_gpio_mux_ops);
120
121static struct clk_hw *clk_register_gpio(struct device *dev, const char *name,
122 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
123 unsigned long flags, const struct clk_ops *clk_gpio_ops)
124{
125 struct clk_gpio *clk_gpio;
126 struct clk_hw *hw;
127 struct clk_init_data init = {};
128 int err;
129
130 if (dev)
131 clk_gpio = devm_kzalloc(dev, sizeof(*clk_gpio), GFP_KERNEL);
132 else
133 clk_gpio = kzalloc(sizeof(*clk_gpio), GFP_KERNEL);
134
135 if (!clk_gpio)
136 return ERR_PTR(-ENOMEM);
137
138 init.name = name;
139 init.ops = clk_gpio_ops;
140 init.flags = flags;
141 init.parent_names = parent_names;
142 init.num_parents = num_parents;
143
144 clk_gpio->gpiod = gpiod;
145 clk_gpio->hw.init = &init;
146
147 hw = &clk_gpio->hw;
148 if (dev)
149 err = devm_clk_hw_register(dev, hw);
150 else
151 err = clk_hw_register(NULL, hw);
152
153 if (!err)
154 return hw;
155
156 if (!dev) {
157 kfree(clk_gpio);
158 }
159
160 return ERR_PTR(err);
161}
162
163/**
164 * clk_hw_register_gpio_gate - register a gpio clock gate with the clock
165 * framework
166 * @dev: device that is registering this clock
167 * @name: name of this clock
168 * @parent_name: name of this clock's parent
169 * @gpiod: gpio descriptor to gate this clock
170 * @flags: clock flags
171 */
172struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name,
173 const char *parent_name, struct gpio_desc *gpiod,
174 unsigned long flags)
175{
176 const struct clk_ops *ops;
177
178 if (gpiod_cansleep(gpiod))
179 ops = &clk_sleeping_gpio_gate_ops;
180 else
181 ops = &clk_gpio_gate_ops;
182
183 return clk_register_gpio(dev, name,
184 (parent_name ? &parent_name : NULL),
185 (parent_name ? 1 : 0), gpiod, flags, ops);
186}
187EXPORT_SYMBOL_GPL(clk_hw_register_gpio_gate);
188
189struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
190 const char *parent_name, struct gpio_desc *gpiod,
191 unsigned long flags)
192{
193 struct clk_hw *hw;
194
195 hw = clk_hw_register_gpio_gate(dev, name, parent_name, gpiod, flags);
196 if (IS_ERR(hw))
197 return ERR_CAST(hw);
198 return hw->clk;
199}
200EXPORT_SYMBOL_GPL(clk_register_gpio_gate);
201
202/**
203 * clk_hw_register_gpio_mux - register a gpio clock mux with the clock framework
204 * @dev: device that is registering this clock
205 * @name: name of this clock
206 * @parent_names: names of this clock's parents
207 * @num_parents: number of parents listed in @parent_names
208 * @gpiod: gpio descriptor to gate this clock
209 * @flags: clock flags
210 */
211struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name,
212 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
213 unsigned long flags)
214{
215 if (num_parents != 2) {
216 pr_err("mux-clock %s must have 2 parents\n", name);
217 return ERR_PTR(-EINVAL);
218 }
219
220 return clk_register_gpio(dev, name, parent_names, num_parents,
221 gpiod, flags, &clk_gpio_mux_ops);
222}
223EXPORT_SYMBOL_GPL(clk_hw_register_gpio_mux);
224
225struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
226 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
227 unsigned long flags)
228{
229 struct clk_hw *hw;
230
231 hw = clk_hw_register_gpio_mux(dev, name, parent_names, num_parents,
232 gpiod, flags);
233 if (IS_ERR(hw))
234 return ERR_CAST(hw);
235 return hw->clk;
236}
237EXPORT_SYMBOL_GPL(clk_register_gpio_mux);
238
239static int gpio_clk_driver_probe(struct platform_device *pdev)
240{
241 struct device_node *node = pdev->dev.of_node;
242 const char **parent_names, *gpio_name;
243 unsigned int num_parents;
244 struct gpio_desc *gpiod;
245 struct clk *clk;
246 bool is_mux;
247 int ret;
248
249 num_parents = of_clk_get_parent_count(node);
250 if (num_parents) {
251 parent_names = devm_kcalloc(&pdev->dev, num_parents,
252 sizeof(char *), GFP_KERNEL);
253 if (!parent_names)
254 return -ENOMEM;
255
256 of_clk_parent_fill(node, parent_names, num_parents);
257 } else {
258 parent_names = NULL;
259 }
260
261 is_mux = of_device_is_compatible(node, "gpio-mux-clock");
262
263 gpio_name = is_mux ? "select" : "enable";
264 gpiod = devm_gpiod_get(&pdev->dev, gpio_name, GPIOD_OUT_LOW);
265 if (IS_ERR(gpiod)) {
266 ret = PTR_ERR(gpiod);
267 if (ret == -EPROBE_DEFER)
268 pr_debug("%pOFn: %s: GPIOs not yet available, retry later\n",
269 node, __func__);
270 else
271 pr_err("%pOFn: %s: Can't get '%s' named GPIO property\n",
272 node, __func__,
273 gpio_name);
274 return ret;
275 }
276
277 if (is_mux)
278 clk = clk_register_gpio_mux(&pdev->dev, node->name,
279 parent_names, num_parents, gpiod, 0);
280 else
281 clk = clk_register_gpio_gate(&pdev->dev, node->name,
282 parent_names ? parent_names[0] : NULL, gpiod,
283 0);
284 if (IS_ERR(clk))
285 return PTR_ERR(clk);
286
287 return of_clk_add_provider(node, of_clk_src_simple_get, clk);
288}
289
290static const struct of_device_id gpio_clk_match_table[] = {
291 { .compatible = "gpio-mux-clock" },
292 { .compatible = "gpio-gate-clock" },
293 { }
294};
295
296static struct platform_driver gpio_clk_driver = {
297 .probe = gpio_clk_driver_probe,
298 .driver = {
299 .name = "gpio-clk",
300 .of_match_table = gpio_clk_match_table,
301 },
302};
303builtin_platform_driver(gpio_clk_driver);