Loading...
Note: File does not exist in v5.4.
1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright (C) 2020-2023 Intel Corporation
4 */
5
6#ifndef VPU_BOOT_API_H
7#define VPU_BOOT_API_H
8
9/*
10 * =========== FW API version information beginning ================
11 * The bellow values will be used to construct the version info this way:
12 * fw_bin_header->api_version[VPU_BOOT_API_VER_ID] = (VPU_BOOT_API_VER_MAJOR << 16) |
13 * VPU_BOOT_API_VER_MINOR;
14 * VPU_BOOT_API_VER_PATCH will be ignored. KMD and compatibility is not affected if this changes
15 * This information is collected by using vpuip_2/application/vpuFirmware/make_std_fw_image.py
16 * If a header is missing this info we ignore the header, if a header is missing or contains
17 * partial info a build error will be generated.
18 */
19
20/*
21 * Major version changes that break backward compatibility.
22 * Major version must start from 1 and can only be incremented.
23 */
24#define VPU_BOOT_API_VER_MAJOR 3
25
26/*
27 * Minor version changes when API backward compatibility is preserved.
28 * Resets to 0 if Major version is incremented.
29 */
30#define VPU_BOOT_API_VER_MINOR 20
31
32/*
33 * API header changed (field names, documentation, formatting) but API itself has not been changed
34 */
35#define VPU_BOOT_API_VER_PATCH 4
36
37/*
38 * Index in the API version table
39 * Must be unique for each API
40 */
41#define VPU_BOOT_API_VER_INDEX 0
42/* ------------ FW API version information end ---------------------*/
43
44#pragma pack(push, 1)
45
46/*
47 * Firmware image header format
48 */
49#define VPU_FW_HEADER_SIZE 4096
50#define VPU_FW_HEADER_VERSION 0x1
51#define VPU_FW_VERSION_SIZE 32
52#define VPU_FW_API_VER_NUM 16
53
54struct vpu_firmware_header {
55 u32 header_version;
56 u32 image_format;
57 u64 image_load_address;
58 u32 image_size;
59 u64 entry_point;
60 u8 vpu_version[VPU_FW_VERSION_SIZE];
61 u32 compression_type;
62 u64 firmware_version_load_address;
63 u32 firmware_version_size;
64 u64 boot_params_load_address;
65 u32 api_version[VPU_FW_API_VER_NUM];
66 /* Size of memory require for firmware execution */
67 u32 runtime_size;
68 u32 shave_nn_fw_size;
69 /* Size of primary preemption buffer. */
70 u32 preemption_buffer_1_size;
71 /* Size of secondary preemption buffer. */
72 u32 preemption_buffer_2_size;
73 /* Space reserved for future preemption-related fields. */
74 u32 preemption_reserved[6];
75};
76
77/*
78 * Firmware boot parameters format
79 */
80
81#define VPU_BOOT_PLL_COUNT 3
82#define VPU_BOOT_PLL_OUT_COUNT 4
83
84/** Values for boot_type field */
85#define VPU_BOOT_TYPE_COLDBOOT 0
86#define VPU_BOOT_TYPE_WARMBOOT 1
87
88/** Value for magic filed */
89#define VPU_BOOT_PARAMS_MAGIC 0x10000
90
91/** VPU scheduling mode. By default, OS scheduling is used. */
92#define VPU_SCHEDULING_MODE_OS 0
93#define VPU_SCHEDULING_MODE_HW 1
94
95enum VPU_BOOT_L2_CACHE_CFG_TYPE {
96 VPU_BOOT_L2_CACHE_CFG_UPA = 0,
97 VPU_BOOT_L2_CACHE_CFG_NN = 1,
98 VPU_BOOT_L2_CACHE_CFG_NUM = 2
99};
100
101/** VPU MCA ECC signalling mode. By default, no signalling is used */
102enum VPU_BOOT_MCA_ECC_SIGNAL_TYPE {
103 VPU_BOOT_MCA_ECC_NONE = 0,
104 VPU_BOOT_MCA_ECC_CORR = 1,
105 VPU_BOOT_MCA_ECC_FATAL = 2,
106 VPU_BOOT_MCA_ECC_BOTH = 3
107};
108
109/**
110 * Logging destinations.
111 *
112 * Logging output can be directed to different logging destinations. This enum
113 * defines the list of logging destinations supported by the VPU firmware (NOTE:
114 * a specific VPU FW binary may support only a subset of such output
115 * destinations, depending on the target platform and compile options).
116 */
117enum vpu_trace_destination {
118 VPU_TRACE_DESTINATION_PIPEPRINT = 0x1,
119 VPU_TRACE_DESTINATION_VERBOSE_TRACING = 0x2,
120 VPU_TRACE_DESTINATION_NORTH_PEAK = 0x4,
121};
122
123/*
124 * Processor bit shifts (for loggable HW components).
125 */
126#define VPU_TRACE_PROC_BIT_ARM 0
127#define VPU_TRACE_PROC_BIT_LRT 1
128#define VPU_TRACE_PROC_BIT_LNN 2
129#define VPU_TRACE_PROC_BIT_SHV_0 3
130#define VPU_TRACE_PROC_BIT_SHV_1 4
131#define VPU_TRACE_PROC_BIT_SHV_2 5
132#define VPU_TRACE_PROC_BIT_SHV_3 6
133#define VPU_TRACE_PROC_BIT_SHV_4 7
134#define VPU_TRACE_PROC_BIT_SHV_5 8
135#define VPU_TRACE_PROC_BIT_SHV_6 9
136#define VPU_TRACE_PROC_BIT_SHV_7 10
137#define VPU_TRACE_PROC_BIT_SHV_8 11
138#define VPU_TRACE_PROC_BIT_SHV_9 12
139#define VPU_TRACE_PROC_BIT_SHV_10 13
140#define VPU_TRACE_PROC_BIT_SHV_11 14
141#define VPU_TRACE_PROC_BIT_SHV_12 15
142#define VPU_TRACE_PROC_BIT_SHV_13 16
143#define VPU_TRACE_PROC_BIT_SHV_14 17
144#define VPU_TRACE_PROC_BIT_SHV_15 18
145#define VPU_TRACE_PROC_BIT_ACT_SHV_0 19
146#define VPU_TRACE_PROC_BIT_ACT_SHV_1 20
147#define VPU_TRACE_PROC_BIT_ACT_SHV_2 21
148#define VPU_TRACE_PROC_BIT_ACT_SHV_3 22
149#define VPU_TRACE_PROC_NO_OF_HW_DEVS 23
150
151/* VPU 30xx HW component IDs are sequential, so define first and last IDs. */
152#define VPU_TRACE_PROC_BIT_30XX_FIRST VPU_TRACE_PROC_BIT_LRT
153#define VPU_TRACE_PROC_BIT_30XX_LAST VPU_TRACE_PROC_BIT_SHV_15
154#define VPU_TRACE_PROC_BIT_KMB_FIRST VPU_TRACE_PROC_BIT_30XX_FIRST
155#define VPU_TRACE_PROC_BIT_KMB_LAST VPU_TRACE_PROC_BIT_30XX_LAST
156
157struct vpu_boot_l2_cache_config {
158 u8 use;
159 u8 cfg;
160};
161
162struct vpu_warm_boot_section {
163 u32 src;
164 u32 dst;
165 u32 size;
166 u32 core_id;
167 u32 is_clear_op;
168};
169
170/*
171 * When HW scheduling mode is enabled, a present period is defined.
172 * It will be used by VPU to swap between normal and focus priorities
173 * to prevent starving of normal priority band (when implemented).
174 * Host must provide a valid value at boot time in
175 * `vpu_focus_present_timer_ms`. If the value provided by the host is not within the
176 * defined range a default value will be used. Here we define the min. and max.
177 * allowed values and the and default value of the present period. Units are milliseconds.
178 */
179#define VPU_PRESENT_CALL_PERIOD_MS_DEFAULT 50
180#define VPU_PRESENT_CALL_PERIOD_MS_MIN 16
181#define VPU_PRESENT_CALL_PERIOD_MS_MAX 10000
182
183/**
184 * Macros to enable various operation modes within the VPU.
185 * To be defined as part of 32 bit mask.
186 */
187#define VPU_OP_MODE_SURVIVABILITY 0x1
188
189struct vpu_boot_params {
190 u32 magic;
191 u32 vpu_id;
192 u32 vpu_count;
193 u32 pad0[5];
194 /* Clock frequencies: 0x20 - 0xFF */
195 u32 frequency;
196 u32 pll[VPU_BOOT_PLL_COUNT][VPU_BOOT_PLL_OUT_COUNT];
197 u32 perf_clk_frequency;
198 u32 pad1[42];
199 /* Memory regions: 0x100 - 0x1FF */
200 u64 ipc_header_area_start;
201 u32 ipc_header_area_size;
202 u64 shared_region_base;
203 u32 shared_region_size;
204 u64 ipc_payload_area_start;
205 u32 ipc_payload_area_size;
206 u64 global_aliased_pio_base;
207 u32 global_aliased_pio_size;
208 u32 autoconfig;
209 struct vpu_boot_l2_cache_config cache_defaults[VPU_BOOT_L2_CACHE_CFG_NUM];
210 u64 global_memory_allocator_base;
211 u32 global_memory_allocator_size;
212 /**
213 * ShaveNN FW section VPU base address
214 * On VPU2.7 HW this address must be within 2GB range starting from L2C_PAGE_TABLE base
215 */
216 u64 shave_nn_fw_base;
217 u64 save_restore_ret_address; /* stores the address of FW's restore entry point */
218 u32 pad2[43];
219 /* IRQ re-direct numbers: 0x200 - 0x2FF */
220 s32 watchdog_irq_mss;
221 s32 watchdog_irq_nce;
222 /* ARM -> VPU doorbell interrupt. ARM is notifying VPU of async command or compute job. */
223 u32 host_to_vpu_irq;
224 /* VPU -> ARM job done interrupt. VPU is notifying ARM of compute job completion. */
225 u32 job_done_irq;
226 /* VPU -> ARM IRQ line to use to request MMU update. */
227 u32 mmu_update_request_irq;
228 /* ARM -> VPU IRQ line to use to notify of MMU update completion. */
229 u32 mmu_update_done_irq;
230 /* ARM -> VPU IRQ line to use to request power level change. */
231 u32 set_power_level_irq;
232 /* VPU -> ARM IRQ line to use to notify of power level change completion. */
233 u32 set_power_level_done_irq;
234 /* VPU -> ARM IRQ line to use to notify of VPU idle state change */
235 u32 set_vpu_idle_update_irq;
236 /* VPU -> ARM IRQ line to use to request counter reset. */
237 u32 metric_query_event_irq;
238 /* ARM -> VPU IRQ line to use to notify of counter reset completion. */
239 u32 metric_query_event_done_irq;
240 /* VPU -> ARM IRQ line to use to notify of preemption completion. */
241 u32 preemption_done_irq;
242 /* Padding. */
243 u32 pad3[52];
244 /* Silicon information: 0x300 - 0x3FF */
245 u32 host_version_id;
246 u32 si_stepping;
247 u64 device_id;
248 u64 feature_exclusion;
249 u64 sku;
250 /** PLL ratio for minimum clock frequency */
251 u32 min_freq_pll_ratio;
252 /** PLL ratio for maximum clock frequency */
253 u32 max_freq_pll_ratio;
254 /**
255 * Initial log level threshold (messages with log level severity less than
256 * the threshold will not be logged); applies to every enabled logging
257 * destination and loggable HW component. See 'mvLog_t' enum for acceptable
258 * values.
259 * TODO: EISW-33556: Move log level definition (mvLog_t) to this file.
260 */
261 u32 default_trace_level;
262 u32 boot_type;
263 u64 punit_telemetry_sram_base;
264 u64 punit_telemetry_sram_size;
265 u32 vpu_telemetry_enable;
266 u64 crit_tracing_buff_addr;
267 u32 crit_tracing_buff_size;
268 u64 verbose_tracing_buff_addr;
269 u32 verbose_tracing_buff_size;
270 u64 verbose_tracing_sw_component_mask; /* TO BE REMOVED */
271 /**
272 * Mask of destinations to which logging messages are delivered; bitwise OR
273 * of values defined in vpu_trace_destination enum.
274 */
275 u32 trace_destination_mask;
276 /**
277 * Mask of hardware components for which logging is enabled; bitwise OR of
278 * bits defined by the VPU_TRACE_PROC_BIT_* macros.
279 */
280 u64 trace_hw_component_mask;
281 /** Mask of trace message formats supported by the driver */
282 u64 tracing_buff_message_format_mask;
283 u64 trace_reserved_1[2];
284 /**
285 * Period at which the VPU reads the temp sensor values into MMIO, on
286 * platforms where that is necessary (in ms). 0 to disable reads.
287 */
288 u32 temp_sensor_period_ms;
289 /** PLL ratio for efficient clock frequency */
290 u32 pn_freq_pll_ratio;
291 /** DVFS Mode: Default: 0, Max Performance: 1, On Demand: 2, Power Save: 3 */
292 u32 dvfs_mode;
293 /**
294 * Depending on DVFS Mode:
295 * On-demand: Default if 0.
296 * Bit 0-7 - uint8_t: Highest residency percent
297 * Bit 8-15 - uint8_t: High residency percent
298 * Bit 16-23 - uint8_t: Low residency percent
299 * Bit 24-31 - uint8_t: Lowest residency percent
300 * Bit 32-35 - unsigned 4b: PLL Ratio increase amount on highest residency
301 * Bit 36-39 - unsigned 4b: PLL Ratio increase amount on high residency
302 * Bit 40-43 - unsigned 4b: PLL Ratio decrease amount on low residency
303 * Bit 44-47 - unsigned 4b: PLL Ratio decrease amount on lowest frequency
304 * Bit 48-55 - uint8_t: Period (ms) for residency decisions
305 * Bit 56-63 - uint8_t: Averaging windows (as multiples of period. Max: 30 decimal)
306 * Power Save/Max Performance: Unused
307 */
308 u64 dvfs_param;
309 /**
310 * D0i3 delayed entry
311 * Bit0: Disable CPU state save on D0i2 entry flow.
312 * 0: Every D0i2 entry saves state. Save state IPC message ignored.
313 * 1: IPC message required to save state on D0i3 entry flow.
314 */
315 u32 d0i3_delayed_entry;
316 /* Time spent by VPU in D0i3 state */
317 u64 d0i3_residency_time_us;
318 /* Value of VPU perf counter at the time of entering D0i3 state . */
319 u64 d0i3_entry_vpu_ts;
320 u32 pad4[20];
321 /* Warm boot information: 0x400 - 0x43F */
322 u32 warm_boot_sections_count;
323 u32 warm_boot_start_address_reference;
324 u32 warm_boot_section_info_address_offset;
325 u32 pad5[13];
326 /* Power States transitions timestamps: 0x440 - 0x46F*/
327 struct {
328 /* VPU_IDLE -> VPU_ACTIVE transition initiated timestamp */
329 u64 vpu_active_state_requested;
330 /* VPU_IDLE -> VPU_ACTIVE transition completed timestamp */
331 u64 vpu_active_state_achieved;
332 /* VPU_ACTIVE -> VPU_IDLE transition initiated timestamp */
333 u64 vpu_idle_state_requested;
334 /* VPU_ACTIVE -> VPU_IDLE transition completed timestamp */
335 u64 vpu_idle_state_achieved;
336 /* VPU_IDLE -> VPU_STANDBY transition initiated timestamp */
337 u64 vpu_standby_state_requested;
338 /* VPU_IDLE -> VPU_STANDBY transition completed timestamp */
339 u64 vpu_standby_state_achieved;
340 } power_states_timestamps;
341 /* VPU scheduling mode. Values defined by VPU_SCHEDULING_MODE_* macros. */
342 u32 vpu_scheduling_mode;
343 /* Present call period in milliseconds. */
344 u32 vpu_focus_present_timer_ms;
345 /* VPU ECC Signaling */
346 u32 vpu_uses_ecc_mca_signal;
347 /* Values defined by VPU_OP_MODE* macros */
348 u32 vpu_operation_mode;
349 /* Unused/reserved: 0x480 - 0xFFF */
350 u32 pad6[736];
351};
352
353/*
354 * Magic numbers set between host and vpu to detect corruptio of tracing init
355 */
356
357#define VPU_TRACING_BUFFER_CANARY (0xCAFECAFE)
358
359/* Tracing buffer message format definitions */
360#define VPU_TRACING_FORMAT_STRING 0
361#define VPU_TRACING_FORMAT_MIPI 2
362/*
363 * Header of the tracing buffer.
364 * The below defined header will be stored at the beginning of
365 * each allocated tracing buffer, followed by a series of 256b
366 * of ASCII trace message entries.
367 */
368struct vpu_tracing_buffer_header {
369 /**
370 * Magic number set by host to detect corruption
371 * @see VPU_TRACING_BUFFER_CANARY
372 */
373 u32 host_canary_start;
374 /* offset from start of buffer for trace entries */
375 u32 read_index;
376 u32 pad_to_cache_line_size_0[14];
377 /* End of first cache line */
378
379 /**
380 * Magic number set by host to detect corruption
381 * @see VPU_TRACING_BUFFER_CANARY
382 */
383 u32 vpu_canary_start;
384 /* offset from start of buffer from write start */
385 u32 write_index;
386 /* counter for buffer wrapping */
387 u32 wrap_count;
388 /* legacy field - do not use */
389 u32 reserved_0;
390 /**
391 * Size of the log buffer include this header (@header_size) and space
392 * reserved for all messages. If @alignment` is greater that 0 the @Size
393 * must be multiple of @Alignment.
394 */
395 u32 size;
396 /* Header version */
397 u16 header_version;
398 /* Header size */
399 u16 header_size;
400 /*
401 * Format of the messages in the trace buffer
402 * 0 - null terminated string
403 * 1 - size + null terminated string
404 * 2 - MIPI-SysT encoding
405 */
406 u32 format;
407 /*
408 * Message alignment
409 * 0 - messages are place 1 after another
410 * n - every message starts and multiple on offset
411 */
412 u32 alignment; /* 64, 128, 256 */
413 /* Name of the logging entity, i.e "LRT", "LNN", "SHV0", etc */
414 char name[16];
415 u32 pad_to_cache_line_size_1[4];
416 /* End of second cache line */
417};
418
419#pragma pack(pop)
420
421#endif