1# SPDX-License-Identifier: GPL-2.0
  2#
  3# For a description of the syntax of this configuration file,
  4# see Documentation/kbuild/kconfig-language.rst.
  5#
  6
  7config OPENRISC
  8	def_bool y
  9	select ARCH_32BIT_OFF_T
 10	select ARCH_HAS_DMA_SET_UNCACHED
 11	select ARCH_HAS_DMA_CLEAR_UNCACHED
 12	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
 13	select COMMON_CLK
 14	select OF
 15	select OF_EARLY_FLATTREE
 16	select IRQ_DOMAIN
 
 17	select GPIOLIB
 18	select HAVE_ARCH_TRACEHOOK
 19	select SPARSE_IRQ
 20	select GENERIC_IRQ_CHIP
 21	select GENERIC_IRQ_PROBE
 22	select GENERIC_IRQ_SHOW
 23	select GENERIC_PCI_IOMAP
 24	select GENERIC_IOREMAP
 25	select GENERIC_CPU_DEVICES
 26	select HAVE_PCI
 27	select HAVE_UID16
 28	select GENERIC_ATOMIC64
 
 29	select GENERIC_CLOCKEVENTS_BROADCAST
 
 
 30	select GENERIC_SMP_IDLE_THREAD
 31	select MODULES_USE_ELF_RELA
 32	select HAVE_DEBUG_STACKOVERFLOW
 33	select OR1K_PIC
 34	select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
 
 35	select ARCH_USE_QUEUED_RWLOCKS
 36	select OMPIC if SMP
 37	select PCI_DOMAINS_GENERIC if PCI
 38	select PCI_MSI if PCI
 39	select ARCH_WANT_FRAME_POINTERS
 40	select GENERIC_IRQ_MULTI_HANDLER
 41	select MMU_GATHER_NO_RANGE if MMU
 42	select TRACE_IRQFLAGS_SUPPORT
 43
 44config CPU_BIG_ENDIAN
 45	def_bool y
 46
 47config MMU
 48	def_bool y
 49
 50config GENERIC_HWEIGHT
 51	def_bool y
 52
 53config NO_IOPORT_MAP
 54	def_bool y
 55
 
 
 
 56# For now, use generic checksum functions
 57#These can be reimplemented in assembly later if so inclined
 58config GENERIC_CSUM
 59	def_bool y
 60
 61config STACKTRACE_SUPPORT
 62	def_bool y
 63
 64config LOCKDEP_SUPPORT
 65	def_bool  y
 66
 67menu "Processor type and features"
 68
 69choice
 70	prompt "Subarchitecture"
 71	default OR1K_1200
 72
 73config OR1K_1200
 74	bool "OR1200"
 75	help
 76	  Generic OpenRISC 1200 architecture
 77
 78endchoice
 79
 80config DCACHE_WRITETHROUGH
 81	bool "Have write through data caches"
 82	default n
 83	help
 84	  Select this if your implementation features write through data caches.
 85	  Selecting 'N' here will allow the kernel to force flushing of data
 86	  caches at relevant times. Most OpenRISC implementations support write-
 87	  through data caches.
 88
 89	  If unsure say N here
 90
 91config OPENRISC_BUILTIN_DTB
 92	string "Builtin DTB"
 93	default ""
 94
 95menu "Class II Instructions"
 96
 97config OPENRISC_HAVE_INST_FF1
 98	bool "Have instruction l.ff1"
 99	default y
100	help
101	  Select this if your implementation has the Class II instruction l.ff1
102
103config OPENRISC_HAVE_INST_FL1
104	bool "Have instruction l.fl1"
105	default y
106	help
107	  Select this if your implementation has the Class II instruction l.fl1
108
109config OPENRISC_HAVE_INST_MUL
110	bool "Have instruction l.mul for hardware multiply"
111	default y
112	help
113	  Select this if your implementation has a hardware multiply instruction
114
115config OPENRISC_HAVE_INST_DIV
116	bool "Have instruction l.div for hardware divide"
117	default y
118	help
119	  Select this if your implementation has a hardware divide instruction
120
121config OPENRISC_HAVE_INST_CMOV
122	bool "Have instruction l.cmov for conditional move"
123	default n
124	help
125	  This config enables gcc to generate l.cmov instructions when compiling
126	  the kernel which in general will improve performance and reduce the
127	  binary size.
128
129	  Select this if your implementation has support for the Class II
130	  l.cmov conistional move instruction.
131
132	  Say N if you are unsure.
133
134config OPENRISC_HAVE_INST_ROR
135	bool "Have instruction l.ror for rotate right"
136	default n
137	help
138	  This config enables gcc to generate l.ror instructions when compiling
139	  the kernel which in general will improve performance and reduce the
140	  binary size.
141
142	  Select this if your implementation has support for the Class II
143	  l.ror rotate right instruction.
144
145	  Say N if you are unsure.
146
147config OPENRISC_HAVE_INST_RORI
148	bool "Have instruction l.rori for rotate right with immediate"
149	default n
150	help
151	  This config enables gcc to generate l.rori instructions when compiling
152	  the kernel which in general will improve performance and reduce the
153	  binary size.
154
155	  Select this if your implementation has support for the Class II
156	  l.rori rotate right with immediate instruction.
157
158	  Say N if you are unsure.
159
160config OPENRISC_HAVE_INST_SEXT
161	bool "Have instructions l.ext* for sign extension"
162	default n
163	help
164	  This config enables gcc to generate l.ext* instructions when compiling
165	  the kernel which in general will improve performance and reduce the
166	  binary size.
167
168	  Select this if your implementation has support for the Class II
169	  l.exths, l.extbs, l.exthz and l.extbz size extend instructions.
170
171	  Say N if you are unsure.
172
173endmenu
174
175config NR_CPUS
176	int "Maximum number of CPUs (2-32)"
177	range 2 32
178	depends on SMP
179	default "2"
180
181config SMP
182	bool "Symmetric Multi-Processing support"
183	help
184	  This enables support for systems with more than one CPU. If you have
185	  a system with only one CPU, say N. If you have a system with more
186	  than one CPU, say Y.
187
188	  If you don't know what to do here, say N.
189
190source "kernel/Kconfig.hz"
191
192config OPENRISC_NO_SPR_SR_DSX
193	bool "use SPR_SR_DSX software emulation" if OR1K_1200
194	default y
195	help
196	  SPR_SR_DSX bit is status register bit indicating whether
197	  the last exception has happened in delay slot.
198
199	  OpenRISC architecture makes it optional to have it implemented
200	  in hardware and the OR1200 does not have it.
201
202	  Say N here if you know that your OpenRISC processor has
203	  SPR_SR_DSX bit implemented. Say Y if you are unsure.
204
205config OPENRISC_HAVE_SHADOW_GPRS
206	bool "Support for shadow gpr files" if !SMP
207	default y if SMP
208	help
209	  Say Y here if your OpenRISC processor features shadowed
210	  register files. They will in such case be used as a
211	  scratch reg storage on exception entry.
212
213	  On SMP systems, this feature is mandatory.
214	  On a unicore system it's safe to say N here if you are unsure.
215
216config CMDLINE
217	string "Default kernel command string"
218	default ""
219	help
220	  On some architectures there is currently no way for the boot loader
221	  to pass arguments to the kernel. For these architectures, you should
222	  supply some command-line options at build time by entering them
223	  here.
224
225menu "Debugging options"
226
227config JUMP_UPON_UNHANDLED_EXCEPTION
228	bool "Try to die gracefully"
229	default y
230	help
231	  Now this puts kernel into infinite loop after first oops. Till
232	  your kernel crashes this doesn't have any influence.
233
234	  Say Y if you are unsure.
235
236config OPENRISC_ESR_EXCEPTION_BUG_CHECK
237	bool "Check for possible ESR exception bug"
238	default n
239	help
240	  This option enables some checks that might expose some problems
241	  in kernel.
242
243	  Say N if you are unsure.
244
245endmenu
246
247endmenu

  1# SPDX-License-Identifier: GPL-2.0
  2#
  3# For a description of the syntax of this configuration file,
  4# see Documentation/kbuild/kconfig-language.rst.
  5#
  6
  7config OPENRISC
  8	def_bool y
  9	select ARCH_32BIT_OFF_T
 
 
 10	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
 
 11	select OF
 12	select OF_EARLY_FLATTREE
 13	select IRQ_DOMAIN
 14	select HANDLE_DOMAIN_IRQ
 15	select GPIOLIB
 16        select HAVE_ARCH_TRACEHOOK
 17	select SPARSE_IRQ
 18	select GENERIC_IRQ_CHIP
 19	select GENERIC_IRQ_PROBE
 20	select GENERIC_IRQ_SHOW
 21	select GENERIC_IOMAP
 
 22	select GENERIC_CPU_DEVICES
 
 23	select HAVE_UID16
 24	select GENERIC_ATOMIC64
 25	select GENERIC_CLOCKEVENTS
 26	select GENERIC_CLOCKEVENTS_BROADCAST
 27	select GENERIC_STRNCPY_FROM_USER
 28	select GENERIC_STRNLEN_USER
 29	select GENERIC_SMP_IDLE_THREAD
 30	select MODULES_USE_ELF_RELA
 31	select HAVE_DEBUG_STACKOVERFLOW
 32	select OR1K_PIC
 33	select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
 34	select ARCH_USE_QUEUED_SPINLOCKS
 35	select ARCH_USE_QUEUED_RWLOCKS
 36	select OMPIC if SMP
 
 
 37	select ARCH_WANT_FRAME_POINTERS
 38	select GENERIC_IRQ_MULTI_HANDLER
 39	select MMU_GATHER_NO_RANGE if MMU
 
 40
 41config CPU_BIG_ENDIAN
 42	def_bool y
 43
 44config MMU
 45	def_bool y
 46
 47config GENERIC_HWEIGHT
 48	def_bool y
 49
 50config NO_IOPORT_MAP
 51	def_bool y
 52
 53config TRACE_IRQFLAGS_SUPPORT
 54        def_bool y
 55
 56# For now, use generic checksum functions
 57#These can be reimplemented in assembly later if so inclined
 58config GENERIC_CSUM
 59        def_bool y
 60
 61config STACKTRACE_SUPPORT
 62	def_bool y
 63
 64config LOCKDEP_SUPPORT
 65	def_bool  y
 66
 67menu "Processor type and features"
 68
 69choice
 70	prompt "Subarchitecture"
 71	default OR1K_1200
 72
 73config OR1K_1200
 74	bool "OR1200"
 75	help
 76	  Generic OpenRISC 1200 architecture
 77
 78endchoice
 79
 80config DCACHE_WRITETHROUGH
 81	bool "Have write through data caches"
 82	default n
 83	help
 84	  Select this if your implementation features write through data caches.
 85	  Selecting 'N' here will allow the kernel to force flushing of data
 86	  caches at relevant times. Most OpenRISC implementations support write-
 87	  through data caches.
 88
 89	  If unsure say N here
 90
 91config OPENRISC_BUILTIN_DTB
 92        string "Builtin DTB"
 93        default ""
 94
 95menu "Class II Instructions"
 96
 97config OPENRISC_HAVE_INST_FF1
 98	bool "Have instruction l.ff1"
 99	default y
100	help
101	  Select this if your implementation has the Class II instruction l.ff1
102
103config OPENRISC_HAVE_INST_FL1
104	bool "Have instruction l.fl1"
105	default y
106	help
107	  Select this if your implementation has the Class II instruction l.fl1
108
109config OPENRISC_HAVE_INST_MUL
110	bool "Have instruction l.mul for hardware multiply"
111	default y
112	help
113	  Select this if your implementation has a hardware multiply instruction
114
115config OPENRISC_HAVE_INST_DIV
116	bool "Have instruction l.div for hardware divide"
117	default y
118	help
119	  Select this if your implementation has a hardware divide instruction
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
120endmenu
121
122config NR_CPUS
123	int "Maximum number of CPUs (2-32)"
124	range 2 32
125	depends on SMP
126	default "2"
127
128config SMP
129	bool "Symmetric Multi-Processing support"
130	help
131	  This enables support for systems with more than one CPU. If you have
132	  a system with only one CPU, say N. If you have a system with more
133	  than one CPU, say Y.
134
135	  If you don't know what to do here, say N.
136
137source "kernel/Kconfig.hz"
138
139config OPENRISC_NO_SPR_SR_DSX
140	bool "use SPR_SR_DSX software emulation" if OR1K_1200
141	default y
142	help
143	  SPR_SR_DSX bit is status register bit indicating whether
144	  the last exception has happened in delay slot.
145
146	  OpenRISC architecture makes it optional to have it implemented
147	  in hardware and the OR1200 does not have it.
148
149	  Say N here if you know that your OpenRISC processor has
150	  SPR_SR_DSX bit implemented. Say Y if you are unsure.
151
152config OPENRISC_HAVE_SHADOW_GPRS
153	bool "Support for shadow gpr files" if !SMP
154	default y if SMP
155	help
156	  Say Y here if your OpenRISC processor features shadowed
157	  register files. They will in such case be used as a
158	  scratch reg storage on exception entry.
159
160	  On SMP systems, this feature is mandatory.
161	  On a unicore system it's safe to say N here if you are unsure.
162
163config CMDLINE
164        string "Default kernel command string"
165        default ""
166        help
167          On some architectures there is currently no way for the boot loader
168          to pass arguments to the kernel. For these architectures, you should
169          supply some command-line options at build time by entering them
170          here.
171
172menu "Debugging options"
173
174config JUMP_UPON_UNHANDLED_EXCEPTION
175	bool "Try to die gracefully"
176	default y
177	help
178	  Now this puts kernel into infinite loop after first oops. Till
179	  your kernel crashes this doesn't have any influence.
180
181	  Say Y if you are unsure.
182
183config OPENRISC_ESR_EXCEPTION_BUG_CHECK
184	bool "Check for possible ESR exception bug"
185	default n
186	help
187	  This option enables some checks that might expose some problems
188          in kernel.
189
190	  Say N if you are unsure.
191
192endmenu
193
194endmenu