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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com>
5 * Copyright (C) 2015 John Crispin <john@phrozen.org>
6 */
7
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/slab.h>
11#include <linux/sys_soc.h>
12#include <linux/memblock.h>
13#include <linux/pci.h>
14#include <linux/bug.h>
15
16#include <asm/bootinfo.h>
17#include <asm/mipsregs.h>
18#include <asm/smp-ops.h>
19#include <asm/mips-cps.h>
20#include <asm/mach-ralink/ralink_regs.h>
21#include <asm/mach-ralink/mt7621.h>
22
23#include "common.h"
24
25#define MT7621_MEM_TEST_PATTERN 0xaa5555aa
26
27static u32 detect_magic __initdata;
28static struct ralink_soc_info *soc_info_ptr;
29
30int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
31{
32 struct resource_entry *entry;
33 resource_size_t mask;
34
35 entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);
36 if (!entry) {
37 pr_err("Cannot get memory resource\n");
38 return -EINVAL;
39 }
40
41 if (mips_cps_numiocu(0)) {
42 /*
43 * Hardware doesn't accept mask values with 1s after
44 * 0s (e.g. 0xffef), so warn if that's happen
45 */
46 mask = ~(entry->res->end - entry->res->start) & CM_GCR_REGn_MASK_ADDRMASK;
47 WARN_ON(mask && BIT(ffz(~mask)) - 1 != ~mask);
48
49 write_gcr_reg1_base(entry->res->start);
50 write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
51 pr_info("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
52 (unsigned long long)read_gcr_reg1_base(),
53 (unsigned long long)read_gcr_reg1_mask());
54 }
55
56 return 0;
57}
58
59phys_addr_t mips_cpc_default_phys_base(void)
60{
61 panic("Cannot detect cpc address");
62}
63
64static bool __init mt7621_addr_wraparound_test(phys_addr_t size)
65{
66 void *dm = (void *)KSEG1ADDR(&detect_magic);
67
68 if (CPHYSADDR(dm + size) >= MT7621_LOWMEM_MAX_SIZE)
69 return true;
70 __raw_writel(MT7621_MEM_TEST_PATTERN, dm);
71 if (__raw_readl(dm) != __raw_readl(dm + size))
72 return false;
73 __raw_writel(~MT7621_MEM_TEST_PATTERN, dm);
74 return __raw_readl(dm) == __raw_readl(dm + size);
75}
76
77static void __init mt7621_memory_detect(void)
78{
79 phys_addr_t size;
80
81 for (size = 32 * SZ_1M; size <= 256 * SZ_1M; size <<= 1) {
82 if (mt7621_addr_wraparound_test(size)) {
83 memblock_add(MT7621_LOWMEM_BASE, size);
84 return;
85 }
86 }
87
88 memblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE);
89 memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);
90}
91
92static unsigned int __init mt7621_get_soc_name0(void)
93{
94 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME0);
95}
96
97static unsigned int __init mt7621_get_soc_name1(void)
98{
99 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME1);
100}
101
102static bool __init mt7621_soc_valid(void)
103{
104 if (mt7621_get_soc_name0() == MT7621_CHIP_NAME0 &&
105 mt7621_get_soc_name1() == MT7621_CHIP_NAME1)
106 return true;
107 else
108 return false;
109}
110
111static const char __init *mt7621_get_soc_id(void)
112{
113 if (mt7621_soc_valid())
114 return "MT7621";
115 else
116 return "invalid";
117}
118
119static unsigned int __init mt7621_get_soc_rev(void)
120{
121 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_REV);
122}
123
124static unsigned int __init mt7621_get_soc_ver(void)
125{
126 return (mt7621_get_soc_rev() >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK;
127}
128
129static unsigned int __init mt7621_get_soc_eco(void)
130{
131 return (mt7621_get_soc_rev() & CHIP_REV_ECO_MASK);
132}
133
134static const char __init *mt7621_get_soc_revision(void)
135{
136 if (mt7621_get_soc_rev() == 1 && mt7621_get_soc_eco() == 1)
137 return "E2";
138 else
139 return "E1";
140}
141
142static int __init mt7621_soc_dev_init(void)
143{
144 struct soc_device *soc_dev;
145 struct soc_device_attribute *soc_dev_attr;
146
147 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
148 if (!soc_dev_attr)
149 return -ENOMEM;
150
151 soc_dev_attr->soc_id = "mt7621";
152 soc_dev_attr->family = "Ralink";
153 soc_dev_attr->revision = mt7621_get_soc_revision();
154
155 soc_dev_attr->data = soc_info_ptr;
156
157 soc_dev = soc_device_register(soc_dev_attr);
158 if (IS_ERR(soc_dev)) {
159 kfree(soc_dev_attr);
160 return PTR_ERR(soc_dev);
161 }
162
163 return 0;
164}
165device_initcall(mt7621_soc_dev_init);
166
167void __init prom_soc_init(struct ralink_soc_info *soc_info)
168{
169 /* Early detection of CMP support */
170 mips_cm_probe();
171 mips_cpc_probe();
172
173 if (mips_cps_numiocu(0)) {
174 /*
175 * mips_cm_probe() wipes out bootloader
176 * config for CM regions and we have to configure them
177 * again. This SoC cannot talk to pamlbus devices
178 * without proper iocu region set up.
179 *
180 * FIXME: it would be better to do this with values
181 * from DT, but we need this very early because
182 * without this we cannot talk to pretty much anything
183 * including serial.
184 */
185 write_gcr_reg0_base(MT7621_PALMBUS_BASE);
186 write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
187 CM_GCR_REGn_MASK_CMTGT_IOCU0);
188 __sync();
189 }
190
191 if (mt7621_soc_valid())
192 soc_info->compatible = "mediatek,mt7621-soc";
193 else
194 panic("mt7621: unknown SoC, n0:%08x n1:%08x\n",
195 mt7621_get_soc_name0(),
196 mt7621_get_soc_name1());
197 ralink_soc = MT762X_SOC_MT7621AT;
198
199 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
200 "MediaTek %s ver:%u eco:%u",
201 mt7621_get_soc_id(),
202 mt7621_get_soc_ver(),
203 mt7621_get_soc_eco());
204
205 soc_info->mem_detect = mt7621_memory_detect;
206
207 soc_info_ptr = soc_info;
208
209 if (!register_cps_smp_ops())
210 return;
211 if (!register_vsmp_smp_ops())
212 return;
213}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com>
5 * Copyright (C) 2015 John Crispin <john@phrozen.org>
6 */
7
8#include <linux/kernel.h>
9#include <linux/init.h>
10
11#include <asm/mipsregs.h>
12#include <asm/smp-ops.h>
13#include <asm/mips-cps.h>
14#include <asm/mach-ralink/ralink_regs.h>
15#include <asm/mach-ralink/mt7621.h>
16
17#include <pinmux.h>
18
19#include "common.h"
20
21#define SYSC_REG_SYSCFG 0x10
22#define SYSC_REG_CPLL_CLKCFG0 0x2c
23#define SYSC_REG_CUR_CLK_STS 0x44
24#define CPU_CLK_SEL (BIT(30) | BIT(31))
25
26#define MT7621_GPIO_MODE_UART1 1
27#define MT7621_GPIO_MODE_I2C 2
28#define MT7621_GPIO_MODE_UART3_MASK 0x3
29#define MT7621_GPIO_MODE_UART3_SHIFT 3
30#define MT7621_GPIO_MODE_UART3_GPIO 1
31#define MT7621_GPIO_MODE_UART2_MASK 0x3
32#define MT7621_GPIO_MODE_UART2_SHIFT 5
33#define MT7621_GPIO_MODE_UART2_GPIO 1
34#define MT7621_GPIO_MODE_JTAG 7
35#define MT7621_GPIO_MODE_WDT_MASK 0x3
36#define MT7621_GPIO_MODE_WDT_SHIFT 8
37#define MT7621_GPIO_MODE_WDT_GPIO 1
38#define MT7621_GPIO_MODE_PCIE_RST 0
39#define MT7621_GPIO_MODE_PCIE_REF 2
40#define MT7621_GPIO_MODE_PCIE_MASK 0x3
41#define MT7621_GPIO_MODE_PCIE_SHIFT 10
42#define MT7621_GPIO_MODE_PCIE_GPIO 1
43#define MT7621_GPIO_MODE_MDIO_MASK 0x3
44#define MT7621_GPIO_MODE_MDIO_SHIFT 12
45#define MT7621_GPIO_MODE_MDIO_GPIO 1
46#define MT7621_GPIO_MODE_RGMII1 14
47#define MT7621_GPIO_MODE_RGMII2 15
48#define MT7621_GPIO_MODE_SPI_MASK 0x3
49#define MT7621_GPIO_MODE_SPI_SHIFT 16
50#define MT7621_GPIO_MODE_SPI_GPIO 1
51#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
52#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
53#define MT7621_GPIO_MODE_SDHCI_GPIO 1
54
55static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
56static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
57static struct rt2880_pmx_func uart3_grp[] = {
58 FUNC("uart3", 0, 5, 4),
59 FUNC("i2s", 2, 5, 4),
60 FUNC("spdif3", 3, 5, 4),
61};
62static struct rt2880_pmx_func uart2_grp[] = {
63 FUNC("uart2", 0, 9, 4),
64 FUNC("pcm", 2, 9, 4),
65 FUNC("spdif2", 3, 9, 4),
66};
67static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
68static struct rt2880_pmx_func wdt_grp[] = {
69 FUNC("wdt rst", 0, 18, 1),
70 FUNC("wdt refclk", 2, 18, 1),
71};
72static struct rt2880_pmx_func pcie_rst_grp[] = {
73 FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
74 FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
75};
76static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
77static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
78static struct rt2880_pmx_func spi_grp[] = {
79 FUNC("spi", 0, 34, 7),
80 FUNC("nand1", 2, 34, 7),
81};
82static struct rt2880_pmx_func sdhci_grp[] = {
83 FUNC("sdhci", 0, 41, 8),
84 FUNC("nand2", 2, 41, 8),
85};
86static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
87
88static struct rt2880_pmx_group mt7621_pinmux_data[] = {
89 GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
90 GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
91 GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,
92 MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),
93 GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,
94 MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),
95 GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
96 GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
97 MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
98 GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
99 MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
100 GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,
101 MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),
102 GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
103 GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
104 MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
105 GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
106 MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
107 GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
108 { 0 }
109};
110
111phys_addr_t mips_cpc_default_phys_base(void)
112{
113 panic("Cannot detect cpc address");
114}
115
116void __init ralink_clk_init(void)
117{
118 int cpu_fdiv = 0;
119 int cpu_ffrac = 0;
120 int fbdiv = 0;
121 u32 clk_sts, syscfg;
122 u8 clk_sel = 0, xtal_mode;
123 u32 cpu_clk;
124
125 if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
126 clk_sel = 1;
127
128 switch (clk_sel) {
129 case 0:
130 clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
131 cpu_fdiv = ((clk_sts >> 8) & 0x1F);
132 cpu_ffrac = (clk_sts & 0x1F);
133 cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
134 break;
135
136 case 1:
137 fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
138 syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
139 xtal_mode = (syscfg >> 6) & 0x7;
140 if (xtal_mode >= 6) {
141 /* 25Mhz Xtal */
142 cpu_clk = 25 * fbdiv * 1000 * 1000;
143 } else if (xtal_mode >= 3) {
144 /* 40Mhz Xtal */
145 cpu_clk = 40 * fbdiv * 1000 * 1000;
146 } else {
147 /* 20Mhz Xtal */
148 cpu_clk = 20 * fbdiv * 1000 * 1000;
149 }
150 break;
151 }
152}
153
154void __init ralink_of_remap(void)
155{
156 rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
157 rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
158
159 if (!rt_sysc_membase || !rt_memc_membase)
160 panic("Failed to remap core resources");
161}
162
163void prom_soc_init(struct ralink_soc_info *soc_info)
164{
165 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
166 unsigned char *name = NULL;
167 u32 n0;
168 u32 n1;
169 u32 rev;
170
171 /* Early detection of CMP support */
172 mips_cm_probe();
173 mips_cpc_probe();
174
175 if (mips_cps_numiocu(0)) {
176 /*
177 * mips_cm_probe() wipes out bootloader
178 * config for CM regions and we have to configure them
179 * again. This SoC cannot talk to pamlbus devices
180 * witout proper iocu region set up.
181 *
182 * FIXME: it would be better to do this with values
183 * from DT, but we need this very early because
184 * without this we cannot talk to pretty much anything
185 * including serial.
186 */
187 write_gcr_reg0_base(MT7621_PALMBUS_BASE);
188 write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
189 CM_GCR_REGn_MASK_CMTGT_IOCU0);
190 __sync();
191 }
192
193 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
194 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
195
196 if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
197 name = "MT7621";
198 soc_info->compatible = "mtk,mt7621-soc";
199 } else {
200 panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
201 }
202 ralink_soc = MT762X_SOC_MT7621AT;
203 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
204
205 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
206 "MediaTek %s ver:%u eco:%u",
207 name,
208 (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
209 (rev & CHIP_REV_ECO_MASK));
210
211 soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
212 soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
213 soc_info->mem_base = MT7621_DRAM_BASE;
214
215 rt2880_pinmux_data = mt7621_pinmux_data;
216
217
218 if (!register_cps_smp_ops())
219 return;
220 if (!register_cmp_smp_ops())
221 return;
222 if (!register_vsmp_smp_ops())
223 return;
224}