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1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2//
3// This file is provided under a dual BSD/GPLv2 license. When using or
4// redistributing this file, you may do so under either license.
5//
6// Copyright(c) 2018 Intel Corporation. All rights reserved.
7//
8// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10// Rander Wang <rander.wang@intel.com>
11// Keyon Jie <yang.jie@linux.intel.com>
12//
13
14/*
15 * Hardware interface for generic Intel audio DSP HDA IP
16 */
17
18#include <linux/module.h>
19#include <sound/hdaudio_ext.h>
20#include <sound/hda_register.h>
21#include <sound/hda_component.h>
22#include <sound/hda-mlink.h>
23#include "../ops.h"
24#include "hda.h"
25
26/*
27 * HDA Operations.
28 */
29
30int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset)
31{
32 unsigned long timeout;
33 u32 gctl = 0;
34 u32 val;
35
36 /* 0 to enter reset and 1 to exit reset */
37 val = reset ? 0 : SOF_HDA_GCTL_RESET;
38
39 /* enter/exit HDA controller reset */
40 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL,
41 SOF_HDA_GCTL_RESET, val);
42
43 /* wait to enter/exit reset */
44 timeout = jiffies + msecs_to_jiffies(HDA_DSP_CTRL_RESET_TIMEOUT);
45 while (time_before(jiffies, timeout)) {
46 gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL);
47 if ((gctl & SOF_HDA_GCTL_RESET) == val)
48 return 0;
49 usleep_range(500, 1000);
50 }
51
52 /* enter/exit reset failed */
53 dev_err(sdev->dev, "error: failed to %s HDA controller gctl 0x%x\n",
54 reset ? "reset" : "ready", gctl);
55 return -EIO;
56}
57
58int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev)
59{
60 struct hdac_bus *bus = sof_to_bus(sdev);
61 u32 cap, offset, feature;
62 int count = 0;
63 int ret;
64
65 /*
66 * On some devices, one reset cycle is necessary before reading
67 * capabilities
68 */
69 ret = hda_dsp_ctrl_link_reset(sdev, true);
70 if (ret < 0)
71 return ret;
72 ret = hda_dsp_ctrl_link_reset(sdev, false);
73 if (ret < 0)
74 return ret;
75
76 offset = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_LLCH);
77
78 do {
79 dev_dbg(sdev->dev, "checking for capabilities at offset 0x%x\n",
80 offset & SOF_HDA_CAP_NEXT_MASK);
81
82 cap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, offset);
83
84 if (cap == -1) {
85 dev_dbg(bus->dev, "Invalid capability reg read\n");
86 break;
87 }
88
89 feature = (cap & SOF_HDA_CAP_ID_MASK) >> SOF_HDA_CAP_ID_OFF;
90
91 switch (feature) {
92 case SOF_HDA_PP_CAP_ID:
93 dev_dbg(sdev->dev, "found DSP capability at 0x%x\n",
94 offset);
95 bus->ppcap = bus->remap_addr + offset;
96 sdev->bar[HDA_DSP_PP_BAR] = bus->ppcap;
97 break;
98 case SOF_HDA_SPIB_CAP_ID:
99 dev_dbg(sdev->dev, "found SPIB capability at 0x%x\n",
100 offset);
101 bus->spbcap = bus->remap_addr + offset;
102 sdev->bar[HDA_DSP_SPIB_BAR] = bus->spbcap;
103 break;
104 case SOF_HDA_DRSM_CAP_ID:
105 dev_dbg(sdev->dev, "found DRSM capability at 0x%x\n",
106 offset);
107 bus->drsmcap = bus->remap_addr + offset;
108 sdev->bar[HDA_DSP_DRSM_BAR] = bus->drsmcap;
109 break;
110 case SOF_HDA_GTS_CAP_ID:
111 dev_dbg(sdev->dev, "found GTS capability at 0x%x\n",
112 offset);
113 bus->gtscap = bus->remap_addr + offset;
114 break;
115 case SOF_HDA_ML_CAP_ID:
116 dev_dbg(sdev->dev, "found ML capability at 0x%x\n",
117 offset);
118 bus->mlcap = bus->remap_addr + offset;
119 break;
120 default:
121 dev_dbg(sdev->dev, "found capability %d at 0x%x\n",
122 feature, offset);
123 break;
124 }
125
126 offset = cap & SOF_HDA_CAP_NEXT_MASK;
127 } while (count++ <= SOF_HDA_MAX_CAPS && offset);
128
129 return 0;
130}
131
132void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable)
133{
134 u32 val = enable ? SOF_HDA_PPCTL_GPROCEN : 0;
135
136 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
137 SOF_HDA_PPCTL_GPROCEN, val);
138}
139
140void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable)
141{
142 u32 val = enable ? SOF_HDA_PPCTL_PIE : 0;
143
144 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
145 SOF_HDA_PPCTL_PIE, val);
146}
147
148void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable)
149{
150 u32 val = enable ? PCI_CGCTL_MISCBDCGE_MASK : 0;
151
152 snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_MISCBDCGE_MASK, val);
153}
154
155/*
156 * enable/disable audio dsp clock gating and power gating bits.
157 * This allows the HW to opportunistically power and clock gate
158 * the audio dsp when it is idle
159 */
160int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable)
161{
162 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
163 u32 val;
164
165 /* enable/disable audio dsp clock gating */
166 val = enable ? PCI_CGCTL_ADSPDCGE : 0;
167 snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_ADSPDCGE, val);
168
169 /* disable the DMI link when requested. But enable only if it wasn't disabled previously */
170 val = enable ? HDA_VS_INTEL_EM2_L1SEN : 0;
171 if (!enable || !hda->l1_disabled)
172 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2,
173 HDA_VS_INTEL_EM2_L1SEN, val);
174
175 /* enable/disable audio dsp power gating */
176 val = enable ? 0 : PCI_PGCTL_ADSPPGD;
177 snd_sof_pci_update_bits(sdev, PCI_PGCTL, PCI_PGCTL_ADSPPGD, val);
178
179 return 0;
180}
181
182int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev)
183{
184 struct hdac_bus *bus = sof_to_bus(sdev);
185 struct hdac_stream *stream;
186 int sd_offset, ret = 0;
187
188 if (bus->chip_init)
189 return 0;
190
191 hda_codec_set_codec_wakeup(sdev, true);
192
193 hda_dsp_ctrl_misc_clock_gating(sdev, false);
194
195 /* reset HDA controller */
196 ret = hda_dsp_ctrl_link_reset(sdev, true);
197 if (ret < 0) {
198 dev_err(sdev->dev, "error: failed to reset HDA controller\n");
199 goto err;
200 }
201
202 usleep_range(500, 1000);
203
204 /* exit HDA controller reset */
205 ret = hda_dsp_ctrl_link_reset(sdev, false);
206 if (ret < 0) {
207 dev_err(sdev->dev, "error: failed to exit HDA controller reset\n");
208 goto err;
209 }
210 usleep_range(1000, 1200);
211
212 hda_codec_detect_mask(sdev);
213
214 /* clear stream status */
215 list_for_each_entry(stream, &bus->stream_list, list) {
216 sd_offset = SOF_STREAM_SD_OFFSET(stream);
217 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
218 sd_offset + SOF_HDA_ADSP_REG_SD_STS,
219 SOF_HDA_CL_DMA_SD_INT_MASK);
220 }
221
222 /* clear WAKESTS */
223 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
224 SOF_HDA_WAKESTS_INT_MASK);
225
226 hda_codec_rirb_status_clear(sdev);
227
228 /* clear interrupt status register */
229 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,
230 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_ALL_STREAM);
231
232 hda_codec_init_cmd_io(sdev);
233
234 /* enable CIE and GIE interrupts */
235 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
236 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN,
237 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN);
238
239 /* program the position buffer */
240 if (bus->use_posbuf && bus->posbuf.addr) {
241 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE,
242 (u32)bus->posbuf.addr);
243 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE,
244 upper_32_bits(bus->posbuf.addr));
245 }
246
247 hda_bus_ml_reset_losidv(bus);
248
249 bus->chip_init = true;
250
251err:
252 hda_dsp_ctrl_misc_clock_gating(sdev, true);
253
254 hda_codec_set_codec_wakeup(sdev, false);
255
256 return ret;
257}
258
259void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev)
260{
261 struct hdac_bus *bus = sof_to_bus(sdev);
262 struct hdac_stream *stream;
263 int sd_offset;
264
265 if (!bus->chip_init)
266 return;
267
268 /* disable interrupts in stream descriptor */
269 list_for_each_entry(stream, &bus->stream_list, list) {
270 sd_offset = SOF_STREAM_SD_OFFSET(stream);
271 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
272 sd_offset +
273 SOF_HDA_ADSP_REG_SD_CTL,
274 SOF_HDA_CL_DMA_SD_INT_MASK,
275 0);
276 }
277
278 /* disable SIE for all streams */
279 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
280 SOF_HDA_INT_ALL_STREAM, 0);
281
282 /* disable controller CIE and GIE */
283 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
284 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN,
285 0);
286
287 /* clear stream status */
288 list_for_each_entry(stream, &bus->stream_list, list) {
289 sd_offset = SOF_STREAM_SD_OFFSET(stream);
290 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
291 sd_offset + SOF_HDA_ADSP_REG_SD_STS,
292 SOF_HDA_CL_DMA_SD_INT_MASK);
293 }
294
295 /* clear WAKESTS */
296 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
297 SOF_HDA_WAKESTS_INT_MASK);
298
299 hda_codec_rirb_status_clear(sdev);
300
301 /* clear interrupt status register */
302 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,
303 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_ALL_STREAM);
304
305 hda_codec_stop_cmd_io(sdev);
306
307 /* disable position buffer */
308 if (bus->use_posbuf && bus->posbuf.addr) {
309 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
310 SOF_HDA_ADSP_DPLBASE, 0);
311 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
312 SOF_HDA_ADSP_DPUBASE, 0);
313 }
314
315 bus->chip_init = false;
316}
1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2//
3// This file is provided under a dual BSD/GPLv2 license. When using or
4// redistributing this file, you may do so under either license.
5//
6// Copyright(c) 2018 Intel Corporation. All rights reserved.
7//
8// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10// Rander Wang <rander.wang@intel.com>
11// Keyon Jie <yang.jie@linux.intel.com>
12//
13
14/*
15 * Hardware interface for generic Intel audio DSP HDA IP
16 */
17
18#include <sound/hdaudio_ext.h>
19#include <sound/hda_register.h>
20#include "../ops.h"
21#include "hda.h"
22
23/*
24 * HDA Operations.
25 */
26
27int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset)
28{
29 unsigned long timeout;
30 u32 gctl = 0;
31 u32 val;
32
33 /* 0 to enter reset and 1 to exit reset */
34 val = reset ? 0 : SOF_HDA_GCTL_RESET;
35
36 /* enter/exit HDA controller reset */
37 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL,
38 SOF_HDA_GCTL_RESET, val);
39
40 /* wait to enter/exit reset */
41 timeout = jiffies + msecs_to_jiffies(HDA_DSP_CTRL_RESET_TIMEOUT);
42 while (time_before(jiffies, timeout)) {
43 gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL);
44 if ((gctl & SOF_HDA_GCTL_RESET) == val)
45 return 0;
46 usleep_range(500, 1000);
47 }
48
49 /* enter/exit reset failed */
50 dev_err(sdev->dev, "error: failed to %s HDA controller gctl 0x%x\n",
51 reset ? "reset" : "ready", gctl);
52 return -EIO;
53}
54
55int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev)
56{
57 struct hdac_bus *bus = sof_to_bus(sdev);
58 u32 cap, offset, feature;
59 int count = 0;
60
61 offset = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_LLCH);
62
63 do {
64 cap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, offset);
65
66 dev_dbg(sdev->dev, "checking for capabilities at offset 0x%x\n",
67 offset & SOF_HDA_CAP_NEXT_MASK);
68
69 feature = (cap & SOF_HDA_CAP_ID_MASK) >> SOF_HDA_CAP_ID_OFF;
70
71 switch (feature) {
72 case SOF_HDA_PP_CAP_ID:
73 dev_dbg(sdev->dev, "found DSP capability at 0x%x\n",
74 offset);
75 bus->ppcap = bus->remap_addr + offset;
76 sdev->bar[HDA_DSP_PP_BAR] = bus->ppcap;
77 break;
78 case SOF_HDA_SPIB_CAP_ID:
79 dev_dbg(sdev->dev, "found SPIB capability at 0x%x\n",
80 offset);
81 bus->spbcap = bus->remap_addr + offset;
82 sdev->bar[HDA_DSP_SPIB_BAR] = bus->spbcap;
83 break;
84 case SOF_HDA_DRSM_CAP_ID:
85 dev_dbg(sdev->dev, "found DRSM capability at 0x%x\n",
86 offset);
87 bus->drsmcap = bus->remap_addr + offset;
88 sdev->bar[HDA_DSP_DRSM_BAR] = bus->drsmcap;
89 break;
90 case SOF_HDA_GTS_CAP_ID:
91 dev_dbg(sdev->dev, "found GTS capability at 0x%x\n",
92 offset);
93 bus->gtscap = bus->remap_addr + offset;
94 break;
95 case SOF_HDA_ML_CAP_ID:
96 dev_dbg(sdev->dev, "found ML capability at 0x%x\n",
97 offset);
98 bus->mlcap = bus->remap_addr + offset;
99 break;
100 default:
101 dev_vdbg(sdev->dev, "found capability %d at 0x%x\n",
102 feature, offset);
103 break;
104 }
105
106 offset = cap & SOF_HDA_CAP_NEXT_MASK;
107 } while (count++ <= SOF_HDA_MAX_CAPS && offset);
108
109 return 0;
110}
111
112void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable)
113{
114 u32 val = enable ? SOF_HDA_PPCTL_GPROCEN : 0;
115
116 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
117 SOF_HDA_PPCTL_GPROCEN, val);
118}
119
120void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable)
121{
122 u32 val = enable ? SOF_HDA_PPCTL_PIE : 0;
123
124 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
125 SOF_HDA_PPCTL_PIE, val);
126}
127
128void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable)
129{
130 u32 val = enable ? PCI_CGCTL_MISCBDCGE_MASK : 0;
131
132 snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_MISCBDCGE_MASK, val);
133}
134
135/*
136 * enable/disable audio dsp clock gating and power gating bits.
137 * This allows the HW to opportunistically power and clock gate
138 * the audio dsp when it is idle
139 */
140int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable)
141{
142 u32 val;
143
144 /* enable/disable audio dsp clock gating */
145 val = enable ? PCI_CGCTL_ADSPDCGE : 0;
146 snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_ADSPDCGE, val);
147
148 /* enable/disable DMI Link L1 support */
149 val = enable ? HDA_VS_INTEL_EM2_L1SEN : 0;
150 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2,
151 HDA_VS_INTEL_EM2_L1SEN, val);
152
153 /* enable/disable audio dsp power gating */
154 val = enable ? 0 : PCI_PGCTL_ADSPPGD;
155 snd_sof_pci_update_bits(sdev, PCI_PGCTL, PCI_PGCTL_ADSPPGD, val);
156
157 return 0;
158}
159
160int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset)
161{
162 struct hdac_bus *bus = sof_to_bus(sdev);
163#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
164 struct hdac_ext_link *hlink;
165#endif
166 struct hdac_stream *stream;
167 int sd_offset, ret = 0;
168
169 if (bus->chip_init)
170 return 0;
171
172 hda_dsp_ctrl_misc_clock_gating(sdev, false);
173
174 if (full_reset) {
175 /* reset HDA controller */
176 ret = hda_dsp_ctrl_link_reset(sdev, true);
177 if (ret < 0) {
178 dev_err(sdev->dev, "error: failed to reset HDA controller\n");
179 return ret;
180 }
181
182 usleep_range(500, 1000);
183
184 /* exit HDA controller reset */
185 ret = hda_dsp_ctrl_link_reset(sdev, false);
186 if (ret < 0) {
187 dev_err(sdev->dev, "error: failed to exit HDA controller reset\n");
188 return ret;
189 }
190
191 usleep_range(1000, 1200);
192 }
193
194#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
195 /* check to see if controller is ready */
196 if (!snd_hdac_chip_readb(bus, GCTL)) {
197 dev_dbg(bus->dev, "controller not ready!\n");
198 return -EBUSY;
199 }
200
201 /* Accept unsolicited responses */
202 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL);
203
204 /* detect codecs */
205 if (!bus->codec_mask) {
206 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
207 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
208 }
209#endif
210
211 /* clear stream status */
212 list_for_each_entry(stream, &bus->stream_list, list) {
213 sd_offset = SOF_STREAM_SD_OFFSET(stream);
214 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
215 sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
216 SOF_HDA_CL_DMA_SD_INT_MASK);
217 }
218
219 /* clear WAKESTS */
220 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
221 SOF_HDA_WAKESTS_INT_MASK);
222
223#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
224 /* clear rirb status */
225 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
226#endif
227
228 /* clear interrupt status register */
229 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,
230 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_ALL_STREAM);
231
232#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
233 /* initialize the codec command I/O */
234 snd_hdac_bus_init_cmd_io(bus);
235#endif
236
237 /* enable CIE and GIE interrupts */
238 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
239 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN,
240 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN);
241
242 /* program the position buffer */
243 if (bus->use_posbuf && bus->posbuf.addr) {
244 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE,
245 (u32)bus->posbuf.addr);
246 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE,
247 upper_32_bits(bus->posbuf.addr));
248 }
249
250#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
251 /* Reset stream-to-link mapping */
252 list_for_each_entry(hlink, &bus->hlink_list, list)
253 writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
254#endif
255
256 bus->chip_init = true;
257
258 hda_dsp_ctrl_misc_clock_gating(sdev, true);
259
260 return ret;
261}
262
263void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev)
264{
265 struct hdac_bus *bus = sof_to_bus(sdev);
266 struct hdac_stream *stream;
267 int sd_offset;
268
269 if (!bus->chip_init)
270 return;
271
272 /* disable interrupts in stream descriptor */
273 list_for_each_entry(stream, &bus->stream_list, list) {
274 sd_offset = SOF_STREAM_SD_OFFSET(stream);
275 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
276 sd_offset +
277 SOF_HDA_ADSP_REG_CL_SD_CTL,
278 SOF_HDA_CL_DMA_SD_INT_MASK,
279 0);
280 }
281
282 /* disable SIE for all streams */
283 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
284 SOF_HDA_INT_ALL_STREAM, 0);
285
286 /* disable controller CIE and GIE */
287 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
288 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN,
289 0);
290
291 /* clear stream status */
292 list_for_each_entry(stream, &bus->stream_list, list) {
293 sd_offset = SOF_STREAM_SD_OFFSET(stream);
294 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
295 sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
296 SOF_HDA_CL_DMA_SD_INT_MASK);
297 }
298
299 /* clear WAKESTS */
300 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
301 SOF_HDA_WAKESTS_INT_MASK);
302
303#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
304 /* clear rirb status */
305 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
306#endif
307
308 /* clear interrupt status register */
309 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,
310 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_ALL_STREAM);
311
312#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
313 /* disable CORB/RIRB */
314 snd_hdac_bus_stop_cmd_io(bus);
315#endif
316 /* disable position buffer */
317 if (bus->posbuf.addr) {
318 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
319 SOF_HDA_ADSP_DPLBASE, 0);
320 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
321 SOF_HDA_ADSP_DPUBASE, 0);
322 }
323
324 bus->chip_init = false;
325}