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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * USB Gadget driver for LPC32xx
4 *
5 * Authors:
6 * Kevin Wells <kevin.wells@nxp.com>
7 * Mike James
8 * Roland Stigge <stigge@antcom.de>
9 *
10 * Copyright (C) 2006 Philips Semiconductors
11 * Copyright (C) 2009 NXP Semiconductors
12 * Copyright (C) 2012 Roland Stigge
13 *
14 * Note: This driver is based on original work done by Mike James for
15 * the LPC3180.
16 */
17
18#include <linux/clk.h>
19#include <linux/delay.h>
20#include <linux/dma-mapping.h>
21#include <linux/dmapool.h>
22#include <linux/i2c.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/platform_device.h>
27#include <linux/prefetch.h>
28#include <linux/proc_fs.h>
29#include <linux/slab.h>
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32#include <linux/usb/isp1301.h>
33
34#ifdef CONFIG_USB_GADGET_DEBUG_FILES
35#include <linux/debugfs.h>
36#include <linux/seq_file.h>
37#endif
38
39/*
40 * USB device configuration structure
41 */
42typedef void (*usc_chg_event)(int);
43struct lpc32xx_usbd_cfg {
44 int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */
45 usc_chg_event conn_chgb; /* Connection change event (optional) */
46 usc_chg_event susp_chgb; /* Suspend/resume event (optional) */
47 usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */
48};
49
50/*
51 * controller driver data structures
52 */
53
54/* 16 endpoints (not to be confused with 32 hardware endpoints) */
55#define NUM_ENDPOINTS 16
56
57/*
58 * IRQ indices make reading the code a little easier
59 */
60#define IRQ_USB_LP 0
61#define IRQ_USB_HP 1
62#define IRQ_USB_DEVDMA 2
63#define IRQ_USB_ATX 3
64
65#define EP_OUT 0 /* RX (from host) */
66#define EP_IN 1 /* TX (to host) */
67
68/* Returns the interrupt mask for the selected hardware endpoint */
69#define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
70
71#define EP_INT_TYPE 0
72#define EP_ISO_TYPE 1
73#define EP_BLK_TYPE 2
74#define EP_CTL_TYPE 3
75
76/* EP0 states */
77#define WAIT_FOR_SETUP 0 /* Wait for setup packet */
78#define DATA_IN 1 /* Expect dev->host transfer */
79#define DATA_OUT 2 /* Expect host->dev transfer */
80
81/* DD (DMA Descriptor) structure, requires word alignment, this is already
82 * defined in the LPC32XX USB device header file, but this version is slightly
83 * modified to tag some work data with each DMA descriptor. */
84struct lpc32xx_usbd_dd_gad {
85 u32 dd_next_phy;
86 u32 dd_setup;
87 u32 dd_buffer_addr;
88 u32 dd_status;
89 u32 dd_iso_ps_mem_addr;
90 u32 this_dma;
91 u32 iso_status[6]; /* 5 spare */
92 u32 dd_next_v;
93};
94
95/*
96 * Logical endpoint structure
97 */
98struct lpc32xx_ep {
99 struct usb_ep ep;
100 struct list_head queue;
101 struct lpc32xx_udc *udc;
102
103 u32 hwep_num_base; /* Physical hardware EP */
104 u32 hwep_num; /* Maps to hardware endpoint */
105 u32 maxpacket;
106 u32 lep;
107
108 bool is_in;
109 bool req_pending;
110 u32 eptype;
111
112 u32 totalints;
113
114 bool wedge;
115};
116
117enum atx_type {
118 ISP1301,
119 STOTG04,
120};
121
122/*
123 * Common UDC structure
124 */
125struct lpc32xx_udc {
126 struct usb_gadget gadget;
127 struct usb_gadget_driver *driver;
128 struct platform_device *pdev;
129 struct device *dev;
130 spinlock_t lock;
131 struct i2c_client *isp1301_i2c_client;
132
133 /* Board and device specific */
134 struct lpc32xx_usbd_cfg *board;
135 void __iomem *udp_baseaddr;
136 int udp_irq[4];
137 struct clk *usb_slv_clk;
138
139 /* DMA support */
140 u32 *udca_v_base;
141 u32 udca_p_base;
142 struct dma_pool *dd_cache;
143
144 /* Common EP and control data */
145 u32 enabled_devints;
146 u32 enabled_hwepints;
147 u32 dev_status;
148 u32 realized_eps;
149
150 /* VBUS detection, pullup, and power flags */
151 u8 vbus;
152 u8 last_vbus;
153 int pullup;
154 int poweron;
155 enum atx_type atx;
156
157 /* Work queues related to I2C support */
158 struct work_struct pullup_job;
159 struct work_struct power_job;
160
161 /* USB device peripheral - various */
162 struct lpc32xx_ep ep[NUM_ENDPOINTS];
163 bool enabled;
164 bool clocked;
165 bool suspended;
166 int ep0state;
167 atomic_t enabled_ep_cnt;
168 wait_queue_head_t ep_disable_wait_queue;
169};
170
171/*
172 * Endpoint request
173 */
174struct lpc32xx_request {
175 struct usb_request req;
176 struct list_head queue;
177 struct lpc32xx_usbd_dd_gad *dd_desc_ptr;
178 bool mapped;
179 bool send_zlp;
180};
181
182static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g)
183{
184 return container_of(g, struct lpc32xx_udc, gadget);
185}
186
187#define ep_dbg(epp, fmt, arg...) \
188 dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg)
189#define ep_err(epp, fmt, arg...) \
190 dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg)
191#define ep_info(epp, fmt, arg...) \
192 dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg)
193#define ep_warn(epp, fmt, arg...) \
194 dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg)
195
196#define UDCA_BUFF_SIZE (128)
197
198/**********************************************************************
199 * USB device controller register offsets
200 **********************************************************************/
201
202#define USBD_DEVINTST(x) ((x) + 0x200)
203#define USBD_DEVINTEN(x) ((x) + 0x204)
204#define USBD_DEVINTCLR(x) ((x) + 0x208)
205#define USBD_DEVINTSET(x) ((x) + 0x20C)
206#define USBD_CMDCODE(x) ((x) + 0x210)
207#define USBD_CMDDATA(x) ((x) + 0x214)
208#define USBD_RXDATA(x) ((x) + 0x218)
209#define USBD_TXDATA(x) ((x) + 0x21C)
210#define USBD_RXPLEN(x) ((x) + 0x220)
211#define USBD_TXPLEN(x) ((x) + 0x224)
212#define USBD_CTRL(x) ((x) + 0x228)
213#define USBD_DEVINTPRI(x) ((x) + 0x22C)
214#define USBD_EPINTST(x) ((x) + 0x230)
215#define USBD_EPINTEN(x) ((x) + 0x234)
216#define USBD_EPINTCLR(x) ((x) + 0x238)
217#define USBD_EPINTSET(x) ((x) + 0x23C)
218#define USBD_EPINTPRI(x) ((x) + 0x240)
219#define USBD_REEP(x) ((x) + 0x244)
220#define USBD_EPIND(x) ((x) + 0x248)
221#define USBD_EPMAXPSIZE(x) ((x) + 0x24C)
222/* DMA support registers only below */
223/* Set, clear, or get enabled state of the DMA request status. If
224 * enabled, an IN or OUT token will start a DMA transfer for the EP */
225#define USBD_DMARST(x) ((x) + 0x250)
226#define USBD_DMARCLR(x) ((x) + 0x254)
227#define USBD_DMARSET(x) ((x) + 0x258)
228/* DMA UDCA head pointer */
229#define USBD_UDCAH(x) ((x) + 0x280)
230/* EP DMA status, enable, and disable. This is used to specifically
231 * enabled or disable DMA for a specific EP */
232#define USBD_EPDMAST(x) ((x) + 0x284)
233#define USBD_EPDMAEN(x) ((x) + 0x288)
234#define USBD_EPDMADIS(x) ((x) + 0x28C)
235/* DMA master interrupts enable and pending interrupts */
236#define USBD_DMAINTST(x) ((x) + 0x290)
237#define USBD_DMAINTEN(x) ((x) + 0x294)
238/* DMA end of transfer interrupt enable, disable, status */
239#define USBD_EOTINTST(x) ((x) + 0x2A0)
240#define USBD_EOTINTCLR(x) ((x) + 0x2A4)
241#define USBD_EOTINTSET(x) ((x) + 0x2A8)
242/* New DD request interrupt enable, disable, status */
243#define USBD_NDDRTINTST(x) ((x) + 0x2AC)
244#define USBD_NDDRTINTCLR(x) ((x) + 0x2B0)
245#define USBD_NDDRTINTSET(x) ((x) + 0x2B4)
246/* DMA error interrupt enable, disable, status */
247#define USBD_SYSERRTINTST(x) ((x) + 0x2B8)
248#define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC)
249#define USBD_SYSERRTINTSET(x) ((x) + 0x2C0)
250
251/**********************************************************************
252 * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/
253 * USBD_DEVINTPRI register definitions
254 **********************************************************************/
255#define USBD_ERR_INT (1 << 9)
256#define USBD_EP_RLZED (1 << 8)
257#define USBD_TXENDPKT (1 << 7)
258#define USBD_RXENDPKT (1 << 6)
259#define USBD_CDFULL (1 << 5)
260#define USBD_CCEMPTY (1 << 4)
261#define USBD_DEV_STAT (1 << 3)
262#define USBD_EP_SLOW (1 << 2)
263#define USBD_EP_FAST (1 << 1)
264#define USBD_FRAME (1 << 0)
265
266/**********************************************************************
267 * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/
268 * USBD_EPINTPRI register definitions
269 **********************************************************************/
270/* End point selection macro (RX) */
271#define USBD_RX_EP_SEL(e) (1 << ((e) << 1))
272
273/* End point selection macro (TX) */
274#define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1))
275
276/**********************************************************************
277 * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/
278 * USBD_EPDMAEN/USBD_EPDMADIS/
279 * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/
280 * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/
281 * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET
282 * register definitions
283 **********************************************************************/
284/* Endpoint selection macro */
285#define USBD_EP_SEL(e) (1 << (e))
286
287/**********************************************************************
288 * SBD_DMAINTST/USBD_DMAINTEN
289 **********************************************************************/
290#define USBD_SYS_ERR_INT (1 << 2)
291#define USBD_NEW_DD_INT (1 << 1)
292#define USBD_EOT_INT (1 << 0)
293
294/**********************************************************************
295 * USBD_RXPLEN register definitions
296 **********************************************************************/
297#define USBD_PKT_RDY (1 << 11)
298#define USBD_DV (1 << 10)
299#define USBD_PK_LEN_MASK 0x3FF
300
301/**********************************************************************
302 * USBD_CTRL register definitions
303 **********************************************************************/
304#define USBD_LOG_ENDPOINT(e) ((e) << 2)
305#define USBD_WR_EN (1 << 1)
306#define USBD_RD_EN (1 << 0)
307
308/**********************************************************************
309 * USBD_CMDCODE register definitions
310 **********************************************************************/
311#define USBD_CMD_CODE(c) ((c) << 16)
312#define USBD_CMD_PHASE(p) ((p) << 8)
313
314/**********************************************************************
315 * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions
316 **********************************************************************/
317#define USBD_DMAEP(e) (1 << (e))
318
319/* DD (DMA Descriptor) structure, requires word alignment */
320struct lpc32xx_usbd_dd {
321 u32 *dd_next;
322 u32 dd_setup;
323 u32 dd_buffer_addr;
324 u32 dd_status;
325 u32 dd_iso_ps_mem_addr;
326};
327
328/* dd_setup bit defines */
329#define DD_SETUP_ATLE_DMA_MODE 0x01
330#define DD_SETUP_NEXT_DD_VALID 0x04
331#define DD_SETUP_ISO_EP 0x10
332#define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5)
333#define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16)
334
335/* dd_status bit defines */
336#define DD_STATUS_DD_RETIRED 0x01
337#define DD_STATUS_STS_MASK 0x1E
338#define DD_STATUS_STS_NS 0x00 /* Not serviced */
339#define DD_STATUS_STS_BS 0x02 /* Being serviced */
340#define DD_STATUS_STS_NC 0x04 /* Normal completion */
341#define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */
342#define DD_STATUS_STS_DOR 0x08 /* Data overrun */
343#define DD_STATUS_STS_SE 0x12 /* System error */
344#define DD_STATUS_PKT_VAL 0x20 /* Packet valid */
345#define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */
346#define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */
347#define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F)
348#define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF)
349
350/*
351 *
352 * Protocol engine bits below
353 *
354 */
355/* Device Interrupt Bit Definitions */
356#define FRAME_INT 0x00000001
357#define EP_FAST_INT 0x00000002
358#define EP_SLOW_INT 0x00000004
359#define DEV_STAT_INT 0x00000008
360#define CCEMTY_INT 0x00000010
361#define CDFULL_INT 0x00000020
362#define RxENDPKT_INT 0x00000040
363#define TxENDPKT_INT 0x00000080
364#define EP_RLZED_INT 0x00000100
365#define ERR_INT 0x00000200
366
367/* Rx & Tx Packet Length Definitions */
368#define PKT_LNGTH_MASK 0x000003FF
369#define PKT_DV 0x00000400
370#define PKT_RDY 0x00000800
371
372/* USB Control Definitions */
373#define CTRL_RD_EN 0x00000001
374#define CTRL_WR_EN 0x00000002
375
376/* Command Codes */
377#define CMD_SET_ADDR 0x00D00500
378#define CMD_CFG_DEV 0x00D80500
379#define CMD_SET_MODE 0x00F30500
380#define CMD_RD_FRAME 0x00F50500
381#define DAT_RD_FRAME 0x00F50200
382#define CMD_RD_TEST 0x00FD0500
383#define DAT_RD_TEST 0x00FD0200
384#define CMD_SET_DEV_STAT 0x00FE0500
385#define CMD_GET_DEV_STAT 0x00FE0500
386#define DAT_GET_DEV_STAT 0x00FE0200
387#define CMD_GET_ERR_CODE 0x00FF0500
388#define DAT_GET_ERR_CODE 0x00FF0200
389#define CMD_RD_ERR_STAT 0x00FB0500
390#define DAT_RD_ERR_STAT 0x00FB0200
391#define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
392#define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
393#define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
394#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
395#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
396#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
397#define CMD_CLR_BUF 0x00F20500
398#define DAT_CLR_BUF 0x00F20200
399#define CMD_VALID_BUF 0x00FA0500
400
401/* Device Address Register Definitions */
402#define DEV_ADDR_MASK 0x7F
403#define DEV_EN 0x80
404
405/* Device Configure Register Definitions */
406#define CONF_DVICE 0x01
407
408/* Device Mode Register Definitions */
409#define AP_CLK 0x01
410#define INAK_CI 0x02
411#define INAK_CO 0x04
412#define INAK_II 0x08
413#define INAK_IO 0x10
414#define INAK_BI 0x20
415#define INAK_BO 0x40
416
417/* Device Status Register Definitions */
418#define DEV_CON 0x01
419#define DEV_CON_CH 0x02
420#define DEV_SUS 0x04
421#define DEV_SUS_CH 0x08
422#define DEV_RST 0x10
423
424/* Error Code Register Definitions */
425#define ERR_EC_MASK 0x0F
426#define ERR_EA 0x10
427
428/* Error Status Register Definitions */
429#define ERR_PID 0x01
430#define ERR_UEPKT 0x02
431#define ERR_DCRC 0x04
432#define ERR_TIMOUT 0x08
433#define ERR_EOP 0x10
434#define ERR_B_OVRN 0x20
435#define ERR_BTSTF 0x40
436#define ERR_TGL 0x80
437
438/* Endpoint Select Register Definitions */
439#define EP_SEL_F 0x01
440#define EP_SEL_ST 0x02
441#define EP_SEL_STP 0x04
442#define EP_SEL_PO 0x08
443#define EP_SEL_EPN 0x10
444#define EP_SEL_B_1_FULL 0x20
445#define EP_SEL_B_2_FULL 0x40
446
447/* Endpoint Status Register Definitions */
448#define EP_STAT_ST 0x01
449#define EP_STAT_DA 0x20
450#define EP_STAT_RF_MO 0x40
451#define EP_STAT_CND_ST 0x80
452
453/* Clear Buffer Register Definitions */
454#define CLR_BUF_PO 0x01
455
456/* DMA Interrupt Bit Definitions */
457#define EOT_INT 0x01
458#define NDD_REQ_INT 0x02
459#define SYS_ERR_INT 0x04
460
461#define DRIVER_VERSION "1.03"
462static const char driver_name[] = "lpc32xx_udc";
463
464/*
465 *
466 * proc interface support
467 *
468 */
469#ifdef CONFIG_USB_GADGET_DEBUG_FILES
470static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"};
471static const char debug_filename[] = "driver/udc";
472
473static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep)
474{
475 struct lpc32xx_request *req;
476
477 seq_printf(s, "\n");
478 seq_printf(s, "%12s, maxpacket %4d %3s",
479 ep->ep.name, ep->ep.maxpacket,
480 ep->is_in ? "in" : "out");
481 seq_printf(s, " type %4s", epnames[ep->eptype]);
482 seq_printf(s, " ints: %12d", ep->totalints);
483
484 if (list_empty(&ep->queue))
485 seq_printf(s, "\t(queue empty)\n");
486 else {
487 list_for_each_entry(req, &ep->queue, queue) {
488 u32 length = req->req.actual;
489
490 seq_printf(s, "\treq %p len %d/%d buf %p\n",
491 &req->req, length,
492 req->req.length, req->req.buf);
493 }
494 }
495}
496
497static int udc_show(struct seq_file *s, void *unused)
498{
499 struct lpc32xx_udc *udc = s->private;
500 struct lpc32xx_ep *ep;
501 unsigned long flags;
502
503 seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION);
504
505 spin_lock_irqsave(&udc->lock, flags);
506
507 seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
508 udc->vbus ? "present" : "off",
509 udc->enabled ? (udc->vbus ? "active" : "enabled") :
510 "disabled",
511 udc->gadget.is_selfpowered ? "self" : "VBUS",
512 udc->suspended ? ", suspended" : "",
513 udc->driver ? udc->driver->driver.name : "(none)");
514
515 if (udc->enabled && udc->vbus) {
516 proc_ep_show(s, &udc->ep[0]);
517 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
518 proc_ep_show(s, ep);
519 }
520
521 spin_unlock_irqrestore(&udc->lock, flags);
522
523 return 0;
524}
525
526DEFINE_SHOW_ATTRIBUTE(udc);
527
528static void create_debug_file(struct lpc32xx_udc *udc)
529{
530 debugfs_create_file(debug_filename, 0, NULL, udc, &udc_fops);
531}
532
533static void remove_debug_file(struct lpc32xx_udc *udc)
534{
535 debugfs_lookup_and_remove(debug_filename, NULL);
536}
537
538#else
539static inline void create_debug_file(struct lpc32xx_udc *udc) {}
540static inline void remove_debug_file(struct lpc32xx_udc *udc) {}
541#endif
542
543/* Primary initialization sequence for the ISP1301 transceiver */
544static void isp1301_udc_configure(struct lpc32xx_udc *udc)
545{
546 u8 value;
547 s32 vendor, product;
548
549 vendor = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00);
550 product = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02);
551
552 if (vendor == 0x0483 && product == 0xa0c4)
553 udc->atx = STOTG04;
554
555 /* LPC32XX only supports DAT_SE0 USB mode */
556 /* This sequence is important */
557
558 /* Disable transparent UART mode first */
559 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
560 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
561 MC1_UART_EN);
562
563 /* Set full speed and SE0 mode */
564 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
565 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
566 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
567 ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0));
568
569 /*
570 * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide
571 */
572 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
573 (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
574
575 value = MC2_BI_DI;
576 if (udc->atx != STOTG04)
577 value |= MC2_SPD_SUSP_CTRL;
578 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
579 ISP1301_I2C_MODE_CONTROL_2, value);
580
581 /* Driver VBUS_DRV high or low depending on board setup */
582 if (udc->board->vbus_drv_pol != 0)
583 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
584 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
585 else
586 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
587 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
588 OTG1_VBUS_DRV);
589
590 /* Bi-directional mode with suspend control
591 * Enable both pulldowns for now - the pullup will be enable when VBUS
592 * is detected */
593 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
594 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
595 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
596 ISP1301_I2C_OTG_CONTROL_1,
597 (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
598
599 /* Discharge VBUS (just in case) */
600 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
601 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
602 msleep(1);
603 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
604 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
605 OTG1_VBUS_DISCHRG);
606
607 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
608 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
609
610 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
611 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
612 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
613 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
614
615 dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n", vendor);
616 dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n", product);
617 dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n",
618 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14));
619
620}
621
622/* Enables or disables the USB device pullup via the ISP1301 transceiver */
623static void isp1301_pullup_set(struct lpc32xx_udc *udc)
624{
625 if (udc->pullup)
626 /* Enable pullup for bus signalling */
627 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
628 ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP);
629 else
630 /* Enable pullup for bus signalling */
631 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
632 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
633 OTG1_DP_PULLUP);
634}
635
636static void pullup_work(struct work_struct *work)
637{
638 struct lpc32xx_udc *udc =
639 container_of(work, struct lpc32xx_udc, pullup_job);
640
641 isp1301_pullup_set(udc);
642}
643
644static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
645 int block)
646{
647 if (en_pullup == udc->pullup)
648 return;
649
650 udc->pullup = en_pullup;
651 if (block)
652 isp1301_pullup_set(udc);
653 else
654 /* defer slow i2c pull up setting */
655 schedule_work(&udc->pullup_job);
656}
657
658#ifdef CONFIG_PM
659/* Powers up or down the ISP1301 transceiver */
660static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable)
661{
662 /* There is no "global power down" register for stotg04 */
663 if (udc->atx == STOTG04)
664 return;
665
666 if (enable != 0)
667 /* Power up ISP1301 - this ISP1301 will automatically wakeup
668 when VBUS is detected */
669 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
670 ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
671 MC2_GLOBAL_PWR_DN);
672 else
673 /* Power down ISP1301 */
674 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
675 ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
676}
677
678static void power_work(struct work_struct *work)
679{
680 struct lpc32xx_udc *udc =
681 container_of(work, struct lpc32xx_udc, power_job);
682
683 isp1301_set_powerstate(udc, udc->poweron);
684}
685#endif
686
687/*
688 *
689 * USB protocol engine command/data read/write helper functions
690 *
691 */
692/* Issues a single command to the USB device state machine */
693static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
694{
695 u32 pass = 0;
696 int to;
697
698 /* EP may lock on CLRI if this read isn't done */
699 u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
700 (void) tmp;
701
702 while (pass == 0) {
703 writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
704
705 /* Write command code */
706 writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
707 to = 10000;
708 while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) &
709 USBD_CCEMPTY) == 0) && (to > 0)) {
710 to--;
711 }
712
713 if (to > 0)
714 pass = 1;
715
716 cpu_relax();
717 }
718}
719
720/* Issues 2 commands (or command and data) to the USB device state machine */
721static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
722 u32 data)
723{
724 udc_protocol_cmd_w(udc, cmd);
725 udc_protocol_cmd_w(udc, data);
726}
727
728/* Issues a single command to the USB device state machine and reads
729 * response data */
730static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
731{
732 int to = 1000;
733
734 /* Write a command and read data from the protocol engine */
735 writel((USBD_CDFULL | USBD_CCEMPTY),
736 USBD_DEVINTCLR(udc->udp_baseaddr));
737
738 /* Write command code */
739 udc_protocol_cmd_w(udc, cmd);
740
741 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
742 && (to > 0))
743 to--;
744 if (!to)
745 dev_dbg(udc->dev,
746 "Protocol engine didn't receive response (CDFULL)\n");
747
748 return readl(USBD_CMDDATA(udc->udp_baseaddr));
749}
750
751/*
752 *
753 * USB device interrupt mask support functions
754 *
755 */
756/* Enable one or more USB device interrupts */
757static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask)
758{
759 udc->enabled_devints |= devmask;
760 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
761}
762
763/* Disable one or more USB device interrupts */
764static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask)
765{
766 udc->enabled_devints &= ~mask;
767 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
768}
769
770/* Clear one or more USB device interrupts */
771static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask)
772{
773 writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr));
774}
775
776/*
777 *
778 * Endpoint interrupt disable/enable functions
779 *
780 */
781/* Enable one or more USB endpoint interrupts */
782static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
783{
784 udc->enabled_hwepints |= (1 << hwep);
785 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
786}
787
788/* Disable one or more USB endpoint interrupts */
789static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
790{
791 udc->enabled_hwepints &= ~(1 << hwep);
792 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
793}
794
795/* Clear one or more USB endpoint interrupts */
796static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep)
797{
798 writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
799}
800
801/* Enable DMA for the HW channel */
802static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep)
803{
804 writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
805}
806
807/* Disable DMA for the HW channel */
808static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep)
809{
810 writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
811}
812
813/*
814 *
815 * Endpoint realize/unrealize functions
816 *
817 */
818/* Before an endpoint can be used, it needs to be realized
819 * in the USB protocol engine - this realizes the endpoint.
820 * The interrupt (FIFO or DMA) is not enabled with this function */
821static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep,
822 u32 maxpacket)
823{
824 int to = 1000;
825
826 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
827 writel(hwep, USBD_EPIND(udc->udp_baseaddr));
828 udc->realized_eps |= (1 << hwep);
829 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
830 writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
831
832 /* Wait until endpoint is realized in hardware */
833 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) &
834 USBD_EP_RLZED)) && (to > 0))
835 to--;
836 if (!to)
837 dev_dbg(udc->dev, "EP not correctly realized in hardware\n");
838
839 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
840}
841
842/* Unrealize an EP */
843static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep)
844{
845 udc->realized_eps &= ~(1 << hwep);
846 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
847}
848
849/*
850 *
851 * Endpoint support functions
852 *
853 */
854/* Select and clear endpoint interrupt */
855static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep)
856{
857 udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep));
858 return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep));
859}
860
861/* Disables the endpoint in the USB protocol engine */
862static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep)
863{
864 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
865 DAT_WR_BYTE(EP_STAT_DA));
866}
867
868/* Stalls the endpoint - endpoint will return STALL */
869static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep)
870{
871 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
872 DAT_WR_BYTE(EP_STAT_ST));
873}
874
875/* Clear stall or reset endpoint */
876static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep)
877{
878 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
879 DAT_WR_BYTE(0));
880}
881
882/* Select an endpoint for endpoint status, clear, validate */
883static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep)
884{
885 udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep));
886}
887
888/*
889 *
890 * Endpoint buffer management functions
891 *
892 */
893/* Clear the current endpoint's buffer */
894static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
895{
896 udc_select_hwep(udc, hwep);
897 udc_protocol_cmd_w(udc, CMD_CLR_BUF);
898}
899
900/* Validate the current endpoint's buffer */
901static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
902{
903 udc_select_hwep(udc, hwep);
904 udc_protocol_cmd_w(udc, CMD_VALID_BUF);
905}
906
907static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep)
908{
909 /* Clear EP interrupt */
910 uda_clear_hwepint(udc, hwep);
911 return udc_selep_clrint(udc, hwep);
912}
913
914/*
915 *
916 * USB EP DMA support
917 *
918 */
919/* Allocate a DMA Descriptor */
920static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc)
921{
922 dma_addr_t dma;
923 struct lpc32xx_usbd_dd_gad *dd;
924
925 dd = dma_pool_alloc(udc->dd_cache, GFP_ATOMIC | GFP_DMA, &dma);
926 if (dd)
927 dd->this_dma = dma;
928
929 return dd;
930}
931
932/* Free a DMA Descriptor */
933static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd)
934{
935 dma_pool_free(udc->dd_cache, dd, dd->this_dma);
936}
937
938/*
939 *
940 * USB setup and shutdown functions
941 *
942 */
943/* Enables or disables most of the USB system clocks when low power mode is
944 * needed. Clocks are typically started on a connection event, and disabled
945 * when a cable is disconnected */
946static void udc_clk_set(struct lpc32xx_udc *udc, int enable)
947{
948 if (enable != 0) {
949 if (udc->clocked)
950 return;
951
952 udc->clocked = 1;
953 clk_prepare_enable(udc->usb_slv_clk);
954 } else {
955 if (!udc->clocked)
956 return;
957
958 udc->clocked = 0;
959 clk_disable_unprepare(udc->usb_slv_clk);
960 }
961}
962
963/* Set/reset USB device address */
964static void udc_set_address(struct lpc32xx_udc *udc, u32 addr)
965{
966 /* Address will be latched at the end of the status phase, or
967 latched immediately if function is called twice */
968 udc_protocol_cmd_data_w(udc, CMD_SET_ADDR,
969 DAT_WR_BYTE(DEV_EN | addr));
970}
971
972/* Setup up a IN request for DMA transfer - this consists of determining the
973 * list of DMA addresses for the transfer, allocating DMA Descriptors,
974 * installing the DD into the UDCA, and then enabling the DMA for that EP */
975static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
976{
977 struct lpc32xx_request *req;
978 u32 hwep = ep->hwep_num;
979
980 ep->req_pending = 1;
981
982 /* There will always be a request waiting here */
983 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
984
985 /* Place the DD Descriptor into the UDCA */
986 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
987
988 /* Enable DMA and interrupt for the HW EP */
989 udc_ep_dma_enable(udc, hwep);
990
991 /* Clear ZLP if last packet is not of MAXP size */
992 if (req->req.length % ep->ep.maxpacket)
993 req->send_zlp = 0;
994
995 return 0;
996}
997
998/* Setup up a OUT request for DMA transfer - this consists of determining the
999 * list of DMA addresses for the transfer, allocating DMA Descriptors,
1000 * installing the DD into the UDCA, and then enabling the DMA for that EP */
1001static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1002{
1003 struct lpc32xx_request *req;
1004 u32 hwep = ep->hwep_num;
1005
1006 ep->req_pending = 1;
1007
1008 /* There will always be a request waiting here */
1009 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1010
1011 /* Place the DD Descriptor into the UDCA */
1012 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1013
1014 /* Enable DMA and interrupt for the HW EP */
1015 udc_ep_dma_enable(udc, hwep);
1016 return 0;
1017}
1018
1019static void udc_disable(struct lpc32xx_udc *udc)
1020{
1021 u32 i;
1022
1023 /* Disable device */
1024 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1025 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0));
1026
1027 /* Disable all device interrupts (including EP0) */
1028 uda_disable_devint(udc, 0x3FF);
1029
1030 /* Disable and reset all endpoint interrupts */
1031 for (i = 0; i < 32; i++) {
1032 uda_disable_hwepint(udc, i);
1033 uda_clear_hwepint(udc, i);
1034 udc_disable_hwep(udc, i);
1035 udc_unrealize_hwep(udc, i);
1036 udc->udca_v_base[i] = 0;
1037
1038 /* Disable and clear all interrupts and DMA */
1039 udc_ep_dma_disable(udc, i);
1040 writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr));
1041 writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr));
1042 writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1043 writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr));
1044 }
1045
1046 /* Disable DMA interrupts */
1047 writel(0, USBD_DMAINTEN(udc->udp_baseaddr));
1048
1049 writel(0, USBD_UDCAH(udc->udp_baseaddr));
1050}
1051
1052static void udc_enable(struct lpc32xx_udc *udc)
1053{
1054 u32 i;
1055 struct lpc32xx_ep *ep = &udc->ep[0];
1056
1057 /* Start with known state */
1058 udc_disable(udc);
1059
1060 /* Enable device */
1061 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));
1062
1063 /* EP interrupts on high priority, FRAME interrupt on low priority */
1064 writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr));
1065 writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr));
1066
1067 /* Clear any pending device interrupts */
1068 writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr));
1069
1070 /* Setup UDCA - not yet used (DMA) */
1071 writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr));
1072
1073 /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */
1074 for (i = 0; i <= 1; i++) {
1075 udc_realize_hwep(udc, i, ep->ep.maxpacket);
1076 uda_enable_hwepint(udc, i);
1077 udc_select_hwep(udc, i);
1078 udc_clrstall_hwep(udc, i);
1079 udc_clr_buffer_hwep(udc, i);
1080 }
1081
1082 /* Device interrupt setup */
1083 uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1084 USBD_EP_FAST));
1085 uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1086 USBD_EP_FAST));
1087
1088 /* Set device address to 0 - called twice to force a latch in the USB
1089 engine without the need of a setup packet status closure */
1090 udc_set_address(udc, 0);
1091 udc_set_address(udc, 0);
1092
1093 /* Enable master DMA interrupts */
1094 writel((USBD_SYS_ERR_INT | USBD_EOT_INT),
1095 USBD_DMAINTEN(udc->udp_baseaddr));
1096
1097 udc->dev_status = 0;
1098}
1099
1100/*
1101 *
1102 * USB device board specific events handled via callbacks
1103 *
1104 */
1105/* Connection change event - notify board function of change */
1106static void uda_power_event(struct lpc32xx_udc *udc, u32 conn)
1107{
1108 /* Just notify of a connection change event (optional) */
1109 if (udc->board->conn_chgb != NULL)
1110 udc->board->conn_chgb(conn);
1111}
1112
1113/* Suspend/resume event - notify board function of change */
1114static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn)
1115{
1116 /* Just notify of a Suspend/resume change event (optional) */
1117 if (udc->board->susp_chgb != NULL)
1118 udc->board->susp_chgb(conn);
1119
1120 if (conn)
1121 udc->suspended = 0;
1122 else
1123 udc->suspended = 1;
1124}
1125
1126/* Remote wakeup enable/disable - notify board function of change */
1127static void uda_remwkp_cgh(struct lpc32xx_udc *udc)
1128{
1129 if (udc->board->rmwk_chgb != NULL)
1130 udc->board->rmwk_chgb(udc->dev_status &
1131 (1 << USB_DEVICE_REMOTE_WAKEUP));
1132}
1133
1134/* Reads data from FIFO, adjusts for alignment and data size */
1135static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1136{
1137 int n, i, bl;
1138 u16 *p16;
1139 u32 *p32, tmp, cbytes;
1140
1141 /* Use optimal data transfer method based on source address and size */
1142 switch (((uintptr_t) data) & 0x3) {
1143 case 0: /* 32-bit aligned */
1144 p32 = (u32 *) data;
1145 cbytes = (bytes & ~0x3);
1146
1147 /* Copy 32-bit aligned data first */
1148 for (n = 0; n < cbytes; n += 4)
1149 *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr));
1150
1151 /* Handle any remaining bytes */
1152 bl = bytes - cbytes;
1153 if (bl) {
1154 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1155 for (n = 0; n < bl; n++)
1156 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1157
1158 }
1159 break;
1160
1161 case 1: /* 8-bit aligned */
1162 case 3:
1163 /* Each byte has to be handled independently */
1164 for (n = 0; n < bytes; n += 4) {
1165 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1166
1167 bl = bytes - n;
1168 if (bl > 4)
1169 bl = 4;
1170
1171 for (i = 0; i < bl; i++)
1172 data[n + i] = (u8) ((tmp >> (i * 8)) & 0xFF);
1173 }
1174 break;
1175
1176 case 2: /* 16-bit aligned */
1177 p16 = (u16 *) data;
1178 cbytes = (bytes & ~0x3);
1179
1180 /* Copy 32-bit sized objects first with 16-bit alignment */
1181 for (n = 0; n < cbytes; n += 4) {
1182 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1183 *p16++ = (u16)(tmp & 0xFFFF);
1184 *p16++ = (u16)((tmp >> 16) & 0xFFFF);
1185 }
1186
1187 /* Handle any remaining bytes */
1188 bl = bytes - cbytes;
1189 if (bl) {
1190 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1191 for (n = 0; n < bl; n++)
1192 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1193 }
1194 break;
1195 }
1196}
1197
1198/* Read data from the FIFO for an endpoint. This function is for endpoints (such
1199 * as EP0) that don't use DMA. This function should only be called if a packet
1200 * is known to be ready to read for the endpoint. Note that the endpoint must
1201 * be selected in the protocol engine prior to this call. */
1202static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1203 u32 bytes)
1204{
1205 u32 tmpv;
1206 int to = 1000;
1207 u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN;
1208
1209 /* Setup read of endpoint */
1210 writel(hwrep, USBD_CTRL(udc->udp_baseaddr));
1211
1212 /* Wait until packet is ready */
1213 while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) &
1214 PKT_RDY) == 0) && (to > 0))
1215 to--;
1216 if (!to)
1217 dev_dbg(udc->dev, "No packet ready on FIFO EP read\n");
1218
1219 /* Mask out count */
1220 tmp = tmpv & PKT_LNGTH_MASK;
1221 if (bytes < tmp)
1222 tmp = bytes;
1223
1224 if ((tmp > 0) && (data != NULL))
1225 udc_pop_fifo(udc, (u8 *) data, tmp);
1226
1227 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1228
1229 /* Clear the buffer */
1230 udc_clr_buffer_hwep(udc, hwep);
1231
1232 return tmp;
1233}
1234
1235/* Stuffs data into the FIFO, adjusts for alignment and data size */
1236static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1237{
1238 int n, i, bl;
1239 u16 *p16;
1240 u32 *p32, tmp, cbytes;
1241
1242 /* Use optimal data transfer method based on source address and size */
1243 switch (((uintptr_t) data) & 0x3) {
1244 case 0: /* 32-bit aligned */
1245 p32 = (u32 *) data;
1246 cbytes = (bytes & ~0x3);
1247
1248 /* Copy 32-bit aligned data first */
1249 for (n = 0; n < cbytes; n += 4)
1250 writel(*p32++, USBD_TXDATA(udc->udp_baseaddr));
1251
1252 /* Handle any remaining bytes */
1253 bl = bytes - cbytes;
1254 if (bl) {
1255 tmp = 0;
1256 for (n = 0; n < bl; n++)
1257 tmp |= data[cbytes + n] << (n * 8);
1258
1259 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1260 }
1261 break;
1262
1263 case 1: /* 8-bit aligned */
1264 case 3:
1265 /* Each byte has to be handled independently */
1266 for (n = 0; n < bytes; n += 4) {
1267 bl = bytes - n;
1268 if (bl > 4)
1269 bl = 4;
1270
1271 tmp = 0;
1272 for (i = 0; i < bl; i++)
1273 tmp |= data[n + i] << (i * 8);
1274
1275 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1276 }
1277 break;
1278
1279 case 2: /* 16-bit aligned */
1280 p16 = (u16 *) data;
1281 cbytes = (bytes & ~0x3);
1282
1283 /* Copy 32-bit aligned data first */
1284 for (n = 0; n < cbytes; n += 4) {
1285 tmp = *p16++ & 0xFFFF;
1286 tmp |= (*p16++ & 0xFFFF) << 16;
1287 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1288 }
1289
1290 /* Handle any remaining bytes */
1291 bl = bytes - cbytes;
1292 if (bl) {
1293 tmp = 0;
1294 for (n = 0; n < bl; n++)
1295 tmp |= data[cbytes + n] << (n * 8);
1296
1297 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1298 }
1299 break;
1300 }
1301}
1302
1303/* Write data to the FIFO for an endpoint. This function is for endpoints (such
1304 * as EP0) that don't use DMA. Note that the endpoint must be selected in the
1305 * protocol engine prior to this call. */
1306static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1307 u32 bytes)
1308{
1309 u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN;
1310
1311 if ((bytes > 0) && (data == NULL))
1312 return;
1313
1314 /* Setup write of endpoint */
1315 writel(hwwep, USBD_CTRL(udc->udp_baseaddr));
1316
1317 writel(bytes, USBD_TXPLEN(udc->udp_baseaddr));
1318
1319 /* Need at least 1 byte to trigger TX */
1320 if (bytes == 0)
1321 writel(0, USBD_TXDATA(udc->udp_baseaddr));
1322 else
1323 udc_stuff_fifo(udc, (u8 *) data, bytes);
1324
1325 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1326
1327 udc_val_buffer_hwep(udc, hwep);
1328}
1329
1330/* USB device reset - resets USB to a default state with just EP0
1331 enabled */
1332static void uda_usb_reset(struct lpc32xx_udc *udc)
1333{
1334 u32 i = 0;
1335 /* Re-init device controller and EP0 */
1336 udc_enable(udc);
1337 udc->gadget.speed = USB_SPEED_FULL;
1338
1339 for (i = 1; i < NUM_ENDPOINTS; i++) {
1340 struct lpc32xx_ep *ep = &udc->ep[i];
1341 ep->req_pending = 0;
1342 }
1343}
1344
1345/* Send a ZLP on EP0 */
1346static void udc_ep0_send_zlp(struct lpc32xx_udc *udc)
1347{
1348 udc_write_hwep(udc, EP_IN, NULL, 0);
1349}
1350
1351/* Get current frame number */
1352static u16 udc_get_current_frame(struct lpc32xx_udc *udc)
1353{
1354 u16 flo, fhi;
1355
1356 udc_protocol_cmd_w(udc, CMD_RD_FRAME);
1357 flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1358 fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1359
1360 return (fhi << 8) | flo;
1361}
1362
1363/* Set the device as configured - enables all endpoints */
1364static inline void udc_set_device_configured(struct lpc32xx_udc *udc)
1365{
1366 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE));
1367}
1368
1369/* Set the device as unconfigured - disables all endpoints */
1370static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc)
1371{
1372 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1373}
1374
1375/* reinit == restore initial software state */
1376static void udc_reinit(struct lpc32xx_udc *udc)
1377{
1378 u32 i;
1379
1380 INIT_LIST_HEAD(&udc->gadget.ep_list);
1381 INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
1382
1383 for (i = 0; i < NUM_ENDPOINTS; i++) {
1384 struct lpc32xx_ep *ep = &udc->ep[i];
1385
1386 if (i != 0)
1387 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1388 usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket);
1389 INIT_LIST_HEAD(&ep->queue);
1390 ep->req_pending = 0;
1391 }
1392
1393 udc->ep0state = WAIT_FOR_SETUP;
1394}
1395
1396/* Must be called with lock */
1397static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status)
1398{
1399 struct lpc32xx_udc *udc = ep->udc;
1400
1401 list_del_init(&req->queue);
1402 if (req->req.status == -EINPROGRESS)
1403 req->req.status = status;
1404 else
1405 status = req->req.status;
1406
1407 if (ep->lep) {
1408 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
1409
1410 /* Free DDs */
1411 udc_dd_free(udc, req->dd_desc_ptr);
1412 }
1413
1414 if (status && status != -ESHUTDOWN)
1415 ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status);
1416
1417 ep->req_pending = 0;
1418 spin_unlock(&udc->lock);
1419 usb_gadget_giveback_request(&ep->ep, &req->req);
1420 spin_lock(&udc->lock);
1421}
1422
1423/* Must be called with lock */
1424static void nuke(struct lpc32xx_ep *ep, int status)
1425{
1426 struct lpc32xx_request *req;
1427
1428 while (!list_empty(&ep->queue)) {
1429 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1430 done(ep, req, status);
1431 }
1432
1433 if (status == -ESHUTDOWN) {
1434 uda_disable_hwepint(ep->udc, ep->hwep_num);
1435 udc_disable_hwep(ep->udc, ep->hwep_num);
1436 }
1437}
1438
1439/* IN endpoint 0 transfer */
1440static int udc_ep0_in_req(struct lpc32xx_udc *udc)
1441{
1442 struct lpc32xx_request *req;
1443 struct lpc32xx_ep *ep0 = &udc->ep[0];
1444 u32 tsend, ts = 0;
1445
1446 if (list_empty(&ep0->queue))
1447 /* Nothing to send */
1448 return 0;
1449 else
1450 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1451 queue);
1452
1453 tsend = ts = req->req.length - req->req.actual;
1454 if (ts == 0) {
1455 /* Send a ZLP */
1456 udc_ep0_send_zlp(udc);
1457 done(ep0, req, 0);
1458 return 1;
1459 } else if (ts > ep0->ep.maxpacket)
1460 ts = ep0->ep.maxpacket; /* Just send what we can */
1461
1462 /* Write data to the EP0 FIFO and start transfer */
1463 udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts);
1464
1465 /* Increment data pointer */
1466 req->req.actual += ts;
1467
1468 if (tsend >= ep0->ep.maxpacket)
1469 return 0; /* Stay in data transfer state */
1470
1471 /* Transfer request is complete */
1472 udc->ep0state = WAIT_FOR_SETUP;
1473 done(ep0, req, 0);
1474 return 1;
1475}
1476
1477/* OUT endpoint 0 transfer */
1478static int udc_ep0_out_req(struct lpc32xx_udc *udc)
1479{
1480 struct lpc32xx_request *req;
1481 struct lpc32xx_ep *ep0 = &udc->ep[0];
1482 u32 tr, bufferspace;
1483
1484 if (list_empty(&ep0->queue))
1485 return 0;
1486 else
1487 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1488 queue);
1489
1490 if (req) {
1491 if (req->req.length == 0) {
1492 /* Just dequeue request */
1493 done(ep0, req, 0);
1494 udc->ep0state = WAIT_FOR_SETUP;
1495 return 1;
1496 }
1497
1498 /* Get data from FIFO */
1499 bufferspace = req->req.length - req->req.actual;
1500 if (bufferspace > ep0->ep.maxpacket)
1501 bufferspace = ep0->ep.maxpacket;
1502
1503 /* Copy data to buffer */
1504 prefetchw(req->req.buf + req->req.actual);
1505 tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual,
1506 bufferspace);
1507 req->req.actual += bufferspace;
1508
1509 if (tr < ep0->ep.maxpacket) {
1510 /* This is the last packet */
1511 done(ep0, req, 0);
1512 udc->ep0state = WAIT_FOR_SETUP;
1513 return 1;
1514 }
1515 }
1516
1517 return 0;
1518}
1519
1520/* Must be called with lock */
1521static void stop_activity(struct lpc32xx_udc *udc)
1522{
1523 struct usb_gadget_driver *driver = udc->driver;
1524 int i;
1525
1526 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1527 driver = NULL;
1528
1529 udc->gadget.speed = USB_SPEED_UNKNOWN;
1530 udc->suspended = 0;
1531
1532 for (i = 0; i < NUM_ENDPOINTS; i++) {
1533 struct lpc32xx_ep *ep = &udc->ep[i];
1534 nuke(ep, -ESHUTDOWN);
1535 }
1536 if (driver) {
1537 spin_unlock(&udc->lock);
1538 driver->disconnect(&udc->gadget);
1539 spin_lock(&udc->lock);
1540 }
1541
1542 isp1301_pullup_enable(udc, 0, 0);
1543 udc_disable(udc);
1544 udc_reinit(udc);
1545}
1546
1547/*
1548 * Activate or kill host pullup
1549 * Can be called with or without lock
1550 */
1551static void pullup(struct lpc32xx_udc *udc, int is_on)
1552{
1553 if (!udc->clocked)
1554 return;
1555
1556 if (!udc->enabled || !udc->vbus)
1557 is_on = 0;
1558
1559 if (is_on != udc->pullup)
1560 isp1301_pullup_enable(udc, is_on, 0);
1561}
1562
1563/* Must be called without lock */
1564static int lpc32xx_ep_disable(struct usb_ep *_ep)
1565{
1566 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1567 struct lpc32xx_udc *udc = ep->udc;
1568 unsigned long flags;
1569
1570 if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0))
1571 return -EINVAL;
1572 spin_lock_irqsave(&udc->lock, flags);
1573
1574 nuke(ep, -ESHUTDOWN);
1575
1576 /* Clear all DMA statuses for this EP */
1577 udc_ep_dma_disable(udc, ep->hwep_num);
1578 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1579 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1580 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1581 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1582
1583 /* Remove the DD pointer in the UDCA */
1584 udc->udca_v_base[ep->hwep_num] = 0;
1585
1586 /* Disable and reset endpoint and interrupt */
1587 uda_clear_hwepint(udc, ep->hwep_num);
1588 udc_unrealize_hwep(udc, ep->hwep_num);
1589
1590 ep->hwep_num = 0;
1591
1592 spin_unlock_irqrestore(&udc->lock, flags);
1593
1594 atomic_dec(&udc->enabled_ep_cnt);
1595 wake_up(&udc->ep_disable_wait_queue);
1596
1597 return 0;
1598}
1599
1600/* Must be called without lock */
1601static int lpc32xx_ep_enable(struct usb_ep *_ep,
1602 const struct usb_endpoint_descriptor *desc)
1603{
1604 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1605 struct lpc32xx_udc *udc;
1606 u16 maxpacket;
1607 u32 tmp;
1608 unsigned long flags;
1609
1610 /* Verify EP data */
1611 if ((!_ep) || (!ep) || (!desc) ||
1612 (desc->bDescriptorType != USB_DT_ENDPOINT))
1613 return -EINVAL;
1614
1615 udc = ep->udc;
1616 maxpacket = usb_endpoint_maxp(desc);
1617 if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) {
1618 dev_dbg(udc->dev, "bad ep descriptor's packet size\n");
1619 return -EINVAL;
1620 }
1621
1622 /* Don't touch EP0 */
1623 if (ep->hwep_num_base == 0) {
1624 dev_dbg(udc->dev, "Can't re-enable EP0!!!\n");
1625 return -EINVAL;
1626 }
1627
1628 /* Is driver ready? */
1629 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1630 dev_dbg(udc->dev, "bogus device state\n");
1631 return -ESHUTDOWN;
1632 }
1633
1634 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1635 switch (tmp) {
1636 case USB_ENDPOINT_XFER_CONTROL:
1637 return -EINVAL;
1638
1639 case USB_ENDPOINT_XFER_INT:
1640 if (maxpacket > ep->maxpacket) {
1641 dev_dbg(udc->dev,
1642 "Bad INT endpoint maxpacket %d\n", maxpacket);
1643 return -EINVAL;
1644 }
1645 break;
1646
1647 case USB_ENDPOINT_XFER_BULK:
1648 switch (maxpacket) {
1649 case 8:
1650 case 16:
1651 case 32:
1652 case 64:
1653 break;
1654
1655 default:
1656 dev_dbg(udc->dev,
1657 "Bad BULK endpoint maxpacket %d\n", maxpacket);
1658 return -EINVAL;
1659 }
1660 break;
1661
1662 case USB_ENDPOINT_XFER_ISOC:
1663 break;
1664 }
1665 spin_lock_irqsave(&udc->lock, flags);
1666
1667 /* Initialize endpoint to match the selected descriptor */
1668 ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
1669 ep->ep.maxpacket = maxpacket;
1670
1671 /* Map hardware endpoint from base and direction */
1672 if (ep->is_in)
1673 /* IN endpoints are offset 1 from the OUT endpoint */
1674 ep->hwep_num = ep->hwep_num_base + EP_IN;
1675 else
1676 ep->hwep_num = ep->hwep_num_base;
1677
1678 ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name,
1679 ep->hwep_num, maxpacket, (ep->is_in == 1));
1680
1681 /* Realize the endpoint, interrupt is enabled later when
1682 * buffers are queued, IN EPs will NAK until buffers are ready */
1683 udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket);
1684 udc_clr_buffer_hwep(udc, ep->hwep_num);
1685 uda_disable_hwepint(udc, ep->hwep_num);
1686 udc_clrstall_hwep(udc, ep->hwep_num);
1687
1688 /* Clear all DMA statuses for this EP */
1689 udc_ep_dma_disable(udc, ep->hwep_num);
1690 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1691 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1692 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1693 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1694
1695 spin_unlock_irqrestore(&udc->lock, flags);
1696
1697 atomic_inc(&udc->enabled_ep_cnt);
1698 return 0;
1699}
1700
1701/*
1702 * Allocate a USB request list
1703 * Can be called with or without lock
1704 */
1705static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep,
1706 gfp_t gfp_flags)
1707{
1708 struct lpc32xx_request *req;
1709
1710 req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags);
1711 if (!req)
1712 return NULL;
1713
1714 INIT_LIST_HEAD(&req->queue);
1715 return &req->req;
1716}
1717
1718/*
1719 * De-allocate a USB request list
1720 * Can be called with or without lock
1721 */
1722static void lpc32xx_ep_free_request(struct usb_ep *_ep,
1723 struct usb_request *_req)
1724{
1725 struct lpc32xx_request *req;
1726
1727 req = container_of(_req, struct lpc32xx_request, req);
1728 BUG_ON(!list_empty(&req->queue));
1729 kfree(req);
1730}
1731
1732/* Must be called without lock */
1733static int lpc32xx_ep_queue(struct usb_ep *_ep,
1734 struct usb_request *_req, gfp_t gfp_flags)
1735{
1736 struct lpc32xx_request *req;
1737 struct lpc32xx_ep *ep;
1738 struct lpc32xx_udc *udc;
1739 unsigned long flags;
1740 int status = 0;
1741
1742 req = container_of(_req, struct lpc32xx_request, req);
1743 ep = container_of(_ep, struct lpc32xx_ep, ep);
1744
1745 if (!_ep || !_req || !_req->complete || !_req->buf ||
1746 !list_empty(&req->queue))
1747 return -EINVAL;
1748
1749 udc = ep->udc;
1750
1751 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1752 return -EPIPE;
1753
1754 if (ep->lep) {
1755 struct lpc32xx_usbd_dd_gad *dd;
1756
1757 status = usb_gadget_map_request(&udc->gadget, _req, ep->is_in);
1758 if (status)
1759 return status;
1760
1761 /* For the request, build a list of DDs */
1762 dd = udc_dd_alloc(udc);
1763 if (!dd) {
1764 /* Error allocating DD */
1765 return -ENOMEM;
1766 }
1767 req->dd_desc_ptr = dd;
1768
1769 /* Setup the DMA descriptor */
1770 dd->dd_next_phy = dd->dd_next_v = 0;
1771 dd->dd_buffer_addr = req->req.dma;
1772 dd->dd_status = 0;
1773
1774 /* Special handling for ISO EPs */
1775 if (ep->eptype == EP_ISO_TYPE) {
1776 dd->dd_setup = DD_SETUP_ISO_EP |
1777 DD_SETUP_PACKETLEN(0) |
1778 DD_SETUP_DMALENBYTES(1);
1779 dd->dd_iso_ps_mem_addr = dd->this_dma + 24;
1780 if (ep->is_in)
1781 dd->iso_status[0] = req->req.length;
1782 else
1783 dd->iso_status[0] = 0;
1784 } else
1785 dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) |
1786 DD_SETUP_DMALENBYTES(req->req.length);
1787 }
1788
1789 ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name,
1790 _req, _req->length, _req->buf, ep->is_in, _req->zero);
1791
1792 spin_lock_irqsave(&udc->lock, flags);
1793
1794 _req->status = -EINPROGRESS;
1795 _req->actual = 0;
1796 req->send_zlp = _req->zero;
1797
1798 /* Kickstart empty queues */
1799 if (list_empty(&ep->queue)) {
1800 list_add_tail(&req->queue, &ep->queue);
1801
1802 if (ep->hwep_num_base == 0) {
1803 /* Handle expected data direction */
1804 if (ep->is_in) {
1805 /* IN packet to host */
1806 udc->ep0state = DATA_IN;
1807 status = udc_ep0_in_req(udc);
1808 } else {
1809 /* OUT packet from host */
1810 udc->ep0state = DATA_OUT;
1811 status = udc_ep0_out_req(udc);
1812 }
1813 } else if (ep->is_in) {
1814 /* IN packet to host and kick off transfer */
1815 if (!ep->req_pending)
1816 udc_ep_in_req_dma(udc, ep);
1817 } else
1818 /* OUT packet from host and kick off list */
1819 if (!ep->req_pending)
1820 udc_ep_out_req_dma(udc, ep);
1821 } else
1822 list_add_tail(&req->queue, &ep->queue);
1823
1824 spin_unlock_irqrestore(&udc->lock, flags);
1825
1826 return (status < 0) ? status : 0;
1827}
1828
1829/* Must be called without lock */
1830static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1831{
1832 struct lpc32xx_ep *ep;
1833 struct lpc32xx_request *req = NULL, *iter;
1834 unsigned long flags;
1835
1836 ep = container_of(_ep, struct lpc32xx_ep, ep);
1837 if (!_ep || ep->hwep_num_base == 0)
1838 return -EINVAL;
1839
1840 spin_lock_irqsave(&ep->udc->lock, flags);
1841
1842 /* make sure it's actually queued on this endpoint */
1843 list_for_each_entry(iter, &ep->queue, queue) {
1844 if (&iter->req != _req)
1845 continue;
1846 req = iter;
1847 break;
1848 }
1849 if (!req) {
1850 spin_unlock_irqrestore(&ep->udc->lock, flags);
1851 return -EINVAL;
1852 }
1853
1854 done(ep, req, -ECONNRESET);
1855
1856 spin_unlock_irqrestore(&ep->udc->lock, flags);
1857
1858 return 0;
1859}
1860
1861/* Must be called without lock */
1862static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value)
1863{
1864 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1865 struct lpc32xx_udc *udc;
1866 unsigned long flags;
1867
1868 if ((!ep) || (ep->hwep_num <= 1))
1869 return -EINVAL;
1870
1871 /* Don't halt an IN EP */
1872 if (ep->is_in)
1873 return -EAGAIN;
1874
1875 udc = ep->udc;
1876 spin_lock_irqsave(&udc->lock, flags);
1877
1878 if (value == 1) {
1879 /* stall */
1880 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1881 DAT_WR_BYTE(EP_STAT_ST));
1882 } else {
1883 /* End stall */
1884 ep->wedge = 0;
1885 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1886 DAT_WR_BYTE(0));
1887 }
1888
1889 spin_unlock_irqrestore(&udc->lock, flags);
1890
1891 return 0;
1892}
1893
1894/* set the halt feature and ignores clear requests */
1895static int lpc32xx_ep_set_wedge(struct usb_ep *_ep)
1896{
1897 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1898
1899 if (!_ep || !ep->udc)
1900 return -EINVAL;
1901
1902 ep->wedge = 1;
1903
1904 return usb_ep_set_halt(_ep);
1905}
1906
1907static const struct usb_ep_ops lpc32xx_ep_ops = {
1908 .enable = lpc32xx_ep_enable,
1909 .disable = lpc32xx_ep_disable,
1910 .alloc_request = lpc32xx_ep_alloc_request,
1911 .free_request = lpc32xx_ep_free_request,
1912 .queue = lpc32xx_ep_queue,
1913 .dequeue = lpc32xx_ep_dequeue,
1914 .set_halt = lpc32xx_ep_set_halt,
1915 .set_wedge = lpc32xx_ep_set_wedge,
1916};
1917
1918/* Send a ZLP on a non-0 IN EP */
1919static void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1920{
1921 /* Clear EP status */
1922 udc_clearep_getsts(udc, ep->hwep_num);
1923
1924 /* Send ZLP via FIFO mechanism */
1925 udc_write_hwep(udc, ep->hwep_num, NULL, 0);
1926}
1927
1928/*
1929 * Handle EP completion for ZLP
1930 * This function will only be called when a delayed ZLP needs to be sent out
1931 * after a DMA transfer has filled both buffers.
1932 */
1933static void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1934{
1935 u32 epstatus;
1936 struct lpc32xx_request *req;
1937
1938 if (ep->hwep_num <= 0)
1939 return;
1940
1941 uda_clear_hwepint(udc, ep->hwep_num);
1942
1943 /* If this interrupt isn't enabled, return now */
1944 if (!(udc->enabled_hwepints & (1 << ep->hwep_num)))
1945 return;
1946
1947 /* Get endpoint status */
1948 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
1949
1950 /*
1951 * This should never happen, but protect against writing to the
1952 * buffer when full.
1953 */
1954 if (epstatus & EP_SEL_F)
1955 return;
1956
1957 if (ep->is_in) {
1958 udc_send_in_zlp(udc, ep);
1959 uda_disable_hwepint(udc, ep->hwep_num);
1960 } else
1961 return;
1962
1963 /* If there isn't a request waiting, something went wrong */
1964 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1965 if (req) {
1966 done(ep, req, 0);
1967
1968 /* Start another request if ready */
1969 if (!list_empty(&ep->queue)) {
1970 if (ep->is_in)
1971 udc_ep_in_req_dma(udc, ep);
1972 else
1973 udc_ep_out_req_dma(udc, ep);
1974 } else
1975 ep->req_pending = 0;
1976 }
1977}
1978
1979
1980/* DMA end of transfer completion */
1981static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1982{
1983 u32 status;
1984 struct lpc32xx_request *req;
1985 struct lpc32xx_usbd_dd_gad *dd;
1986
1987#ifdef CONFIG_USB_GADGET_DEBUG_FILES
1988 ep->totalints++;
1989#endif
1990
1991 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1992 if (!req) {
1993 ep_err(ep, "DMA interrupt on no req!\n");
1994 return;
1995 }
1996 dd = req->dd_desc_ptr;
1997
1998 /* DMA descriptor should always be retired for this call */
1999 if (!(dd->dd_status & DD_STATUS_DD_RETIRED))
2000 ep_warn(ep, "DMA descriptor did not retire\n");
2001
2002 /* Disable DMA */
2003 udc_ep_dma_disable(udc, ep->hwep_num);
2004 writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr));
2005 writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr));
2006
2007 /* System error? */
2008 if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) &
2009 (1 << ep->hwep_num)) {
2010 writel((1 << ep->hwep_num),
2011 USBD_SYSERRTINTCLR(udc->udp_baseaddr));
2012 ep_err(ep, "AHB critical error!\n");
2013 ep->req_pending = 0;
2014
2015 /* The error could have occurred on a packet of a multipacket
2016 * transfer, so recovering the transfer is not possible. Close
2017 * the request with an error */
2018 done(ep, req, -ECONNABORTED);
2019 return;
2020 }
2021
2022 /* Handle the current DD's status */
2023 status = dd->dd_status;
2024 switch (status & DD_STATUS_STS_MASK) {
2025 case DD_STATUS_STS_NS:
2026 /* DD not serviced? This shouldn't happen! */
2027 ep->req_pending = 0;
2028 ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n",
2029 status);
2030
2031 done(ep, req, -ECONNABORTED);
2032 return;
2033
2034 case DD_STATUS_STS_BS:
2035 /* Interrupt only fires on EOT - This shouldn't happen! */
2036 ep->req_pending = 0;
2037 ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n",
2038 status);
2039 done(ep, req, -ECONNABORTED);
2040 return;
2041
2042 case DD_STATUS_STS_NC:
2043 case DD_STATUS_STS_DUR:
2044 /* Really just a short packet, not an underrun */
2045 /* This is a good status and what we expect */
2046 break;
2047
2048 default:
2049 /* Data overrun, system error, or unknown */
2050 ep->req_pending = 0;
2051 ep_err(ep, "DMA critical EP error: System error (0x%x)!\n",
2052 status);
2053 done(ep, req, -ECONNABORTED);
2054 return;
2055 }
2056
2057 /* ISO endpoints are handled differently */
2058 if (ep->eptype == EP_ISO_TYPE) {
2059 if (ep->is_in)
2060 req->req.actual = req->req.length;
2061 else
2062 req->req.actual = dd->iso_status[0] & 0xFFFF;
2063 } else
2064 req->req.actual += DD_STATUS_CURDMACNT(status);
2065
2066 /* Send a ZLP if necessary. This will be done for non-int
2067 * packets which have a size that is a divisor of MAXP */
2068 if (req->send_zlp) {
2069 /*
2070 * If at least 1 buffer is available, send the ZLP now.
2071 * Otherwise, the ZLP send needs to be deferred until a
2072 * buffer is available.
2073 */
2074 if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) {
2075 udc_clearep_getsts(udc, ep->hwep_num);
2076 uda_enable_hwepint(udc, ep->hwep_num);
2077 udc_clearep_getsts(udc, ep->hwep_num);
2078
2079 /* Let the EP interrupt handle the ZLP */
2080 return;
2081 } else
2082 udc_send_in_zlp(udc, ep);
2083 }
2084
2085 /* Transfer request is complete */
2086 done(ep, req, 0);
2087
2088 /* Start another request if ready */
2089 udc_clearep_getsts(udc, ep->hwep_num);
2090 if (!list_empty((&ep->queue))) {
2091 if (ep->is_in)
2092 udc_ep_in_req_dma(udc, ep);
2093 else
2094 udc_ep_out_req_dma(udc, ep);
2095 } else
2096 ep->req_pending = 0;
2097
2098}
2099
2100/*
2101 *
2102 * Endpoint 0 functions
2103 *
2104 */
2105static void udc_handle_dev(struct lpc32xx_udc *udc)
2106{
2107 u32 tmp;
2108
2109 udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT);
2110 tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT);
2111
2112 if (tmp & DEV_RST)
2113 uda_usb_reset(udc);
2114 else if (tmp & DEV_CON_CH)
2115 uda_power_event(udc, (tmp & DEV_CON));
2116 else if (tmp & DEV_SUS_CH) {
2117 if (tmp & DEV_SUS) {
2118 if (udc->vbus == 0)
2119 stop_activity(udc);
2120 else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2121 udc->driver) {
2122 /* Power down transceiver */
2123 udc->poweron = 0;
2124 schedule_work(&udc->pullup_job);
2125 uda_resm_susp_event(udc, 1);
2126 }
2127 } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2128 udc->driver && udc->vbus) {
2129 uda_resm_susp_event(udc, 0);
2130 /* Power up transceiver */
2131 udc->poweron = 1;
2132 schedule_work(&udc->pullup_job);
2133 }
2134 }
2135}
2136
2137static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex)
2138{
2139 struct lpc32xx_ep *ep;
2140 u32 ep0buff = 0, tmp;
2141
2142 switch (reqtype & USB_RECIP_MASK) {
2143 case USB_RECIP_INTERFACE:
2144 break; /* Not supported */
2145
2146 case USB_RECIP_DEVICE:
2147 ep0buff = udc->gadget.is_selfpowered;
2148 if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP))
2149 ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP);
2150 break;
2151
2152 case USB_RECIP_ENDPOINT:
2153 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2154 ep = &udc->ep[tmp];
2155 if ((tmp == 0) || (tmp >= NUM_ENDPOINTS))
2156 return -EOPNOTSUPP;
2157
2158 if (wIndex & USB_DIR_IN) {
2159 if (!ep->is_in)
2160 return -EOPNOTSUPP; /* Something's wrong */
2161 } else if (ep->is_in)
2162 return -EOPNOTSUPP; /* Not an IN endpoint */
2163
2164 /* Get status of the endpoint */
2165 udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num));
2166 tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num));
2167
2168 if (tmp & EP_SEL_ST)
2169 ep0buff = (1 << USB_ENDPOINT_HALT);
2170 else
2171 ep0buff = 0;
2172 break;
2173
2174 default:
2175 break;
2176 }
2177
2178 /* Return data */
2179 udc_write_hwep(udc, EP_IN, &ep0buff, 2);
2180
2181 return 0;
2182}
2183
2184static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
2185{
2186 struct lpc32xx_ep *ep, *ep0 = &udc->ep[0];
2187 struct usb_ctrlrequest ctrlpkt;
2188 int i, bytes;
2189 u16 wIndex, wValue, reqtype, req, tmp;
2190
2191 /* Nuke previous transfers */
2192 nuke(ep0, -EPROTO);
2193
2194 /* Get setup packet */
2195 bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8);
2196 if (bytes != 8) {
2197 ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n",
2198 bytes);
2199 return;
2200 }
2201
2202 /* Native endianness */
2203 wIndex = le16_to_cpu(ctrlpkt.wIndex);
2204 wValue = le16_to_cpu(ctrlpkt.wValue);
2205 reqtype = le16_to_cpu(ctrlpkt.bRequestType);
2206
2207 /* Set direction of EP0 */
2208 if (likely(reqtype & USB_DIR_IN))
2209 ep0->is_in = 1;
2210 else
2211 ep0->is_in = 0;
2212
2213 /* Handle SETUP packet */
2214 req = le16_to_cpu(ctrlpkt.bRequest);
2215 switch (req) {
2216 case USB_REQ_CLEAR_FEATURE:
2217 case USB_REQ_SET_FEATURE:
2218 switch (reqtype) {
2219 case (USB_TYPE_STANDARD | USB_RECIP_DEVICE):
2220 if (wValue != USB_DEVICE_REMOTE_WAKEUP)
2221 goto stall; /* Nothing else handled */
2222
2223 /* Tell board about event */
2224 if (req == USB_REQ_CLEAR_FEATURE)
2225 udc->dev_status &=
2226 ~(1 << USB_DEVICE_REMOTE_WAKEUP);
2227 else
2228 udc->dev_status |=
2229 (1 << USB_DEVICE_REMOTE_WAKEUP);
2230 uda_remwkp_cgh(udc);
2231 goto zlp_send;
2232
2233 case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
2234 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2235 if ((wValue != USB_ENDPOINT_HALT) ||
2236 (tmp >= NUM_ENDPOINTS))
2237 break;
2238
2239 /* Find hardware endpoint from logical endpoint */
2240 ep = &udc->ep[tmp];
2241 tmp = ep->hwep_num;
2242 if (tmp == 0)
2243 break;
2244
2245 if (req == USB_REQ_SET_FEATURE)
2246 udc_stall_hwep(udc, tmp);
2247 else if (!ep->wedge)
2248 udc_clrstall_hwep(udc, tmp);
2249
2250 goto zlp_send;
2251
2252 default:
2253 break;
2254 }
2255 break;
2256
2257 case USB_REQ_SET_ADDRESS:
2258 if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
2259 udc_set_address(udc, wValue);
2260 goto zlp_send;
2261 }
2262 break;
2263
2264 case USB_REQ_GET_STATUS:
2265 udc_get_status(udc, reqtype, wIndex);
2266 return;
2267
2268 default:
2269 break; /* Let GadgetFS handle the descriptor instead */
2270 }
2271
2272 if (likely(udc->driver)) {
2273 /* device-2-host (IN) or no data setup command, process
2274 * immediately */
2275 spin_unlock(&udc->lock);
2276 i = udc->driver->setup(&udc->gadget, &ctrlpkt);
2277
2278 spin_lock(&udc->lock);
2279 if (req == USB_REQ_SET_CONFIGURATION) {
2280 /* Configuration is set after endpoints are realized */
2281 if (wValue) {
2282 /* Set configuration */
2283 udc_set_device_configured(udc);
2284
2285 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2286 DAT_WR_BYTE(AP_CLK |
2287 INAK_BI | INAK_II));
2288 } else {
2289 /* Clear configuration */
2290 udc_set_device_unconfigured(udc);
2291
2292 /* Disable NAK interrupts */
2293 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2294 DAT_WR_BYTE(AP_CLK));
2295 }
2296 }
2297
2298 if (i < 0) {
2299 /* setup processing failed, force stall */
2300 dev_dbg(udc->dev,
2301 "req %02x.%02x protocol STALL; stat %d\n",
2302 reqtype, req, i);
2303 udc->ep0state = WAIT_FOR_SETUP;
2304 goto stall;
2305 }
2306 }
2307
2308 if (!ep0->is_in)
2309 udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */
2310
2311 return;
2312
2313stall:
2314 udc_stall_hwep(udc, EP_IN);
2315 return;
2316
2317zlp_send:
2318 udc_ep0_send_zlp(udc);
2319 return;
2320}
2321
2322/* IN endpoint 0 transfer */
2323static void udc_handle_ep0_in(struct lpc32xx_udc *udc)
2324{
2325 struct lpc32xx_ep *ep0 = &udc->ep[0];
2326 u32 epstatus;
2327
2328 /* Clear EP interrupt */
2329 epstatus = udc_clearep_getsts(udc, EP_IN);
2330
2331#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2332 ep0->totalints++;
2333#endif
2334
2335 /* Stalled? Clear stall and reset buffers */
2336 if (epstatus & EP_SEL_ST) {
2337 udc_clrstall_hwep(udc, EP_IN);
2338 nuke(ep0, -ECONNABORTED);
2339 udc->ep0state = WAIT_FOR_SETUP;
2340 return;
2341 }
2342
2343 /* Is a buffer available? */
2344 if (!(epstatus & EP_SEL_F)) {
2345 /* Handle based on current state */
2346 if (udc->ep0state == DATA_IN)
2347 udc_ep0_in_req(udc);
2348 else {
2349 /* Unknown state for EP0 oe end of DATA IN phase */
2350 nuke(ep0, -ECONNABORTED);
2351 udc->ep0state = WAIT_FOR_SETUP;
2352 }
2353 }
2354}
2355
2356/* OUT endpoint 0 transfer */
2357static void udc_handle_ep0_out(struct lpc32xx_udc *udc)
2358{
2359 struct lpc32xx_ep *ep0 = &udc->ep[0];
2360 u32 epstatus;
2361
2362 /* Clear EP interrupt */
2363 epstatus = udc_clearep_getsts(udc, EP_OUT);
2364
2365
2366#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2367 ep0->totalints++;
2368#endif
2369
2370 /* Stalled? */
2371 if (epstatus & EP_SEL_ST) {
2372 udc_clrstall_hwep(udc, EP_OUT);
2373 nuke(ep0, -ECONNABORTED);
2374 udc->ep0state = WAIT_FOR_SETUP;
2375 return;
2376 }
2377
2378 /* A NAK may occur if a packet couldn't be received yet */
2379 if (epstatus & EP_SEL_EPN)
2380 return;
2381 /* Setup packet incoming? */
2382 if (epstatus & EP_SEL_STP) {
2383 nuke(ep0, 0);
2384 udc->ep0state = WAIT_FOR_SETUP;
2385 }
2386
2387 /* Data available? */
2388 if (epstatus & EP_SEL_F)
2389 /* Handle based on current state */
2390 switch (udc->ep0state) {
2391 case WAIT_FOR_SETUP:
2392 udc_handle_ep0_setup(udc);
2393 break;
2394
2395 case DATA_OUT:
2396 udc_ep0_out_req(udc);
2397 break;
2398
2399 default:
2400 /* Unknown state for EP0 */
2401 nuke(ep0, -ECONNABORTED);
2402 udc->ep0state = WAIT_FOR_SETUP;
2403 }
2404}
2405
2406/* Must be called without lock */
2407static int lpc32xx_get_frame(struct usb_gadget *gadget)
2408{
2409 int frame;
2410 unsigned long flags;
2411 struct lpc32xx_udc *udc = to_udc(gadget);
2412
2413 if (!udc->clocked)
2414 return -EINVAL;
2415
2416 spin_lock_irqsave(&udc->lock, flags);
2417
2418 frame = (int) udc_get_current_frame(udc);
2419
2420 spin_unlock_irqrestore(&udc->lock, flags);
2421
2422 return frame;
2423}
2424
2425static int lpc32xx_wakeup(struct usb_gadget *gadget)
2426{
2427 return -ENOTSUPP;
2428}
2429
2430static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on)
2431{
2432 gadget->is_selfpowered = (is_on != 0);
2433
2434 return 0;
2435}
2436
2437/*
2438 * vbus is here! turn everything on that's ready
2439 * Must be called without lock
2440 */
2441static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active)
2442{
2443 unsigned long flags;
2444 struct lpc32xx_udc *udc = to_udc(gadget);
2445
2446 spin_lock_irqsave(&udc->lock, flags);
2447
2448 /* Doesn't need lock */
2449 if (udc->driver) {
2450 udc_clk_set(udc, 1);
2451 udc_enable(udc);
2452 pullup(udc, is_active);
2453 } else {
2454 stop_activity(udc);
2455 pullup(udc, 0);
2456
2457 spin_unlock_irqrestore(&udc->lock, flags);
2458 /*
2459 * Wait for all the endpoints to disable,
2460 * before disabling clocks. Don't wait if
2461 * endpoints are not enabled.
2462 */
2463 if (atomic_read(&udc->enabled_ep_cnt))
2464 wait_event_interruptible(udc->ep_disable_wait_queue,
2465 (atomic_read(&udc->enabled_ep_cnt) == 0));
2466
2467 spin_lock_irqsave(&udc->lock, flags);
2468
2469 udc_clk_set(udc, 0);
2470 }
2471
2472 spin_unlock_irqrestore(&udc->lock, flags);
2473
2474 return 0;
2475}
2476
2477/* Can be called with or without lock */
2478static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on)
2479{
2480 struct lpc32xx_udc *udc = to_udc(gadget);
2481
2482 /* Doesn't need lock */
2483 pullup(udc, is_on);
2484
2485 return 0;
2486}
2487
2488static int lpc32xx_start(struct usb_gadget *, struct usb_gadget_driver *);
2489static int lpc32xx_stop(struct usb_gadget *);
2490
2491static const struct usb_gadget_ops lpc32xx_udc_ops = {
2492 .get_frame = lpc32xx_get_frame,
2493 .wakeup = lpc32xx_wakeup,
2494 .set_selfpowered = lpc32xx_set_selfpowered,
2495 .vbus_session = lpc32xx_vbus_session,
2496 .pullup = lpc32xx_pullup,
2497 .udc_start = lpc32xx_start,
2498 .udc_stop = lpc32xx_stop,
2499};
2500
2501static void nop_release(struct device *dev)
2502{
2503 /* nothing to free */
2504}
2505
2506static const struct lpc32xx_udc controller_template = {
2507 .gadget = {
2508 .ops = &lpc32xx_udc_ops,
2509 .name = driver_name,
2510 .dev = {
2511 .init_name = "gadget",
2512 .release = nop_release,
2513 }
2514 },
2515 .ep[0] = {
2516 .ep = {
2517 .name = "ep0",
2518 .ops = &lpc32xx_ep_ops,
2519 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
2520 USB_EP_CAPS_DIR_ALL),
2521 },
2522 .maxpacket = 64,
2523 .hwep_num_base = 0,
2524 .hwep_num = 0, /* Can be 0 or 1, has special handling */
2525 .lep = 0,
2526 .eptype = EP_CTL_TYPE,
2527 },
2528 .ep[1] = {
2529 .ep = {
2530 .name = "ep1-int",
2531 .ops = &lpc32xx_ep_ops,
2532 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2533 USB_EP_CAPS_DIR_ALL),
2534 },
2535 .maxpacket = 64,
2536 .hwep_num_base = 2,
2537 .hwep_num = 0, /* 2 or 3, will be set later */
2538 .lep = 1,
2539 .eptype = EP_INT_TYPE,
2540 },
2541 .ep[2] = {
2542 .ep = {
2543 .name = "ep2-bulk",
2544 .ops = &lpc32xx_ep_ops,
2545 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2546 USB_EP_CAPS_DIR_ALL),
2547 },
2548 .maxpacket = 64,
2549 .hwep_num_base = 4,
2550 .hwep_num = 0, /* 4 or 5, will be set later */
2551 .lep = 2,
2552 .eptype = EP_BLK_TYPE,
2553 },
2554 .ep[3] = {
2555 .ep = {
2556 .name = "ep3-iso",
2557 .ops = &lpc32xx_ep_ops,
2558 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2559 USB_EP_CAPS_DIR_ALL),
2560 },
2561 .maxpacket = 1023,
2562 .hwep_num_base = 6,
2563 .hwep_num = 0, /* 6 or 7, will be set later */
2564 .lep = 3,
2565 .eptype = EP_ISO_TYPE,
2566 },
2567 .ep[4] = {
2568 .ep = {
2569 .name = "ep4-int",
2570 .ops = &lpc32xx_ep_ops,
2571 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2572 USB_EP_CAPS_DIR_ALL),
2573 },
2574 .maxpacket = 64,
2575 .hwep_num_base = 8,
2576 .hwep_num = 0, /* 8 or 9, will be set later */
2577 .lep = 4,
2578 .eptype = EP_INT_TYPE,
2579 },
2580 .ep[5] = {
2581 .ep = {
2582 .name = "ep5-bulk",
2583 .ops = &lpc32xx_ep_ops,
2584 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2585 USB_EP_CAPS_DIR_ALL),
2586 },
2587 .maxpacket = 64,
2588 .hwep_num_base = 10,
2589 .hwep_num = 0, /* 10 or 11, will be set later */
2590 .lep = 5,
2591 .eptype = EP_BLK_TYPE,
2592 },
2593 .ep[6] = {
2594 .ep = {
2595 .name = "ep6-iso",
2596 .ops = &lpc32xx_ep_ops,
2597 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2598 USB_EP_CAPS_DIR_ALL),
2599 },
2600 .maxpacket = 1023,
2601 .hwep_num_base = 12,
2602 .hwep_num = 0, /* 12 or 13, will be set later */
2603 .lep = 6,
2604 .eptype = EP_ISO_TYPE,
2605 },
2606 .ep[7] = {
2607 .ep = {
2608 .name = "ep7-int",
2609 .ops = &lpc32xx_ep_ops,
2610 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2611 USB_EP_CAPS_DIR_ALL),
2612 },
2613 .maxpacket = 64,
2614 .hwep_num_base = 14,
2615 .hwep_num = 0,
2616 .lep = 7,
2617 .eptype = EP_INT_TYPE,
2618 },
2619 .ep[8] = {
2620 .ep = {
2621 .name = "ep8-bulk",
2622 .ops = &lpc32xx_ep_ops,
2623 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2624 USB_EP_CAPS_DIR_ALL),
2625 },
2626 .maxpacket = 64,
2627 .hwep_num_base = 16,
2628 .hwep_num = 0,
2629 .lep = 8,
2630 .eptype = EP_BLK_TYPE,
2631 },
2632 .ep[9] = {
2633 .ep = {
2634 .name = "ep9-iso",
2635 .ops = &lpc32xx_ep_ops,
2636 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2637 USB_EP_CAPS_DIR_ALL),
2638 },
2639 .maxpacket = 1023,
2640 .hwep_num_base = 18,
2641 .hwep_num = 0,
2642 .lep = 9,
2643 .eptype = EP_ISO_TYPE,
2644 },
2645 .ep[10] = {
2646 .ep = {
2647 .name = "ep10-int",
2648 .ops = &lpc32xx_ep_ops,
2649 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2650 USB_EP_CAPS_DIR_ALL),
2651 },
2652 .maxpacket = 64,
2653 .hwep_num_base = 20,
2654 .hwep_num = 0,
2655 .lep = 10,
2656 .eptype = EP_INT_TYPE,
2657 },
2658 .ep[11] = {
2659 .ep = {
2660 .name = "ep11-bulk",
2661 .ops = &lpc32xx_ep_ops,
2662 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2663 USB_EP_CAPS_DIR_ALL),
2664 },
2665 .maxpacket = 64,
2666 .hwep_num_base = 22,
2667 .hwep_num = 0,
2668 .lep = 11,
2669 .eptype = EP_BLK_TYPE,
2670 },
2671 .ep[12] = {
2672 .ep = {
2673 .name = "ep12-iso",
2674 .ops = &lpc32xx_ep_ops,
2675 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2676 USB_EP_CAPS_DIR_ALL),
2677 },
2678 .maxpacket = 1023,
2679 .hwep_num_base = 24,
2680 .hwep_num = 0,
2681 .lep = 12,
2682 .eptype = EP_ISO_TYPE,
2683 },
2684 .ep[13] = {
2685 .ep = {
2686 .name = "ep13-int",
2687 .ops = &lpc32xx_ep_ops,
2688 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2689 USB_EP_CAPS_DIR_ALL),
2690 },
2691 .maxpacket = 64,
2692 .hwep_num_base = 26,
2693 .hwep_num = 0,
2694 .lep = 13,
2695 .eptype = EP_INT_TYPE,
2696 },
2697 .ep[14] = {
2698 .ep = {
2699 .name = "ep14-bulk",
2700 .ops = &lpc32xx_ep_ops,
2701 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2702 USB_EP_CAPS_DIR_ALL),
2703 },
2704 .maxpacket = 64,
2705 .hwep_num_base = 28,
2706 .hwep_num = 0,
2707 .lep = 14,
2708 .eptype = EP_BLK_TYPE,
2709 },
2710 .ep[15] = {
2711 .ep = {
2712 .name = "ep15-bulk",
2713 .ops = &lpc32xx_ep_ops,
2714 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2715 USB_EP_CAPS_DIR_ALL),
2716 },
2717 .maxpacket = 1023,
2718 .hwep_num_base = 30,
2719 .hwep_num = 0,
2720 .lep = 15,
2721 .eptype = EP_BLK_TYPE,
2722 },
2723};
2724
2725/* ISO and status interrupts */
2726static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc)
2727{
2728 u32 tmp, devstat;
2729 struct lpc32xx_udc *udc = _udc;
2730
2731 spin_lock(&udc->lock);
2732
2733 /* Read the device status register */
2734 devstat = readl(USBD_DEVINTST(udc->udp_baseaddr));
2735
2736 devstat &= ~USBD_EP_FAST;
2737 writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr));
2738 devstat = devstat & udc->enabled_devints;
2739
2740 /* Device specific handling needed? */
2741 if (devstat & USBD_DEV_STAT)
2742 udc_handle_dev(udc);
2743
2744 /* Start of frame? (devstat & FRAME_INT):
2745 * The frame interrupt isn't really needed for ISO support,
2746 * as the driver will queue the necessary packets */
2747
2748 /* Error? */
2749 if (devstat & ERR_INT) {
2750 /* All types of errors, from cable removal during transfer to
2751 * misc protocol and bit errors. These are mostly for just info,
2752 * as the USB hardware will work around these. If these errors
2753 * happen alot, something is wrong. */
2754 udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT);
2755 tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT);
2756 dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp);
2757 }
2758
2759 spin_unlock(&udc->lock);
2760
2761 return IRQ_HANDLED;
2762}
2763
2764/* EP interrupts */
2765static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc)
2766{
2767 u32 tmp;
2768 struct lpc32xx_udc *udc = _udc;
2769
2770 spin_lock(&udc->lock);
2771
2772 /* Read the device status register */
2773 writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr));
2774
2775 /* Endpoints */
2776 tmp = readl(USBD_EPINTST(udc->udp_baseaddr));
2777
2778 /* Special handling for EP0 */
2779 if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2780 /* Handle EP0 IN */
2781 if (tmp & (EP_MASK_SEL(0, EP_IN)))
2782 udc_handle_ep0_in(udc);
2783
2784 /* Handle EP0 OUT */
2785 if (tmp & (EP_MASK_SEL(0, EP_OUT)))
2786 udc_handle_ep0_out(udc);
2787 }
2788
2789 /* All other EPs */
2790 if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2791 int i;
2792
2793 /* Handle other EP interrupts */
2794 for (i = 1; i < NUM_ENDPOINTS; i++) {
2795 if (tmp & (1 << udc->ep[i].hwep_num))
2796 udc_handle_eps(udc, &udc->ep[i]);
2797 }
2798 }
2799
2800 spin_unlock(&udc->lock);
2801
2802 return IRQ_HANDLED;
2803}
2804
2805static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc)
2806{
2807 struct lpc32xx_udc *udc = _udc;
2808
2809 int i;
2810 u32 tmp;
2811
2812 spin_lock(&udc->lock);
2813
2814 /* Handle EP DMA EOT interrupts */
2815 tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) |
2816 (readl(USBD_EPDMAST(udc->udp_baseaddr)) &
2817 readl(USBD_NDDRTINTST(udc->udp_baseaddr))) |
2818 readl(USBD_SYSERRTINTST(udc->udp_baseaddr));
2819 for (i = 1; i < NUM_ENDPOINTS; i++) {
2820 if (tmp & (1 << udc->ep[i].hwep_num))
2821 udc_handle_dma_ep(udc, &udc->ep[i]);
2822 }
2823
2824 spin_unlock(&udc->lock);
2825
2826 return IRQ_HANDLED;
2827}
2828
2829/*
2830 *
2831 * VBUS detection, pullup handler, and Gadget cable state notification
2832 *
2833 */
2834static void vbus_work(struct lpc32xx_udc *udc)
2835{
2836 u8 value;
2837
2838 if (udc->enabled != 0) {
2839 /* Discharge VBUS real quick */
2840 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2841 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
2842
2843 /* Give VBUS some time (100mS) to discharge */
2844 msleep(100);
2845
2846 /* Disable VBUS discharge resistor */
2847 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2848 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
2849 OTG1_VBUS_DISCHRG);
2850
2851 /* Clear interrupt */
2852 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2853 ISP1301_I2C_INTERRUPT_LATCH |
2854 ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2855
2856 /* Get the VBUS status from the transceiver */
2857 value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client,
2858 ISP1301_I2C_INTERRUPT_SOURCE);
2859
2860 /* VBUS on or off? */
2861 if (value & INT_SESS_VLD)
2862 udc->vbus = 1;
2863 else
2864 udc->vbus = 0;
2865
2866 /* VBUS changed? */
2867 if (udc->last_vbus != udc->vbus) {
2868 udc->last_vbus = udc->vbus;
2869 lpc32xx_vbus_session(&udc->gadget, udc->vbus);
2870 }
2871 }
2872}
2873
2874static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc)
2875{
2876 struct lpc32xx_udc *udc = _udc;
2877
2878 vbus_work(udc);
2879
2880 return IRQ_HANDLED;
2881}
2882
2883static int lpc32xx_start(struct usb_gadget *gadget,
2884 struct usb_gadget_driver *driver)
2885{
2886 struct lpc32xx_udc *udc = to_udc(gadget);
2887
2888 if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) {
2889 dev_err(udc->dev, "bad parameter.\n");
2890 return -EINVAL;
2891 }
2892
2893 if (udc->driver) {
2894 dev_err(udc->dev, "UDC already has a gadget driver\n");
2895 return -EBUSY;
2896 }
2897
2898 udc->driver = driver;
2899 udc->gadget.dev.of_node = udc->dev->of_node;
2900 udc->enabled = 1;
2901 udc->gadget.is_selfpowered = 1;
2902 udc->vbus = 0;
2903
2904 /* Force VBUS process once to check for cable insertion */
2905 udc->last_vbus = udc->vbus = 0;
2906 vbus_work(udc);
2907
2908 /* enable interrupts */
2909 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2910 ISP1301_I2C_INTERRUPT_FALLING, INT_SESS_VLD | INT_VBUS_VLD);
2911 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2912 ISP1301_I2C_INTERRUPT_RISING, INT_SESS_VLD | INT_VBUS_VLD);
2913
2914 return 0;
2915}
2916
2917static int lpc32xx_stop(struct usb_gadget *gadget)
2918{
2919 struct lpc32xx_udc *udc = to_udc(gadget);
2920
2921 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2922 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2923 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2924 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2925
2926 if (udc->clocked) {
2927 spin_lock(&udc->lock);
2928 stop_activity(udc);
2929 spin_unlock(&udc->lock);
2930
2931 /*
2932 * Wait for all the endpoints to disable,
2933 * before disabling clocks. Don't wait if
2934 * endpoints are not enabled.
2935 */
2936 if (atomic_read(&udc->enabled_ep_cnt))
2937 wait_event_interruptible(udc->ep_disable_wait_queue,
2938 (atomic_read(&udc->enabled_ep_cnt) == 0));
2939
2940 spin_lock(&udc->lock);
2941 udc_clk_set(udc, 0);
2942 spin_unlock(&udc->lock);
2943 }
2944
2945 udc->enabled = 0;
2946 udc->driver = NULL;
2947
2948 return 0;
2949}
2950
2951static void lpc32xx_udc_shutdown(struct platform_device *dev)
2952{
2953 /* Force disconnect on reboot */
2954 struct lpc32xx_udc *udc = platform_get_drvdata(dev);
2955
2956 pullup(udc, 0);
2957}
2958
2959/*
2960 * Callbacks to be overridden by options passed via OF (TODO)
2961 */
2962
2963static void lpc32xx_usbd_conn_chg(int conn)
2964{
2965 /* Do nothing, it might be nice to enable an LED
2966 * based on conn state being !0 */
2967}
2968
2969static void lpc32xx_usbd_susp_chg(int susp)
2970{
2971 /* Device suspend if susp != 0 */
2972}
2973
2974static void lpc32xx_rmwkup_chg(int remote_wakup_enable)
2975{
2976 /* Enable or disable USB remote wakeup */
2977}
2978
2979static struct lpc32xx_usbd_cfg lpc32xx_usbddata = {
2980 .vbus_drv_pol = 0,
2981 .conn_chgb = &lpc32xx_usbd_conn_chg,
2982 .susp_chgb = &lpc32xx_usbd_susp_chg,
2983 .rmwk_chgb = &lpc32xx_rmwkup_chg,
2984};
2985
2986
2987static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F;
2988
2989static int lpc32xx_udc_probe(struct platform_device *pdev)
2990{
2991 struct device *dev = &pdev->dev;
2992 struct lpc32xx_udc *udc;
2993 int retval, i;
2994 dma_addr_t dma_handle;
2995 struct device_node *isp1301_node;
2996
2997 udc = devm_kmemdup(dev, &controller_template, sizeof(*udc), GFP_KERNEL);
2998 if (!udc)
2999 return -ENOMEM;
3000
3001 for (i = 0; i <= 15; i++)
3002 udc->ep[i].udc = udc;
3003 udc->gadget.ep0 = &udc->ep[0].ep;
3004
3005 /* init software state */
3006 udc->gadget.dev.parent = dev;
3007 udc->pdev = pdev;
3008 udc->dev = &pdev->dev;
3009 udc->enabled = 0;
3010
3011 if (pdev->dev.of_node) {
3012 isp1301_node = of_parse_phandle(pdev->dev.of_node,
3013 "transceiver", 0);
3014 } else {
3015 isp1301_node = NULL;
3016 }
3017
3018 udc->isp1301_i2c_client = isp1301_get_client(isp1301_node);
3019 of_node_put(isp1301_node);
3020 if (!udc->isp1301_i2c_client) {
3021 return -EPROBE_DEFER;
3022 }
3023
3024 dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n",
3025 udc->isp1301_i2c_client->addr);
3026
3027 pdev->dev.dma_mask = &lpc32xx_usbd_dmamask;
3028 retval = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
3029 if (retval)
3030 return retval;
3031
3032 udc->board = &lpc32xx_usbddata;
3033
3034 /*
3035 * Resources are mapped as follows:
3036 * IORESOURCE_MEM, base address and size of USB space
3037 * IORESOURCE_IRQ, USB device low priority interrupt number
3038 * IORESOURCE_IRQ, USB device high priority interrupt number
3039 * IORESOURCE_IRQ, USB device interrupt number
3040 * IORESOURCE_IRQ, USB transceiver interrupt number
3041 */
3042
3043 spin_lock_init(&udc->lock);
3044
3045 /* Get IRQs */
3046 for (i = 0; i < 4; i++) {
3047 udc->udp_irq[i] = platform_get_irq(pdev, i);
3048 if (udc->udp_irq[i] < 0)
3049 return udc->udp_irq[i];
3050 }
3051
3052 udc->udp_baseaddr = devm_platform_ioremap_resource(pdev, 0);
3053 if (IS_ERR(udc->udp_baseaddr)) {
3054 dev_err(udc->dev, "IO map failure\n");
3055 return PTR_ERR(udc->udp_baseaddr);
3056 }
3057
3058 /* Get USB device clock */
3059 udc->usb_slv_clk = devm_clk_get(&pdev->dev, NULL);
3060 if (IS_ERR(udc->usb_slv_clk)) {
3061 dev_err(udc->dev, "failed to acquire USB device clock\n");
3062 return PTR_ERR(udc->usb_slv_clk);
3063 }
3064
3065 /* Enable USB device clock */
3066 retval = clk_prepare_enable(udc->usb_slv_clk);
3067 if (retval < 0) {
3068 dev_err(udc->dev, "failed to start USB device clock\n");
3069 return retval;
3070 }
3071
3072 /* Setup deferred workqueue data */
3073 udc->poweron = udc->pullup = 0;
3074 INIT_WORK(&udc->pullup_job, pullup_work);
3075#ifdef CONFIG_PM
3076 INIT_WORK(&udc->power_job, power_work);
3077#endif
3078
3079 /* All clocks are now on */
3080 udc->clocked = 1;
3081
3082 isp1301_udc_configure(udc);
3083 /* Allocate memory for the UDCA */
3084 udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3085 &dma_handle,
3086 (GFP_KERNEL | GFP_DMA));
3087 if (!udc->udca_v_base) {
3088 dev_err(udc->dev, "error getting UDCA region\n");
3089 retval = -ENOMEM;
3090 goto i2c_fail;
3091 }
3092 udc->udca_p_base = dma_handle;
3093 dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n",
3094 UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base);
3095
3096 /* Setup the DD DMA memory pool */
3097 udc->dd_cache = dma_pool_create("udc_dd", udc->dev,
3098 sizeof(struct lpc32xx_usbd_dd_gad),
3099 sizeof(u32), 0);
3100 if (!udc->dd_cache) {
3101 dev_err(udc->dev, "error getting DD DMA region\n");
3102 retval = -ENOMEM;
3103 goto dma_alloc_fail;
3104 }
3105
3106 /* Clear USB peripheral and initialize gadget endpoints */
3107 udc_disable(udc);
3108 udc_reinit(udc);
3109
3110 /* Request IRQs - low and high priority USB device IRQs are routed to
3111 * the same handler, while the DMA interrupt is routed elsewhere */
3112 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_LP],
3113 lpc32xx_usb_lp_irq, 0, "udc_lp", udc);
3114 if (retval < 0) {
3115 dev_err(udc->dev, "LP request irq %d failed\n",
3116 udc->udp_irq[IRQ_USB_LP]);
3117 goto irq_req_fail;
3118 }
3119 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_HP],
3120 lpc32xx_usb_hp_irq, 0, "udc_hp", udc);
3121 if (retval < 0) {
3122 dev_err(udc->dev, "HP request irq %d failed\n",
3123 udc->udp_irq[IRQ_USB_HP]);
3124 goto irq_req_fail;
3125 }
3126
3127 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_DEVDMA],
3128 lpc32xx_usb_devdma_irq, 0, "udc_dma", udc);
3129 if (retval < 0) {
3130 dev_err(udc->dev, "DEV request irq %d failed\n",
3131 udc->udp_irq[IRQ_USB_DEVDMA]);
3132 goto irq_req_fail;
3133 }
3134
3135 /* The transceiver interrupt is used for VBUS detection and will
3136 kick off the VBUS handler function */
3137 retval = devm_request_threaded_irq(dev, udc->udp_irq[IRQ_USB_ATX], NULL,
3138 lpc32xx_usb_vbus_irq, IRQF_ONESHOT,
3139 "udc_otg", udc);
3140 if (retval < 0) {
3141 dev_err(udc->dev, "VBUS request irq %d failed\n",
3142 udc->udp_irq[IRQ_USB_ATX]);
3143 goto irq_req_fail;
3144 }
3145
3146 /* Initialize wait queue */
3147 init_waitqueue_head(&udc->ep_disable_wait_queue);
3148 atomic_set(&udc->enabled_ep_cnt, 0);
3149
3150 retval = usb_add_gadget_udc(dev, &udc->gadget);
3151 if (retval < 0)
3152 goto add_gadget_fail;
3153
3154 dev_set_drvdata(dev, udc);
3155 device_init_wakeup(dev, 1);
3156 create_debug_file(udc);
3157
3158 /* Disable clocks for now */
3159 udc_clk_set(udc, 0);
3160
3161 dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION);
3162 return 0;
3163
3164add_gadget_fail:
3165irq_req_fail:
3166 dma_pool_destroy(udc->dd_cache);
3167dma_alloc_fail:
3168 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3169 udc->udca_v_base, udc->udca_p_base);
3170i2c_fail:
3171 clk_disable_unprepare(udc->usb_slv_clk);
3172 dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval);
3173
3174 return retval;
3175}
3176
3177static void lpc32xx_udc_remove(struct platform_device *pdev)
3178{
3179 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3180
3181 usb_del_gadget_udc(&udc->gadget);
3182 if (udc->driver) {
3183 dev_err(&pdev->dev,
3184 "Driver still in use but removing anyhow\n");
3185 return;
3186 }
3187
3188 udc_clk_set(udc, 1);
3189 udc_disable(udc);
3190 pullup(udc, 0);
3191
3192 device_init_wakeup(&pdev->dev, 0);
3193 remove_debug_file(udc);
3194
3195 dma_pool_destroy(udc->dd_cache);
3196 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3197 udc->udca_v_base, udc->udca_p_base);
3198
3199 clk_disable_unprepare(udc->usb_slv_clk);
3200}
3201
3202#ifdef CONFIG_PM
3203static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
3204{
3205 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3206
3207 if (udc->clocked) {
3208 /* Power down ISP */
3209 udc->poweron = 0;
3210 isp1301_set_powerstate(udc, 0);
3211
3212 /* Disable clocking */
3213 udc_clk_set(udc, 0);
3214
3215 /* Keep clock flag on, so we know to re-enable clocks
3216 on resume */
3217 udc->clocked = 1;
3218
3219 /* Kill global USB clock */
3220 clk_disable_unprepare(udc->usb_slv_clk);
3221 }
3222
3223 return 0;
3224}
3225
3226static int lpc32xx_udc_resume(struct platform_device *pdev)
3227{
3228 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3229
3230 if (udc->clocked) {
3231 /* Enable global USB clock */
3232 clk_prepare_enable(udc->usb_slv_clk);
3233
3234 /* Enable clocking */
3235 udc_clk_set(udc, 1);
3236
3237 /* ISP back to normal power mode */
3238 udc->poweron = 1;
3239 isp1301_set_powerstate(udc, 1);
3240 }
3241
3242 return 0;
3243}
3244#else
3245#define lpc32xx_udc_suspend NULL
3246#define lpc32xx_udc_resume NULL
3247#endif
3248
3249#ifdef CONFIG_OF
3250static const struct of_device_id lpc32xx_udc_of_match[] = {
3251 { .compatible = "nxp,lpc3220-udc", },
3252 { },
3253};
3254MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match);
3255#endif
3256
3257static struct platform_driver lpc32xx_udc_driver = {
3258 .probe = lpc32xx_udc_probe,
3259 .remove_new = lpc32xx_udc_remove,
3260 .shutdown = lpc32xx_udc_shutdown,
3261 .suspend = lpc32xx_udc_suspend,
3262 .resume = lpc32xx_udc_resume,
3263 .driver = {
3264 .name = driver_name,
3265 .of_match_table = of_match_ptr(lpc32xx_udc_of_match),
3266 },
3267};
3268
3269module_platform_driver(lpc32xx_udc_driver);
3270
3271MODULE_DESCRIPTION("LPC32XX udc driver");
3272MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
3273MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
3274MODULE_LICENSE("GPL");
3275MODULE_ALIAS("platform:lpc32xx_udc");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * USB Gadget driver for LPC32xx
4 *
5 * Authors:
6 * Kevin Wells <kevin.wells@nxp.com>
7 * Mike James
8 * Roland Stigge <stigge@antcom.de>
9 *
10 * Copyright (C) 2006 Philips Semiconductors
11 * Copyright (C) 2009 NXP Semiconductors
12 * Copyright (C) 2012 Roland Stigge
13 *
14 * Note: This driver is based on original work done by Mike James for
15 * the LPC3180.
16 */
17
18#include <linux/clk.h>
19#include <linux/delay.h>
20#include <linux/dma-mapping.h>
21#include <linux/dmapool.h>
22#include <linux/i2c.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/platform_device.h>
27#include <linux/prefetch.h>
28#include <linux/proc_fs.h>
29#include <linux/slab.h>
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32#include <linux/usb/isp1301.h>
33
34#ifdef CONFIG_USB_GADGET_DEBUG_FILES
35#include <linux/debugfs.h>
36#include <linux/seq_file.h>
37#endif
38
39/*
40 * USB device configuration structure
41 */
42typedef void (*usc_chg_event)(int);
43struct lpc32xx_usbd_cfg {
44 int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */
45 usc_chg_event conn_chgb; /* Connection change event (optional) */
46 usc_chg_event susp_chgb; /* Suspend/resume event (optional) */
47 usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */
48};
49
50/*
51 * controller driver data structures
52 */
53
54/* 16 endpoints (not to be confused with 32 hardware endpoints) */
55#define NUM_ENDPOINTS 16
56
57/*
58 * IRQ indices make reading the code a little easier
59 */
60#define IRQ_USB_LP 0
61#define IRQ_USB_HP 1
62#define IRQ_USB_DEVDMA 2
63#define IRQ_USB_ATX 3
64
65#define EP_OUT 0 /* RX (from host) */
66#define EP_IN 1 /* TX (to host) */
67
68/* Returns the interrupt mask for the selected hardware endpoint */
69#define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
70
71#define EP_INT_TYPE 0
72#define EP_ISO_TYPE 1
73#define EP_BLK_TYPE 2
74#define EP_CTL_TYPE 3
75
76/* EP0 states */
77#define WAIT_FOR_SETUP 0 /* Wait for setup packet */
78#define DATA_IN 1 /* Expect dev->host transfer */
79#define DATA_OUT 2 /* Expect host->dev transfer */
80
81/* DD (DMA Descriptor) structure, requires word alignment, this is already
82 * defined in the LPC32XX USB device header file, but this version is slightly
83 * modified to tag some work data with each DMA descriptor. */
84struct lpc32xx_usbd_dd_gad {
85 u32 dd_next_phy;
86 u32 dd_setup;
87 u32 dd_buffer_addr;
88 u32 dd_status;
89 u32 dd_iso_ps_mem_addr;
90 u32 this_dma;
91 u32 iso_status[6]; /* 5 spare */
92 u32 dd_next_v;
93};
94
95/*
96 * Logical endpoint structure
97 */
98struct lpc32xx_ep {
99 struct usb_ep ep;
100 struct list_head queue;
101 struct lpc32xx_udc *udc;
102
103 u32 hwep_num_base; /* Physical hardware EP */
104 u32 hwep_num; /* Maps to hardware endpoint */
105 u32 maxpacket;
106 u32 lep;
107
108 bool is_in;
109 bool req_pending;
110 u32 eptype;
111
112 u32 totalints;
113
114 bool wedge;
115};
116
117enum atx_type {
118 ISP1301,
119 STOTG04,
120};
121
122/*
123 * Common UDC structure
124 */
125struct lpc32xx_udc {
126 struct usb_gadget gadget;
127 struct usb_gadget_driver *driver;
128 struct platform_device *pdev;
129 struct device *dev;
130 struct dentry *pde;
131 spinlock_t lock;
132 struct i2c_client *isp1301_i2c_client;
133
134 /* Board and device specific */
135 struct lpc32xx_usbd_cfg *board;
136 void __iomem *udp_baseaddr;
137 int udp_irq[4];
138 struct clk *usb_slv_clk;
139
140 /* DMA support */
141 u32 *udca_v_base;
142 u32 udca_p_base;
143 struct dma_pool *dd_cache;
144
145 /* Common EP and control data */
146 u32 enabled_devints;
147 u32 enabled_hwepints;
148 u32 dev_status;
149 u32 realized_eps;
150
151 /* VBUS detection, pullup, and power flags */
152 u8 vbus;
153 u8 last_vbus;
154 int pullup;
155 int poweron;
156 enum atx_type atx;
157
158 /* Work queues related to I2C support */
159 struct work_struct pullup_job;
160 struct work_struct power_job;
161
162 /* USB device peripheral - various */
163 struct lpc32xx_ep ep[NUM_ENDPOINTS];
164 bool enabled;
165 bool clocked;
166 bool suspended;
167 int ep0state;
168 atomic_t enabled_ep_cnt;
169 wait_queue_head_t ep_disable_wait_queue;
170};
171
172/*
173 * Endpoint request
174 */
175struct lpc32xx_request {
176 struct usb_request req;
177 struct list_head queue;
178 struct lpc32xx_usbd_dd_gad *dd_desc_ptr;
179 bool mapped;
180 bool send_zlp;
181};
182
183static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g)
184{
185 return container_of(g, struct lpc32xx_udc, gadget);
186}
187
188#define ep_dbg(epp, fmt, arg...) \
189 dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg)
190#define ep_err(epp, fmt, arg...) \
191 dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg)
192#define ep_info(epp, fmt, arg...) \
193 dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg)
194#define ep_warn(epp, fmt, arg...) \
195 dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg)
196
197#define UDCA_BUFF_SIZE (128)
198
199/**********************************************************************
200 * USB device controller register offsets
201 **********************************************************************/
202
203#define USBD_DEVINTST(x) ((x) + 0x200)
204#define USBD_DEVINTEN(x) ((x) + 0x204)
205#define USBD_DEVINTCLR(x) ((x) + 0x208)
206#define USBD_DEVINTSET(x) ((x) + 0x20C)
207#define USBD_CMDCODE(x) ((x) + 0x210)
208#define USBD_CMDDATA(x) ((x) + 0x214)
209#define USBD_RXDATA(x) ((x) + 0x218)
210#define USBD_TXDATA(x) ((x) + 0x21C)
211#define USBD_RXPLEN(x) ((x) + 0x220)
212#define USBD_TXPLEN(x) ((x) + 0x224)
213#define USBD_CTRL(x) ((x) + 0x228)
214#define USBD_DEVINTPRI(x) ((x) + 0x22C)
215#define USBD_EPINTST(x) ((x) + 0x230)
216#define USBD_EPINTEN(x) ((x) + 0x234)
217#define USBD_EPINTCLR(x) ((x) + 0x238)
218#define USBD_EPINTSET(x) ((x) + 0x23C)
219#define USBD_EPINTPRI(x) ((x) + 0x240)
220#define USBD_REEP(x) ((x) + 0x244)
221#define USBD_EPIND(x) ((x) + 0x248)
222#define USBD_EPMAXPSIZE(x) ((x) + 0x24C)
223/* DMA support registers only below */
224/* Set, clear, or get enabled state of the DMA request status. If
225 * enabled, an IN or OUT token will start a DMA transfer for the EP */
226#define USBD_DMARST(x) ((x) + 0x250)
227#define USBD_DMARCLR(x) ((x) + 0x254)
228#define USBD_DMARSET(x) ((x) + 0x258)
229/* DMA UDCA head pointer */
230#define USBD_UDCAH(x) ((x) + 0x280)
231/* EP DMA status, enable, and disable. This is used to specifically
232 * enabled or disable DMA for a specific EP */
233#define USBD_EPDMAST(x) ((x) + 0x284)
234#define USBD_EPDMAEN(x) ((x) + 0x288)
235#define USBD_EPDMADIS(x) ((x) + 0x28C)
236/* DMA master interrupts enable and pending interrupts */
237#define USBD_DMAINTST(x) ((x) + 0x290)
238#define USBD_DMAINTEN(x) ((x) + 0x294)
239/* DMA end of transfer interrupt enable, disable, status */
240#define USBD_EOTINTST(x) ((x) + 0x2A0)
241#define USBD_EOTINTCLR(x) ((x) + 0x2A4)
242#define USBD_EOTINTSET(x) ((x) + 0x2A8)
243/* New DD request interrupt enable, disable, status */
244#define USBD_NDDRTINTST(x) ((x) + 0x2AC)
245#define USBD_NDDRTINTCLR(x) ((x) + 0x2B0)
246#define USBD_NDDRTINTSET(x) ((x) + 0x2B4)
247/* DMA error interrupt enable, disable, status */
248#define USBD_SYSERRTINTST(x) ((x) + 0x2B8)
249#define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC)
250#define USBD_SYSERRTINTSET(x) ((x) + 0x2C0)
251
252/**********************************************************************
253 * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/
254 * USBD_DEVINTPRI register definitions
255 **********************************************************************/
256#define USBD_ERR_INT (1 << 9)
257#define USBD_EP_RLZED (1 << 8)
258#define USBD_TXENDPKT (1 << 7)
259#define USBD_RXENDPKT (1 << 6)
260#define USBD_CDFULL (1 << 5)
261#define USBD_CCEMPTY (1 << 4)
262#define USBD_DEV_STAT (1 << 3)
263#define USBD_EP_SLOW (1 << 2)
264#define USBD_EP_FAST (1 << 1)
265#define USBD_FRAME (1 << 0)
266
267/**********************************************************************
268 * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/
269 * USBD_EPINTPRI register definitions
270 **********************************************************************/
271/* End point selection macro (RX) */
272#define USBD_RX_EP_SEL(e) (1 << ((e) << 1))
273
274/* End point selection macro (TX) */
275#define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1))
276
277/**********************************************************************
278 * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/
279 * USBD_EPDMAEN/USBD_EPDMADIS/
280 * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/
281 * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/
282 * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET
283 * register definitions
284 **********************************************************************/
285/* Endpoint selection macro */
286#define USBD_EP_SEL(e) (1 << (e))
287
288/**********************************************************************
289 * SBD_DMAINTST/USBD_DMAINTEN
290 **********************************************************************/
291#define USBD_SYS_ERR_INT (1 << 2)
292#define USBD_NEW_DD_INT (1 << 1)
293#define USBD_EOT_INT (1 << 0)
294
295/**********************************************************************
296 * USBD_RXPLEN register definitions
297 **********************************************************************/
298#define USBD_PKT_RDY (1 << 11)
299#define USBD_DV (1 << 10)
300#define USBD_PK_LEN_MASK 0x3FF
301
302/**********************************************************************
303 * USBD_CTRL register definitions
304 **********************************************************************/
305#define USBD_LOG_ENDPOINT(e) ((e) << 2)
306#define USBD_WR_EN (1 << 1)
307#define USBD_RD_EN (1 << 0)
308
309/**********************************************************************
310 * USBD_CMDCODE register definitions
311 **********************************************************************/
312#define USBD_CMD_CODE(c) ((c) << 16)
313#define USBD_CMD_PHASE(p) ((p) << 8)
314
315/**********************************************************************
316 * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions
317 **********************************************************************/
318#define USBD_DMAEP(e) (1 << (e))
319
320/* DD (DMA Descriptor) structure, requires word alignment */
321struct lpc32xx_usbd_dd {
322 u32 *dd_next;
323 u32 dd_setup;
324 u32 dd_buffer_addr;
325 u32 dd_status;
326 u32 dd_iso_ps_mem_addr;
327};
328
329/* dd_setup bit defines */
330#define DD_SETUP_ATLE_DMA_MODE 0x01
331#define DD_SETUP_NEXT_DD_VALID 0x04
332#define DD_SETUP_ISO_EP 0x10
333#define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5)
334#define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16)
335
336/* dd_status bit defines */
337#define DD_STATUS_DD_RETIRED 0x01
338#define DD_STATUS_STS_MASK 0x1E
339#define DD_STATUS_STS_NS 0x00 /* Not serviced */
340#define DD_STATUS_STS_BS 0x02 /* Being serviced */
341#define DD_STATUS_STS_NC 0x04 /* Normal completion */
342#define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */
343#define DD_STATUS_STS_DOR 0x08 /* Data overrun */
344#define DD_STATUS_STS_SE 0x12 /* System error */
345#define DD_STATUS_PKT_VAL 0x20 /* Packet valid */
346#define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */
347#define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */
348#define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F)
349#define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF)
350
351/*
352 *
353 * Protocol engine bits below
354 *
355 */
356/* Device Interrupt Bit Definitions */
357#define FRAME_INT 0x00000001
358#define EP_FAST_INT 0x00000002
359#define EP_SLOW_INT 0x00000004
360#define DEV_STAT_INT 0x00000008
361#define CCEMTY_INT 0x00000010
362#define CDFULL_INT 0x00000020
363#define RxENDPKT_INT 0x00000040
364#define TxENDPKT_INT 0x00000080
365#define EP_RLZED_INT 0x00000100
366#define ERR_INT 0x00000200
367
368/* Rx & Tx Packet Length Definitions */
369#define PKT_LNGTH_MASK 0x000003FF
370#define PKT_DV 0x00000400
371#define PKT_RDY 0x00000800
372
373/* USB Control Definitions */
374#define CTRL_RD_EN 0x00000001
375#define CTRL_WR_EN 0x00000002
376
377/* Command Codes */
378#define CMD_SET_ADDR 0x00D00500
379#define CMD_CFG_DEV 0x00D80500
380#define CMD_SET_MODE 0x00F30500
381#define CMD_RD_FRAME 0x00F50500
382#define DAT_RD_FRAME 0x00F50200
383#define CMD_RD_TEST 0x00FD0500
384#define DAT_RD_TEST 0x00FD0200
385#define CMD_SET_DEV_STAT 0x00FE0500
386#define CMD_GET_DEV_STAT 0x00FE0500
387#define DAT_GET_DEV_STAT 0x00FE0200
388#define CMD_GET_ERR_CODE 0x00FF0500
389#define DAT_GET_ERR_CODE 0x00FF0200
390#define CMD_RD_ERR_STAT 0x00FB0500
391#define DAT_RD_ERR_STAT 0x00FB0200
392#define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
393#define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
394#define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
395#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
396#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
397#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
398#define CMD_CLR_BUF 0x00F20500
399#define DAT_CLR_BUF 0x00F20200
400#define CMD_VALID_BUF 0x00FA0500
401
402/* Device Address Register Definitions */
403#define DEV_ADDR_MASK 0x7F
404#define DEV_EN 0x80
405
406/* Device Configure Register Definitions */
407#define CONF_DVICE 0x01
408
409/* Device Mode Register Definitions */
410#define AP_CLK 0x01
411#define INAK_CI 0x02
412#define INAK_CO 0x04
413#define INAK_II 0x08
414#define INAK_IO 0x10
415#define INAK_BI 0x20
416#define INAK_BO 0x40
417
418/* Device Status Register Definitions */
419#define DEV_CON 0x01
420#define DEV_CON_CH 0x02
421#define DEV_SUS 0x04
422#define DEV_SUS_CH 0x08
423#define DEV_RST 0x10
424
425/* Error Code Register Definitions */
426#define ERR_EC_MASK 0x0F
427#define ERR_EA 0x10
428
429/* Error Status Register Definitions */
430#define ERR_PID 0x01
431#define ERR_UEPKT 0x02
432#define ERR_DCRC 0x04
433#define ERR_TIMOUT 0x08
434#define ERR_EOP 0x10
435#define ERR_B_OVRN 0x20
436#define ERR_BTSTF 0x40
437#define ERR_TGL 0x80
438
439/* Endpoint Select Register Definitions */
440#define EP_SEL_F 0x01
441#define EP_SEL_ST 0x02
442#define EP_SEL_STP 0x04
443#define EP_SEL_PO 0x08
444#define EP_SEL_EPN 0x10
445#define EP_SEL_B_1_FULL 0x20
446#define EP_SEL_B_2_FULL 0x40
447
448/* Endpoint Status Register Definitions */
449#define EP_STAT_ST 0x01
450#define EP_STAT_DA 0x20
451#define EP_STAT_RF_MO 0x40
452#define EP_STAT_CND_ST 0x80
453
454/* Clear Buffer Register Definitions */
455#define CLR_BUF_PO 0x01
456
457/* DMA Interrupt Bit Definitions */
458#define EOT_INT 0x01
459#define NDD_REQ_INT 0x02
460#define SYS_ERR_INT 0x04
461
462#define DRIVER_VERSION "1.03"
463static const char driver_name[] = "lpc32xx_udc";
464
465/*
466 *
467 * proc interface support
468 *
469 */
470#ifdef CONFIG_USB_GADGET_DEBUG_FILES
471static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"};
472static const char debug_filename[] = "driver/udc";
473
474static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep)
475{
476 struct lpc32xx_request *req;
477
478 seq_printf(s, "\n");
479 seq_printf(s, "%12s, maxpacket %4d %3s",
480 ep->ep.name, ep->ep.maxpacket,
481 ep->is_in ? "in" : "out");
482 seq_printf(s, " type %4s", epnames[ep->eptype]);
483 seq_printf(s, " ints: %12d", ep->totalints);
484
485 if (list_empty(&ep->queue))
486 seq_printf(s, "\t(queue empty)\n");
487 else {
488 list_for_each_entry(req, &ep->queue, queue) {
489 u32 length = req->req.actual;
490
491 seq_printf(s, "\treq %p len %d/%d buf %p\n",
492 &req->req, length,
493 req->req.length, req->req.buf);
494 }
495 }
496}
497
498static int proc_udc_show(struct seq_file *s, void *unused)
499{
500 struct lpc32xx_udc *udc = s->private;
501 struct lpc32xx_ep *ep;
502 unsigned long flags;
503
504 seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION);
505
506 spin_lock_irqsave(&udc->lock, flags);
507
508 seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
509 udc->vbus ? "present" : "off",
510 udc->enabled ? (udc->vbus ? "active" : "enabled") :
511 "disabled",
512 udc->gadget.is_selfpowered ? "self" : "VBUS",
513 udc->suspended ? ", suspended" : "",
514 udc->driver ? udc->driver->driver.name : "(none)");
515
516 if (udc->enabled && udc->vbus) {
517 proc_ep_show(s, &udc->ep[0]);
518 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
519 proc_ep_show(s, ep);
520 }
521
522 spin_unlock_irqrestore(&udc->lock, flags);
523
524 return 0;
525}
526
527static int proc_udc_open(struct inode *inode, struct file *file)
528{
529 return single_open(file, proc_udc_show, PDE_DATA(inode));
530}
531
532static const struct file_operations proc_ops = {
533 .owner = THIS_MODULE,
534 .open = proc_udc_open,
535 .read = seq_read,
536 .llseek = seq_lseek,
537 .release = single_release,
538};
539
540static void create_debug_file(struct lpc32xx_udc *udc)
541{
542 udc->pde = debugfs_create_file(debug_filename, 0, NULL, udc, &proc_ops);
543}
544
545static void remove_debug_file(struct lpc32xx_udc *udc)
546{
547 debugfs_remove(udc->pde);
548}
549
550#else
551static inline void create_debug_file(struct lpc32xx_udc *udc) {}
552static inline void remove_debug_file(struct lpc32xx_udc *udc) {}
553#endif
554
555/* Primary initialization sequence for the ISP1301 transceiver */
556static void isp1301_udc_configure(struct lpc32xx_udc *udc)
557{
558 u8 value;
559 s32 vendor, product;
560
561 vendor = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00);
562 product = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02);
563
564 if (vendor == 0x0483 && product == 0xa0c4)
565 udc->atx = STOTG04;
566
567 /* LPC32XX only supports DAT_SE0 USB mode */
568 /* This sequence is important */
569
570 /* Disable transparent UART mode first */
571 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
572 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
573 MC1_UART_EN);
574
575 /* Set full speed and SE0 mode */
576 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
577 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
578 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
579 ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0));
580
581 /*
582 * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide
583 */
584 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
585 (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
586
587 value = MC2_BI_DI;
588 if (udc->atx != STOTG04)
589 value |= MC2_SPD_SUSP_CTRL;
590 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
591 ISP1301_I2C_MODE_CONTROL_2, value);
592
593 /* Driver VBUS_DRV high or low depending on board setup */
594 if (udc->board->vbus_drv_pol != 0)
595 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
596 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
597 else
598 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
599 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
600 OTG1_VBUS_DRV);
601
602 /* Bi-directional mode with suspend control
603 * Enable both pulldowns for now - the pullup will be enable when VBUS
604 * is detected */
605 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
606 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
607 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
608 ISP1301_I2C_OTG_CONTROL_1,
609 (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
610
611 /* Discharge VBUS (just in case) */
612 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
613 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
614 msleep(1);
615 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
616 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
617 OTG1_VBUS_DISCHRG);
618
619 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
620 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
621
622 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
623 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
624 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
625 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
626
627 dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n", vendor);
628 dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n", product);
629 dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n",
630 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14));
631
632}
633
634/* Enables or disables the USB device pullup via the ISP1301 transceiver */
635static void isp1301_pullup_set(struct lpc32xx_udc *udc)
636{
637 if (udc->pullup)
638 /* Enable pullup for bus signalling */
639 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
640 ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP);
641 else
642 /* Enable pullup for bus signalling */
643 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
644 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
645 OTG1_DP_PULLUP);
646}
647
648static void pullup_work(struct work_struct *work)
649{
650 struct lpc32xx_udc *udc =
651 container_of(work, struct lpc32xx_udc, pullup_job);
652
653 isp1301_pullup_set(udc);
654}
655
656static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
657 int block)
658{
659 if (en_pullup == udc->pullup)
660 return;
661
662 udc->pullup = en_pullup;
663 if (block)
664 isp1301_pullup_set(udc);
665 else
666 /* defer slow i2c pull up setting */
667 schedule_work(&udc->pullup_job);
668}
669
670#ifdef CONFIG_PM
671/* Powers up or down the ISP1301 transceiver */
672static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable)
673{
674 /* There is no "global power down" register for stotg04 */
675 if (udc->atx == STOTG04)
676 return;
677
678 if (enable != 0)
679 /* Power up ISP1301 - this ISP1301 will automatically wakeup
680 when VBUS is detected */
681 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
682 ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
683 MC2_GLOBAL_PWR_DN);
684 else
685 /* Power down ISP1301 */
686 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
687 ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
688}
689
690static void power_work(struct work_struct *work)
691{
692 struct lpc32xx_udc *udc =
693 container_of(work, struct lpc32xx_udc, power_job);
694
695 isp1301_set_powerstate(udc, udc->poweron);
696}
697#endif
698
699/*
700 *
701 * USB protocol engine command/data read/write helper functions
702 *
703 */
704/* Issues a single command to the USB device state machine */
705static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
706{
707 u32 pass = 0;
708 int to;
709
710 /* EP may lock on CLRI if this read isn't done */
711 u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
712 (void) tmp;
713
714 while (pass == 0) {
715 writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
716
717 /* Write command code */
718 writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
719 to = 10000;
720 while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) &
721 USBD_CCEMPTY) == 0) && (to > 0)) {
722 to--;
723 }
724
725 if (to > 0)
726 pass = 1;
727
728 cpu_relax();
729 }
730}
731
732/* Issues 2 commands (or command and data) to the USB device state machine */
733static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
734 u32 data)
735{
736 udc_protocol_cmd_w(udc, cmd);
737 udc_protocol_cmd_w(udc, data);
738}
739
740/* Issues a single command to the USB device state machine and reads
741 * response data */
742static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
743{
744 int to = 1000;
745
746 /* Write a command and read data from the protocol engine */
747 writel((USBD_CDFULL | USBD_CCEMPTY),
748 USBD_DEVINTCLR(udc->udp_baseaddr));
749
750 /* Write command code */
751 udc_protocol_cmd_w(udc, cmd);
752
753 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
754 && (to > 0))
755 to--;
756 if (!to)
757 dev_dbg(udc->dev,
758 "Protocol engine didn't receive response (CDFULL)\n");
759
760 return readl(USBD_CMDDATA(udc->udp_baseaddr));
761}
762
763/*
764 *
765 * USB device interrupt mask support functions
766 *
767 */
768/* Enable one or more USB device interrupts */
769static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask)
770{
771 udc->enabled_devints |= devmask;
772 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
773}
774
775/* Disable one or more USB device interrupts */
776static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask)
777{
778 udc->enabled_devints &= ~mask;
779 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
780}
781
782/* Clear one or more USB device interrupts */
783static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask)
784{
785 writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr));
786}
787
788/*
789 *
790 * Endpoint interrupt disable/enable functions
791 *
792 */
793/* Enable one or more USB endpoint interrupts */
794static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
795{
796 udc->enabled_hwepints |= (1 << hwep);
797 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
798}
799
800/* Disable one or more USB endpoint interrupts */
801static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
802{
803 udc->enabled_hwepints &= ~(1 << hwep);
804 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
805}
806
807/* Clear one or more USB endpoint interrupts */
808static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep)
809{
810 writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
811}
812
813/* Enable DMA for the HW channel */
814static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep)
815{
816 writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
817}
818
819/* Disable DMA for the HW channel */
820static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep)
821{
822 writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
823}
824
825/*
826 *
827 * Endpoint realize/unrealize functions
828 *
829 */
830/* Before an endpoint can be used, it needs to be realized
831 * in the USB protocol engine - this realizes the endpoint.
832 * The interrupt (FIFO or DMA) is not enabled with this function */
833static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep,
834 u32 maxpacket)
835{
836 int to = 1000;
837
838 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
839 writel(hwep, USBD_EPIND(udc->udp_baseaddr));
840 udc->realized_eps |= (1 << hwep);
841 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
842 writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
843
844 /* Wait until endpoint is realized in hardware */
845 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) &
846 USBD_EP_RLZED)) && (to > 0))
847 to--;
848 if (!to)
849 dev_dbg(udc->dev, "EP not correctly realized in hardware\n");
850
851 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
852}
853
854/* Unrealize an EP */
855static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep)
856{
857 udc->realized_eps &= ~(1 << hwep);
858 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
859}
860
861/*
862 *
863 * Endpoint support functions
864 *
865 */
866/* Select and clear endpoint interrupt */
867static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep)
868{
869 udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep));
870 return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep));
871}
872
873/* Disables the endpoint in the USB protocol engine */
874static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep)
875{
876 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
877 DAT_WR_BYTE(EP_STAT_DA));
878}
879
880/* Stalls the endpoint - endpoint will return STALL */
881static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep)
882{
883 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
884 DAT_WR_BYTE(EP_STAT_ST));
885}
886
887/* Clear stall or reset endpoint */
888static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep)
889{
890 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
891 DAT_WR_BYTE(0));
892}
893
894/* Select an endpoint for endpoint status, clear, validate */
895static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep)
896{
897 udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep));
898}
899
900/*
901 *
902 * Endpoint buffer management functions
903 *
904 */
905/* Clear the current endpoint's buffer */
906static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
907{
908 udc_select_hwep(udc, hwep);
909 udc_protocol_cmd_w(udc, CMD_CLR_BUF);
910}
911
912/* Validate the current endpoint's buffer */
913static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
914{
915 udc_select_hwep(udc, hwep);
916 udc_protocol_cmd_w(udc, CMD_VALID_BUF);
917}
918
919static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep)
920{
921 /* Clear EP interrupt */
922 uda_clear_hwepint(udc, hwep);
923 return udc_selep_clrint(udc, hwep);
924}
925
926/*
927 *
928 * USB EP DMA support
929 *
930 */
931/* Allocate a DMA Descriptor */
932static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc)
933{
934 dma_addr_t dma;
935 struct lpc32xx_usbd_dd_gad *dd;
936
937 dd = dma_pool_alloc(udc->dd_cache, GFP_ATOMIC | GFP_DMA, &dma);
938 if (dd)
939 dd->this_dma = dma;
940
941 return dd;
942}
943
944/* Free a DMA Descriptor */
945static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd)
946{
947 dma_pool_free(udc->dd_cache, dd, dd->this_dma);
948}
949
950/*
951 *
952 * USB setup and shutdown functions
953 *
954 */
955/* Enables or disables most of the USB system clocks when low power mode is
956 * needed. Clocks are typically started on a connection event, and disabled
957 * when a cable is disconnected */
958static void udc_clk_set(struct lpc32xx_udc *udc, int enable)
959{
960 if (enable != 0) {
961 if (udc->clocked)
962 return;
963
964 udc->clocked = 1;
965 clk_prepare_enable(udc->usb_slv_clk);
966 } else {
967 if (!udc->clocked)
968 return;
969
970 udc->clocked = 0;
971 clk_disable_unprepare(udc->usb_slv_clk);
972 }
973}
974
975/* Set/reset USB device address */
976static void udc_set_address(struct lpc32xx_udc *udc, u32 addr)
977{
978 /* Address will be latched at the end of the status phase, or
979 latched immediately if function is called twice */
980 udc_protocol_cmd_data_w(udc, CMD_SET_ADDR,
981 DAT_WR_BYTE(DEV_EN | addr));
982}
983
984/* Setup up a IN request for DMA transfer - this consists of determining the
985 * list of DMA addresses for the transfer, allocating DMA Descriptors,
986 * installing the DD into the UDCA, and then enabling the DMA for that EP */
987static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
988{
989 struct lpc32xx_request *req;
990 u32 hwep = ep->hwep_num;
991
992 ep->req_pending = 1;
993
994 /* There will always be a request waiting here */
995 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
996
997 /* Place the DD Descriptor into the UDCA */
998 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
999
1000 /* Enable DMA and interrupt for the HW EP */
1001 udc_ep_dma_enable(udc, hwep);
1002
1003 /* Clear ZLP if last packet is not of MAXP size */
1004 if (req->req.length % ep->ep.maxpacket)
1005 req->send_zlp = 0;
1006
1007 return 0;
1008}
1009
1010/* Setup up a OUT request for DMA transfer - this consists of determining the
1011 * list of DMA addresses for the transfer, allocating DMA Descriptors,
1012 * installing the DD into the UDCA, and then enabling the DMA for that EP */
1013static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1014{
1015 struct lpc32xx_request *req;
1016 u32 hwep = ep->hwep_num;
1017
1018 ep->req_pending = 1;
1019
1020 /* There will always be a request waiting here */
1021 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1022
1023 /* Place the DD Descriptor into the UDCA */
1024 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1025
1026 /* Enable DMA and interrupt for the HW EP */
1027 udc_ep_dma_enable(udc, hwep);
1028 return 0;
1029}
1030
1031static void udc_disable(struct lpc32xx_udc *udc)
1032{
1033 u32 i;
1034
1035 /* Disable device */
1036 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1037 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0));
1038
1039 /* Disable all device interrupts (including EP0) */
1040 uda_disable_devint(udc, 0x3FF);
1041
1042 /* Disable and reset all endpoint interrupts */
1043 for (i = 0; i < 32; i++) {
1044 uda_disable_hwepint(udc, i);
1045 uda_clear_hwepint(udc, i);
1046 udc_disable_hwep(udc, i);
1047 udc_unrealize_hwep(udc, i);
1048 udc->udca_v_base[i] = 0;
1049
1050 /* Disable and clear all interrupts and DMA */
1051 udc_ep_dma_disable(udc, i);
1052 writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr));
1053 writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr));
1054 writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1055 writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr));
1056 }
1057
1058 /* Disable DMA interrupts */
1059 writel(0, USBD_DMAINTEN(udc->udp_baseaddr));
1060
1061 writel(0, USBD_UDCAH(udc->udp_baseaddr));
1062}
1063
1064static void udc_enable(struct lpc32xx_udc *udc)
1065{
1066 u32 i;
1067 struct lpc32xx_ep *ep = &udc->ep[0];
1068
1069 /* Start with known state */
1070 udc_disable(udc);
1071
1072 /* Enable device */
1073 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));
1074
1075 /* EP interrupts on high priority, FRAME interrupt on low priority */
1076 writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr));
1077 writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr));
1078
1079 /* Clear any pending device interrupts */
1080 writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr));
1081
1082 /* Setup UDCA - not yet used (DMA) */
1083 writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr));
1084
1085 /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */
1086 for (i = 0; i <= 1; i++) {
1087 udc_realize_hwep(udc, i, ep->ep.maxpacket);
1088 uda_enable_hwepint(udc, i);
1089 udc_select_hwep(udc, i);
1090 udc_clrstall_hwep(udc, i);
1091 udc_clr_buffer_hwep(udc, i);
1092 }
1093
1094 /* Device interrupt setup */
1095 uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1096 USBD_EP_FAST));
1097 uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1098 USBD_EP_FAST));
1099
1100 /* Set device address to 0 - called twice to force a latch in the USB
1101 engine without the need of a setup packet status closure */
1102 udc_set_address(udc, 0);
1103 udc_set_address(udc, 0);
1104
1105 /* Enable master DMA interrupts */
1106 writel((USBD_SYS_ERR_INT | USBD_EOT_INT),
1107 USBD_DMAINTEN(udc->udp_baseaddr));
1108
1109 udc->dev_status = 0;
1110}
1111
1112/*
1113 *
1114 * USB device board specific events handled via callbacks
1115 *
1116 */
1117/* Connection change event - notify board function of change */
1118static void uda_power_event(struct lpc32xx_udc *udc, u32 conn)
1119{
1120 /* Just notify of a connection change event (optional) */
1121 if (udc->board->conn_chgb != NULL)
1122 udc->board->conn_chgb(conn);
1123}
1124
1125/* Suspend/resume event - notify board function of change */
1126static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn)
1127{
1128 /* Just notify of a Suspend/resume change event (optional) */
1129 if (udc->board->susp_chgb != NULL)
1130 udc->board->susp_chgb(conn);
1131
1132 if (conn)
1133 udc->suspended = 0;
1134 else
1135 udc->suspended = 1;
1136}
1137
1138/* Remote wakeup enable/disable - notify board function of change */
1139static void uda_remwkp_cgh(struct lpc32xx_udc *udc)
1140{
1141 if (udc->board->rmwk_chgb != NULL)
1142 udc->board->rmwk_chgb(udc->dev_status &
1143 (1 << USB_DEVICE_REMOTE_WAKEUP));
1144}
1145
1146/* Reads data from FIFO, adjusts for alignment and data size */
1147static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1148{
1149 int n, i, bl;
1150 u16 *p16;
1151 u32 *p32, tmp, cbytes;
1152
1153 /* Use optimal data transfer method based on source address and size */
1154 switch (((uintptr_t) data) & 0x3) {
1155 case 0: /* 32-bit aligned */
1156 p32 = (u32 *) data;
1157 cbytes = (bytes & ~0x3);
1158
1159 /* Copy 32-bit aligned data first */
1160 for (n = 0; n < cbytes; n += 4)
1161 *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr));
1162
1163 /* Handle any remaining bytes */
1164 bl = bytes - cbytes;
1165 if (bl) {
1166 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1167 for (n = 0; n < bl; n++)
1168 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1169
1170 }
1171 break;
1172
1173 case 1: /* 8-bit aligned */
1174 case 3:
1175 /* Each byte has to be handled independently */
1176 for (n = 0; n < bytes; n += 4) {
1177 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1178
1179 bl = bytes - n;
1180 if (bl > 4)
1181 bl = 4;
1182
1183 for (i = 0; i < bl; i++)
1184 data[n + i] = (u8) ((tmp >> (i * 8)) & 0xFF);
1185 }
1186 break;
1187
1188 case 2: /* 16-bit aligned */
1189 p16 = (u16 *) data;
1190 cbytes = (bytes & ~0x3);
1191
1192 /* Copy 32-bit sized objects first with 16-bit alignment */
1193 for (n = 0; n < cbytes; n += 4) {
1194 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1195 *p16++ = (u16)(tmp & 0xFFFF);
1196 *p16++ = (u16)((tmp >> 16) & 0xFFFF);
1197 }
1198
1199 /* Handle any remaining bytes */
1200 bl = bytes - cbytes;
1201 if (bl) {
1202 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1203 for (n = 0; n < bl; n++)
1204 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1205 }
1206 break;
1207 }
1208}
1209
1210/* Read data from the FIFO for an endpoint. This function is for endpoints (such
1211 * as EP0) that don't use DMA. This function should only be called if a packet
1212 * is known to be ready to read for the endpoint. Note that the endpoint must
1213 * be selected in the protocol engine prior to this call. */
1214static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1215 u32 bytes)
1216{
1217 u32 tmpv;
1218 int to = 1000;
1219 u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN;
1220
1221 /* Setup read of endpoint */
1222 writel(hwrep, USBD_CTRL(udc->udp_baseaddr));
1223
1224 /* Wait until packet is ready */
1225 while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) &
1226 PKT_RDY) == 0) && (to > 0))
1227 to--;
1228 if (!to)
1229 dev_dbg(udc->dev, "No packet ready on FIFO EP read\n");
1230
1231 /* Mask out count */
1232 tmp = tmpv & PKT_LNGTH_MASK;
1233 if (bytes < tmp)
1234 tmp = bytes;
1235
1236 if ((tmp > 0) && (data != NULL))
1237 udc_pop_fifo(udc, (u8 *) data, tmp);
1238
1239 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1240
1241 /* Clear the buffer */
1242 udc_clr_buffer_hwep(udc, hwep);
1243
1244 return tmp;
1245}
1246
1247/* Stuffs data into the FIFO, adjusts for alignment and data size */
1248static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1249{
1250 int n, i, bl;
1251 u16 *p16;
1252 u32 *p32, tmp, cbytes;
1253
1254 /* Use optimal data transfer method based on source address and size */
1255 switch (((uintptr_t) data) & 0x3) {
1256 case 0: /* 32-bit aligned */
1257 p32 = (u32 *) data;
1258 cbytes = (bytes & ~0x3);
1259
1260 /* Copy 32-bit aligned data first */
1261 for (n = 0; n < cbytes; n += 4)
1262 writel(*p32++, USBD_TXDATA(udc->udp_baseaddr));
1263
1264 /* Handle any remaining bytes */
1265 bl = bytes - cbytes;
1266 if (bl) {
1267 tmp = 0;
1268 for (n = 0; n < bl; n++)
1269 tmp |= data[cbytes + n] << (n * 8);
1270
1271 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1272 }
1273 break;
1274
1275 case 1: /* 8-bit aligned */
1276 case 3:
1277 /* Each byte has to be handled independently */
1278 for (n = 0; n < bytes; n += 4) {
1279 bl = bytes - n;
1280 if (bl > 4)
1281 bl = 4;
1282
1283 tmp = 0;
1284 for (i = 0; i < bl; i++)
1285 tmp |= data[n + i] << (i * 8);
1286
1287 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1288 }
1289 break;
1290
1291 case 2: /* 16-bit aligned */
1292 p16 = (u16 *) data;
1293 cbytes = (bytes & ~0x3);
1294
1295 /* Copy 32-bit aligned data first */
1296 for (n = 0; n < cbytes; n += 4) {
1297 tmp = *p16++ & 0xFFFF;
1298 tmp |= (*p16++ & 0xFFFF) << 16;
1299 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1300 }
1301
1302 /* Handle any remaining bytes */
1303 bl = bytes - cbytes;
1304 if (bl) {
1305 tmp = 0;
1306 for (n = 0; n < bl; n++)
1307 tmp |= data[cbytes + n] << (n * 8);
1308
1309 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1310 }
1311 break;
1312 }
1313}
1314
1315/* Write data to the FIFO for an endpoint. This function is for endpoints (such
1316 * as EP0) that don't use DMA. Note that the endpoint must be selected in the
1317 * protocol engine prior to this call. */
1318static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1319 u32 bytes)
1320{
1321 u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN;
1322
1323 if ((bytes > 0) && (data == NULL))
1324 return;
1325
1326 /* Setup write of endpoint */
1327 writel(hwwep, USBD_CTRL(udc->udp_baseaddr));
1328
1329 writel(bytes, USBD_TXPLEN(udc->udp_baseaddr));
1330
1331 /* Need at least 1 byte to trigger TX */
1332 if (bytes == 0)
1333 writel(0, USBD_TXDATA(udc->udp_baseaddr));
1334 else
1335 udc_stuff_fifo(udc, (u8 *) data, bytes);
1336
1337 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1338
1339 udc_val_buffer_hwep(udc, hwep);
1340}
1341
1342/* USB device reset - resets USB to a default state with just EP0
1343 enabled */
1344static void uda_usb_reset(struct lpc32xx_udc *udc)
1345{
1346 u32 i = 0;
1347 /* Re-init device controller and EP0 */
1348 udc_enable(udc);
1349 udc->gadget.speed = USB_SPEED_FULL;
1350
1351 for (i = 1; i < NUM_ENDPOINTS; i++) {
1352 struct lpc32xx_ep *ep = &udc->ep[i];
1353 ep->req_pending = 0;
1354 }
1355}
1356
1357/* Send a ZLP on EP0 */
1358static void udc_ep0_send_zlp(struct lpc32xx_udc *udc)
1359{
1360 udc_write_hwep(udc, EP_IN, NULL, 0);
1361}
1362
1363/* Get current frame number */
1364static u16 udc_get_current_frame(struct lpc32xx_udc *udc)
1365{
1366 u16 flo, fhi;
1367
1368 udc_protocol_cmd_w(udc, CMD_RD_FRAME);
1369 flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1370 fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1371
1372 return (fhi << 8) | flo;
1373}
1374
1375/* Set the device as configured - enables all endpoints */
1376static inline void udc_set_device_configured(struct lpc32xx_udc *udc)
1377{
1378 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE));
1379}
1380
1381/* Set the device as unconfigured - disables all endpoints */
1382static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc)
1383{
1384 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1385}
1386
1387/* reinit == restore initial software state */
1388static void udc_reinit(struct lpc32xx_udc *udc)
1389{
1390 u32 i;
1391
1392 INIT_LIST_HEAD(&udc->gadget.ep_list);
1393 INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
1394
1395 for (i = 0; i < NUM_ENDPOINTS; i++) {
1396 struct lpc32xx_ep *ep = &udc->ep[i];
1397
1398 if (i != 0)
1399 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1400 usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket);
1401 INIT_LIST_HEAD(&ep->queue);
1402 ep->req_pending = 0;
1403 }
1404
1405 udc->ep0state = WAIT_FOR_SETUP;
1406}
1407
1408/* Must be called with lock */
1409static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status)
1410{
1411 struct lpc32xx_udc *udc = ep->udc;
1412
1413 list_del_init(&req->queue);
1414 if (req->req.status == -EINPROGRESS)
1415 req->req.status = status;
1416 else
1417 status = req->req.status;
1418
1419 if (ep->lep) {
1420 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
1421
1422 /* Free DDs */
1423 udc_dd_free(udc, req->dd_desc_ptr);
1424 }
1425
1426 if (status && status != -ESHUTDOWN)
1427 ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status);
1428
1429 ep->req_pending = 0;
1430 spin_unlock(&udc->lock);
1431 usb_gadget_giveback_request(&ep->ep, &req->req);
1432 spin_lock(&udc->lock);
1433}
1434
1435/* Must be called with lock */
1436static void nuke(struct lpc32xx_ep *ep, int status)
1437{
1438 struct lpc32xx_request *req;
1439
1440 while (!list_empty(&ep->queue)) {
1441 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1442 done(ep, req, status);
1443 }
1444
1445 if (status == -ESHUTDOWN) {
1446 uda_disable_hwepint(ep->udc, ep->hwep_num);
1447 udc_disable_hwep(ep->udc, ep->hwep_num);
1448 }
1449}
1450
1451/* IN endpoint 0 transfer */
1452static int udc_ep0_in_req(struct lpc32xx_udc *udc)
1453{
1454 struct lpc32xx_request *req;
1455 struct lpc32xx_ep *ep0 = &udc->ep[0];
1456 u32 tsend, ts = 0;
1457
1458 if (list_empty(&ep0->queue))
1459 /* Nothing to send */
1460 return 0;
1461 else
1462 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1463 queue);
1464
1465 tsend = ts = req->req.length - req->req.actual;
1466 if (ts == 0) {
1467 /* Send a ZLP */
1468 udc_ep0_send_zlp(udc);
1469 done(ep0, req, 0);
1470 return 1;
1471 } else if (ts > ep0->ep.maxpacket)
1472 ts = ep0->ep.maxpacket; /* Just send what we can */
1473
1474 /* Write data to the EP0 FIFO and start transfer */
1475 udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts);
1476
1477 /* Increment data pointer */
1478 req->req.actual += ts;
1479
1480 if (tsend >= ep0->ep.maxpacket)
1481 return 0; /* Stay in data transfer state */
1482
1483 /* Transfer request is complete */
1484 udc->ep0state = WAIT_FOR_SETUP;
1485 done(ep0, req, 0);
1486 return 1;
1487}
1488
1489/* OUT endpoint 0 transfer */
1490static int udc_ep0_out_req(struct lpc32xx_udc *udc)
1491{
1492 struct lpc32xx_request *req;
1493 struct lpc32xx_ep *ep0 = &udc->ep[0];
1494 u32 tr, bufferspace;
1495
1496 if (list_empty(&ep0->queue))
1497 return 0;
1498 else
1499 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1500 queue);
1501
1502 if (req) {
1503 if (req->req.length == 0) {
1504 /* Just dequeue request */
1505 done(ep0, req, 0);
1506 udc->ep0state = WAIT_FOR_SETUP;
1507 return 1;
1508 }
1509
1510 /* Get data from FIFO */
1511 bufferspace = req->req.length - req->req.actual;
1512 if (bufferspace > ep0->ep.maxpacket)
1513 bufferspace = ep0->ep.maxpacket;
1514
1515 /* Copy data to buffer */
1516 prefetchw(req->req.buf + req->req.actual);
1517 tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual,
1518 bufferspace);
1519 req->req.actual += bufferspace;
1520
1521 if (tr < ep0->ep.maxpacket) {
1522 /* This is the last packet */
1523 done(ep0, req, 0);
1524 udc->ep0state = WAIT_FOR_SETUP;
1525 return 1;
1526 }
1527 }
1528
1529 return 0;
1530}
1531
1532/* Must be called with lock */
1533static void stop_activity(struct lpc32xx_udc *udc)
1534{
1535 struct usb_gadget_driver *driver = udc->driver;
1536 int i;
1537
1538 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1539 driver = NULL;
1540
1541 udc->gadget.speed = USB_SPEED_UNKNOWN;
1542 udc->suspended = 0;
1543
1544 for (i = 0; i < NUM_ENDPOINTS; i++) {
1545 struct lpc32xx_ep *ep = &udc->ep[i];
1546 nuke(ep, -ESHUTDOWN);
1547 }
1548 if (driver) {
1549 spin_unlock(&udc->lock);
1550 driver->disconnect(&udc->gadget);
1551 spin_lock(&udc->lock);
1552 }
1553
1554 isp1301_pullup_enable(udc, 0, 0);
1555 udc_disable(udc);
1556 udc_reinit(udc);
1557}
1558
1559/*
1560 * Activate or kill host pullup
1561 * Can be called with or without lock
1562 */
1563static void pullup(struct lpc32xx_udc *udc, int is_on)
1564{
1565 if (!udc->clocked)
1566 return;
1567
1568 if (!udc->enabled || !udc->vbus)
1569 is_on = 0;
1570
1571 if (is_on != udc->pullup)
1572 isp1301_pullup_enable(udc, is_on, 0);
1573}
1574
1575/* Must be called without lock */
1576static int lpc32xx_ep_disable(struct usb_ep *_ep)
1577{
1578 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1579 struct lpc32xx_udc *udc = ep->udc;
1580 unsigned long flags;
1581
1582 if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0))
1583 return -EINVAL;
1584 spin_lock_irqsave(&udc->lock, flags);
1585
1586 nuke(ep, -ESHUTDOWN);
1587
1588 /* Clear all DMA statuses for this EP */
1589 udc_ep_dma_disable(udc, ep->hwep_num);
1590 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1591 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1592 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1593 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1594
1595 /* Remove the DD pointer in the UDCA */
1596 udc->udca_v_base[ep->hwep_num] = 0;
1597
1598 /* Disable and reset endpoint and interrupt */
1599 uda_clear_hwepint(udc, ep->hwep_num);
1600 udc_unrealize_hwep(udc, ep->hwep_num);
1601
1602 ep->hwep_num = 0;
1603
1604 spin_unlock_irqrestore(&udc->lock, flags);
1605
1606 atomic_dec(&udc->enabled_ep_cnt);
1607 wake_up(&udc->ep_disable_wait_queue);
1608
1609 return 0;
1610}
1611
1612/* Must be called without lock */
1613static int lpc32xx_ep_enable(struct usb_ep *_ep,
1614 const struct usb_endpoint_descriptor *desc)
1615{
1616 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1617 struct lpc32xx_udc *udc = ep->udc;
1618 u16 maxpacket;
1619 u32 tmp;
1620 unsigned long flags;
1621
1622 /* Verify EP data */
1623 if ((!_ep) || (!ep) || (!desc) ||
1624 (desc->bDescriptorType != USB_DT_ENDPOINT)) {
1625 dev_dbg(udc->dev, "bad ep or descriptor\n");
1626 return -EINVAL;
1627 }
1628 maxpacket = usb_endpoint_maxp(desc);
1629 if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) {
1630 dev_dbg(udc->dev, "bad ep descriptor's packet size\n");
1631 return -EINVAL;
1632 }
1633
1634 /* Don't touch EP0 */
1635 if (ep->hwep_num_base == 0) {
1636 dev_dbg(udc->dev, "Can't re-enable EP0!!!\n");
1637 return -EINVAL;
1638 }
1639
1640 /* Is driver ready? */
1641 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1642 dev_dbg(udc->dev, "bogus device state\n");
1643 return -ESHUTDOWN;
1644 }
1645
1646 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1647 switch (tmp) {
1648 case USB_ENDPOINT_XFER_CONTROL:
1649 return -EINVAL;
1650
1651 case USB_ENDPOINT_XFER_INT:
1652 if (maxpacket > ep->maxpacket) {
1653 dev_dbg(udc->dev,
1654 "Bad INT endpoint maxpacket %d\n", maxpacket);
1655 return -EINVAL;
1656 }
1657 break;
1658
1659 case USB_ENDPOINT_XFER_BULK:
1660 switch (maxpacket) {
1661 case 8:
1662 case 16:
1663 case 32:
1664 case 64:
1665 break;
1666
1667 default:
1668 dev_dbg(udc->dev,
1669 "Bad BULK endpoint maxpacket %d\n", maxpacket);
1670 return -EINVAL;
1671 }
1672 break;
1673
1674 case USB_ENDPOINT_XFER_ISOC:
1675 break;
1676 }
1677 spin_lock_irqsave(&udc->lock, flags);
1678
1679 /* Initialize endpoint to match the selected descriptor */
1680 ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
1681 ep->ep.maxpacket = maxpacket;
1682
1683 /* Map hardware endpoint from base and direction */
1684 if (ep->is_in)
1685 /* IN endpoints are offset 1 from the OUT endpoint */
1686 ep->hwep_num = ep->hwep_num_base + EP_IN;
1687 else
1688 ep->hwep_num = ep->hwep_num_base;
1689
1690 ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name,
1691 ep->hwep_num, maxpacket, (ep->is_in == 1));
1692
1693 /* Realize the endpoint, interrupt is enabled later when
1694 * buffers are queued, IN EPs will NAK until buffers are ready */
1695 udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket);
1696 udc_clr_buffer_hwep(udc, ep->hwep_num);
1697 uda_disable_hwepint(udc, ep->hwep_num);
1698 udc_clrstall_hwep(udc, ep->hwep_num);
1699
1700 /* Clear all DMA statuses for this EP */
1701 udc_ep_dma_disable(udc, ep->hwep_num);
1702 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1703 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1704 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1705 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1706
1707 spin_unlock_irqrestore(&udc->lock, flags);
1708
1709 atomic_inc(&udc->enabled_ep_cnt);
1710 return 0;
1711}
1712
1713/*
1714 * Allocate a USB request list
1715 * Can be called with or without lock
1716 */
1717static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep,
1718 gfp_t gfp_flags)
1719{
1720 struct lpc32xx_request *req;
1721
1722 req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags);
1723 if (!req)
1724 return NULL;
1725
1726 INIT_LIST_HEAD(&req->queue);
1727 return &req->req;
1728}
1729
1730/*
1731 * De-allocate a USB request list
1732 * Can be called with or without lock
1733 */
1734static void lpc32xx_ep_free_request(struct usb_ep *_ep,
1735 struct usb_request *_req)
1736{
1737 struct lpc32xx_request *req;
1738
1739 req = container_of(_req, struct lpc32xx_request, req);
1740 BUG_ON(!list_empty(&req->queue));
1741 kfree(req);
1742}
1743
1744/* Must be called without lock */
1745static int lpc32xx_ep_queue(struct usb_ep *_ep,
1746 struct usb_request *_req, gfp_t gfp_flags)
1747{
1748 struct lpc32xx_request *req;
1749 struct lpc32xx_ep *ep;
1750 struct lpc32xx_udc *udc;
1751 unsigned long flags;
1752 int status = 0;
1753
1754 req = container_of(_req, struct lpc32xx_request, req);
1755 ep = container_of(_ep, struct lpc32xx_ep, ep);
1756
1757 if (!_ep || !_req || !_req->complete || !_req->buf ||
1758 !list_empty(&req->queue))
1759 return -EINVAL;
1760
1761 udc = ep->udc;
1762
1763 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1764 return -EPIPE;
1765
1766 if (ep->lep) {
1767 struct lpc32xx_usbd_dd_gad *dd;
1768
1769 status = usb_gadget_map_request(&udc->gadget, _req, ep->is_in);
1770 if (status)
1771 return status;
1772
1773 /* For the request, build a list of DDs */
1774 dd = udc_dd_alloc(udc);
1775 if (!dd) {
1776 /* Error allocating DD */
1777 return -ENOMEM;
1778 }
1779 req->dd_desc_ptr = dd;
1780
1781 /* Setup the DMA descriptor */
1782 dd->dd_next_phy = dd->dd_next_v = 0;
1783 dd->dd_buffer_addr = req->req.dma;
1784 dd->dd_status = 0;
1785
1786 /* Special handling for ISO EPs */
1787 if (ep->eptype == EP_ISO_TYPE) {
1788 dd->dd_setup = DD_SETUP_ISO_EP |
1789 DD_SETUP_PACKETLEN(0) |
1790 DD_SETUP_DMALENBYTES(1);
1791 dd->dd_iso_ps_mem_addr = dd->this_dma + 24;
1792 if (ep->is_in)
1793 dd->iso_status[0] = req->req.length;
1794 else
1795 dd->iso_status[0] = 0;
1796 } else
1797 dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) |
1798 DD_SETUP_DMALENBYTES(req->req.length);
1799 }
1800
1801 ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name,
1802 _req, _req->length, _req->buf, ep->is_in, _req->zero);
1803
1804 spin_lock_irqsave(&udc->lock, flags);
1805
1806 _req->status = -EINPROGRESS;
1807 _req->actual = 0;
1808 req->send_zlp = _req->zero;
1809
1810 /* Kickstart empty queues */
1811 if (list_empty(&ep->queue)) {
1812 list_add_tail(&req->queue, &ep->queue);
1813
1814 if (ep->hwep_num_base == 0) {
1815 /* Handle expected data direction */
1816 if (ep->is_in) {
1817 /* IN packet to host */
1818 udc->ep0state = DATA_IN;
1819 status = udc_ep0_in_req(udc);
1820 } else {
1821 /* OUT packet from host */
1822 udc->ep0state = DATA_OUT;
1823 status = udc_ep0_out_req(udc);
1824 }
1825 } else if (ep->is_in) {
1826 /* IN packet to host and kick off transfer */
1827 if (!ep->req_pending)
1828 udc_ep_in_req_dma(udc, ep);
1829 } else
1830 /* OUT packet from host and kick off list */
1831 if (!ep->req_pending)
1832 udc_ep_out_req_dma(udc, ep);
1833 } else
1834 list_add_tail(&req->queue, &ep->queue);
1835
1836 spin_unlock_irqrestore(&udc->lock, flags);
1837
1838 return (status < 0) ? status : 0;
1839}
1840
1841/* Must be called without lock */
1842static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1843{
1844 struct lpc32xx_ep *ep;
1845 struct lpc32xx_request *req;
1846 unsigned long flags;
1847
1848 ep = container_of(_ep, struct lpc32xx_ep, ep);
1849 if (!_ep || ep->hwep_num_base == 0)
1850 return -EINVAL;
1851
1852 spin_lock_irqsave(&ep->udc->lock, flags);
1853
1854 /* make sure it's actually queued on this endpoint */
1855 list_for_each_entry(req, &ep->queue, queue) {
1856 if (&req->req == _req)
1857 break;
1858 }
1859 if (&req->req != _req) {
1860 spin_unlock_irqrestore(&ep->udc->lock, flags);
1861 return -EINVAL;
1862 }
1863
1864 done(ep, req, -ECONNRESET);
1865
1866 spin_unlock_irqrestore(&ep->udc->lock, flags);
1867
1868 return 0;
1869}
1870
1871/* Must be called without lock */
1872static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value)
1873{
1874 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1875 struct lpc32xx_udc *udc = ep->udc;
1876 unsigned long flags;
1877
1878 if ((!ep) || (ep->hwep_num <= 1))
1879 return -EINVAL;
1880
1881 /* Don't halt an IN EP */
1882 if (ep->is_in)
1883 return -EAGAIN;
1884
1885 spin_lock_irqsave(&udc->lock, flags);
1886
1887 if (value == 1) {
1888 /* stall */
1889 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1890 DAT_WR_BYTE(EP_STAT_ST));
1891 } else {
1892 /* End stall */
1893 ep->wedge = 0;
1894 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1895 DAT_WR_BYTE(0));
1896 }
1897
1898 spin_unlock_irqrestore(&udc->lock, flags);
1899
1900 return 0;
1901}
1902
1903/* set the halt feature and ignores clear requests */
1904static int lpc32xx_ep_set_wedge(struct usb_ep *_ep)
1905{
1906 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1907
1908 if (!_ep || !ep->udc)
1909 return -EINVAL;
1910
1911 ep->wedge = 1;
1912
1913 return usb_ep_set_halt(_ep);
1914}
1915
1916static const struct usb_ep_ops lpc32xx_ep_ops = {
1917 .enable = lpc32xx_ep_enable,
1918 .disable = lpc32xx_ep_disable,
1919 .alloc_request = lpc32xx_ep_alloc_request,
1920 .free_request = lpc32xx_ep_free_request,
1921 .queue = lpc32xx_ep_queue,
1922 .dequeue = lpc32xx_ep_dequeue,
1923 .set_halt = lpc32xx_ep_set_halt,
1924 .set_wedge = lpc32xx_ep_set_wedge,
1925};
1926
1927/* Send a ZLP on a non-0 IN EP */
1928void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1929{
1930 /* Clear EP status */
1931 udc_clearep_getsts(udc, ep->hwep_num);
1932
1933 /* Send ZLP via FIFO mechanism */
1934 udc_write_hwep(udc, ep->hwep_num, NULL, 0);
1935}
1936
1937/*
1938 * Handle EP completion for ZLP
1939 * This function will only be called when a delayed ZLP needs to be sent out
1940 * after a DMA transfer has filled both buffers.
1941 */
1942void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1943{
1944 u32 epstatus;
1945 struct lpc32xx_request *req;
1946
1947 if (ep->hwep_num <= 0)
1948 return;
1949
1950 uda_clear_hwepint(udc, ep->hwep_num);
1951
1952 /* If this interrupt isn't enabled, return now */
1953 if (!(udc->enabled_hwepints & (1 << ep->hwep_num)))
1954 return;
1955
1956 /* Get endpoint status */
1957 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
1958
1959 /*
1960 * This should never happen, but protect against writing to the
1961 * buffer when full.
1962 */
1963 if (epstatus & EP_SEL_F)
1964 return;
1965
1966 if (ep->is_in) {
1967 udc_send_in_zlp(udc, ep);
1968 uda_disable_hwepint(udc, ep->hwep_num);
1969 } else
1970 return;
1971
1972 /* If there isn't a request waiting, something went wrong */
1973 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1974 if (req) {
1975 done(ep, req, 0);
1976
1977 /* Start another request if ready */
1978 if (!list_empty(&ep->queue)) {
1979 if (ep->is_in)
1980 udc_ep_in_req_dma(udc, ep);
1981 else
1982 udc_ep_out_req_dma(udc, ep);
1983 } else
1984 ep->req_pending = 0;
1985 }
1986}
1987
1988
1989/* DMA end of transfer completion */
1990static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1991{
1992 u32 status;
1993 struct lpc32xx_request *req;
1994 struct lpc32xx_usbd_dd_gad *dd;
1995
1996#ifdef CONFIG_USB_GADGET_DEBUG_FILES
1997 ep->totalints++;
1998#endif
1999
2000 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
2001 if (!req) {
2002 ep_err(ep, "DMA interrupt on no req!\n");
2003 return;
2004 }
2005 dd = req->dd_desc_ptr;
2006
2007 /* DMA descriptor should always be retired for this call */
2008 if (!(dd->dd_status & DD_STATUS_DD_RETIRED))
2009 ep_warn(ep, "DMA descriptor did not retire\n");
2010
2011 /* Disable DMA */
2012 udc_ep_dma_disable(udc, ep->hwep_num);
2013 writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr));
2014 writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr));
2015
2016 /* System error? */
2017 if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) &
2018 (1 << ep->hwep_num)) {
2019 writel((1 << ep->hwep_num),
2020 USBD_SYSERRTINTCLR(udc->udp_baseaddr));
2021 ep_err(ep, "AHB critical error!\n");
2022 ep->req_pending = 0;
2023
2024 /* The error could have occurred on a packet of a multipacket
2025 * transfer, so recovering the transfer is not possible. Close
2026 * the request with an error */
2027 done(ep, req, -ECONNABORTED);
2028 return;
2029 }
2030
2031 /* Handle the current DD's status */
2032 status = dd->dd_status;
2033 switch (status & DD_STATUS_STS_MASK) {
2034 case DD_STATUS_STS_NS:
2035 /* DD not serviced? This shouldn't happen! */
2036 ep->req_pending = 0;
2037 ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n",
2038 status);
2039
2040 done(ep, req, -ECONNABORTED);
2041 return;
2042
2043 case DD_STATUS_STS_BS:
2044 /* Interrupt only fires on EOT - This shouldn't happen! */
2045 ep->req_pending = 0;
2046 ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n",
2047 status);
2048 done(ep, req, -ECONNABORTED);
2049 return;
2050
2051 case DD_STATUS_STS_NC:
2052 case DD_STATUS_STS_DUR:
2053 /* Really just a short packet, not an underrun */
2054 /* This is a good status and what we expect */
2055 break;
2056
2057 default:
2058 /* Data overrun, system error, or unknown */
2059 ep->req_pending = 0;
2060 ep_err(ep, "DMA critical EP error: System error (0x%x)!\n",
2061 status);
2062 done(ep, req, -ECONNABORTED);
2063 return;
2064 }
2065
2066 /* ISO endpoints are handled differently */
2067 if (ep->eptype == EP_ISO_TYPE) {
2068 if (ep->is_in)
2069 req->req.actual = req->req.length;
2070 else
2071 req->req.actual = dd->iso_status[0] & 0xFFFF;
2072 } else
2073 req->req.actual += DD_STATUS_CURDMACNT(status);
2074
2075 /* Send a ZLP if necessary. This will be done for non-int
2076 * packets which have a size that is a divisor of MAXP */
2077 if (req->send_zlp) {
2078 /*
2079 * If at least 1 buffer is available, send the ZLP now.
2080 * Otherwise, the ZLP send needs to be deferred until a
2081 * buffer is available.
2082 */
2083 if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) {
2084 udc_clearep_getsts(udc, ep->hwep_num);
2085 uda_enable_hwepint(udc, ep->hwep_num);
2086 udc_clearep_getsts(udc, ep->hwep_num);
2087
2088 /* Let the EP interrupt handle the ZLP */
2089 return;
2090 } else
2091 udc_send_in_zlp(udc, ep);
2092 }
2093
2094 /* Transfer request is complete */
2095 done(ep, req, 0);
2096
2097 /* Start another request if ready */
2098 udc_clearep_getsts(udc, ep->hwep_num);
2099 if (!list_empty((&ep->queue))) {
2100 if (ep->is_in)
2101 udc_ep_in_req_dma(udc, ep);
2102 else
2103 udc_ep_out_req_dma(udc, ep);
2104 } else
2105 ep->req_pending = 0;
2106
2107}
2108
2109/*
2110 *
2111 * Endpoint 0 functions
2112 *
2113 */
2114static void udc_handle_dev(struct lpc32xx_udc *udc)
2115{
2116 u32 tmp;
2117
2118 udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT);
2119 tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT);
2120
2121 if (tmp & DEV_RST)
2122 uda_usb_reset(udc);
2123 else if (tmp & DEV_CON_CH)
2124 uda_power_event(udc, (tmp & DEV_CON));
2125 else if (tmp & DEV_SUS_CH) {
2126 if (tmp & DEV_SUS) {
2127 if (udc->vbus == 0)
2128 stop_activity(udc);
2129 else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2130 udc->driver) {
2131 /* Power down transceiver */
2132 udc->poweron = 0;
2133 schedule_work(&udc->pullup_job);
2134 uda_resm_susp_event(udc, 1);
2135 }
2136 } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2137 udc->driver && udc->vbus) {
2138 uda_resm_susp_event(udc, 0);
2139 /* Power up transceiver */
2140 udc->poweron = 1;
2141 schedule_work(&udc->pullup_job);
2142 }
2143 }
2144}
2145
2146static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex)
2147{
2148 struct lpc32xx_ep *ep;
2149 u32 ep0buff = 0, tmp;
2150
2151 switch (reqtype & USB_RECIP_MASK) {
2152 case USB_RECIP_INTERFACE:
2153 break; /* Not supported */
2154
2155 case USB_RECIP_DEVICE:
2156 ep0buff = udc->gadget.is_selfpowered;
2157 if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP))
2158 ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP);
2159 break;
2160
2161 case USB_RECIP_ENDPOINT:
2162 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2163 ep = &udc->ep[tmp];
2164 if ((tmp == 0) || (tmp >= NUM_ENDPOINTS))
2165 return -EOPNOTSUPP;
2166
2167 if (wIndex & USB_DIR_IN) {
2168 if (!ep->is_in)
2169 return -EOPNOTSUPP; /* Something's wrong */
2170 } else if (ep->is_in)
2171 return -EOPNOTSUPP; /* Not an IN endpoint */
2172
2173 /* Get status of the endpoint */
2174 udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num));
2175 tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num));
2176
2177 if (tmp & EP_SEL_ST)
2178 ep0buff = (1 << USB_ENDPOINT_HALT);
2179 else
2180 ep0buff = 0;
2181 break;
2182
2183 default:
2184 break;
2185 }
2186
2187 /* Return data */
2188 udc_write_hwep(udc, EP_IN, &ep0buff, 2);
2189
2190 return 0;
2191}
2192
2193static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
2194{
2195 struct lpc32xx_ep *ep, *ep0 = &udc->ep[0];
2196 struct usb_ctrlrequest ctrlpkt;
2197 int i, bytes;
2198 u16 wIndex, wValue, reqtype, req, tmp;
2199
2200 /* Nuke previous transfers */
2201 nuke(ep0, -EPROTO);
2202
2203 /* Get setup packet */
2204 bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8);
2205 if (bytes != 8) {
2206 ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n",
2207 bytes);
2208 return;
2209 }
2210
2211 /* Native endianness */
2212 wIndex = le16_to_cpu(ctrlpkt.wIndex);
2213 wValue = le16_to_cpu(ctrlpkt.wValue);
2214 reqtype = le16_to_cpu(ctrlpkt.bRequestType);
2215
2216 /* Set direction of EP0 */
2217 if (likely(reqtype & USB_DIR_IN))
2218 ep0->is_in = 1;
2219 else
2220 ep0->is_in = 0;
2221
2222 /* Handle SETUP packet */
2223 req = le16_to_cpu(ctrlpkt.bRequest);
2224 switch (req) {
2225 case USB_REQ_CLEAR_FEATURE:
2226 case USB_REQ_SET_FEATURE:
2227 switch (reqtype) {
2228 case (USB_TYPE_STANDARD | USB_RECIP_DEVICE):
2229 if (wValue != USB_DEVICE_REMOTE_WAKEUP)
2230 goto stall; /* Nothing else handled */
2231
2232 /* Tell board about event */
2233 if (req == USB_REQ_CLEAR_FEATURE)
2234 udc->dev_status &=
2235 ~(1 << USB_DEVICE_REMOTE_WAKEUP);
2236 else
2237 udc->dev_status |=
2238 (1 << USB_DEVICE_REMOTE_WAKEUP);
2239 uda_remwkp_cgh(udc);
2240 goto zlp_send;
2241
2242 case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
2243 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2244 if ((wValue != USB_ENDPOINT_HALT) ||
2245 (tmp >= NUM_ENDPOINTS))
2246 break;
2247
2248 /* Find hardware endpoint from logical endpoint */
2249 ep = &udc->ep[tmp];
2250 tmp = ep->hwep_num;
2251 if (tmp == 0)
2252 break;
2253
2254 if (req == USB_REQ_SET_FEATURE)
2255 udc_stall_hwep(udc, tmp);
2256 else if (!ep->wedge)
2257 udc_clrstall_hwep(udc, tmp);
2258
2259 goto zlp_send;
2260
2261 default:
2262 break;
2263 }
2264 break;
2265
2266 case USB_REQ_SET_ADDRESS:
2267 if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
2268 udc_set_address(udc, wValue);
2269 goto zlp_send;
2270 }
2271 break;
2272
2273 case USB_REQ_GET_STATUS:
2274 udc_get_status(udc, reqtype, wIndex);
2275 return;
2276
2277 default:
2278 break; /* Let GadgetFS handle the descriptor instead */
2279 }
2280
2281 if (likely(udc->driver)) {
2282 /* device-2-host (IN) or no data setup command, process
2283 * immediately */
2284 spin_unlock(&udc->lock);
2285 i = udc->driver->setup(&udc->gadget, &ctrlpkt);
2286
2287 spin_lock(&udc->lock);
2288 if (req == USB_REQ_SET_CONFIGURATION) {
2289 /* Configuration is set after endpoints are realized */
2290 if (wValue) {
2291 /* Set configuration */
2292 udc_set_device_configured(udc);
2293
2294 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2295 DAT_WR_BYTE(AP_CLK |
2296 INAK_BI | INAK_II));
2297 } else {
2298 /* Clear configuration */
2299 udc_set_device_unconfigured(udc);
2300
2301 /* Disable NAK interrupts */
2302 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2303 DAT_WR_BYTE(AP_CLK));
2304 }
2305 }
2306
2307 if (i < 0) {
2308 /* setup processing failed, force stall */
2309 dev_dbg(udc->dev,
2310 "req %02x.%02x protocol STALL; stat %d\n",
2311 reqtype, req, i);
2312 udc->ep0state = WAIT_FOR_SETUP;
2313 goto stall;
2314 }
2315 }
2316
2317 if (!ep0->is_in)
2318 udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */
2319
2320 return;
2321
2322stall:
2323 udc_stall_hwep(udc, EP_IN);
2324 return;
2325
2326zlp_send:
2327 udc_ep0_send_zlp(udc);
2328 return;
2329}
2330
2331/* IN endpoint 0 transfer */
2332static void udc_handle_ep0_in(struct lpc32xx_udc *udc)
2333{
2334 struct lpc32xx_ep *ep0 = &udc->ep[0];
2335 u32 epstatus;
2336
2337 /* Clear EP interrupt */
2338 epstatus = udc_clearep_getsts(udc, EP_IN);
2339
2340#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2341 ep0->totalints++;
2342#endif
2343
2344 /* Stalled? Clear stall and reset buffers */
2345 if (epstatus & EP_SEL_ST) {
2346 udc_clrstall_hwep(udc, EP_IN);
2347 nuke(ep0, -ECONNABORTED);
2348 udc->ep0state = WAIT_FOR_SETUP;
2349 return;
2350 }
2351
2352 /* Is a buffer available? */
2353 if (!(epstatus & EP_SEL_F)) {
2354 /* Handle based on current state */
2355 if (udc->ep0state == DATA_IN)
2356 udc_ep0_in_req(udc);
2357 else {
2358 /* Unknown state for EP0 oe end of DATA IN phase */
2359 nuke(ep0, -ECONNABORTED);
2360 udc->ep0state = WAIT_FOR_SETUP;
2361 }
2362 }
2363}
2364
2365/* OUT endpoint 0 transfer */
2366static void udc_handle_ep0_out(struct lpc32xx_udc *udc)
2367{
2368 struct lpc32xx_ep *ep0 = &udc->ep[0];
2369 u32 epstatus;
2370
2371 /* Clear EP interrupt */
2372 epstatus = udc_clearep_getsts(udc, EP_OUT);
2373
2374
2375#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2376 ep0->totalints++;
2377#endif
2378
2379 /* Stalled? */
2380 if (epstatus & EP_SEL_ST) {
2381 udc_clrstall_hwep(udc, EP_OUT);
2382 nuke(ep0, -ECONNABORTED);
2383 udc->ep0state = WAIT_FOR_SETUP;
2384 return;
2385 }
2386
2387 /* A NAK may occur if a packet couldn't be received yet */
2388 if (epstatus & EP_SEL_EPN)
2389 return;
2390 /* Setup packet incoming? */
2391 if (epstatus & EP_SEL_STP) {
2392 nuke(ep0, 0);
2393 udc->ep0state = WAIT_FOR_SETUP;
2394 }
2395
2396 /* Data available? */
2397 if (epstatus & EP_SEL_F)
2398 /* Handle based on current state */
2399 switch (udc->ep0state) {
2400 case WAIT_FOR_SETUP:
2401 udc_handle_ep0_setup(udc);
2402 break;
2403
2404 case DATA_OUT:
2405 udc_ep0_out_req(udc);
2406 break;
2407
2408 default:
2409 /* Unknown state for EP0 */
2410 nuke(ep0, -ECONNABORTED);
2411 udc->ep0state = WAIT_FOR_SETUP;
2412 }
2413}
2414
2415/* Must be called without lock */
2416static int lpc32xx_get_frame(struct usb_gadget *gadget)
2417{
2418 int frame;
2419 unsigned long flags;
2420 struct lpc32xx_udc *udc = to_udc(gadget);
2421
2422 if (!udc->clocked)
2423 return -EINVAL;
2424
2425 spin_lock_irqsave(&udc->lock, flags);
2426
2427 frame = (int) udc_get_current_frame(udc);
2428
2429 spin_unlock_irqrestore(&udc->lock, flags);
2430
2431 return frame;
2432}
2433
2434static int lpc32xx_wakeup(struct usb_gadget *gadget)
2435{
2436 return -ENOTSUPP;
2437}
2438
2439static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on)
2440{
2441 gadget->is_selfpowered = (is_on != 0);
2442
2443 return 0;
2444}
2445
2446/*
2447 * vbus is here! turn everything on that's ready
2448 * Must be called without lock
2449 */
2450static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active)
2451{
2452 unsigned long flags;
2453 struct lpc32xx_udc *udc = to_udc(gadget);
2454
2455 spin_lock_irqsave(&udc->lock, flags);
2456
2457 /* Doesn't need lock */
2458 if (udc->driver) {
2459 udc_clk_set(udc, 1);
2460 udc_enable(udc);
2461 pullup(udc, is_active);
2462 } else {
2463 stop_activity(udc);
2464 pullup(udc, 0);
2465
2466 spin_unlock_irqrestore(&udc->lock, flags);
2467 /*
2468 * Wait for all the endpoints to disable,
2469 * before disabling clocks. Don't wait if
2470 * endpoints are not enabled.
2471 */
2472 if (atomic_read(&udc->enabled_ep_cnt))
2473 wait_event_interruptible(udc->ep_disable_wait_queue,
2474 (atomic_read(&udc->enabled_ep_cnt) == 0));
2475
2476 spin_lock_irqsave(&udc->lock, flags);
2477
2478 udc_clk_set(udc, 0);
2479 }
2480
2481 spin_unlock_irqrestore(&udc->lock, flags);
2482
2483 return 0;
2484}
2485
2486/* Can be called with or without lock */
2487static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on)
2488{
2489 struct lpc32xx_udc *udc = to_udc(gadget);
2490
2491 /* Doesn't need lock */
2492 pullup(udc, is_on);
2493
2494 return 0;
2495}
2496
2497static int lpc32xx_start(struct usb_gadget *, struct usb_gadget_driver *);
2498static int lpc32xx_stop(struct usb_gadget *);
2499
2500static const struct usb_gadget_ops lpc32xx_udc_ops = {
2501 .get_frame = lpc32xx_get_frame,
2502 .wakeup = lpc32xx_wakeup,
2503 .set_selfpowered = lpc32xx_set_selfpowered,
2504 .vbus_session = lpc32xx_vbus_session,
2505 .pullup = lpc32xx_pullup,
2506 .udc_start = lpc32xx_start,
2507 .udc_stop = lpc32xx_stop,
2508};
2509
2510static void nop_release(struct device *dev)
2511{
2512 /* nothing to free */
2513}
2514
2515static const struct lpc32xx_udc controller_template = {
2516 .gadget = {
2517 .ops = &lpc32xx_udc_ops,
2518 .name = driver_name,
2519 .dev = {
2520 .init_name = "gadget",
2521 .release = nop_release,
2522 }
2523 },
2524 .ep[0] = {
2525 .ep = {
2526 .name = "ep0",
2527 .ops = &lpc32xx_ep_ops,
2528 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
2529 USB_EP_CAPS_DIR_ALL),
2530 },
2531 .maxpacket = 64,
2532 .hwep_num_base = 0,
2533 .hwep_num = 0, /* Can be 0 or 1, has special handling */
2534 .lep = 0,
2535 .eptype = EP_CTL_TYPE,
2536 },
2537 .ep[1] = {
2538 .ep = {
2539 .name = "ep1-int",
2540 .ops = &lpc32xx_ep_ops,
2541 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2542 USB_EP_CAPS_DIR_ALL),
2543 },
2544 .maxpacket = 64,
2545 .hwep_num_base = 2,
2546 .hwep_num = 0, /* 2 or 3, will be set later */
2547 .lep = 1,
2548 .eptype = EP_INT_TYPE,
2549 },
2550 .ep[2] = {
2551 .ep = {
2552 .name = "ep2-bulk",
2553 .ops = &lpc32xx_ep_ops,
2554 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2555 USB_EP_CAPS_DIR_ALL),
2556 },
2557 .maxpacket = 64,
2558 .hwep_num_base = 4,
2559 .hwep_num = 0, /* 4 or 5, will be set later */
2560 .lep = 2,
2561 .eptype = EP_BLK_TYPE,
2562 },
2563 .ep[3] = {
2564 .ep = {
2565 .name = "ep3-iso",
2566 .ops = &lpc32xx_ep_ops,
2567 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2568 USB_EP_CAPS_DIR_ALL),
2569 },
2570 .maxpacket = 1023,
2571 .hwep_num_base = 6,
2572 .hwep_num = 0, /* 6 or 7, will be set later */
2573 .lep = 3,
2574 .eptype = EP_ISO_TYPE,
2575 },
2576 .ep[4] = {
2577 .ep = {
2578 .name = "ep4-int",
2579 .ops = &lpc32xx_ep_ops,
2580 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2581 USB_EP_CAPS_DIR_ALL),
2582 },
2583 .maxpacket = 64,
2584 .hwep_num_base = 8,
2585 .hwep_num = 0, /* 8 or 9, will be set later */
2586 .lep = 4,
2587 .eptype = EP_INT_TYPE,
2588 },
2589 .ep[5] = {
2590 .ep = {
2591 .name = "ep5-bulk",
2592 .ops = &lpc32xx_ep_ops,
2593 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2594 USB_EP_CAPS_DIR_ALL),
2595 },
2596 .maxpacket = 64,
2597 .hwep_num_base = 10,
2598 .hwep_num = 0, /* 10 or 11, will be set later */
2599 .lep = 5,
2600 .eptype = EP_BLK_TYPE,
2601 },
2602 .ep[6] = {
2603 .ep = {
2604 .name = "ep6-iso",
2605 .ops = &lpc32xx_ep_ops,
2606 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2607 USB_EP_CAPS_DIR_ALL),
2608 },
2609 .maxpacket = 1023,
2610 .hwep_num_base = 12,
2611 .hwep_num = 0, /* 12 or 13, will be set later */
2612 .lep = 6,
2613 .eptype = EP_ISO_TYPE,
2614 },
2615 .ep[7] = {
2616 .ep = {
2617 .name = "ep7-int",
2618 .ops = &lpc32xx_ep_ops,
2619 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2620 USB_EP_CAPS_DIR_ALL),
2621 },
2622 .maxpacket = 64,
2623 .hwep_num_base = 14,
2624 .hwep_num = 0,
2625 .lep = 7,
2626 .eptype = EP_INT_TYPE,
2627 },
2628 .ep[8] = {
2629 .ep = {
2630 .name = "ep8-bulk",
2631 .ops = &lpc32xx_ep_ops,
2632 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2633 USB_EP_CAPS_DIR_ALL),
2634 },
2635 .maxpacket = 64,
2636 .hwep_num_base = 16,
2637 .hwep_num = 0,
2638 .lep = 8,
2639 .eptype = EP_BLK_TYPE,
2640 },
2641 .ep[9] = {
2642 .ep = {
2643 .name = "ep9-iso",
2644 .ops = &lpc32xx_ep_ops,
2645 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2646 USB_EP_CAPS_DIR_ALL),
2647 },
2648 .maxpacket = 1023,
2649 .hwep_num_base = 18,
2650 .hwep_num = 0,
2651 .lep = 9,
2652 .eptype = EP_ISO_TYPE,
2653 },
2654 .ep[10] = {
2655 .ep = {
2656 .name = "ep10-int",
2657 .ops = &lpc32xx_ep_ops,
2658 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2659 USB_EP_CAPS_DIR_ALL),
2660 },
2661 .maxpacket = 64,
2662 .hwep_num_base = 20,
2663 .hwep_num = 0,
2664 .lep = 10,
2665 .eptype = EP_INT_TYPE,
2666 },
2667 .ep[11] = {
2668 .ep = {
2669 .name = "ep11-bulk",
2670 .ops = &lpc32xx_ep_ops,
2671 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2672 USB_EP_CAPS_DIR_ALL),
2673 },
2674 .maxpacket = 64,
2675 .hwep_num_base = 22,
2676 .hwep_num = 0,
2677 .lep = 11,
2678 .eptype = EP_BLK_TYPE,
2679 },
2680 .ep[12] = {
2681 .ep = {
2682 .name = "ep12-iso",
2683 .ops = &lpc32xx_ep_ops,
2684 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2685 USB_EP_CAPS_DIR_ALL),
2686 },
2687 .maxpacket = 1023,
2688 .hwep_num_base = 24,
2689 .hwep_num = 0,
2690 .lep = 12,
2691 .eptype = EP_ISO_TYPE,
2692 },
2693 .ep[13] = {
2694 .ep = {
2695 .name = "ep13-int",
2696 .ops = &lpc32xx_ep_ops,
2697 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2698 USB_EP_CAPS_DIR_ALL),
2699 },
2700 .maxpacket = 64,
2701 .hwep_num_base = 26,
2702 .hwep_num = 0,
2703 .lep = 13,
2704 .eptype = EP_INT_TYPE,
2705 },
2706 .ep[14] = {
2707 .ep = {
2708 .name = "ep14-bulk",
2709 .ops = &lpc32xx_ep_ops,
2710 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2711 USB_EP_CAPS_DIR_ALL),
2712 },
2713 .maxpacket = 64,
2714 .hwep_num_base = 28,
2715 .hwep_num = 0,
2716 .lep = 14,
2717 .eptype = EP_BLK_TYPE,
2718 },
2719 .ep[15] = {
2720 .ep = {
2721 .name = "ep15-bulk",
2722 .ops = &lpc32xx_ep_ops,
2723 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2724 USB_EP_CAPS_DIR_ALL),
2725 },
2726 .maxpacket = 1023,
2727 .hwep_num_base = 30,
2728 .hwep_num = 0,
2729 .lep = 15,
2730 .eptype = EP_BLK_TYPE,
2731 },
2732};
2733
2734/* ISO and status interrupts */
2735static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc)
2736{
2737 u32 tmp, devstat;
2738 struct lpc32xx_udc *udc = _udc;
2739
2740 spin_lock(&udc->lock);
2741
2742 /* Read the device status register */
2743 devstat = readl(USBD_DEVINTST(udc->udp_baseaddr));
2744
2745 devstat &= ~USBD_EP_FAST;
2746 writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr));
2747 devstat = devstat & udc->enabled_devints;
2748
2749 /* Device specific handling needed? */
2750 if (devstat & USBD_DEV_STAT)
2751 udc_handle_dev(udc);
2752
2753 /* Start of frame? (devstat & FRAME_INT):
2754 * The frame interrupt isn't really needed for ISO support,
2755 * as the driver will queue the necessary packets */
2756
2757 /* Error? */
2758 if (devstat & ERR_INT) {
2759 /* All types of errors, from cable removal during transfer to
2760 * misc protocol and bit errors. These are mostly for just info,
2761 * as the USB hardware will work around these. If these errors
2762 * happen alot, something is wrong. */
2763 udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT);
2764 tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT);
2765 dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp);
2766 }
2767
2768 spin_unlock(&udc->lock);
2769
2770 return IRQ_HANDLED;
2771}
2772
2773/* EP interrupts */
2774static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc)
2775{
2776 u32 tmp;
2777 struct lpc32xx_udc *udc = _udc;
2778
2779 spin_lock(&udc->lock);
2780
2781 /* Read the device status register */
2782 writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr));
2783
2784 /* Endpoints */
2785 tmp = readl(USBD_EPINTST(udc->udp_baseaddr));
2786
2787 /* Special handling for EP0 */
2788 if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2789 /* Handle EP0 IN */
2790 if (tmp & (EP_MASK_SEL(0, EP_IN)))
2791 udc_handle_ep0_in(udc);
2792
2793 /* Handle EP0 OUT */
2794 if (tmp & (EP_MASK_SEL(0, EP_OUT)))
2795 udc_handle_ep0_out(udc);
2796 }
2797
2798 /* All other EPs */
2799 if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2800 int i;
2801
2802 /* Handle other EP interrupts */
2803 for (i = 1; i < NUM_ENDPOINTS; i++) {
2804 if (tmp & (1 << udc->ep[i].hwep_num))
2805 udc_handle_eps(udc, &udc->ep[i]);
2806 }
2807 }
2808
2809 spin_unlock(&udc->lock);
2810
2811 return IRQ_HANDLED;
2812}
2813
2814static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc)
2815{
2816 struct lpc32xx_udc *udc = _udc;
2817
2818 int i;
2819 u32 tmp;
2820
2821 spin_lock(&udc->lock);
2822
2823 /* Handle EP DMA EOT interrupts */
2824 tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) |
2825 (readl(USBD_EPDMAST(udc->udp_baseaddr)) &
2826 readl(USBD_NDDRTINTST(udc->udp_baseaddr))) |
2827 readl(USBD_SYSERRTINTST(udc->udp_baseaddr));
2828 for (i = 1; i < NUM_ENDPOINTS; i++) {
2829 if (tmp & (1 << udc->ep[i].hwep_num))
2830 udc_handle_dma_ep(udc, &udc->ep[i]);
2831 }
2832
2833 spin_unlock(&udc->lock);
2834
2835 return IRQ_HANDLED;
2836}
2837
2838/*
2839 *
2840 * VBUS detection, pullup handler, and Gadget cable state notification
2841 *
2842 */
2843static void vbus_work(struct lpc32xx_udc *udc)
2844{
2845 u8 value;
2846
2847 if (udc->enabled != 0) {
2848 /* Discharge VBUS real quick */
2849 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2850 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
2851
2852 /* Give VBUS some time (100mS) to discharge */
2853 msleep(100);
2854
2855 /* Disable VBUS discharge resistor */
2856 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2857 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
2858 OTG1_VBUS_DISCHRG);
2859
2860 /* Clear interrupt */
2861 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2862 ISP1301_I2C_INTERRUPT_LATCH |
2863 ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2864
2865 /* Get the VBUS status from the transceiver */
2866 value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client,
2867 ISP1301_I2C_INTERRUPT_SOURCE);
2868
2869 /* VBUS on or off? */
2870 if (value & INT_SESS_VLD)
2871 udc->vbus = 1;
2872 else
2873 udc->vbus = 0;
2874
2875 /* VBUS changed? */
2876 if (udc->last_vbus != udc->vbus) {
2877 udc->last_vbus = udc->vbus;
2878 lpc32xx_vbus_session(&udc->gadget, udc->vbus);
2879 }
2880 }
2881}
2882
2883static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc)
2884{
2885 struct lpc32xx_udc *udc = _udc;
2886
2887 vbus_work(udc);
2888
2889 return IRQ_HANDLED;
2890}
2891
2892static int lpc32xx_start(struct usb_gadget *gadget,
2893 struct usb_gadget_driver *driver)
2894{
2895 struct lpc32xx_udc *udc = to_udc(gadget);
2896
2897 if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) {
2898 dev_err(udc->dev, "bad parameter.\n");
2899 return -EINVAL;
2900 }
2901
2902 if (udc->driver) {
2903 dev_err(udc->dev, "UDC already has a gadget driver\n");
2904 return -EBUSY;
2905 }
2906
2907 udc->driver = driver;
2908 udc->gadget.dev.of_node = udc->dev->of_node;
2909 udc->enabled = 1;
2910 udc->gadget.is_selfpowered = 1;
2911 udc->vbus = 0;
2912
2913 /* Force VBUS process once to check for cable insertion */
2914 udc->last_vbus = udc->vbus = 0;
2915 vbus_work(udc);
2916
2917 /* enable interrupts */
2918 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2919 ISP1301_I2C_INTERRUPT_FALLING, INT_SESS_VLD | INT_VBUS_VLD);
2920 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2921 ISP1301_I2C_INTERRUPT_RISING, INT_SESS_VLD | INT_VBUS_VLD);
2922
2923 return 0;
2924}
2925
2926static int lpc32xx_stop(struct usb_gadget *gadget)
2927{
2928 struct lpc32xx_udc *udc = to_udc(gadget);
2929
2930 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2931 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2932 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2933 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2934
2935 if (udc->clocked) {
2936 spin_lock(&udc->lock);
2937 stop_activity(udc);
2938 spin_unlock(&udc->lock);
2939
2940 /*
2941 * Wait for all the endpoints to disable,
2942 * before disabling clocks. Don't wait if
2943 * endpoints are not enabled.
2944 */
2945 if (atomic_read(&udc->enabled_ep_cnt))
2946 wait_event_interruptible(udc->ep_disable_wait_queue,
2947 (atomic_read(&udc->enabled_ep_cnt) == 0));
2948
2949 spin_lock(&udc->lock);
2950 udc_clk_set(udc, 0);
2951 spin_unlock(&udc->lock);
2952 }
2953
2954 udc->enabled = 0;
2955 udc->driver = NULL;
2956
2957 return 0;
2958}
2959
2960static void lpc32xx_udc_shutdown(struct platform_device *dev)
2961{
2962 /* Force disconnect on reboot */
2963 struct lpc32xx_udc *udc = platform_get_drvdata(dev);
2964
2965 pullup(udc, 0);
2966}
2967
2968/*
2969 * Callbacks to be overridden by options passed via OF (TODO)
2970 */
2971
2972static void lpc32xx_usbd_conn_chg(int conn)
2973{
2974 /* Do nothing, it might be nice to enable an LED
2975 * based on conn state being !0 */
2976}
2977
2978static void lpc32xx_usbd_susp_chg(int susp)
2979{
2980 /* Device suspend if susp != 0 */
2981}
2982
2983static void lpc32xx_rmwkup_chg(int remote_wakup_enable)
2984{
2985 /* Enable or disable USB remote wakeup */
2986}
2987
2988struct lpc32xx_usbd_cfg lpc32xx_usbddata = {
2989 .vbus_drv_pol = 0,
2990 .conn_chgb = &lpc32xx_usbd_conn_chg,
2991 .susp_chgb = &lpc32xx_usbd_susp_chg,
2992 .rmwk_chgb = &lpc32xx_rmwkup_chg,
2993};
2994
2995
2996static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F;
2997
2998static int lpc32xx_udc_probe(struct platform_device *pdev)
2999{
3000 struct device *dev = &pdev->dev;
3001 struct lpc32xx_udc *udc;
3002 int retval, i;
3003 struct resource *res;
3004 dma_addr_t dma_handle;
3005 struct device_node *isp1301_node;
3006
3007 udc = devm_kmemdup(dev, &controller_template, sizeof(*udc), GFP_KERNEL);
3008 if (!udc)
3009 return -ENOMEM;
3010
3011 for (i = 0; i <= 15; i++)
3012 udc->ep[i].udc = udc;
3013 udc->gadget.ep0 = &udc->ep[0].ep;
3014
3015 /* init software state */
3016 udc->gadget.dev.parent = dev;
3017 udc->pdev = pdev;
3018 udc->dev = &pdev->dev;
3019 udc->enabled = 0;
3020
3021 if (pdev->dev.of_node) {
3022 isp1301_node = of_parse_phandle(pdev->dev.of_node,
3023 "transceiver", 0);
3024 } else {
3025 isp1301_node = NULL;
3026 }
3027
3028 udc->isp1301_i2c_client = isp1301_get_client(isp1301_node);
3029 if (!udc->isp1301_i2c_client) {
3030 return -EPROBE_DEFER;
3031 }
3032
3033 dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n",
3034 udc->isp1301_i2c_client->addr);
3035
3036 pdev->dev.dma_mask = &lpc32xx_usbd_dmamask;
3037 retval = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
3038 if (retval)
3039 return retval;
3040
3041 udc->board = &lpc32xx_usbddata;
3042
3043 /*
3044 * Resources are mapped as follows:
3045 * IORESOURCE_MEM, base address and size of USB space
3046 * IORESOURCE_IRQ, USB device low priority interrupt number
3047 * IORESOURCE_IRQ, USB device high priority interrupt number
3048 * IORESOURCE_IRQ, USB device interrupt number
3049 * IORESOURCE_IRQ, USB transceiver interrupt number
3050 */
3051 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3052 if (!res)
3053 return -ENXIO;
3054
3055 spin_lock_init(&udc->lock);
3056
3057 /* Get IRQs */
3058 for (i = 0; i < 4; i++) {
3059 udc->udp_irq[i] = platform_get_irq(pdev, i);
3060 if (udc->udp_irq[i] < 0)
3061 return udc->udp_irq[i];
3062 }
3063
3064 udc->udp_baseaddr = devm_ioremap_resource(dev, res);
3065 if (IS_ERR(udc->udp_baseaddr)) {
3066 dev_err(udc->dev, "IO map failure\n");
3067 return PTR_ERR(udc->udp_baseaddr);
3068 }
3069
3070 /* Get USB device clock */
3071 udc->usb_slv_clk = devm_clk_get(&pdev->dev, NULL);
3072 if (IS_ERR(udc->usb_slv_clk)) {
3073 dev_err(udc->dev, "failed to acquire USB device clock\n");
3074 return PTR_ERR(udc->usb_slv_clk);
3075 }
3076
3077 /* Enable USB device clock */
3078 retval = clk_prepare_enable(udc->usb_slv_clk);
3079 if (retval < 0) {
3080 dev_err(udc->dev, "failed to start USB device clock\n");
3081 return retval;
3082 }
3083
3084 /* Setup deferred workqueue data */
3085 udc->poweron = udc->pullup = 0;
3086 INIT_WORK(&udc->pullup_job, pullup_work);
3087#ifdef CONFIG_PM
3088 INIT_WORK(&udc->power_job, power_work);
3089#endif
3090
3091 /* All clocks are now on */
3092 udc->clocked = 1;
3093
3094 isp1301_udc_configure(udc);
3095 /* Allocate memory for the UDCA */
3096 udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3097 &dma_handle,
3098 (GFP_KERNEL | GFP_DMA));
3099 if (!udc->udca_v_base) {
3100 dev_err(udc->dev, "error getting UDCA region\n");
3101 retval = -ENOMEM;
3102 goto i2c_fail;
3103 }
3104 udc->udca_p_base = dma_handle;
3105 dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n",
3106 UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base);
3107
3108 /* Setup the DD DMA memory pool */
3109 udc->dd_cache = dma_pool_create("udc_dd", udc->dev,
3110 sizeof(struct lpc32xx_usbd_dd_gad),
3111 sizeof(u32), 0);
3112 if (!udc->dd_cache) {
3113 dev_err(udc->dev, "error getting DD DMA region\n");
3114 retval = -ENOMEM;
3115 goto dma_alloc_fail;
3116 }
3117
3118 /* Clear USB peripheral and initialize gadget endpoints */
3119 udc_disable(udc);
3120 udc_reinit(udc);
3121
3122 /* Request IRQs - low and high priority USB device IRQs are routed to
3123 * the same handler, while the DMA interrupt is routed elsewhere */
3124 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_LP],
3125 lpc32xx_usb_lp_irq, 0, "udc_lp", udc);
3126 if (retval < 0) {
3127 dev_err(udc->dev, "LP request irq %d failed\n",
3128 udc->udp_irq[IRQ_USB_LP]);
3129 goto irq_req_fail;
3130 }
3131 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_HP],
3132 lpc32xx_usb_hp_irq, 0, "udc_hp", udc);
3133 if (retval < 0) {
3134 dev_err(udc->dev, "HP request irq %d failed\n",
3135 udc->udp_irq[IRQ_USB_HP]);
3136 goto irq_req_fail;
3137 }
3138
3139 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_DEVDMA],
3140 lpc32xx_usb_devdma_irq, 0, "udc_dma", udc);
3141 if (retval < 0) {
3142 dev_err(udc->dev, "DEV request irq %d failed\n",
3143 udc->udp_irq[IRQ_USB_DEVDMA]);
3144 goto irq_req_fail;
3145 }
3146
3147 /* The transceiver interrupt is used for VBUS detection and will
3148 kick off the VBUS handler function */
3149 retval = devm_request_threaded_irq(dev, udc->udp_irq[IRQ_USB_ATX], NULL,
3150 lpc32xx_usb_vbus_irq, IRQF_ONESHOT,
3151 "udc_otg", udc);
3152 if (retval < 0) {
3153 dev_err(udc->dev, "VBUS request irq %d failed\n",
3154 udc->udp_irq[IRQ_USB_ATX]);
3155 goto irq_req_fail;
3156 }
3157
3158 /* Initialize wait queue */
3159 init_waitqueue_head(&udc->ep_disable_wait_queue);
3160 atomic_set(&udc->enabled_ep_cnt, 0);
3161
3162 retval = usb_add_gadget_udc(dev, &udc->gadget);
3163 if (retval < 0)
3164 goto add_gadget_fail;
3165
3166 dev_set_drvdata(dev, udc);
3167 device_init_wakeup(dev, 1);
3168 create_debug_file(udc);
3169
3170 /* Disable clocks for now */
3171 udc_clk_set(udc, 0);
3172
3173 dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION);
3174 return 0;
3175
3176add_gadget_fail:
3177irq_req_fail:
3178 dma_pool_destroy(udc->dd_cache);
3179dma_alloc_fail:
3180 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3181 udc->udca_v_base, udc->udca_p_base);
3182i2c_fail:
3183 clk_disable_unprepare(udc->usb_slv_clk);
3184 dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval);
3185
3186 return retval;
3187}
3188
3189static int lpc32xx_udc_remove(struct platform_device *pdev)
3190{
3191 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3192
3193 usb_del_gadget_udc(&udc->gadget);
3194 if (udc->driver)
3195 return -EBUSY;
3196
3197 udc_clk_set(udc, 1);
3198 udc_disable(udc);
3199 pullup(udc, 0);
3200
3201 device_init_wakeup(&pdev->dev, 0);
3202 remove_debug_file(udc);
3203
3204 dma_pool_destroy(udc->dd_cache);
3205 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3206 udc->udca_v_base, udc->udca_p_base);
3207
3208 clk_disable_unprepare(udc->usb_slv_clk);
3209
3210 return 0;
3211}
3212
3213#ifdef CONFIG_PM
3214static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
3215{
3216 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3217
3218 if (udc->clocked) {
3219 /* Power down ISP */
3220 udc->poweron = 0;
3221 isp1301_set_powerstate(udc, 0);
3222
3223 /* Disable clocking */
3224 udc_clk_set(udc, 0);
3225
3226 /* Keep clock flag on, so we know to re-enable clocks
3227 on resume */
3228 udc->clocked = 1;
3229
3230 /* Kill global USB clock */
3231 clk_disable_unprepare(udc->usb_slv_clk);
3232 }
3233
3234 return 0;
3235}
3236
3237static int lpc32xx_udc_resume(struct platform_device *pdev)
3238{
3239 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3240
3241 if (udc->clocked) {
3242 /* Enable global USB clock */
3243 clk_prepare_enable(udc->usb_slv_clk);
3244
3245 /* Enable clocking */
3246 udc_clk_set(udc, 1);
3247
3248 /* ISP back to normal power mode */
3249 udc->poweron = 1;
3250 isp1301_set_powerstate(udc, 1);
3251 }
3252
3253 return 0;
3254}
3255#else
3256#define lpc32xx_udc_suspend NULL
3257#define lpc32xx_udc_resume NULL
3258#endif
3259
3260#ifdef CONFIG_OF
3261static const struct of_device_id lpc32xx_udc_of_match[] = {
3262 { .compatible = "nxp,lpc3220-udc", },
3263 { },
3264};
3265MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match);
3266#endif
3267
3268static struct platform_driver lpc32xx_udc_driver = {
3269 .remove = lpc32xx_udc_remove,
3270 .shutdown = lpc32xx_udc_shutdown,
3271 .suspend = lpc32xx_udc_suspend,
3272 .resume = lpc32xx_udc_resume,
3273 .driver = {
3274 .name = (char *) driver_name,
3275 .of_match_table = of_match_ptr(lpc32xx_udc_of_match),
3276 },
3277};
3278
3279module_platform_driver_probe(lpc32xx_udc_driver, lpc32xx_udc_probe);
3280
3281MODULE_DESCRIPTION("LPC32XX udc driver");
3282MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
3283MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
3284MODULE_LICENSE("GPL");
3285MODULE_ALIAS("platform:lpc32xx_udc");