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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * MPC52xx PSC in SPI mode driver.
4 *
5 * Maintainer: Dragos Carp
6 *
7 * Copyright (C) 2006 TOPTICA Photonics AG.
8 */
9
10#include <linux/module.h>
11#include <linux/types.h>
12#include <linux/errno.h>
13#include <linux/interrupt.h>
14#include <linux/platform_device.h>
15#include <linux/property.h>
16#include <linux/workqueue.h>
17#include <linux/completion.h>
18#include <linux/io.h>
19#include <linux/delay.h>
20#include <linux/spi/spi.h>
21#include <linux/slab.h>
22
23#include <asm/mpc52xx.h>
24#include <asm/mpc52xx_psc.h>
25
26#define MCLK 20000000 /* PSC port MClk in hz */
27
28struct mpc52xx_psc_spi {
29 /* driver internal data */
30 struct mpc52xx_psc __iomem *psc;
31 struct mpc52xx_psc_fifo __iomem *fifo;
32 int irq;
33 u8 bits_per_word;
34
35 struct completion done;
36};
37
38/* controller state */
39struct mpc52xx_psc_spi_cs {
40 int bits_per_word;
41 int speed_hz;
42};
43
44/* set clock freq, clock ramp, bits per work
45 * if t is NULL then reset the values to the default values
46 */
47static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi,
48 struct spi_transfer *t)
49{
50 struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
51
52 cs->speed_hz = (t && t->speed_hz)
53 ? t->speed_hz : spi->max_speed_hz;
54 cs->bits_per_word = (t && t->bits_per_word)
55 ? t->bits_per_word : spi->bits_per_word;
56 cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
57 return 0;
58}
59
60static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
61{
62 struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
63 struct mpc52xx_psc_spi *mps = spi_controller_get_devdata(spi->controller);
64 struct mpc52xx_psc __iomem *psc = mps->psc;
65 u32 sicr;
66 u16 ccr;
67
68 sicr = in_be32(&psc->sicr);
69
70 /* Set clock phase and polarity */
71 if (spi->mode & SPI_CPHA)
72 sicr |= 0x00001000;
73 else
74 sicr &= ~0x00001000;
75 if (spi->mode & SPI_CPOL)
76 sicr |= 0x00002000;
77 else
78 sicr &= ~0x00002000;
79
80 if (spi->mode & SPI_LSB_FIRST)
81 sicr |= 0x10000000;
82 else
83 sicr &= ~0x10000000;
84 out_be32(&psc->sicr, sicr);
85
86 /* Set clock frequency and bits per word
87 * Because psc->ccr is defined as 16bit register instead of 32bit
88 * just set the lower byte of BitClkDiv
89 */
90 ccr = in_be16((u16 __iomem *)&psc->ccr);
91 ccr &= 0xFF00;
92 if (cs->speed_hz)
93 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
94 else /* by default SPI Clk 1MHz */
95 ccr |= (MCLK / 1000000 - 1) & 0xFF;
96 out_be16((u16 __iomem *)&psc->ccr, ccr);
97 mps->bits_per_word = cs->bits_per_word;
98}
99
100#define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1)
101/* wake up when 80% fifo full */
102#define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100)
103
104static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi,
105 struct spi_transfer *t)
106{
107 struct mpc52xx_psc_spi *mps = spi_controller_get_devdata(spi->controller);
108 struct mpc52xx_psc __iomem *psc = mps->psc;
109 struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
110 unsigned rb = 0; /* number of bytes receieved */
111 unsigned sb = 0; /* number of bytes sent */
112 unsigned char *rx_buf = (unsigned char *)t->rx_buf;
113 unsigned char *tx_buf = (unsigned char *)t->tx_buf;
114 unsigned rfalarm;
115 unsigned send_at_once = MPC52xx_PSC_BUFSIZE;
116 unsigned recv_at_once;
117 int last_block = 0;
118
119 if (!t->tx_buf && !t->rx_buf && t->len)
120 return -EINVAL;
121
122 /* enable transmiter/receiver */
123 out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
124 while (rb < t->len) {
125 if (t->len - rb > MPC52xx_PSC_BUFSIZE) {
126 rfalarm = MPC52xx_PSC_RFALARM;
127 last_block = 0;
128 } else {
129 send_at_once = t->len - sb;
130 rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb);
131 last_block = 1;
132 }
133
134 dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once);
135 for (; send_at_once; sb++, send_at_once--) {
136 /* set EOF flag before the last word is sent */
137 if (send_at_once == 1 && last_block)
138 out_8(&psc->ircr2, 0x01);
139
140 if (tx_buf)
141 out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);
142 else
143 out_8(&psc->mpc52xx_psc_buffer_8, 0);
144 }
145
146
147 /* enable interrupts and wait for wake up
148 * if just one byte is expected the Rx FIFO genererates no
149 * FFULL interrupt, so activate the RxRDY interrupt
150 */
151 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
152 if (t->len - rb == 1) {
153 out_8(&psc->mode, 0);
154 } else {
155 out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
156 out_be16(&fifo->rfalarm, rfalarm);
157 }
158 out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);
159 wait_for_completion(&mps->done);
160 recv_at_once = in_be16(&fifo->rfnum);
161 dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once);
162
163 send_at_once = recv_at_once;
164 if (rx_buf) {
165 for (; recv_at_once; rb++, recv_at_once--)
166 rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);
167 } else {
168 for (; recv_at_once; rb++, recv_at_once--)
169 in_8(&psc->mpc52xx_psc_buffer_8);
170 }
171 }
172 /* disable transmiter/receiver */
173 out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
174
175 return 0;
176}
177
178static int mpc52xx_psc_spi_transfer_one_message(struct spi_controller *ctlr,
179 struct spi_message *m)
180{
181 struct spi_device *spi;
182 struct spi_transfer *t = NULL;
183 unsigned cs_change;
184 int status;
185
186 spi = m->spi;
187 cs_change = 1;
188 status = 0;
189 list_for_each_entry (t, &m->transfers, transfer_list) {
190 if (t->bits_per_word || t->speed_hz) {
191 status = mpc52xx_psc_spi_transfer_setup(spi, t);
192 if (status < 0)
193 break;
194 }
195
196 if (cs_change)
197 mpc52xx_psc_spi_activate_cs(spi);
198 cs_change = t->cs_change;
199
200 status = mpc52xx_psc_spi_transfer_rxtx(spi, t);
201 if (status)
202 break;
203 m->actual_length += t->len;
204
205 spi_transfer_delay_exec(t);
206 }
207
208 m->status = status;
209
210 mpc52xx_psc_spi_transfer_setup(spi, NULL);
211
212 spi_finalize_current_message(ctlr);
213
214 return 0;
215}
216
217static int mpc52xx_psc_spi_setup(struct spi_device *spi)
218{
219 struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
220
221 if (spi->bits_per_word%8)
222 return -EINVAL;
223
224 if (!cs) {
225 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
226 if (!cs)
227 return -ENOMEM;
228 spi->controller_state = cs;
229 }
230
231 cs->bits_per_word = spi->bits_per_word;
232 cs->speed_hz = spi->max_speed_hz;
233
234 return 0;
235}
236
237static void mpc52xx_psc_spi_cleanup(struct spi_device *spi)
238{
239 kfree(spi->controller_state);
240}
241
242static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
243{
244 struct mpc52xx_psc __iomem *psc = mps->psc;
245 struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
246 u32 mclken_div;
247 int ret;
248
249 /* default sysclk is 512MHz */
250 mclken_div = 512000000 / MCLK;
251 ret = mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
252 if (ret)
253 return ret;
254
255 /* Reset the PSC into a known state */
256 out_8(&psc->command, MPC52xx_PSC_RST_RX);
257 out_8(&psc->command, MPC52xx_PSC_RST_TX);
258 out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
259
260 /* Disable interrupts, interrupts are based on alarm level */
261 out_be16(&psc->mpc52xx_psc_imr, 0);
262 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
263 out_8(&fifo->rfcntl, 0);
264 out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
265
266 /* Configure 8bit codec mode as a SPI host and use EOF flags */
267 /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
268 out_be32(&psc->sicr, 0x0180C800);
269 out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
270
271 /* Set 2ms DTL delay */
272 out_8(&psc->ctur, 0x00);
273 out_8(&psc->ctlr, 0x84);
274
275 mps->bits_per_word = 8;
276
277 return 0;
278}
279
280static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id)
281{
282 struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id;
283 struct mpc52xx_psc __iomem *psc = mps->psc;
284
285 /* disable interrupt and wake up the work queue */
286 if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {
287 out_be16(&psc->mpc52xx_psc_imr, 0);
288 complete(&mps->done);
289 return IRQ_HANDLED;
290 }
291 return IRQ_NONE;
292}
293
294static int mpc52xx_psc_spi_of_probe(struct platform_device *pdev)
295{
296 struct device *dev = &pdev->dev;
297 struct mpc52xx_psc_spi *mps;
298 struct spi_controller *host;
299 u32 bus_num;
300 int ret;
301
302 host = devm_spi_alloc_host(dev, sizeof(*mps));
303 if (host == NULL)
304 return -ENOMEM;
305
306 dev_set_drvdata(dev, host);
307 mps = spi_controller_get_devdata(host);
308
309 /* the spi->mode bits understood by this driver: */
310 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
311
312 ret = device_property_read_u32(dev, "cell-index", &bus_num);
313 if (ret || bus_num > 5)
314 return dev_err_probe(dev, ret ? : -EINVAL, "Invalid cell-index property\n");
315 host->bus_num = bus_num + 1;
316
317 host->num_chipselect = 255;
318 host->setup = mpc52xx_psc_spi_setup;
319 host->transfer_one_message = mpc52xx_psc_spi_transfer_one_message;
320 host->cleanup = mpc52xx_psc_spi_cleanup;
321
322 device_set_node(&host->dev, dev_fwnode(dev));
323
324 mps->psc = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
325 if (IS_ERR(mps->psc))
326 return dev_err_probe(dev, PTR_ERR(mps->psc), "could not ioremap I/O port range\n");
327
328 /* On the 5200, fifo regs are immediately ajacent to the psc regs */
329 mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);
330
331 mps->irq = platform_get_irq(pdev, 0);
332 if (mps->irq < 0)
333 return mps->irq;
334
335 ret = devm_request_irq(dev, mps->irq, mpc52xx_psc_spi_isr, 0,
336 "mpc52xx-psc-spi", mps);
337 if (ret)
338 return ret;
339
340 ret = mpc52xx_psc_spi_port_config(host->bus_num, mps);
341 if (ret < 0)
342 return dev_err_probe(dev, ret, "can't configure PSC! Is it capable of SPI?\n");
343
344 init_completion(&mps->done);
345
346 return devm_spi_register_controller(dev, host);
347}
348
349static const struct of_device_id mpc52xx_psc_spi_of_match[] = {
350 { .compatible = "fsl,mpc5200-psc-spi", },
351 { .compatible = "mpc5200-psc-spi", }, /* old */
352 {}
353};
354
355MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match);
356
357static struct platform_driver mpc52xx_psc_spi_of_driver = {
358 .probe = mpc52xx_psc_spi_of_probe,
359 .driver = {
360 .name = "mpc52xx-psc-spi",
361 .of_match_table = mpc52xx_psc_spi_of_match,
362 },
363};
364module_platform_driver(mpc52xx_psc_spi_of_driver);
365
366MODULE_AUTHOR("Dragos Carp");
367MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");
368MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * MPC52xx PSC in SPI mode driver.
4 *
5 * Maintainer: Dragos Carp
6 *
7 * Copyright (C) 2006 TOPTICA Photonics AG.
8 */
9
10#include <linux/module.h>
11#include <linux/types.h>
12#include <linux/errno.h>
13#include <linux/interrupt.h>
14#include <linux/of_address.h>
15#include <linux/of_platform.h>
16#include <linux/workqueue.h>
17#include <linux/completion.h>
18#include <linux/io.h>
19#include <linux/delay.h>
20#include <linux/spi/spi.h>
21#include <linux/fsl_devices.h>
22#include <linux/slab.h>
23
24#include <asm/mpc52xx.h>
25#include <asm/mpc52xx_psc.h>
26
27#define MCLK 20000000 /* PSC port MClk in hz */
28
29struct mpc52xx_psc_spi {
30 /* fsl_spi_platform data */
31 void (*cs_control)(struct spi_device *spi, bool on);
32 u32 sysclk;
33
34 /* driver internal data */
35 struct mpc52xx_psc __iomem *psc;
36 struct mpc52xx_psc_fifo __iomem *fifo;
37 unsigned int irq;
38 u8 bits_per_word;
39 u8 busy;
40
41 struct work_struct work;
42
43 struct list_head queue;
44 spinlock_t lock;
45
46 struct completion done;
47};
48
49/* controller state */
50struct mpc52xx_psc_spi_cs {
51 int bits_per_word;
52 int speed_hz;
53};
54
55/* set clock freq, clock ramp, bits per work
56 * if t is NULL then reset the values to the default values
57 */
58static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi,
59 struct spi_transfer *t)
60{
61 struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
62
63 cs->speed_hz = (t && t->speed_hz)
64 ? t->speed_hz : spi->max_speed_hz;
65 cs->bits_per_word = (t && t->bits_per_word)
66 ? t->bits_per_word : spi->bits_per_word;
67 cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
68 return 0;
69}
70
71static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
72{
73 struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
74 struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
75 struct mpc52xx_psc __iomem *psc = mps->psc;
76 u32 sicr;
77 u16 ccr;
78
79 sicr = in_be32(&psc->sicr);
80
81 /* Set clock phase and polarity */
82 if (spi->mode & SPI_CPHA)
83 sicr |= 0x00001000;
84 else
85 sicr &= ~0x00001000;
86 if (spi->mode & SPI_CPOL)
87 sicr |= 0x00002000;
88 else
89 sicr &= ~0x00002000;
90
91 if (spi->mode & SPI_LSB_FIRST)
92 sicr |= 0x10000000;
93 else
94 sicr &= ~0x10000000;
95 out_be32(&psc->sicr, sicr);
96
97 /* Set clock frequency and bits per word
98 * Because psc->ccr is defined as 16bit register instead of 32bit
99 * just set the lower byte of BitClkDiv
100 */
101 ccr = in_be16((u16 __iomem *)&psc->ccr);
102 ccr &= 0xFF00;
103 if (cs->speed_hz)
104 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
105 else /* by default SPI Clk 1MHz */
106 ccr |= (MCLK / 1000000 - 1) & 0xFF;
107 out_be16((u16 __iomem *)&psc->ccr, ccr);
108 mps->bits_per_word = cs->bits_per_word;
109
110 if (mps->cs_control)
111 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
112}
113
114static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi)
115{
116 struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
117
118 if (mps->cs_control)
119 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
120}
121
122#define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1)
123/* wake up when 80% fifo full */
124#define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100)
125
126static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi,
127 struct spi_transfer *t)
128{
129 struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
130 struct mpc52xx_psc __iomem *psc = mps->psc;
131 struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
132 unsigned rb = 0; /* number of bytes receieved */
133 unsigned sb = 0; /* number of bytes sent */
134 unsigned char *rx_buf = (unsigned char *)t->rx_buf;
135 unsigned char *tx_buf = (unsigned char *)t->tx_buf;
136 unsigned rfalarm;
137 unsigned send_at_once = MPC52xx_PSC_BUFSIZE;
138 unsigned recv_at_once;
139 int last_block = 0;
140
141 if (!t->tx_buf && !t->rx_buf && t->len)
142 return -EINVAL;
143
144 /* enable transmiter/receiver */
145 out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
146 while (rb < t->len) {
147 if (t->len - rb > MPC52xx_PSC_BUFSIZE) {
148 rfalarm = MPC52xx_PSC_RFALARM;
149 last_block = 0;
150 } else {
151 send_at_once = t->len - sb;
152 rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb);
153 last_block = 1;
154 }
155
156 dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once);
157 for (; send_at_once; sb++, send_at_once--) {
158 /* set EOF flag before the last word is sent */
159 if (send_at_once == 1 && last_block)
160 out_8(&psc->ircr2, 0x01);
161
162 if (tx_buf)
163 out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);
164 else
165 out_8(&psc->mpc52xx_psc_buffer_8, 0);
166 }
167
168
169 /* enable interrupts and wait for wake up
170 * if just one byte is expected the Rx FIFO genererates no
171 * FFULL interrupt, so activate the RxRDY interrupt
172 */
173 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
174 if (t->len - rb == 1) {
175 out_8(&psc->mode, 0);
176 } else {
177 out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
178 out_be16(&fifo->rfalarm, rfalarm);
179 }
180 out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);
181 wait_for_completion(&mps->done);
182 recv_at_once = in_be16(&fifo->rfnum);
183 dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once);
184
185 send_at_once = recv_at_once;
186 if (rx_buf) {
187 for (; recv_at_once; rb++, recv_at_once--)
188 rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);
189 } else {
190 for (; recv_at_once; rb++, recv_at_once--)
191 in_8(&psc->mpc52xx_psc_buffer_8);
192 }
193 }
194 /* disable transmiter/receiver */
195 out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
196
197 return 0;
198}
199
200static void mpc52xx_psc_spi_work(struct work_struct *work)
201{
202 struct mpc52xx_psc_spi *mps =
203 container_of(work, struct mpc52xx_psc_spi, work);
204
205 spin_lock_irq(&mps->lock);
206 mps->busy = 1;
207 while (!list_empty(&mps->queue)) {
208 struct spi_message *m;
209 struct spi_device *spi;
210 struct spi_transfer *t = NULL;
211 unsigned cs_change;
212 int status;
213
214 m = container_of(mps->queue.next, struct spi_message, queue);
215 list_del_init(&m->queue);
216 spin_unlock_irq(&mps->lock);
217
218 spi = m->spi;
219 cs_change = 1;
220 status = 0;
221 list_for_each_entry (t, &m->transfers, transfer_list) {
222 if (t->bits_per_word || t->speed_hz) {
223 status = mpc52xx_psc_spi_transfer_setup(spi, t);
224 if (status < 0)
225 break;
226 }
227
228 if (cs_change)
229 mpc52xx_psc_spi_activate_cs(spi);
230 cs_change = t->cs_change;
231
232 status = mpc52xx_psc_spi_transfer_rxtx(spi, t);
233 if (status)
234 break;
235 m->actual_length += t->len;
236
237 if (t->delay_usecs)
238 udelay(t->delay_usecs);
239
240 if (cs_change)
241 mpc52xx_psc_spi_deactivate_cs(spi);
242 }
243
244 m->status = status;
245 if (m->complete)
246 m->complete(m->context);
247
248 if (status || !cs_change)
249 mpc52xx_psc_spi_deactivate_cs(spi);
250
251 mpc52xx_psc_spi_transfer_setup(spi, NULL);
252
253 spin_lock_irq(&mps->lock);
254 }
255 mps->busy = 0;
256 spin_unlock_irq(&mps->lock);
257}
258
259static int mpc52xx_psc_spi_setup(struct spi_device *spi)
260{
261 struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
262 struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
263 unsigned long flags;
264
265 if (spi->bits_per_word%8)
266 return -EINVAL;
267
268 if (!cs) {
269 cs = kzalloc(sizeof *cs, GFP_KERNEL);
270 if (!cs)
271 return -ENOMEM;
272 spi->controller_state = cs;
273 }
274
275 cs->bits_per_word = spi->bits_per_word;
276 cs->speed_hz = spi->max_speed_hz;
277
278 spin_lock_irqsave(&mps->lock, flags);
279 if (!mps->busy)
280 mpc52xx_psc_spi_deactivate_cs(spi);
281 spin_unlock_irqrestore(&mps->lock, flags);
282
283 return 0;
284}
285
286static int mpc52xx_psc_spi_transfer(struct spi_device *spi,
287 struct spi_message *m)
288{
289 struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
290 unsigned long flags;
291
292 m->actual_length = 0;
293 m->status = -EINPROGRESS;
294
295 spin_lock_irqsave(&mps->lock, flags);
296 list_add_tail(&m->queue, &mps->queue);
297 schedule_work(&mps->work);
298 spin_unlock_irqrestore(&mps->lock, flags);
299
300 return 0;
301}
302
303static void mpc52xx_psc_spi_cleanup(struct spi_device *spi)
304{
305 kfree(spi->controller_state);
306}
307
308static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
309{
310 struct mpc52xx_psc __iomem *psc = mps->psc;
311 struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
312 u32 mclken_div;
313 int ret;
314
315 /* default sysclk is 512MHz */
316 mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK;
317 ret = mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
318 if (ret)
319 return ret;
320
321 /* Reset the PSC into a known state */
322 out_8(&psc->command, MPC52xx_PSC_RST_RX);
323 out_8(&psc->command, MPC52xx_PSC_RST_TX);
324 out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
325
326 /* Disable interrupts, interrupts are based on alarm level */
327 out_be16(&psc->mpc52xx_psc_imr, 0);
328 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
329 out_8(&fifo->rfcntl, 0);
330 out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
331
332 /* Configure 8bit codec mode as a SPI master and use EOF flags */
333 /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
334 out_be32(&psc->sicr, 0x0180C800);
335 out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
336
337 /* Set 2ms DTL delay */
338 out_8(&psc->ctur, 0x00);
339 out_8(&psc->ctlr, 0x84);
340
341 mps->bits_per_word = 8;
342
343 return 0;
344}
345
346static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id)
347{
348 struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id;
349 struct mpc52xx_psc __iomem *psc = mps->psc;
350
351 /* disable interrupt and wake up the work queue */
352 if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {
353 out_be16(&psc->mpc52xx_psc_imr, 0);
354 complete(&mps->done);
355 return IRQ_HANDLED;
356 }
357 return IRQ_NONE;
358}
359
360/* bus_num is used only for the case dev->platform_data == NULL */
361static int mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr,
362 u32 size, unsigned int irq, s16 bus_num)
363{
364 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
365 struct mpc52xx_psc_spi *mps;
366 struct spi_master *master;
367 int ret;
368
369 master = spi_alloc_master(dev, sizeof *mps);
370 if (master == NULL)
371 return -ENOMEM;
372
373 dev_set_drvdata(dev, master);
374 mps = spi_master_get_devdata(master);
375
376 /* the spi->mode bits understood by this driver: */
377 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
378
379 mps->irq = irq;
380 if (pdata == NULL) {
381 dev_warn(dev,
382 "probe called without platform data, no cs_control function will be called\n");
383 mps->cs_control = NULL;
384 mps->sysclk = 0;
385 master->bus_num = bus_num;
386 master->num_chipselect = 255;
387 } else {
388 mps->cs_control = pdata->cs_control;
389 mps->sysclk = pdata->sysclk;
390 master->bus_num = pdata->bus_num;
391 master->num_chipselect = pdata->max_chipselect;
392 }
393 master->setup = mpc52xx_psc_spi_setup;
394 master->transfer = mpc52xx_psc_spi_transfer;
395 master->cleanup = mpc52xx_psc_spi_cleanup;
396 master->dev.of_node = dev->of_node;
397
398 mps->psc = ioremap(regaddr, size);
399 if (!mps->psc) {
400 dev_err(dev, "could not ioremap I/O port range\n");
401 ret = -EFAULT;
402 goto free_master;
403 }
404 /* On the 5200, fifo regs are immediately ajacent to the psc regs */
405 mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);
406
407 ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi",
408 mps);
409 if (ret)
410 goto free_master;
411
412 ret = mpc52xx_psc_spi_port_config(master->bus_num, mps);
413 if (ret < 0) {
414 dev_err(dev, "can't configure PSC! Is it capable of SPI?\n");
415 goto free_irq;
416 }
417
418 spin_lock_init(&mps->lock);
419 init_completion(&mps->done);
420 INIT_WORK(&mps->work, mpc52xx_psc_spi_work);
421 INIT_LIST_HEAD(&mps->queue);
422
423 ret = spi_register_master(master);
424 if (ret < 0)
425 goto free_irq;
426
427 return ret;
428
429free_irq:
430 free_irq(mps->irq, mps);
431free_master:
432 if (mps->psc)
433 iounmap(mps->psc);
434 spi_master_put(master);
435
436 return ret;
437}
438
439static int mpc52xx_psc_spi_of_probe(struct platform_device *op)
440{
441 const u32 *regaddr_p;
442 u64 regaddr64, size64;
443 s16 id = -1;
444
445 regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
446 if (!regaddr_p) {
447 dev_err(&op->dev, "Invalid PSC address\n");
448 return -EINVAL;
449 }
450 regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
451
452 /* get PSC id (1..6, used by port_config) */
453 if (op->dev.platform_data == NULL) {
454 const u32 *psc_nump;
455
456 psc_nump = of_get_property(op->dev.of_node, "cell-index", NULL);
457 if (!psc_nump || *psc_nump > 5) {
458 dev_err(&op->dev, "Invalid cell-index property\n");
459 return -EINVAL;
460 }
461 id = *psc_nump + 1;
462 }
463
464 return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64,
465 irq_of_parse_and_map(op->dev.of_node, 0), id);
466}
467
468static int mpc52xx_psc_spi_of_remove(struct platform_device *op)
469{
470 struct spi_master *master = spi_master_get(platform_get_drvdata(op));
471 struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master);
472
473 flush_work(&mps->work);
474 spi_unregister_master(master);
475 free_irq(mps->irq, mps);
476 if (mps->psc)
477 iounmap(mps->psc);
478 spi_master_put(master);
479
480 return 0;
481}
482
483static const struct of_device_id mpc52xx_psc_spi_of_match[] = {
484 { .compatible = "fsl,mpc5200-psc-spi", },
485 { .compatible = "mpc5200-psc-spi", }, /* old */
486 {}
487};
488
489MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match);
490
491static struct platform_driver mpc52xx_psc_spi_of_driver = {
492 .probe = mpc52xx_psc_spi_of_probe,
493 .remove = mpc52xx_psc_spi_of_remove,
494 .driver = {
495 .name = "mpc52xx-psc-spi",
496 .of_match_table = mpc52xx_psc_spi_of_match,
497 },
498};
499module_platform_driver(mpc52xx_psc_spi_of_driver);
500
501MODULE_AUTHOR("Dragos Carp");
502MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");
503MODULE_LICENSE("GPL");