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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * MPC512x PSC in SPI mode driver.
4 *
5 * Copyright (C) 2007,2008 Freescale Semiconductor Inc.
6 * Original port from 52xx driver:
7 * Hongjun Chen <hong-jun.chen@freescale.com>
8 *
9 * Fork of mpc52xx_psc_spi.c:
10 * Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/errno.h>
16#include <linux/interrupt.h>
17#include <linux/completion.h>
18#include <linux/io.h>
19#include <linux/platform_device.h>
20#include <linux/property.h>
21#include <linux/delay.h>
22#include <linux/clk.h>
23#include <linux/spi/spi.h>
24#include <asm/mpc52xx_psc.h>
25
26enum {
27 TYPE_MPC5121,
28 TYPE_MPC5125,
29};
30
31/*
32 * This macro abstracts the differences in the PSC register layout between
33 * MPC5121 (which uses a struct mpc52xx_psc) and MPC5125 (using mpc5125_psc).
34 */
35#define psc_addr(mps, regname) ({ \
36 void *__ret = NULL; \
37 switch (mps->type) { \
38 case TYPE_MPC5121: { \
39 struct mpc52xx_psc __iomem *psc = mps->psc; \
40 __ret = &psc->regname; \
41 }; \
42 break; \
43 case TYPE_MPC5125: { \
44 struct mpc5125_psc __iomem *psc = mps->psc; \
45 __ret = &psc->regname; \
46 }; \
47 break; \
48 } \
49 __ret; })
50
51struct mpc512x_psc_spi {
52 /* driver internal data */
53 int type;
54 void __iomem *psc;
55 struct mpc512x_psc_fifo __iomem *fifo;
56 int irq;
57 u8 bits_per_word;
58 u32 mclk_rate;
59
60 struct completion txisrdone;
61};
62
63/* controller state */
64struct mpc512x_psc_spi_cs {
65 int bits_per_word;
66 int speed_hz;
67};
68
69/* set clock freq, clock ramp, bits per work
70 * if t is NULL then reset the values to the default values
71 */
72static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi,
73 struct spi_transfer *t)
74{
75 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
76
77 cs->speed_hz = (t && t->speed_hz)
78 ? t->speed_hz : spi->max_speed_hz;
79 cs->bits_per_word = (t && t->bits_per_word)
80 ? t->bits_per_word : spi->bits_per_word;
81 cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
82 return 0;
83}
84
85static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
86{
87 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
88 struct mpc512x_psc_spi *mps = spi_controller_get_devdata(spi->controller);
89 u32 sicr;
90 u32 ccr;
91 int speed;
92 u16 bclkdiv;
93
94 sicr = in_be32(psc_addr(mps, sicr));
95
96 /* Set clock phase and polarity */
97 if (spi->mode & SPI_CPHA)
98 sicr |= 0x00001000;
99 else
100 sicr &= ~0x00001000;
101
102 if (spi->mode & SPI_CPOL)
103 sicr |= 0x00002000;
104 else
105 sicr &= ~0x00002000;
106
107 if (spi->mode & SPI_LSB_FIRST)
108 sicr |= 0x10000000;
109 else
110 sicr &= ~0x10000000;
111 out_be32(psc_addr(mps, sicr), sicr);
112
113 ccr = in_be32(psc_addr(mps, ccr));
114 ccr &= 0xFF000000;
115 speed = cs->speed_hz;
116 if (!speed)
117 speed = 1000000; /* default 1MHz */
118 bclkdiv = (mps->mclk_rate / speed) - 1;
119
120 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
121 out_be32(psc_addr(mps, ccr), ccr);
122 mps->bits_per_word = cs->bits_per_word;
123
124 if (spi_get_csgpiod(spi, 0)) {
125 /* gpiolib will deal with the inversion */
126 gpiod_set_value(spi_get_csgpiod(spi, 0), 1);
127 }
128}
129
130static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi)
131{
132 if (spi_get_csgpiod(spi, 0)) {
133 /* gpiolib will deal with the inversion */
134 gpiod_set_value(spi_get_csgpiod(spi, 0), 0);
135 }
136}
137
138/* extract and scale size field in txsz or rxsz */
139#define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2);
140
141#define EOFBYTE 1
142
143static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi,
144 struct spi_transfer *t)
145{
146 struct mpc512x_psc_spi *mps = spi_controller_get_devdata(spi->controller);
147 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
148 size_t tx_len = t->len;
149 size_t rx_len = t->len;
150 u8 *tx_buf = (u8 *)t->tx_buf;
151 u8 *rx_buf = (u8 *)t->rx_buf;
152
153 if (!tx_buf && !rx_buf && t->len)
154 return -EINVAL;
155
156 while (rx_len || tx_len) {
157 size_t txcount;
158 u8 data;
159 size_t fifosz;
160 size_t rxcount;
161 int rxtries;
162
163 /*
164 * send the TX bytes in as large a chunk as possible
165 * but neither exceed the TX nor the RX FIFOs
166 */
167 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz));
168 txcount = min(fifosz, tx_len);
169 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->rxsz));
170 fifosz -= in_be32(&fifo->rxcnt) + 1;
171 txcount = min(fifosz, txcount);
172 if (txcount) {
173
174 /* fill the TX FIFO */
175 while (txcount-- > 0) {
176 data = tx_buf ? *tx_buf++ : 0;
177 if (tx_len == EOFBYTE && t->cs_change)
178 setbits32(&fifo->txcmd,
179 MPC512x_PSC_FIFO_EOF);
180 out_8(&fifo->txdata_8, data);
181 tx_len--;
182 }
183
184 /* have the ISR trigger when the TX FIFO is empty */
185 reinit_completion(&mps->txisrdone);
186 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
187 out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY);
188 wait_for_completion(&mps->txisrdone);
189 }
190
191 /*
192 * consume as much RX data as the FIFO holds, while we
193 * iterate over the transfer's TX data length
194 *
195 * only insist in draining all the remaining RX bytes
196 * when the TX bytes were exhausted (that's at the very
197 * end of this transfer, not when still iterating over
198 * the transfer's chunks)
199 */
200 rxtries = 50;
201 do {
202
203 /*
204 * grab whatever was in the FIFO when we started
205 * looking, don't bother fetching what was added to
206 * the FIFO while we read from it -- we'll return
207 * here eventually and prefer sending out remaining
208 * TX data
209 */
210 fifosz = in_be32(&fifo->rxcnt);
211 rxcount = min(fifosz, rx_len);
212 while (rxcount-- > 0) {
213 data = in_8(&fifo->rxdata_8);
214 if (rx_buf)
215 *rx_buf++ = data;
216 rx_len--;
217 }
218
219 /*
220 * come back later if there still is TX data to send,
221 * bail out of the RX drain loop if all of the TX data
222 * was sent and all of the RX data was received (i.e.
223 * when the transmission has completed)
224 */
225 if (tx_len)
226 break;
227 if (!rx_len)
228 break;
229
230 /*
231 * TX data transmission has completed while RX data
232 * is still pending -- that's a transient situation
233 * which depends on wire speed and specific
234 * hardware implementation details (buffering) yet
235 * should resolve very quickly
236 *
237 * just yield for a moment to not hog the CPU for
238 * too long when running SPI at low speed
239 *
240 * the timeout range is rather arbitrary and tries
241 * to balance throughput against system load; the
242 * chosen values result in a minimal timeout of 50
243 * times 10us and thus work at speeds as low as
244 * some 20kbps, while the maximum timeout at the
245 * transfer's end could be 5ms _if_ nothing else
246 * ticks in the system _and_ RX data still wasn't
247 * received, which only occurs in situations that
248 * are exceptional; removing the unpredictability
249 * of the timeout either decreases throughput
250 * (longer timeouts), or puts more load on the
251 * system (fixed short timeouts) or requires the
252 * use of a timeout API instead of a counter and an
253 * unknown inner delay
254 */
255 usleep_range(10, 100);
256
257 } while (--rxtries > 0);
258 if (!tx_len && rx_len && !rxtries) {
259 /*
260 * not enough RX bytes even after several retries
261 * and the resulting rather long timeout?
262 */
263 rxcount = in_be32(&fifo->rxcnt);
264 dev_warn(&spi->dev,
265 "short xfer, missing %zd RX bytes, FIFO level %zd\n",
266 rx_len, rxcount);
267 }
268
269 /*
270 * drain and drop RX data which "should not be there" in
271 * the first place, for undisturbed transmission this turns
272 * into a NOP (except for the FIFO level fetch)
273 */
274 if (!tx_len && !rx_len) {
275 while (in_be32(&fifo->rxcnt))
276 in_8(&fifo->rxdata_8);
277 }
278
279 }
280 return 0;
281}
282
283static int mpc512x_psc_spi_msg_xfer(struct spi_controller *host,
284 struct spi_message *m)
285{
286 struct spi_device *spi;
287 unsigned cs_change;
288 int status;
289 struct spi_transfer *t;
290
291 spi = m->spi;
292 cs_change = 1;
293 status = 0;
294 list_for_each_entry(t, &m->transfers, transfer_list) {
295 status = mpc512x_psc_spi_transfer_setup(spi, t);
296 if (status < 0)
297 break;
298
299 if (cs_change)
300 mpc512x_psc_spi_activate_cs(spi);
301 cs_change = t->cs_change;
302
303 status = mpc512x_psc_spi_transfer_rxtx(spi, t);
304 if (status)
305 break;
306 m->actual_length += t->len;
307
308 spi_transfer_delay_exec(t);
309
310 if (cs_change)
311 mpc512x_psc_spi_deactivate_cs(spi);
312 }
313
314 m->status = status;
315 if (m->complete)
316 m->complete(m->context);
317
318 if (status || !cs_change)
319 mpc512x_psc_spi_deactivate_cs(spi);
320
321 mpc512x_psc_spi_transfer_setup(spi, NULL);
322
323 spi_finalize_current_message(host);
324 return status;
325}
326
327static int mpc512x_psc_spi_prep_xfer_hw(struct spi_controller *host)
328{
329 struct mpc512x_psc_spi *mps = spi_controller_get_devdata(host);
330
331 dev_dbg(&host->dev, "%s()\n", __func__);
332
333 /* Zero MR2 */
334 in_8(psc_addr(mps, mr2));
335 out_8(psc_addr(mps, mr2), 0x0);
336
337 /* enable transmitter/receiver */
338 out_8(psc_addr(mps, command), MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
339
340 return 0;
341}
342
343static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_controller *host)
344{
345 struct mpc512x_psc_spi *mps = spi_controller_get_devdata(host);
346 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
347
348 dev_dbg(&host->dev, "%s()\n", __func__);
349
350 /* disable transmitter/receiver and fifo interrupt */
351 out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
352 out_be32(&fifo->tximr, 0);
353
354 return 0;
355}
356
357static int mpc512x_psc_spi_setup(struct spi_device *spi)
358{
359 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
360
361 if (spi->bits_per_word % 8)
362 return -EINVAL;
363
364 if (!cs) {
365 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
366 if (!cs)
367 return -ENOMEM;
368
369 spi->controller_state = cs;
370 }
371
372 cs->bits_per_word = spi->bits_per_word;
373 cs->speed_hz = spi->max_speed_hz;
374
375 return 0;
376}
377
378static void mpc512x_psc_spi_cleanup(struct spi_device *spi)
379{
380 kfree(spi->controller_state);
381}
382
383static int mpc512x_psc_spi_port_config(struct spi_controller *host,
384 struct mpc512x_psc_spi *mps)
385{
386 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
387 u32 sicr;
388 u32 ccr;
389 int speed;
390 u16 bclkdiv;
391
392 /* Reset the PSC into a known state */
393 out_8(psc_addr(mps, command), MPC52xx_PSC_RST_RX);
394 out_8(psc_addr(mps, command), MPC52xx_PSC_RST_TX);
395 out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
396
397 /* Disable psc interrupts all useful interrupts are in fifo */
398 out_be16(psc_addr(mps, isr_imr.imr), 0);
399
400 /* Disable fifo interrupts, will be enabled later */
401 out_be32(&fifo->tximr, 0);
402 out_be32(&fifo->rximr, 0);
403
404 /* Setup fifo slice address and size */
405 /*out_be32(&fifo->txsz, 0x0fe00004);*/
406 /*out_be32(&fifo->rxsz, 0x0ff00004);*/
407
408 sicr = 0x01000000 | /* SIM = 0001 -- 8 bit */
409 0x00800000 | /* GenClk = 1 -- internal clk */
410 0x00008000 | /* SPI = 1 */
411 0x00004000 | /* MSTR = 1 -- SPI host */
412 0x00000800; /* UseEOF = 1 -- SS low until EOF */
413
414 out_be32(psc_addr(mps, sicr), sicr);
415
416 ccr = in_be32(psc_addr(mps, ccr));
417 ccr &= 0xFF000000;
418 speed = 1000000; /* default 1MHz */
419 bclkdiv = (mps->mclk_rate / speed) - 1;
420 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
421 out_be32(psc_addr(mps, ccr), ccr);
422
423 /* Set 2ms DTL delay */
424 out_8(psc_addr(mps, ctur), 0x00);
425 out_8(psc_addr(mps, ctlr), 0x82);
426
427 /* we don't use the alarms */
428 out_be32(&fifo->rxalarm, 0xfff);
429 out_be32(&fifo->txalarm, 0);
430
431 /* Enable FIFO slices for Rx/Tx */
432 out_be32(&fifo->rxcmd,
433 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
434 out_be32(&fifo->txcmd,
435 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
436
437 mps->bits_per_word = 8;
438
439 return 0;
440}
441
442static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
443{
444 struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id;
445 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
446
447 /* clear interrupt and wake up the rx/tx routine */
448 if (in_be32(&fifo->txisr) &
449 in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) {
450 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
451 out_be32(&fifo->tximr, 0);
452 complete(&mps->txisrdone);
453 return IRQ_HANDLED;
454 }
455 return IRQ_NONE;
456}
457
458static int mpc512x_psc_spi_of_probe(struct platform_device *pdev)
459{
460 struct device *dev = &pdev->dev;
461 struct mpc512x_psc_spi *mps;
462 struct spi_controller *host;
463 int ret;
464 void *tempp;
465 struct clk *clk;
466
467 host = devm_spi_alloc_host(dev, sizeof(*mps));
468 if (host == NULL)
469 return -ENOMEM;
470
471 dev_set_drvdata(dev, host);
472 mps = spi_controller_get_devdata(host);
473 mps->type = (int)device_get_match_data(dev);
474
475 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
476 host->setup = mpc512x_psc_spi_setup;
477 host->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw;
478 host->transfer_one_message = mpc512x_psc_spi_msg_xfer;
479 host->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw;
480 host->use_gpio_descriptors = true;
481 host->cleanup = mpc512x_psc_spi_cleanup;
482
483 device_set_node(&host->dev, dev_fwnode(dev));
484
485 tempp = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
486 if (IS_ERR(tempp))
487 return dev_err_probe(dev, PTR_ERR(tempp), "could not ioremap I/O port range\n");
488 mps->psc = tempp;
489 mps->fifo =
490 (struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc));
491
492 mps->irq = platform_get_irq(pdev, 0);
493 if (mps->irq < 0)
494 return mps->irq;
495
496 ret = devm_request_irq(dev, mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED,
497 "mpc512x-psc-spi", mps);
498 if (ret)
499 return ret;
500 init_completion(&mps->txisrdone);
501
502 clk = devm_clk_get_enabled(dev, "mclk");
503 if (IS_ERR(clk))
504 return PTR_ERR(clk);
505
506 mps->mclk_rate = clk_get_rate(clk);
507
508 clk = devm_clk_get_enabled(dev, "ipg");
509 if (IS_ERR(clk))
510 return PTR_ERR(clk);
511
512 ret = mpc512x_psc_spi_port_config(host, mps);
513 if (ret < 0)
514 return ret;
515
516 return devm_spi_register_controller(dev, host);
517}
518
519static const struct of_device_id mpc512x_psc_spi_of_match[] = {
520 { .compatible = "fsl,mpc5121-psc-spi", .data = (void *)TYPE_MPC5121 },
521 { .compatible = "fsl,mpc5125-psc-spi", .data = (void *)TYPE_MPC5125 },
522 {},
523};
524
525MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match);
526
527static struct platform_driver mpc512x_psc_spi_of_driver = {
528 .probe = mpc512x_psc_spi_of_probe,
529 .driver = {
530 .name = "mpc512x-psc-spi",
531 .of_match_table = mpc512x_psc_spi_of_match,
532 },
533};
534module_platform_driver(mpc512x_psc_spi_of_driver);
535
536MODULE_AUTHOR("John Rigby");
537MODULE_DESCRIPTION("MPC512x PSC SPI Driver");
538MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * MPC512x PSC in SPI mode driver.
4 *
5 * Copyright (C) 2007,2008 Freescale Semiconductor Inc.
6 * Original port from 52xx driver:
7 * Hongjun Chen <hong-jun.chen@freescale.com>
8 *
9 * Fork of mpc52xx_psc_spi.c:
10 * Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/errno.h>
16#include <linux/interrupt.h>
17#include <linux/of_address.h>
18#include <linux/of_irq.h>
19#include <linux/of_platform.h>
20#include <linux/completion.h>
21#include <linux/io.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/spi/spi.h>
25#include <linux/fsl_devices.h>
26#include <linux/gpio.h>
27#include <asm/mpc52xx_psc.h>
28
29enum {
30 TYPE_MPC5121,
31 TYPE_MPC5125,
32};
33
34/*
35 * This macro abstracts the differences in the PSC register layout between
36 * MPC5121 (which uses a struct mpc52xx_psc) and MPC5125 (using mpc5125_psc).
37 */
38#define psc_addr(mps, regname) ({ \
39 void *__ret = NULL; \
40 switch (mps->type) { \
41 case TYPE_MPC5121: { \
42 struct mpc52xx_psc __iomem *psc = mps->psc; \
43 __ret = &psc->regname; \
44 }; \
45 break; \
46 case TYPE_MPC5125: { \
47 struct mpc5125_psc __iomem *psc = mps->psc; \
48 __ret = &psc->regname; \
49 }; \
50 break; \
51 } \
52 __ret; })
53
54struct mpc512x_psc_spi {
55 void (*cs_control)(struct spi_device *spi, bool on);
56
57 /* driver internal data */
58 int type;
59 void __iomem *psc;
60 struct mpc512x_psc_fifo __iomem *fifo;
61 unsigned int irq;
62 u8 bits_per_word;
63 struct clk *clk_mclk;
64 struct clk *clk_ipg;
65 u32 mclk_rate;
66
67 struct completion txisrdone;
68};
69
70/* controller state */
71struct mpc512x_psc_spi_cs {
72 int bits_per_word;
73 int speed_hz;
74};
75
76/* set clock freq, clock ramp, bits per work
77 * if t is NULL then reset the values to the default values
78 */
79static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi,
80 struct spi_transfer *t)
81{
82 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
83
84 cs->speed_hz = (t && t->speed_hz)
85 ? t->speed_hz : spi->max_speed_hz;
86 cs->bits_per_word = (t && t->bits_per_word)
87 ? t->bits_per_word : spi->bits_per_word;
88 cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
89 return 0;
90}
91
92static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
93{
94 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
95 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
96 u32 sicr;
97 u32 ccr;
98 int speed;
99 u16 bclkdiv;
100
101 sicr = in_be32(psc_addr(mps, sicr));
102
103 /* Set clock phase and polarity */
104 if (spi->mode & SPI_CPHA)
105 sicr |= 0x00001000;
106 else
107 sicr &= ~0x00001000;
108
109 if (spi->mode & SPI_CPOL)
110 sicr |= 0x00002000;
111 else
112 sicr &= ~0x00002000;
113
114 if (spi->mode & SPI_LSB_FIRST)
115 sicr |= 0x10000000;
116 else
117 sicr &= ~0x10000000;
118 out_be32(psc_addr(mps, sicr), sicr);
119
120 ccr = in_be32(psc_addr(mps, ccr));
121 ccr &= 0xFF000000;
122 speed = cs->speed_hz;
123 if (!speed)
124 speed = 1000000; /* default 1MHz */
125 bclkdiv = (mps->mclk_rate / speed) - 1;
126
127 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
128 out_be32(psc_addr(mps, ccr), ccr);
129 mps->bits_per_word = cs->bits_per_word;
130
131 if (mps->cs_control && gpio_is_valid(spi->cs_gpio))
132 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
133}
134
135static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi)
136{
137 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
138
139 if (mps->cs_control && gpio_is_valid(spi->cs_gpio))
140 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
141
142}
143
144/* extract and scale size field in txsz or rxsz */
145#define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2);
146
147#define EOFBYTE 1
148
149static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi,
150 struct spi_transfer *t)
151{
152 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
153 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
154 size_t tx_len = t->len;
155 size_t rx_len = t->len;
156 u8 *tx_buf = (u8 *)t->tx_buf;
157 u8 *rx_buf = (u8 *)t->rx_buf;
158
159 if (!tx_buf && !rx_buf && t->len)
160 return -EINVAL;
161
162 while (rx_len || tx_len) {
163 size_t txcount;
164 u8 data;
165 size_t fifosz;
166 size_t rxcount;
167 int rxtries;
168
169 /*
170 * send the TX bytes in as large a chunk as possible
171 * but neither exceed the TX nor the RX FIFOs
172 */
173 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz));
174 txcount = min(fifosz, tx_len);
175 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->rxsz));
176 fifosz -= in_be32(&fifo->rxcnt) + 1;
177 txcount = min(fifosz, txcount);
178 if (txcount) {
179
180 /* fill the TX FIFO */
181 while (txcount-- > 0) {
182 data = tx_buf ? *tx_buf++ : 0;
183 if (tx_len == EOFBYTE && t->cs_change)
184 setbits32(&fifo->txcmd,
185 MPC512x_PSC_FIFO_EOF);
186 out_8(&fifo->txdata_8, data);
187 tx_len--;
188 }
189
190 /* have the ISR trigger when the TX FIFO is empty */
191 reinit_completion(&mps->txisrdone);
192 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
193 out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY);
194 wait_for_completion(&mps->txisrdone);
195 }
196
197 /*
198 * consume as much RX data as the FIFO holds, while we
199 * iterate over the transfer's TX data length
200 *
201 * only insist in draining all the remaining RX bytes
202 * when the TX bytes were exhausted (that's at the very
203 * end of this transfer, not when still iterating over
204 * the transfer's chunks)
205 */
206 rxtries = 50;
207 do {
208
209 /*
210 * grab whatever was in the FIFO when we started
211 * looking, don't bother fetching what was added to
212 * the FIFO while we read from it -- we'll return
213 * here eventually and prefer sending out remaining
214 * TX data
215 */
216 fifosz = in_be32(&fifo->rxcnt);
217 rxcount = min(fifosz, rx_len);
218 while (rxcount-- > 0) {
219 data = in_8(&fifo->rxdata_8);
220 if (rx_buf)
221 *rx_buf++ = data;
222 rx_len--;
223 }
224
225 /*
226 * come back later if there still is TX data to send,
227 * bail out of the RX drain loop if all of the TX data
228 * was sent and all of the RX data was received (i.e.
229 * when the transmission has completed)
230 */
231 if (tx_len)
232 break;
233 if (!rx_len)
234 break;
235
236 /*
237 * TX data transmission has completed while RX data
238 * is still pending -- that's a transient situation
239 * which depends on wire speed and specific
240 * hardware implementation details (buffering) yet
241 * should resolve very quickly
242 *
243 * just yield for a moment to not hog the CPU for
244 * too long when running SPI at low speed
245 *
246 * the timeout range is rather arbitrary and tries
247 * to balance throughput against system load; the
248 * chosen values result in a minimal timeout of 50
249 * times 10us and thus work at speeds as low as
250 * some 20kbps, while the maximum timeout at the
251 * transfer's end could be 5ms _if_ nothing else
252 * ticks in the system _and_ RX data still wasn't
253 * received, which only occurs in situations that
254 * are exceptional; removing the unpredictability
255 * of the timeout either decreases throughput
256 * (longer timeouts), or puts more load on the
257 * system (fixed short timeouts) or requires the
258 * use of a timeout API instead of a counter and an
259 * unknown inner delay
260 */
261 usleep_range(10, 100);
262
263 } while (--rxtries > 0);
264 if (!tx_len && rx_len && !rxtries) {
265 /*
266 * not enough RX bytes even after several retries
267 * and the resulting rather long timeout?
268 */
269 rxcount = in_be32(&fifo->rxcnt);
270 dev_warn(&spi->dev,
271 "short xfer, missing %zd RX bytes, FIFO level %zd\n",
272 rx_len, rxcount);
273 }
274
275 /*
276 * drain and drop RX data which "should not be there" in
277 * the first place, for undisturbed transmission this turns
278 * into a NOP (except for the FIFO level fetch)
279 */
280 if (!tx_len && !rx_len) {
281 while (in_be32(&fifo->rxcnt))
282 in_8(&fifo->rxdata_8);
283 }
284
285 }
286 return 0;
287}
288
289static int mpc512x_psc_spi_msg_xfer(struct spi_master *master,
290 struct spi_message *m)
291{
292 struct spi_device *spi;
293 unsigned cs_change;
294 int status;
295 struct spi_transfer *t;
296
297 spi = m->spi;
298 cs_change = 1;
299 status = 0;
300 list_for_each_entry(t, &m->transfers, transfer_list) {
301 status = mpc512x_psc_spi_transfer_setup(spi, t);
302 if (status < 0)
303 break;
304
305 if (cs_change)
306 mpc512x_psc_spi_activate_cs(spi);
307 cs_change = t->cs_change;
308
309 status = mpc512x_psc_spi_transfer_rxtx(spi, t);
310 if (status)
311 break;
312 m->actual_length += t->len;
313
314 if (t->delay_usecs)
315 udelay(t->delay_usecs);
316
317 if (cs_change)
318 mpc512x_psc_spi_deactivate_cs(spi);
319 }
320
321 m->status = status;
322 if (m->complete)
323 m->complete(m->context);
324
325 if (status || !cs_change)
326 mpc512x_psc_spi_deactivate_cs(spi);
327
328 mpc512x_psc_spi_transfer_setup(spi, NULL);
329
330 spi_finalize_current_message(master);
331 return status;
332}
333
334static int mpc512x_psc_spi_prep_xfer_hw(struct spi_master *master)
335{
336 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
337
338 dev_dbg(&master->dev, "%s()\n", __func__);
339
340 /* Zero MR2 */
341 in_8(psc_addr(mps, mr2));
342 out_8(psc_addr(mps, mr2), 0x0);
343
344 /* enable transmitter/receiver */
345 out_8(psc_addr(mps, command), MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
346
347 return 0;
348}
349
350static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_master *master)
351{
352 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
353 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
354
355 dev_dbg(&master->dev, "%s()\n", __func__);
356
357 /* disable transmitter/receiver and fifo interrupt */
358 out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
359 out_be32(&fifo->tximr, 0);
360
361 return 0;
362}
363
364static int mpc512x_psc_spi_setup(struct spi_device *spi)
365{
366 struct mpc512x_psc_spi_cs *cs = spi->controller_state;
367 int ret;
368
369 if (spi->bits_per_word % 8)
370 return -EINVAL;
371
372 if (!cs) {
373 cs = kzalloc(sizeof *cs, GFP_KERNEL);
374 if (!cs)
375 return -ENOMEM;
376
377 if (gpio_is_valid(spi->cs_gpio)) {
378 ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
379 if (ret) {
380 dev_err(&spi->dev, "can't get CS gpio: %d\n",
381 ret);
382 kfree(cs);
383 return ret;
384 }
385 gpio_direction_output(spi->cs_gpio,
386 spi->mode & SPI_CS_HIGH ? 0 : 1);
387 }
388
389 spi->controller_state = cs;
390 }
391
392 cs->bits_per_word = spi->bits_per_word;
393 cs->speed_hz = spi->max_speed_hz;
394
395 return 0;
396}
397
398static void mpc512x_psc_spi_cleanup(struct spi_device *spi)
399{
400 if (gpio_is_valid(spi->cs_gpio))
401 gpio_free(spi->cs_gpio);
402 kfree(spi->controller_state);
403}
404
405static int mpc512x_psc_spi_port_config(struct spi_master *master,
406 struct mpc512x_psc_spi *mps)
407{
408 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
409 u32 sicr;
410 u32 ccr;
411 int speed;
412 u16 bclkdiv;
413
414 /* Reset the PSC into a known state */
415 out_8(psc_addr(mps, command), MPC52xx_PSC_RST_RX);
416 out_8(psc_addr(mps, command), MPC52xx_PSC_RST_TX);
417 out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
418
419 /* Disable psc interrupts all useful interrupts are in fifo */
420 out_be16(psc_addr(mps, isr_imr.imr), 0);
421
422 /* Disable fifo interrupts, will be enabled later */
423 out_be32(&fifo->tximr, 0);
424 out_be32(&fifo->rximr, 0);
425
426 /* Setup fifo slice address and size */
427 /*out_be32(&fifo->txsz, 0x0fe00004);*/
428 /*out_be32(&fifo->rxsz, 0x0ff00004);*/
429
430 sicr = 0x01000000 | /* SIM = 0001 -- 8 bit */
431 0x00800000 | /* GenClk = 1 -- internal clk */
432 0x00008000 | /* SPI = 1 */
433 0x00004000 | /* MSTR = 1 -- SPI master */
434 0x00000800; /* UseEOF = 1 -- SS low until EOF */
435
436 out_be32(psc_addr(mps, sicr), sicr);
437
438 ccr = in_be32(psc_addr(mps, ccr));
439 ccr &= 0xFF000000;
440 speed = 1000000; /* default 1MHz */
441 bclkdiv = (mps->mclk_rate / speed) - 1;
442 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
443 out_be32(psc_addr(mps, ccr), ccr);
444
445 /* Set 2ms DTL delay */
446 out_8(psc_addr(mps, ctur), 0x00);
447 out_8(psc_addr(mps, ctlr), 0x82);
448
449 /* we don't use the alarms */
450 out_be32(&fifo->rxalarm, 0xfff);
451 out_be32(&fifo->txalarm, 0);
452
453 /* Enable FIFO slices for Rx/Tx */
454 out_be32(&fifo->rxcmd,
455 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
456 out_be32(&fifo->txcmd,
457 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
458
459 mps->bits_per_word = 8;
460
461 return 0;
462}
463
464static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
465{
466 struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id;
467 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
468
469 /* clear interrupt and wake up the rx/tx routine */
470 if (in_be32(&fifo->txisr) &
471 in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) {
472 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
473 out_be32(&fifo->tximr, 0);
474 complete(&mps->txisrdone);
475 return IRQ_HANDLED;
476 }
477 return IRQ_NONE;
478}
479
480static void mpc512x_spi_cs_control(struct spi_device *spi, bool onoff)
481{
482 gpio_set_value(spi->cs_gpio, onoff);
483}
484
485static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
486 u32 size, unsigned int irq)
487{
488 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
489 struct mpc512x_psc_spi *mps;
490 struct spi_master *master;
491 int ret;
492 void *tempp;
493 struct clk *clk;
494
495 master = spi_alloc_master(dev, sizeof *mps);
496 if (master == NULL)
497 return -ENOMEM;
498
499 dev_set_drvdata(dev, master);
500 mps = spi_master_get_devdata(master);
501 mps->type = (int)of_device_get_match_data(dev);
502 mps->irq = irq;
503
504 if (pdata == NULL) {
505 mps->cs_control = mpc512x_spi_cs_control;
506 } else {
507 mps->cs_control = pdata->cs_control;
508 master->bus_num = pdata->bus_num;
509 master->num_chipselect = pdata->max_chipselect;
510 }
511
512 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
513 master->setup = mpc512x_psc_spi_setup;
514 master->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw;
515 master->transfer_one_message = mpc512x_psc_spi_msg_xfer;
516 master->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw;
517 master->cleanup = mpc512x_psc_spi_cleanup;
518 master->dev.of_node = dev->of_node;
519
520 tempp = devm_ioremap(dev, regaddr, size);
521 if (!tempp) {
522 dev_err(dev, "could not ioremap I/O port range\n");
523 ret = -EFAULT;
524 goto free_master;
525 }
526 mps->psc = tempp;
527 mps->fifo =
528 (struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc));
529 ret = devm_request_irq(dev, mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED,
530 "mpc512x-psc-spi", mps);
531 if (ret)
532 goto free_master;
533 init_completion(&mps->txisrdone);
534
535 clk = devm_clk_get(dev, "mclk");
536 if (IS_ERR(clk)) {
537 ret = PTR_ERR(clk);
538 goto free_master;
539 }
540 ret = clk_prepare_enable(clk);
541 if (ret)
542 goto free_master;
543 mps->clk_mclk = clk;
544 mps->mclk_rate = clk_get_rate(clk);
545
546 clk = devm_clk_get(dev, "ipg");
547 if (IS_ERR(clk)) {
548 ret = PTR_ERR(clk);
549 goto free_mclk_clock;
550 }
551 ret = clk_prepare_enable(clk);
552 if (ret)
553 goto free_mclk_clock;
554 mps->clk_ipg = clk;
555
556 ret = mpc512x_psc_spi_port_config(master, mps);
557 if (ret < 0)
558 goto free_ipg_clock;
559
560 ret = devm_spi_register_master(dev, master);
561 if (ret < 0)
562 goto free_ipg_clock;
563
564 return ret;
565
566free_ipg_clock:
567 clk_disable_unprepare(mps->clk_ipg);
568free_mclk_clock:
569 clk_disable_unprepare(mps->clk_mclk);
570free_master:
571 spi_master_put(master);
572
573 return ret;
574}
575
576static int mpc512x_psc_spi_do_remove(struct device *dev)
577{
578 struct spi_master *master = dev_get_drvdata(dev);
579 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
580
581 clk_disable_unprepare(mps->clk_mclk);
582 clk_disable_unprepare(mps->clk_ipg);
583
584 return 0;
585}
586
587static int mpc512x_psc_spi_of_probe(struct platform_device *op)
588{
589 const u32 *regaddr_p;
590 u64 regaddr64, size64;
591
592 regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
593 if (!regaddr_p) {
594 dev_err(&op->dev, "Invalid PSC address\n");
595 return -EINVAL;
596 }
597 regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
598
599 return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64,
600 irq_of_parse_and_map(op->dev.of_node, 0));
601}
602
603static int mpc512x_psc_spi_of_remove(struct platform_device *op)
604{
605 return mpc512x_psc_spi_do_remove(&op->dev);
606}
607
608static const struct of_device_id mpc512x_psc_spi_of_match[] = {
609 { .compatible = "fsl,mpc5121-psc-spi", .data = (void *)TYPE_MPC5121 },
610 { .compatible = "fsl,mpc5125-psc-spi", .data = (void *)TYPE_MPC5125 },
611 {},
612};
613
614MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match);
615
616static struct platform_driver mpc512x_psc_spi_of_driver = {
617 .probe = mpc512x_psc_spi_of_probe,
618 .remove = mpc512x_psc_spi_of_remove,
619 .driver = {
620 .name = "mpc512x-psc-spi",
621 .of_match_table = mpc512x_psc_spi_of_match,
622 },
623};
624module_platform_driver(mpc512x_psc_spi_of_driver);
625
626MODULE_AUTHOR("John Rigby");
627MODULE_DESCRIPTION("MPC512x PSC SPI Driver");
628MODULE_LICENSE("GPL");