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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for Allwinner sun4i Pulse Width Modulation Controller
4 *
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
6 *
7 * Limitations:
8 * - When outputing the source clock directly, the PWM logic will be bypassed
9 * and the currently running period is not guaranteed to be completed
10 */
11
12#include <linux/bitops.h>
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/err.h>
16#include <linux/io.h>
17#include <linux/jiffies.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <linux/pwm.h>
22#include <linux/reset.h>
23#include <linux/slab.h>
24#include <linux/spinlock.h>
25#include <linux/time.h>
26
27#define PWM_CTRL_REG 0x0
28
29#define PWM_CH_PRD_BASE 0x4
30#define PWM_CH_PRD_OFFSET 0x4
31#define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
32
33#define PWMCH_OFFSET 15
34#define PWM_PRESCAL_MASK GENMASK(3, 0)
35#define PWM_PRESCAL_OFF 0
36#define PWM_EN BIT(4)
37#define PWM_ACT_STATE BIT(5)
38#define PWM_CLK_GATING BIT(6)
39#define PWM_MODE BIT(7)
40#define PWM_PULSE BIT(8)
41#define PWM_BYPASS BIT(9)
42
43#define PWM_RDY_BASE 28
44#define PWM_RDY_OFFSET 1
45#define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
46
47#define PWM_PRD(prd) (((prd) - 1) << 16)
48#define PWM_PRD_MASK GENMASK(15, 0)
49
50#define PWM_DTY_MASK GENMASK(15, 0)
51
52#define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1)
53#define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK)
54#define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
55
56#define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
57
58static const u32 prescaler_table[] = {
59 120,
60 180,
61 240,
62 360,
63 480,
64 0,
65 0,
66 0,
67 12000,
68 24000,
69 36000,
70 48000,
71 72000,
72 0,
73 0,
74 0, /* Actually 1 but tested separately */
75};
76
77struct sun4i_pwm_data {
78 bool has_prescaler_bypass;
79 bool has_direct_mod_clk_output;
80 unsigned int npwm;
81};
82
83struct sun4i_pwm_chip {
84 struct pwm_chip chip;
85 struct clk *bus_clk;
86 struct clk *clk;
87 struct reset_control *rst;
88 void __iomem *base;
89 spinlock_t ctrl_lock;
90 const struct sun4i_pwm_data *data;
91};
92
93static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
94{
95 return container_of(chip, struct sun4i_pwm_chip, chip);
96}
97
98static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
99 unsigned long offset)
100{
101 return readl(chip->base + offset);
102}
103
104static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
105 u32 val, unsigned long offset)
106{
107 writel(val, chip->base + offset);
108}
109
110static int sun4i_pwm_get_state(struct pwm_chip *chip,
111 struct pwm_device *pwm,
112 struct pwm_state *state)
113{
114 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
115 u64 clk_rate, tmp;
116 u32 val;
117 unsigned int prescaler;
118
119 clk_rate = clk_get_rate(sun4i_pwm->clk);
120 if (!clk_rate)
121 return -EINVAL;
122
123 val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
124
125 /*
126 * PWM chapter in H6 manual has a diagram which explains that if bypass
127 * bit is set, no other setting has any meaning. Even more, experiment
128 * proved that also enable bit is ignored in this case.
129 */
130 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
131 sun4i_pwm->data->has_direct_mod_clk_output) {
132 state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
133 state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
134 state->polarity = PWM_POLARITY_NORMAL;
135 state->enabled = true;
136 return 0;
137 }
138
139 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
140 sun4i_pwm->data->has_prescaler_bypass)
141 prescaler = 1;
142 else
143 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
144
145 if (prescaler == 0)
146 return -EINVAL;
147
148 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
149 state->polarity = PWM_POLARITY_NORMAL;
150 else
151 state->polarity = PWM_POLARITY_INVERSED;
152
153 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
154 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
155 state->enabled = true;
156 else
157 state->enabled = false;
158
159 val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
160
161 tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
162 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
163
164 tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
165 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
166
167 return 0;
168}
169
170static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
171 const struct pwm_state *state,
172 u32 *dty, u32 *prd, unsigned int *prsclr,
173 bool *bypass)
174{
175 u64 clk_rate, div = 0;
176 unsigned int prescaler = 0;
177
178 clk_rate = clk_get_rate(sun4i_pwm->clk);
179
180 *bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
181 state->enabled &&
182 (state->period * clk_rate >= NSEC_PER_SEC) &&
183 (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
184 (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
185
186 /* Skip calculation of other parameters if we bypass them */
187 if (*bypass)
188 return 0;
189
190 if (sun4i_pwm->data->has_prescaler_bypass) {
191 /* First, test without any prescaler when available */
192 prescaler = PWM_PRESCAL_MASK;
193 /*
194 * When not using any prescaler, the clock period in nanoseconds
195 * is not an integer so round it half up instead of
196 * truncating to get less surprising values.
197 */
198 div = clk_rate * state->period + NSEC_PER_SEC / 2;
199 do_div(div, NSEC_PER_SEC);
200 if (div - 1 > PWM_PRD_MASK)
201 prescaler = 0;
202 }
203
204 if (prescaler == 0) {
205 /* Go up from the first divider */
206 for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
207 unsigned int pval = prescaler_table[prescaler];
208
209 if (!pval)
210 continue;
211
212 div = clk_rate;
213 do_div(div, pval);
214 div = div * state->period;
215 do_div(div, NSEC_PER_SEC);
216 if (div - 1 <= PWM_PRD_MASK)
217 break;
218 }
219
220 if (div - 1 > PWM_PRD_MASK)
221 return -EINVAL;
222 }
223
224 *prd = div;
225 div *= state->duty_cycle;
226 do_div(div, state->period);
227 *dty = div;
228 *prsclr = prescaler;
229
230 return 0;
231}
232
233static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
234 const struct pwm_state *state)
235{
236 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
237 struct pwm_state cstate;
238 u32 ctrl, duty = 0, period = 0, val;
239 int ret;
240 unsigned int delay_us, prescaler = 0;
241 bool bypass;
242
243 pwm_get_state(pwm, &cstate);
244
245 if (!cstate.enabled) {
246 ret = clk_prepare_enable(sun4i_pwm->clk);
247 if (ret) {
248 dev_err(chip->dev, "failed to enable PWM clock\n");
249 return ret;
250 }
251 }
252
253 ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
254 &bypass);
255 if (ret) {
256 dev_err(chip->dev, "period exceeds the maximum value\n");
257 if (!cstate.enabled)
258 clk_disable_unprepare(sun4i_pwm->clk);
259 return ret;
260 }
261
262 spin_lock(&sun4i_pwm->ctrl_lock);
263 ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
264
265 if (sun4i_pwm->data->has_direct_mod_clk_output) {
266 if (bypass) {
267 ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
268 /* We can skip other parameter */
269 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
270 spin_unlock(&sun4i_pwm->ctrl_lock);
271 return 0;
272 }
273
274 ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
275 }
276
277 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
278 /* Prescaler changed, the clock has to be gated */
279 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
280 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
281
282 ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
283 ctrl |= BIT_CH(prescaler, pwm->hwpwm);
284 }
285
286 val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
287 sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
288
289 if (state->polarity != PWM_POLARITY_NORMAL)
290 ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
291 else
292 ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
293
294 ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
295
296 if (state->enabled)
297 ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
298
299 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
300
301 spin_unlock(&sun4i_pwm->ctrl_lock);
302
303 if (state->enabled)
304 return 0;
305
306 /* We need a full period to elapse before disabling the channel. */
307 delay_us = DIV_ROUND_UP_ULL(cstate.period, NSEC_PER_USEC);
308 if ((delay_us / 500) > MAX_UDELAY_MS)
309 msleep(delay_us / 1000 + 1);
310 else
311 usleep_range(delay_us, delay_us * 2);
312
313 spin_lock(&sun4i_pwm->ctrl_lock);
314 ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
315 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
316 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
317 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
318 spin_unlock(&sun4i_pwm->ctrl_lock);
319
320 clk_disable_unprepare(sun4i_pwm->clk);
321
322 return 0;
323}
324
325static const struct pwm_ops sun4i_pwm_ops = {
326 .apply = sun4i_pwm_apply,
327 .get_state = sun4i_pwm_get_state,
328};
329
330static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
331 .has_prescaler_bypass = false,
332 .npwm = 2,
333};
334
335static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
336 .has_prescaler_bypass = true,
337 .npwm = 2,
338};
339
340static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
341 .has_prescaler_bypass = true,
342 .npwm = 1,
343};
344
345static const struct sun4i_pwm_data sun50i_a64_pwm_data = {
346 .has_prescaler_bypass = true,
347 .has_direct_mod_clk_output = true,
348 .npwm = 1,
349};
350
351static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
352 .has_prescaler_bypass = true,
353 .has_direct_mod_clk_output = true,
354 .npwm = 2,
355};
356
357static const struct of_device_id sun4i_pwm_dt_ids[] = {
358 {
359 .compatible = "allwinner,sun4i-a10-pwm",
360 .data = &sun4i_pwm_dual_nobypass,
361 }, {
362 .compatible = "allwinner,sun5i-a10s-pwm",
363 .data = &sun4i_pwm_dual_bypass,
364 }, {
365 .compatible = "allwinner,sun5i-a13-pwm",
366 .data = &sun4i_pwm_single_bypass,
367 }, {
368 .compatible = "allwinner,sun7i-a20-pwm",
369 .data = &sun4i_pwm_dual_bypass,
370 }, {
371 .compatible = "allwinner,sun8i-h3-pwm",
372 .data = &sun4i_pwm_single_bypass,
373 }, {
374 .compatible = "allwinner,sun50i-a64-pwm",
375 .data = &sun50i_a64_pwm_data,
376 }, {
377 .compatible = "allwinner,sun50i-h6-pwm",
378 .data = &sun50i_h6_pwm_data,
379 }, {
380 /* sentinel */
381 },
382};
383MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
384
385static int sun4i_pwm_probe(struct platform_device *pdev)
386{
387 struct sun4i_pwm_chip *sun4ichip;
388 int ret;
389
390 sun4ichip = devm_kzalloc(&pdev->dev, sizeof(*sun4ichip), GFP_KERNEL);
391 if (!sun4ichip)
392 return -ENOMEM;
393
394 sun4ichip->data = of_device_get_match_data(&pdev->dev);
395 if (!sun4ichip->data)
396 return -ENODEV;
397
398 sun4ichip->base = devm_platform_ioremap_resource(pdev, 0);
399 if (IS_ERR(sun4ichip->base))
400 return PTR_ERR(sun4ichip->base);
401
402 /*
403 * All hardware variants need a source clock that is divided and
404 * then feeds the counter that defines the output wave form. In the
405 * device tree this clock is either unnamed or called "mod".
406 * Some variants (e.g. H6) need another clock to access the
407 * hardware registers; this is called "bus".
408 * So we request "mod" first (and ignore the corner case that a
409 * parent provides a "mod" clock while the right one would be the
410 * unnamed one of the PWM device) and if this is not found we fall
411 * back to the first clock of the PWM.
412 */
413 sun4ichip->clk = devm_clk_get_optional(&pdev->dev, "mod");
414 if (IS_ERR(sun4ichip->clk))
415 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),
416 "get mod clock failed\n");
417
418 if (!sun4ichip->clk) {
419 sun4ichip->clk = devm_clk_get(&pdev->dev, NULL);
420 if (IS_ERR(sun4ichip->clk))
421 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),
422 "get unnamed clock failed\n");
423 }
424
425 sun4ichip->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
426 if (IS_ERR(sun4ichip->bus_clk))
427 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->bus_clk),
428 "get bus clock failed\n");
429
430 sun4ichip->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
431 if (IS_ERR(sun4ichip->rst))
432 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->rst),
433 "get reset failed\n");
434
435 /* Deassert reset */
436 ret = reset_control_deassert(sun4ichip->rst);
437 if (ret) {
438 dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
439 ERR_PTR(ret));
440 return ret;
441 }
442
443 /*
444 * We're keeping the bus clock on for the sake of simplicity.
445 * Actually it only needs to be on for hardware register accesses.
446 */
447 ret = clk_prepare_enable(sun4ichip->bus_clk);
448 if (ret) {
449 dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
450 ERR_PTR(ret));
451 goto err_bus;
452 }
453
454 sun4ichip->chip.dev = &pdev->dev;
455 sun4ichip->chip.ops = &sun4i_pwm_ops;
456 sun4ichip->chip.npwm = sun4ichip->data->npwm;
457
458 spin_lock_init(&sun4ichip->ctrl_lock);
459
460 ret = pwmchip_add(&sun4ichip->chip);
461 if (ret < 0) {
462 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
463 goto err_pwm_add;
464 }
465
466 platform_set_drvdata(pdev, sun4ichip);
467
468 return 0;
469
470err_pwm_add:
471 clk_disable_unprepare(sun4ichip->bus_clk);
472err_bus:
473 reset_control_assert(sun4ichip->rst);
474
475 return ret;
476}
477
478static void sun4i_pwm_remove(struct platform_device *pdev)
479{
480 struct sun4i_pwm_chip *sun4ichip = platform_get_drvdata(pdev);
481
482 pwmchip_remove(&sun4ichip->chip);
483
484 clk_disable_unprepare(sun4ichip->bus_clk);
485 reset_control_assert(sun4ichip->rst);
486}
487
488static struct platform_driver sun4i_pwm_driver = {
489 .driver = {
490 .name = "sun4i-pwm",
491 .of_match_table = sun4i_pwm_dt_ids,
492 },
493 .probe = sun4i_pwm_probe,
494 .remove_new = sun4i_pwm_remove,
495};
496module_platform_driver(sun4i_pwm_driver);
497
498MODULE_ALIAS("platform:sun4i-pwm");
499MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
500MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
501MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for Allwinner sun4i Pulse Width Modulation Controller
4 *
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
6 */
7
8#include <linux/bitops.h>
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/err.h>
12#include <linux/io.h>
13#include <linux/jiffies.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/platform_device.h>
18#include <linux/pwm.h>
19#include <linux/slab.h>
20#include <linux/spinlock.h>
21#include <linux/time.h>
22
23#define PWM_CTRL_REG 0x0
24
25#define PWM_CH_PRD_BASE 0x4
26#define PWM_CH_PRD_OFFSET 0x4
27#define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
28
29#define PWMCH_OFFSET 15
30#define PWM_PRESCAL_MASK GENMASK(3, 0)
31#define PWM_PRESCAL_OFF 0
32#define PWM_EN BIT(4)
33#define PWM_ACT_STATE BIT(5)
34#define PWM_CLK_GATING BIT(6)
35#define PWM_MODE BIT(7)
36#define PWM_PULSE BIT(8)
37#define PWM_BYPASS BIT(9)
38
39#define PWM_RDY_BASE 28
40#define PWM_RDY_OFFSET 1
41#define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
42
43#define PWM_PRD(prd) (((prd) - 1) << 16)
44#define PWM_PRD_MASK GENMASK(15, 0)
45
46#define PWM_DTY_MASK GENMASK(15, 0)
47
48#define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1)
49#define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK)
50#define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
51
52#define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
53
54static const u32 prescaler_table[] = {
55 120,
56 180,
57 240,
58 360,
59 480,
60 0,
61 0,
62 0,
63 12000,
64 24000,
65 36000,
66 48000,
67 72000,
68 0,
69 0,
70 0, /* Actually 1 but tested separately */
71};
72
73struct sun4i_pwm_data {
74 bool has_prescaler_bypass;
75 unsigned int npwm;
76};
77
78struct sun4i_pwm_chip {
79 struct pwm_chip chip;
80 struct clk *clk;
81 void __iomem *base;
82 spinlock_t ctrl_lock;
83 const struct sun4i_pwm_data *data;
84 unsigned long next_period[2];
85 bool needs_delay[2];
86};
87
88static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
89{
90 return container_of(chip, struct sun4i_pwm_chip, chip);
91}
92
93static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
94 unsigned long offset)
95{
96 return readl(chip->base + offset);
97}
98
99static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
100 u32 val, unsigned long offset)
101{
102 writel(val, chip->base + offset);
103}
104
105static void sun4i_pwm_get_state(struct pwm_chip *chip,
106 struct pwm_device *pwm,
107 struct pwm_state *state)
108{
109 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
110 u64 clk_rate, tmp;
111 u32 val;
112 unsigned int prescaler;
113
114 clk_rate = clk_get_rate(sun4i_pwm->clk);
115
116 val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
117
118 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
119 sun4i_pwm->data->has_prescaler_bypass)
120 prescaler = 1;
121 else
122 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
123
124 if (prescaler == 0)
125 return;
126
127 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
128 state->polarity = PWM_POLARITY_NORMAL;
129 else
130 state->polarity = PWM_POLARITY_INVERSED;
131
132 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
133 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
134 state->enabled = true;
135 else
136 state->enabled = false;
137
138 val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
139
140 tmp = prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
141 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
142
143 tmp = prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
144 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
145}
146
147static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
148 const struct pwm_state *state,
149 u32 *dty, u32 *prd, unsigned int *prsclr)
150{
151 u64 clk_rate, div = 0;
152 unsigned int pval, prescaler = 0;
153
154 clk_rate = clk_get_rate(sun4i_pwm->clk);
155
156 if (sun4i_pwm->data->has_prescaler_bypass) {
157 /* First, test without any prescaler when available */
158 prescaler = PWM_PRESCAL_MASK;
159 pval = 1;
160 /*
161 * When not using any prescaler, the clock period in nanoseconds
162 * is not an integer so round it half up instead of
163 * truncating to get less surprising values.
164 */
165 div = clk_rate * state->period + NSEC_PER_SEC / 2;
166 do_div(div, NSEC_PER_SEC);
167 if (div - 1 > PWM_PRD_MASK)
168 prescaler = 0;
169 }
170
171 if (prescaler == 0) {
172 /* Go up from the first divider */
173 for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
174 if (!prescaler_table[prescaler])
175 continue;
176 pval = prescaler_table[prescaler];
177 div = clk_rate;
178 do_div(div, pval);
179 div = div * state->period;
180 do_div(div, NSEC_PER_SEC);
181 if (div - 1 <= PWM_PRD_MASK)
182 break;
183 }
184
185 if (div - 1 > PWM_PRD_MASK)
186 return -EINVAL;
187 }
188
189 *prd = div;
190 div *= state->duty_cycle;
191 do_div(div, state->period);
192 *dty = div;
193 *prsclr = prescaler;
194
195 return 0;
196}
197
198static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
199 const struct pwm_state *state)
200{
201 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
202 struct pwm_state cstate;
203 u32 ctrl;
204 int ret;
205 unsigned int delay_us;
206 unsigned long now;
207
208 pwm_get_state(pwm, &cstate);
209
210 if (!cstate.enabled) {
211 ret = clk_prepare_enable(sun4i_pwm->clk);
212 if (ret) {
213 dev_err(chip->dev, "failed to enable PWM clock\n");
214 return ret;
215 }
216 }
217
218 spin_lock(&sun4i_pwm->ctrl_lock);
219 ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
220
221 if ((cstate.period != state->period) ||
222 (cstate.duty_cycle != state->duty_cycle)) {
223 u32 period, duty, val;
224 unsigned int prescaler;
225
226 ret = sun4i_pwm_calculate(sun4i_pwm, state,
227 &duty, &period, &prescaler);
228 if (ret) {
229 dev_err(chip->dev, "period exceeds the maximum value\n");
230 spin_unlock(&sun4i_pwm->ctrl_lock);
231 if (!cstate.enabled)
232 clk_disable_unprepare(sun4i_pwm->clk);
233 return ret;
234 }
235
236 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
237 /* Prescaler changed, the clock has to be gated */
238 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
239 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
240
241 ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
242 ctrl |= BIT_CH(prescaler, pwm->hwpwm);
243 }
244
245 val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
246 sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
247 sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
248 usecs_to_jiffies(cstate.period / 1000 + 1);
249 sun4i_pwm->needs_delay[pwm->hwpwm] = true;
250 }
251
252 if (state->polarity != PWM_POLARITY_NORMAL)
253 ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
254 else
255 ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
256
257 ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
258 if (state->enabled) {
259 ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
260 } else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
261 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
262 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
263 }
264
265 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
266
267 spin_unlock(&sun4i_pwm->ctrl_lock);
268
269 if (state->enabled)
270 return 0;
271
272 if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
273 clk_disable_unprepare(sun4i_pwm->clk);
274 return 0;
275 }
276
277 /* We need a full period to elapse before disabling the channel. */
278 now = jiffies;
279 if (sun4i_pwm->needs_delay[pwm->hwpwm] &&
280 time_before(now, sun4i_pwm->next_period[pwm->hwpwm])) {
281 delay_us = jiffies_to_usecs(sun4i_pwm->next_period[pwm->hwpwm] -
282 now);
283 if ((delay_us / 500) > MAX_UDELAY_MS)
284 msleep(delay_us / 1000 + 1);
285 else
286 usleep_range(delay_us, delay_us * 2);
287 }
288 sun4i_pwm->needs_delay[pwm->hwpwm] = false;
289
290 spin_lock(&sun4i_pwm->ctrl_lock);
291 ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
292 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
293 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
294 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
295 spin_unlock(&sun4i_pwm->ctrl_lock);
296
297 clk_disable_unprepare(sun4i_pwm->clk);
298
299 return 0;
300}
301
302static const struct pwm_ops sun4i_pwm_ops = {
303 .apply = sun4i_pwm_apply,
304 .get_state = sun4i_pwm_get_state,
305 .owner = THIS_MODULE,
306};
307
308static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
309 .has_prescaler_bypass = false,
310 .npwm = 2,
311};
312
313static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
314 .has_prescaler_bypass = true,
315 .npwm = 2,
316};
317
318static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
319 .has_prescaler_bypass = true,
320 .npwm = 1,
321};
322
323static const struct of_device_id sun4i_pwm_dt_ids[] = {
324 {
325 .compatible = "allwinner,sun4i-a10-pwm",
326 .data = &sun4i_pwm_dual_nobypass,
327 }, {
328 .compatible = "allwinner,sun5i-a10s-pwm",
329 .data = &sun4i_pwm_dual_bypass,
330 }, {
331 .compatible = "allwinner,sun5i-a13-pwm",
332 .data = &sun4i_pwm_single_bypass,
333 }, {
334 .compatible = "allwinner,sun7i-a20-pwm",
335 .data = &sun4i_pwm_dual_bypass,
336 }, {
337 .compatible = "allwinner,sun8i-h3-pwm",
338 .data = &sun4i_pwm_single_bypass,
339 }, {
340 /* sentinel */
341 },
342};
343MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
344
345static int sun4i_pwm_probe(struct platform_device *pdev)
346{
347 struct sun4i_pwm_chip *pwm;
348 struct resource *res;
349 int ret;
350
351 pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
352 if (!pwm)
353 return -ENOMEM;
354
355 pwm->data = of_device_get_match_data(&pdev->dev);
356 if (!pwm->data)
357 return -ENODEV;
358
359 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
360 pwm->base = devm_ioremap_resource(&pdev->dev, res);
361 if (IS_ERR(pwm->base))
362 return PTR_ERR(pwm->base);
363
364 pwm->clk = devm_clk_get(&pdev->dev, NULL);
365 if (IS_ERR(pwm->clk))
366 return PTR_ERR(pwm->clk);
367
368 pwm->chip.dev = &pdev->dev;
369 pwm->chip.ops = &sun4i_pwm_ops;
370 pwm->chip.base = -1;
371 pwm->chip.npwm = pwm->data->npwm;
372 pwm->chip.of_xlate = of_pwm_xlate_with_flags;
373 pwm->chip.of_pwm_n_cells = 3;
374
375 spin_lock_init(&pwm->ctrl_lock);
376
377 ret = pwmchip_add(&pwm->chip);
378 if (ret < 0) {
379 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
380 return ret;
381 }
382
383 platform_set_drvdata(pdev, pwm);
384
385 return 0;
386}
387
388static int sun4i_pwm_remove(struct platform_device *pdev)
389{
390 struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
391
392 return pwmchip_remove(&pwm->chip);
393}
394
395static struct platform_driver sun4i_pwm_driver = {
396 .driver = {
397 .name = "sun4i-pwm",
398 .of_match_table = sun4i_pwm_dt_ids,
399 },
400 .probe = sun4i_pwm_probe,
401 .remove = sun4i_pwm_remove,
402};
403module_platform_driver(sun4i_pwm_driver);
404
405MODULE_ALIAS("platform:sun4i-pwm");
406MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
407MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
408MODULE_LICENSE("GPL v2");