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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek PCIe host controller driver.
4 *
5 * Copyright (c) 2017 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
7 * Honghui Zhang <honghui.zhang@mediatek.com>
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/iopoll.h>
13#include <linux/irq.h>
14#include <linux/irqchip/chained_irq.h>
15#include <linux/irqdomain.h>
16#include <linux/kernel.h>
17#include <linux/mfd/syscon.h>
18#include <linux/msi.h>
19#include <linux/module.h>
20#include <linux/of_address.h>
21#include <linux/of_pci.h>
22#include <linux/of_platform.h>
23#include <linux/pci.h>
24#include <linux/phy/phy.h>
25#include <linux/platform_device.h>
26#include <linux/pm_runtime.h>
27#include <linux/regmap.h>
28#include <linux/reset.h>
29
30#include "../pci.h"
31
32/* PCIe shared registers */
33#define PCIE_SYS_CFG 0x00
34#define PCIE_INT_ENABLE 0x0c
35#define PCIE_CFG_ADDR 0x20
36#define PCIE_CFG_DATA 0x24
37
38/* PCIe per port registers */
39#define PCIE_BAR0_SETUP 0x10
40#define PCIE_CLASS 0x34
41#define PCIE_LINK_STATUS 0x50
42
43#define PCIE_PORT_INT_EN(x) BIT(20 + (x))
44#define PCIE_PORT_PERST(x) BIT(1 + (x))
45#define PCIE_PORT_LINKUP BIT(0)
46#define PCIE_BAR_MAP_MAX GENMASK(31, 16)
47
48#define PCIE_BAR_ENABLE BIT(0)
49#define PCIE_REVISION_ID BIT(0)
50#define PCIE_CLASS_CODE (0x60400 << 8)
51#define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
52 ((((regn) >> 8) & GENMASK(3, 0)) << 24))
53#define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8))
54#define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11))
55#define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16))
56#define PCIE_CONF_ADDR(regn, fun, dev, bus) \
57 (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \
58 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus))
59
60/* MediaTek specific configuration registers */
61#define PCIE_FTS_NUM 0x70c
62#define PCIE_FTS_NUM_MASK GENMASK(15, 8)
63#define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
64
65#define PCIE_FC_CREDIT 0x73c
66#define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
67#define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
68
69/* PCIe V2 share registers */
70#define PCIE_SYS_CFG_V2 0x0
71#define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8)
72#define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8)
73
74/* PCIe V2 per-port registers */
75#define PCIE_MSI_VECTOR 0x0c0
76
77#define PCIE_CONF_VEND_ID 0x100
78#define PCIE_CONF_DEVICE_ID 0x102
79#define PCIE_CONF_CLASS_ID 0x106
80
81#define PCIE_INT_MASK 0x420
82#define INTX_MASK GENMASK(19, 16)
83#define INTX_SHIFT 16
84#define PCIE_INT_STATUS 0x424
85#define MSI_STATUS BIT(23)
86#define PCIE_IMSI_STATUS 0x42c
87#define PCIE_IMSI_ADDR 0x430
88#define MSI_MASK BIT(23)
89#define MTK_MSI_IRQS_NUM 32
90
91#define PCIE_AHB_TRANS_BASE0_L 0x438
92#define PCIE_AHB_TRANS_BASE0_H 0x43c
93#define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
94#define PCIE_AXI_WINDOW0 0x448
95#define WIN_ENABLE BIT(7)
96/*
97 * Define PCIe to AHB window size as 2^33 to support max 8GB address space
98 * translate, support least 4GB DRAM size access from EP DMA(physical DRAM
99 * start from 0x40000000).
100 */
101#define PCIE2AHB_SIZE 0x21
102
103/* PCIe V2 configuration transaction header */
104#define PCIE_CFG_HEADER0 0x460
105#define PCIE_CFG_HEADER1 0x464
106#define PCIE_CFG_HEADER2 0x468
107#define PCIE_CFG_WDATA 0x470
108#define PCIE_APP_TLP_REQ 0x488
109#define PCIE_CFG_RDATA 0x48c
110#define APP_CFG_REQ BIT(0)
111#define APP_CPL_STATUS GENMASK(7, 5)
112
113#define CFG_WRRD_TYPE_0 4
114#define CFG_WR_FMT 2
115#define CFG_RD_FMT 0
116
117#define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0))
118#define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24))
119#define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29))
120#define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2))
121#define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16))
122#define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19))
123#define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24))
124#define CFG_HEADER_DW0(type, fmt) \
125 (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
126#define CFG_HEADER_DW1(where, size) \
127 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
128#define CFG_HEADER_DW2(regn, fun, dev, bus) \
129 (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
130 CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
131
132#define PCIE_RST_CTRL 0x510
133#define PCIE_PHY_RSTB BIT(0)
134#define PCIE_PIPE_SRSTB BIT(1)
135#define PCIE_MAC_SRSTB BIT(2)
136#define PCIE_CRSTB BIT(3)
137#define PCIE_PERSTB BIT(8)
138#define PCIE_LINKDOWN_RST_EN GENMASK(15, 13)
139#define PCIE_LINK_STATUS_V2 0x804
140#define PCIE_PORT_LINKUP_V2 BIT(10)
141
142struct mtk_pcie_port;
143
144/**
145 * struct mtk_pcie_soc - differentiate between host generations
146 * @need_fix_class_id: whether this host's class ID needed to be fixed or not
147 * @need_fix_device_id: whether this host's device ID needed to be fixed or not
148 * @no_msi: Bridge has no MSI support, and relies on an external block
149 * @device_id: device ID which this host need to be fixed
150 * @ops: pointer to configuration access functions
151 * @startup: pointer to controller setting functions
152 * @setup_irq: pointer to initialize IRQ functions
153 */
154struct mtk_pcie_soc {
155 bool need_fix_class_id;
156 bool need_fix_device_id;
157 bool no_msi;
158 unsigned int device_id;
159 struct pci_ops *ops;
160 int (*startup)(struct mtk_pcie_port *port);
161 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
162};
163
164/**
165 * struct mtk_pcie_port - PCIe port information
166 * @base: IO mapped register base
167 * @list: port list
168 * @pcie: pointer to PCIe host info
169 * @reset: pointer to port reset control
170 * @sys_ck: pointer to transaction/data link layer clock
171 * @ahb_ck: pointer to AHB slave interface operating clock for CSR access
172 * and RC initiated MMIO access
173 * @axi_ck: pointer to application layer MMIO channel operating clock
174 * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock
175 * when pcie_mac_ck/pcie_pipe_ck is turned off
176 * @obff_ck: pointer to OBFF functional block operating clock
177 * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock
178 * @phy: pointer to PHY control block
179 * @slot: port slot
180 * @irq: GIC irq
181 * @irq_domain: legacy INTx IRQ domain
182 * @inner_domain: inner IRQ domain
183 * @msi_domain: MSI IRQ domain
184 * @lock: protect the msi_irq_in_use bitmap
185 * @msi_irq_in_use: bit map for assigned MSI IRQ
186 */
187struct mtk_pcie_port {
188 void __iomem *base;
189 struct list_head list;
190 struct mtk_pcie *pcie;
191 struct reset_control *reset;
192 struct clk *sys_ck;
193 struct clk *ahb_ck;
194 struct clk *axi_ck;
195 struct clk *aux_ck;
196 struct clk *obff_ck;
197 struct clk *pipe_ck;
198 struct phy *phy;
199 u32 slot;
200 int irq;
201 struct irq_domain *irq_domain;
202 struct irq_domain *inner_domain;
203 struct irq_domain *msi_domain;
204 struct mutex lock;
205 DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM);
206};
207
208/**
209 * struct mtk_pcie - PCIe host information
210 * @dev: pointer to PCIe device
211 * @base: IO mapped register base
212 * @cfg: IO mapped register map for PCIe config
213 * @free_ck: free-run reference clock
214 * @mem: non-prefetchable memory resource
215 * @ports: pointer to PCIe port information
216 * @soc: pointer to SoC-dependent operations
217 */
218struct mtk_pcie {
219 struct device *dev;
220 void __iomem *base;
221 struct regmap *cfg;
222 struct clk *free_ck;
223
224 struct list_head ports;
225 const struct mtk_pcie_soc *soc;
226};
227
228static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)
229{
230 struct device *dev = pcie->dev;
231
232 clk_disable_unprepare(pcie->free_ck);
233
234 pm_runtime_put_sync(dev);
235 pm_runtime_disable(dev);
236}
237
238static void mtk_pcie_port_free(struct mtk_pcie_port *port)
239{
240 struct mtk_pcie *pcie = port->pcie;
241 struct device *dev = pcie->dev;
242
243 devm_iounmap(dev, port->base);
244 list_del(&port->list);
245 devm_kfree(dev, port);
246}
247
248static void mtk_pcie_put_resources(struct mtk_pcie *pcie)
249{
250 struct mtk_pcie_port *port, *tmp;
251
252 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
253 phy_power_off(port->phy);
254 phy_exit(port->phy);
255 clk_disable_unprepare(port->pipe_ck);
256 clk_disable_unprepare(port->obff_ck);
257 clk_disable_unprepare(port->axi_ck);
258 clk_disable_unprepare(port->aux_ck);
259 clk_disable_unprepare(port->ahb_ck);
260 clk_disable_unprepare(port->sys_ck);
261 mtk_pcie_port_free(port);
262 }
263
264 mtk_pcie_subsys_powerdown(pcie);
265}
266
267static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
268{
269 u32 val;
270 int err;
271
272 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val,
273 !(val & APP_CFG_REQ), 10,
274 100 * USEC_PER_MSEC);
275 if (err)
276 return PCIBIOS_SET_FAILED;
277
278 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
279 return PCIBIOS_SET_FAILED;
280
281 return PCIBIOS_SUCCESSFUL;
282}
283
284static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
285 int where, int size, u32 *val)
286{
287 u32 tmp;
288
289 /* Write PCIe configuration transaction header for Cfgrd */
290 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
291 port->base + PCIE_CFG_HEADER0);
292 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
293 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
294 port->base + PCIE_CFG_HEADER2);
295
296 /* Trigger h/w to transmit Cfgrd TLP */
297 tmp = readl(port->base + PCIE_APP_TLP_REQ);
298 tmp |= APP_CFG_REQ;
299 writel(tmp, port->base + PCIE_APP_TLP_REQ);
300
301 /* Check completion status */
302 if (mtk_pcie_check_cfg_cpld(port))
303 return PCIBIOS_SET_FAILED;
304
305 /* Read cpld payload of Cfgrd */
306 *val = readl(port->base + PCIE_CFG_RDATA);
307
308 if (size == 1)
309 *val = (*val >> (8 * (where & 3))) & 0xff;
310 else if (size == 2)
311 *val = (*val >> (8 * (where & 3))) & 0xffff;
312
313 return PCIBIOS_SUCCESSFUL;
314}
315
316static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
317 int where, int size, u32 val)
318{
319 /* Write PCIe configuration transaction header for Cfgwr */
320 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
321 port->base + PCIE_CFG_HEADER0);
322 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
323 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
324 port->base + PCIE_CFG_HEADER2);
325
326 /* Write Cfgwr data */
327 val = val << 8 * (where & 3);
328 writel(val, port->base + PCIE_CFG_WDATA);
329
330 /* Trigger h/w to transmit Cfgwr TLP */
331 val = readl(port->base + PCIE_APP_TLP_REQ);
332 val |= APP_CFG_REQ;
333 writel(val, port->base + PCIE_APP_TLP_REQ);
334
335 /* Check completion status */
336 return mtk_pcie_check_cfg_cpld(port);
337}
338
339static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus,
340 unsigned int devfn)
341{
342 struct mtk_pcie *pcie = bus->sysdata;
343 struct mtk_pcie_port *port;
344 struct pci_dev *dev = NULL;
345
346 /*
347 * Walk the bus hierarchy to get the devfn value
348 * of the port in the root bus.
349 */
350 while (bus && bus->number) {
351 dev = bus->self;
352 bus = dev->bus;
353 devfn = dev->devfn;
354 }
355
356 list_for_each_entry(port, &pcie->ports, list)
357 if (port->slot == PCI_SLOT(devfn))
358 return port;
359
360 return NULL;
361}
362
363static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
364 int where, int size, u32 *val)
365{
366 struct mtk_pcie_port *port;
367 u32 bn = bus->number;
368
369 port = mtk_pcie_find_port(bus, devfn);
370 if (!port)
371 return PCIBIOS_DEVICE_NOT_FOUND;
372
373 return mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val);
374}
375
376static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
377 int where, int size, u32 val)
378{
379 struct mtk_pcie_port *port;
380 u32 bn = bus->number;
381
382 port = mtk_pcie_find_port(bus, devfn);
383 if (!port)
384 return PCIBIOS_DEVICE_NOT_FOUND;
385
386 return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val);
387}
388
389static struct pci_ops mtk_pcie_ops_v2 = {
390 .read = mtk_pcie_config_read,
391 .write = mtk_pcie_config_write,
392};
393
394static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
395{
396 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
397 phys_addr_t addr;
398
399 /* MT2712/MT7622 only support 32-bit MSI addresses */
400 addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
401 msg->address_hi = 0;
402 msg->address_lo = lower_32_bits(addr);
403
404 msg->data = data->hwirq;
405
406 dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n",
407 (int)data->hwirq, msg->address_hi, msg->address_lo);
408}
409
410static int mtk_msi_set_affinity(struct irq_data *irq_data,
411 const struct cpumask *mask, bool force)
412{
413 return -EINVAL;
414}
415
416static void mtk_msi_ack_irq(struct irq_data *data)
417{
418 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
419 u32 hwirq = data->hwirq;
420
421 writel(1 << hwirq, port->base + PCIE_IMSI_STATUS);
422}
423
424static struct irq_chip mtk_msi_bottom_irq_chip = {
425 .name = "MTK MSI",
426 .irq_compose_msi_msg = mtk_compose_msi_msg,
427 .irq_set_affinity = mtk_msi_set_affinity,
428 .irq_ack = mtk_msi_ack_irq,
429};
430
431static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
432 unsigned int nr_irqs, void *args)
433{
434 struct mtk_pcie_port *port = domain->host_data;
435 unsigned long bit;
436
437 WARN_ON(nr_irqs != 1);
438 mutex_lock(&port->lock);
439
440 bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);
441 if (bit >= MTK_MSI_IRQS_NUM) {
442 mutex_unlock(&port->lock);
443 return -ENOSPC;
444 }
445
446 __set_bit(bit, port->msi_irq_in_use);
447
448 mutex_unlock(&port->lock);
449
450 irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip,
451 domain->host_data, handle_edge_irq,
452 NULL, NULL);
453
454 return 0;
455}
456
457static void mtk_pcie_irq_domain_free(struct irq_domain *domain,
458 unsigned int virq, unsigned int nr_irqs)
459{
460 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
461 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d);
462
463 mutex_lock(&port->lock);
464
465 if (!test_bit(d->hwirq, port->msi_irq_in_use))
466 dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n",
467 d->hwirq);
468 else
469 __clear_bit(d->hwirq, port->msi_irq_in_use);
470
471 mutex_unlock(&port->lock);
472
473 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
474}
475
476static const struct irq_domain_ops msi_domain_ops = {
477 .alloc = mtk_pcie_irq_domain_alloc,
478 .free = mtk_pcie_irq_domain_free,
479};
480
481static struct irq_chip mtk_msi_irq_chip = {
482 .name = "MTK PCIe MSI",
483 .irq_ack = irq_chip_ack_parent,
484 .irq_mask = pci_msi_mask_irq,
485 .irq_unmask = pci_msi_unmask_irq,
486};
487
488static struct msi_domain_info mtk_msi_domain_info = {
489 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
490 MSI_FLAG_PCI_MSIX),
491 .chip = &mtk_msi_irq_chip,
492};
493
494static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port)
495{
496 struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node);
497
498 mutex_init(&port->lock);
499
500 port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM,
501 &msi_domain_ops, port);
502 if (!port->inner_domain) {
503 dev_err(port->pcie->dev, "failed to create IRQ domain\n");
504 return -ENOMEM;
505 }
506
507 port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info,
508 port->inner_domain);
509 if (!port->msi_domain) {
510 dev_err(port->pcie->dev, "failed to create MSI domain\n");
511 irq_domain_remove(port->inner_domain);
512 return -ENOMEM;
513 }
514
515 return 0;
516}
517
518static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
519{
520 u32 val;
521 phys_addr_t msg_addr;
522
523 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
524 val = lower_32_bits(msg_addr);
525 writel(val, port->base + PCIE_IMSI_ADDR);
526
527 val = readl(port->base + PCIE_INT_MASK);
528 val &= ~MSI_MASK;
529 writel(val, port->base + PCIE_INT_MASK);
530}
531
532static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie)
533{
534 struct mtk_pcie_port *port, *tmp;
535
536 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
537 irq_set_chained_handler_and_data(port->irq, NULL, NULL);
538
539 if (port->irq_domain)
540 irq_domain_remove(port->irq_domain);
541
542 if (IS_ENABLED(CONFIG_PCI_MSI)) {
543 if (port->msi_domain)
544 irq_domain_remove(port->msi_domain);
545 if (port->inner_domain)
546 irq_domain_remove(port->inner_domain);
547 }
548
549 irq_dispose_mapping(port->irq);
550 }
551}
552
553static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
554 irq_hw_number_t hwirq)
555{
556 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
557 irq_set_chip_data(irq, domain->host_data);
558
559 return 0;
560}
561
562static const struct irq_domain_ops intx_domain_ops = {
563 .map = mtk_pcie_intx_map,
564};
565
566static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
567 struct device_node *node)
568{
569 struct device *dev = port->pcie->dev;
570 struct device_node *pcie_intc_node;
571 int ret;
572
573 /* Setup INTx */
574 pcie_intc_node = of_get_next_child(node, NULL);
575 if (!pcie_intc_node) {
576 dev_err(dev, "no PCIe Intc node found\n");
577 return -ENODEV;
578 }
579
580 port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
581 &intx_domain_ops, port);
582 of_node_put(pcie_intc_node);
583 if (!port->irq_domain) {
584 dev_err(dev, "failed to get INTx IRQ domain\n");
585 return -ENODEV;
586 }
587
588 if (IS_ENABLED(CONFIG_PCI_MSI)) {
589 ret = mtk_pcie_allocate_msi_domains(port);
590 if (ret)
591 return ret;
592 }
593
594 return 0;
595}
596
597static void mtk_pcie_intr_handler(struct irq_desc *desc)
598{
599 struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
600 struct irq_chip *irqchip = irq_desc_get_chip(desc);
601 unsigned long status;
602 u32 bit = INTX_SHIFT;
603
604 chained_irq_enter(irqchip, desc);
605
606 status = readl(port->base + PCIE_INT_STATUS);
607 if (status & INTX_MASK) {
608 for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
609 /* Clear the INTx */
610 writel(1 << bit, port->base + PCIE_INT_STATUS);
611 generic_handle_domain_irq(port->irq_domain,
612 bit - INTX_SHIFT);
613 }
614 }
615
616 if (IS_ENABLED(CONFIG_PCI_MSI)) {
617 if (status & MSI_STATUS){
618 unsigned long imsi_status;
619
620 /*
621 * The interrupt status can be cleared even if the
622 * MSI status remains pending. As such, given the
623 * edge-triggered interrupt type, its status should
624 * be cleared before being dispatched to the
625 * handler of the underlying device.
626 */
627 writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
628 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
629 for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM)
630 generic_handle_domain_irq(port->inner_domain, bit);
631 }
632 }
633 }
634
635 chained_irq_exit(irqchip, desc);
636}
637
638static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
639 struct device_node *node)
640{
641 struct mtk_pcie *pcie = port->pcie;
642 struct device *dev = pcie->dev;
643 struct platform_device *pdev = to_platform_device(dev);
644 int err;
645
646 err = mtk_pcie_init_irq_domain(port, node);
647 if (err) {
648 dev_err(dev, "failed to init PCIe IRQ domain\n");
649 return err;
650 }
651
652 if (of_property_present(dev->of_node, "interrupt-names"))
653 port->irq = platform_get_irq_byname(pdev, "pcie_irq");
654 else
655 port->irq = platform_get_irq(pdev, port->slot);
656
657 if (port->irq < 0)
658 return port->irq;
659
660 irq_set_chained_handler_and_data(port->irq,
661 mtk_pcie_intr_handler, port);
662
663 return 0;
664}
665
666static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
667{
668 struct mtk_pcie *pcie = port->pcie;
669 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
670 struct resource *mem = NULL;
671 struct resource_entry *entry;
672 const struct mtk_pcie_soc *soc = port->pcie->soc;
673 u32 val;
674 int err;
675
676 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
677 if (entry)
678 mem = entry->res;
679 if (!mem)
680 return -EINVAL;
681
682 /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
683 if (pcie->base) {
684 val = readl(pcie->base + PCIE_SYS_CFG_V2);
685 val |= PCIE_CSR_LTSSM_EN(port->slot) |
686 PCIE_CSR_ASPM_L1_EN(port->slot);
687 writel(val, pcie->base + PCIE_SYS_CFG_V2);
688 } else if (pcie->cfg) {
689 val = PCIE_CSR_LTSSM_EN(port->slot) |
690 PCIE_CSR_ASPM_L1_EN(port->slot);
691 regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val);
692 }
693
694 /* Assert all reset signals */
695 writel(0, port->base + PCIE_RST_CTRL);
696
697 /*
698 * Enable PCIe link down reset, if link status changed from link up to
699 * link down, this will reset MAC control registers and configuration
700 * space.
701 */
702 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
703
704 /*
705 * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
706 * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
707 * be delayed 100ms (TPVPERL) for the power and clock to become stable.
708 */
709 msleep(100);
710
711 /* De-assert PHY, PE, PIPE, MAC and configuration reset */
712 val = readl(port->base + PCIE_RST_CTRL);
713 val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
714 PCIE_MAC_SRSTB | PCIE_CRSTB;
715 writel(val, port->base + PCIE_RST_CTRL);
716
717 /* Set up vendor ID and class code */
718 if (soc->need_fix_class_id) {
719 val = PCI_VENDOR_ID_MEDIATEK;
720 writew(val, port->base + PCIE_CONF_VEND_ID);
721
722 val = PCI_CLASS_BRIDGE_PCI;
723 writew(val, port->base + PCIE_CONF_CLASS_ID);
724 }
725
726 if (soc->need_fix_device_id)
727 writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID);
728
729 /* 100ms timeout value should be enough for Gen1/2 training */
730 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
731 !!(val & PCIE_PORT_LINKUP_V2), 20,
732 100 * USEC_PER_MSEC);
733 if (err)
734 return -ETIMEDOUT;
735
736 /* Set INTx mask */
737 val = readl(port->base + PCIE_INT_MASK);
738 val &= ~INTX_MASK;
739 writel(val, port->base + PCIE_INT_MASK);
740
741 if (IS_ENABLED(CONFIG_PCI_MSI))
742 mtk_pcie_enable_msi(port);
743
744 /* Set AHB to PCIe translation windows */
745 val = lower_32_bits(mem->start) |
746 AHB2PCIE_SIZE(fls(resource_size(mem)));
747 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
748
749 val = upper_32_bits(mem->start);
750 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
751
752 /* Set PCIe to AXI translation memory space.*/
753 val = PCIE2AHB_SIZE | WIN_ENABLE;
754 writel(val, port->base + PCIE_AXI_WINDOW0);
755
756 return 0;
757}
758
759static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
760 unsigned int devfn, int where)
761{
762 struct mtk_pcie *pcie = bus->sysdata;
763
764 writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn),
765 bus->number), pcie->base + PCIE_CFG_ADDR);
766
767 return pcie->base + PCIE_CFG_DATA + (where & 3);
768}
769
770static struct pci_ops mtk_pcie_ops = {
771 .map_bus = mtk_pcie_map_bus,
772 .read = pci_generic_config_read,
773 .write = pci_generic_config_write,
774};
775
776static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
777{
778 struct mtk_pcie *pcie = port->pcie;
779 u32 func = PCI_FUNC(port->slot);
780 u32 slot = PCI_SLOT(port->slot << 3);
781 u32 val;
782 int err;
783
784 /* assert port PERST_N */
785 val = readl(pcie->base + PCIE_SYS_CFG);
786 val |= PCIE_PORT_PERST(port->slot);
787 writel(val, pcie->base + PCIE_SYS_CFG);
788
789 /* de-assert port PERST_N */
790 val = readl(pcie->base + PCIE_SYS_CFG);
791 val &= ~PCIE_PORT_PERST(port->slot);
792 writel(val, pcie->base + PCIE_SYS_CFG);
793
794 /* 100ms timeout value should be enough for Gen1/2 training */
795 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
796 !!(val & PCIE_PORT_LINKUP), 20,
797 100 * USEC_PER_MSEC);
798 if (err)
799 return -ETIMEDOUT;
800
801 /* enable interrupt */
802 val = readl(pcie->base + PCIE_INT_ENABLE);
803 val |= PCIE_PORT_INT_EN(port->slot);
804 writel(val, pcie->base + PCIE_INT_ENABLE);
805
806 /* map to all DDR region. We need to set it before cfg operation. */
807 writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
808 port->base + PCIE_BAR0_SETUP);
809
810 /* configure class code and revision ID */
811 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
812
813 /* configure FC credit */
814 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
815 pcie->base + PCIE_CFG_ADDR);
816 val = readl(pcie->base + PCIE_CFG_DATA);
817 val &= ~PCIE_FC_CREDIT_MASK;
818 val |= PCIE_FC_CREDIT_VAL(0x806c);
819 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
820 pcie->base + PCIE_CFG_ADDR);
821 writel(val, pcie->base + PCIE_CFG_DATA);
822
823 /* configure RC FTS number to 250 when it leaves L0s */
824 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
825 pcie->base + PCIE_CFG_ADDR);
826 val = readl(pcie->base + PCIE_CFG_DATA);
827 val &= ~PCIE_FTS_NUM_MASK;
828 val |= PCIE_FTS_NUM_L0(0x50);
829 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
830 pcie->base + PCIE_CFG_ADDR);
831 writel(val, pcie->base + PCIE_CFG_DATA);
832
833 return 0;
834}
835
836static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
837{
838 struct mtk_pcie *pcie = port->pcie;
839 struct device *dev = pcie->dev;
840 int err;
841
842 err = clk_prepare_enable(port->sys_ck);
843 if (err) {
844 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot);
845 goto err_sys_clk;
846 }
847
848 err = clk_prepare_enable(port->ahb_ck);
849 if (err) {
850 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot);
851 goto err_ahb_clk;
852 }
853
854 err = clk_prepare_enable(port->aux_ck);
855 if (err) {
856 dev_err(dev, "failed to enable aux_ck%d\n", port->slot);
857 goto err_aux_clk;
858 }
859
860 err = clk_prepare_enable(port->axi_ck);
861 if (err) {
862 dev_err(dev, "failed to enable axi_ck%d\n", port->slot);
863 goto err_axi_clk;
864 }
865
866 err = clk_prepare_enable(port->obff_ck);
867 if (err) {
868 dev_err(dev, "failed to enable obff_ck%d\n", port->slot);
869 goto err_obff_clk;
870 }
871
872 err = clk_prepare_enable(port->pipe_ck);
873 if (err) {
874 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot);
875 goto err_pipe_clk;
876 }
877
878 reset_control_assert(port->reset);
879 reset_control_deassert(port->reset);
880
881 err = phy_init(port->phy);
882 if (err) {
883 dev_err(dev, "failed to initialize port%d phy\n", port->slot);
884 goto err_phy_init;
885 }
886
887 err = phy_power_on(port->phy);
888 if (err) {
889 dev_err(dev, "failed to power on port%d phy\n", port->slot);
890 goto err_phy_on;
891 }
892
893 if (!pcie->soc->startup(port))
894 return;
895
896 dev_info(dev, "Port%d link down\n", port->slot);
897
898 phy_power_off(port->phy);
899err_phy_on:
900 phy_exit(port->phy);
901err_phy_init:
902 clk_disable_unprepare(port->pipe_ck);
903err_pipe_clk:
904 clk_disable_unprepare(port->obff_ck);
905err_obff_clk:
906 clk_disable_unprepare(port->axi_ck);
907err_axi_clk:
908 clk_disable_unprepare(port->aux_ck);
909err_aux_clk:
910 clk_disable_unprepare(port->ahb_ck);
911err_ahb_clk:
912 clk_disable_unprepare(port->sys_ck);
913err_sys_clk:
914 mtk_pcie_port_free(port);
915}
916
917static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
918 struct device_node *node,
919 int slot)
920{
921 struct mtk_pcie_port *port;
922 struct device *dev = pcie->dev;
923 struct platform_device *pdev = to_platform_device(dev);
924 char name[10];
925 int err;
926
927 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
928 if (!port)
929 return -ENOMEM;
930
931 snprintf(name, sizeof(name), "port%d", slot);
932 port->base = devm_platform_ioremap_resource_byname(pdev, name);
933 if (IS_ERR(port->base)) {
934 dev_err(dev, "failed to map port%d base\n", slot);
935 return PTR_ERR(port->base);
936 }
937
938 snprintf(name, sizeof(name), "sys_ck%d", slot);
939 port->sys_ck = devm_clk_get(dev, name);
940 if (IS_ERR(port->sys_ck)) {
941 dev_err(dev, "failed to get sys_ck%d clock\n", slot);
942 return PTR_ERR(port->sys_ck);
943 }
944
945 /* sys_ck might be divided into the following parts in some chips */
946 snprintf(name, sizeof(name), "ahb_ck%d", slot);
947 port->ahb_ck = devm_clk_get_optional(dev, name);
948 if (IS_ERR(port->ahb_ck))
949 return PTR_ERR(port->ahb_ck);
950
951 snprintf(name, sizeof(name), "axi_ck%d", slot);
952 port->axi_ck = devm_clk_get_optional(dev, name);
953 if (IS_ERR(port->axi_ck))
954 return PTR_ERR(port->axi_ck);
955
956 snprintf(name, sizeof(name), "aux_ck%d", slot);
957 port->aux_ck = devm_clk_get_optional(dev, name);
958 if (IS_ERR(port->aux_ck))
959 return PTR_ERR(port->aux_ck);
960
961 snprintf(name, sizeof(name), "obff_ck%d", slot);
962 port->obff_ck = devm_clk_get_optional(dev, name);
963 if (IS_ERR(port->obff_ck))
964 return PTR_ERR(port->obff_ck);
965
966 snprintf(name, sizeof(name), "pipe_ck%d", slot);
967 port->pipe_ck = devm_clk_get_optional(dev, name);
968 if (IS_ERR(port->pipe_ck))
969 return PTR_ERR(port->pipe_ck);
970
971 snprintf(name, sizeof(name), "pcie-rst%d", slot);
972 port->reset = devm_reset_control_get_optional_exclusive(dev, name);
973 if (PTR_ERR(port->reset) == -EPROBE_DEFER)
974 return PTR_ERR(port->reset);
975
976 /* some platforms may use default PHY setting */
977 snprintf(name, sizeof(name), "pcie-phy%d", slot);
978 port->phy = devm_phy_optional_get(dev, name);
979 if (IS_ERR(port->phy))
980 return PTR_ERR(port->phy);
981
982 port->slot = slot;
983 port->pcie = pcie;
984
985 if (pcie->soc->setup_irq) {
986 err = pcie->soc->setup_irq(port, node);
987 if (err)
988 return err;
989 }
990
991 INIT_LIST_HEAD(&port->list);
992 list_add_tail(&port->list, &pcie->ports);
993
994 return 0;
995}
996
997static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
998{
999 struct device *dev = pcie->dev;
1000 struct platform_device *pdev = to_platform_device(dev);
1001 struct resource *regs;
1002 struct device_node *cfg_node;
1003 int err;
1004
1005 /* get shared registers, which are optional */
1006 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys");
1007 if (regs) {
1008 pcie->base = devm_ioremap_resource(dev, regs);
1009 if (IS_ERR(pcie->base))
1010 return PTR_ERR(pcie->base);
1011 }
1012
1013 cfg_node = of_find_compatible_node(NULL, NULL,
1014 "mediatek,generic-pciecfg");
1015 if (cfg_node) {
1016 pcie->cfg = syscon_node_to_regmap(cfg_node);
1017 of_node_put(cfg_node);
1018 if (IS_ERR(pcie->cfg))
1019 return PTR_ERR(pcie->cfg);
1020 }
1021
1022 pcie->free_ck = devm_clk_get(dev, "free_ck");
1023 if (IS_ERR(pcie->free_ck)) {
1024 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
1025 return -EPROBE_DEFER;
1026
1027 pcie->free_ck = NULL;
1028 }
1029
1030 pm_runtime_enable(dev);
1031 pm_runtime_get_sync(dev);
1032
1033 /* enable top level clock */
1034 err = clk_prepare_enable(pcie->free_ck);
1035 if (err) {
1036 dev_err(dev, "failed to enable free_ck\n");
1037 goto err_free_ck;
1038 }
1039
1040 return 0;
1041
1042err_free_ck:
1043 pm_runtime_put_sync(dev);
1044 pm_runtime_disable(dev);
1045
1046 return err;
1047}
1048
1049static int mtk_pcie_setup(struct mtk_pcie *pcie)
1050{
1051 struct device *dev = pcie->dev;
1052 struct device_node *node = dev->of_node, *child;
1053 struct mtk_pcie_port *port, *tmp;
1054 int err, slot;
1055
1056 slot = of_get_pci_domain_nr(dev->of_node);
1057 if (slot < 0) {
1058 for_each_available_child_of_node(node, child) {
1059 err = of_pci_get_devfn(child);
1060 if (err < 0) {
1061 dev_err(dev, "failed to get devfn: %d\n", err);
1062 goto error_put_node;
1063 }
1064
1065 slot = PCI_SLOT(err);
1066
1067 err = mtk_pcie_parse_port(pcie, child, slot);
1068 if (err)
1069 goto error_put_node;
1070 }
1071 } else {
1072 err = mtk_pcie_parse_port(pcie, node, slot);
1073 if (err)
1074 return err;
1075 }
1076
1077 err = mtk_pcie_subsys_powerup(pcie);
1078 if (err)
1079 return err;
1080
1081 /* enable each port, and then check link status */
1082 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1083 mtk_pcie_enable_port(port);
1084
1085 /* power down PCIe subsys if slots are all empty (link down) */
1086 if (list_empty(&pcie->ports))
1087 mtk_pcie_subsys_powerdown(pcie);
1088
1089 return 0;
1090error_put_node:
1091 of_node_put(child);
1092 return err;
1093}
1094
1095static int mtk_pcie_probe(struct platform_device *pdev)
1096{
1097 struct device *dev = &pdev->dev;
1098 struct mtk_pcie *pcie;
1099 struct pci_host_bridge *host;
1100 int err;
1101
1102 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
1103 if (!host)
1104 return -ENOMEM;
1105
1106 pcie = pci_host_bridge_priv(host);
1107
1108 pcie->dev = dev;
1109 pcie->soc = of_device_get_match_data(dev);
1110 platform_set_drvdata(pdev, pcie);
1111 INIT_LIST_HEAD(&pcie->ports);
1112
1113 err = mtk_pcie_setup(pcie);
1114 if (err)
1115 return err;
1116
1117 host->ops = pcie->soc->ops;
1118 host->sysdata = pcie;
1119 host->msi_domain = pcie->soc->no_msi;
1120
1121 err = pci_host_probe(host);
1122 if (err)
1123 goto put_resources;
1124
1125 return 0;
1126
1127put_resources:
1128 if (!list_empty(&pcie->ports))
1129 mtk_pcie_put_resources(pcie);
1130
1131 return err;
1132}
1133
1134
1135static void mtk_pcie_free_resources(struct mtk_pcie *pcie)
1136{
1137 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1138 struct list_head *windows = &host->windows;
1139
1140 pci_free_resource_list(windows);
1141}
1142
1143static void mtk_pcie_remove(struct platform_device *pdev)
1144{
1145 struct mtk_pcie *pcie = platform_get_drvdata(pdev);
1146 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1147
1148 pci_stop_root_bus(host->bus);
1149 pci_remove_root_bus(host->bus);
1150 mtk_pcie_free_resources(pcie);
1151
1152 mtk_pcie_irq_teardown(pcie);
1153
1154 mtk_pcie_put_resources(pcie);
1155}
1156
1157static int mtk_pcie_suspend_noirq(struct device *dev)
1158{
1159 struct mtk_pcie *pcie = dev_get_drvdata(dev);
1160 struct mtk_pcie_port *port;
1161
1162 if (list_empty(&pcie->ports))
1163 return 0;
1164
1165 list_for_each_entry(port, &pcie->ports, list) {
1166 clk_disable_unprepare(port->pipe_ck);
1167 clk_disable_unprepare(port->obff_ck);
1168 clk_disable_unprepare(port->axi_ck);
1169 clk_disable_unprepare(port->aux_ck);
1170 clk_disable_unprepare(port->ahb_ck);
1171 clk_disable_unprepare(port->sys_ck);
1172 phy_power_off(port->phy);
1173 phy_exit(port->phy);
1174 }
1175
1176 clk_disable_unprepare(pcie->free_ck);
1177
1178 return 0;
1179}
1180
1181static int mtk_pcie_resume_noirq(struct device *dev)
1182{
1183 struct mtk_pcie *pcie = dev_get_drvdata(dev);
1184 struct mtk_pcie_port *port, *tmp;
1185
1186 if (list_empty(&pcie->ports))
1187 return 0;
1188
1189 clk_prepare_enable(pcie->free_ck);
1190
1191 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1192 mtk_pcie_enable_port(port);
1193
1194 /* In case of EP was removed while system suspend. */
1195 if (list_empty(&pcie->ports))
1196 clk_disable_unprepare(pcie->free_ck);
1197
1198 return 0;
1199}
1200
1201static const struct dev_pm_ops mtk_pcie_pm_ops = {
1202 NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
1203 mtk_pcie_resume_noirq)
1204};
1205
1206static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
1207 .no_msi = true,
1208 .ops = &mtk_pcie_ops,
1209 .startup = mtk_pcie_startup_port,
1210};
1211
1212static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = {
1213 .ops = &mtk_pcie_ops_v2,
1214 .startup = mtk_pcie_startup_port_v2,
1215 .setup_irq = mtk_pcie_setup_irq,
1216};
1217
1218static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = {
1219 .need_fix_class_id = true,
1220 .ops = &mtk_pcie_ops_v2,
1221 .startup = mtk_pcie_startup_port_v2,
1222 .setup_irq = mtk_pcie_setup_irq,
1223};
1224
1225static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {
1226 .need_fix_class_id = true,
1227 .need_fix_device_id = true,
1228 .device_id = PCI_DEVICE_ID_MEDIATEK_7629,
1229 .ops = &mtk_pcie_ops_v2,
1230 .startup = mtk_pcie_startup_port_v2,
1231 .setup_irq = mtk_pcie_setup_irq,
1232};
1233
1234static const struct of_device_id mtk_pcie_ids[] = {
1235 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1236 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1237 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
1238 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
1239 { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
1240 {},
1241};
1242MODULE_DEVICE_TABLE(of, mtk_pcie_ids);
1243
1244static struct platform_driver mtk_pcie_driver = {
1245 .probe = mtk_pcie_probe,
1246 .remove_new = mtk_pcie_remove,
1247 .driver = {
1248 .name = "mtk-pcie",
1249 .of_match_table = mtk_pcie_ids,
1250 .suppress_bind_attrs = true,
1251 .pm = &mtk_pcie_pm_ops,
1252 },
1253};
1254module_platform_driver(mtk_pcie_driver);
1255MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek PCIe host controller driver.
4 *
5 * Copyright (c) 2017 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
7 * Honghui Zhang <honghui.zhang@mediatek.com>
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/iopoll.h>
13#include <linux/irq.h>
14#include <linux/irqchip/chained_irq.h>
15#include <linux/irqdomain.h>
16#include <linux/kernel.h>
17#include <linux/msi.h>
18#include <linux/module.h>
19#include <linux/of_address.h>
20#include <linux/of_pci.h>
21#include <linux/of_platform.h>
22#include <linux/pci.h>
23#include <linux/phy/phy.h>
24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h>
26#include <linux/reset.h>
27
28#include "../pci.h"
29
30/* PCIe shared registers */
31#define PCIE_SYS_CFG 0x00
32#define PCIE_INT_ENABLE 0x0c
33#define PCIE_CFG_ADDR 0x20
34#define PCIE_CFG_DATA 0x24
35
36/* PCIe per port registers */
37#define PCIE_BAR0_SETUP 0x10
38#define PCIE_CLASS 0x34
39#define PCIE_LINK_STATUS 0x50
40
41#define PCIE_PORT_INT_EN(x) BIT(20 + (x))
42#define PCIE_PORT_PERST(x) BIT(1 + (x))
43#define PCIE_PORT_LINKUP BIT(0)
44#define PCIE_BAR_MAP_MAX GENMASK(31, 16)
45
46#define PCIE_BAR_ENABLE BIT(0)
47#define PCIE_REVISION_ID BIT(0)
48#define PCIE_CLASS_CODE (0x60400 << 8)
49#define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
50 ((((regn) >> 8) & GENMASK(3, 0)) << 24))
51#define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8))
52#define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11))
53#define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16))
54#define PCIE_CONF_ADDR(regn, fun, dev, bus) \
55 (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \
56 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus))
57
58/* MediaTek specific configuration registers */
59#define PCIE_FTS_NUM 0x70c
60#define PCIE_FTS_NUM_MASK GENMASK(15, 8)
61#define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
62
63#define PCIE_FC_CREDIT 0x73c
64#define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
65#define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
66
67/* PCIe V2 share registers */
68#define PCIE_SYS_CFG_V2 0x0
69#define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8)
70#define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8)
71
72/* PCIe V2 per-port registers */
73#define PCIE_MSI_VECTOR 0x0c0
74
75#define PCIE_CONF_VEND_ID 0x100
76#define PCIE_CONF_DEVICE_ID 0x102
77#define PCIE_CONF_CLASS_ID 0x106
78
79#define PCIE_INT_MASK 0x420
80#define INTX_MASK GENMASK(19, 16)
81#define INTX_SHIFT 16
82#define PCIE_INT_STATUS 0x424
83#define MSI_STATUS BIT(23)
84#define PCIE_IMSI_STATUS 0x42c
85#define PCIE_IMSI_ADDR 0x430
86#define MSI_MASK BIT(23)
87#define MTK_MSI_IRQS_NUM 32
88
89#define PCIE_AHB_TRANS_BASE0_L 0x438
90#define PCIE_AHB_TRANS_BASE0_H 0x43c
91#define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
92#define PCIE_AXI_WINDOW0 0x448
93#define WIN_ENABLE BIT(7)
94/*
95 * Define PCIe to AHB window size as 2^33 to support max 8GB address space
96 * translate, support least 4GB DRAM size access from EP DMA(physical DRAM
97 * start from 0x40000000).
98 */
99#define PCIE2AHB_SIZE 0x21
100
101/* PCIe V2 configuration transaction header */
102#define PCIE_CFG_HEADER0 0x460
103#define PCIE_CFG_HEADER1 0x464
104#define PCIE_CFG_HEADER2 0x468
105#define PCIE_CFG_WDATA 0x470
106#define PCIE_APP_TLP_REQ 0x488
107#define PCIE_CFG_RDATA 0x48c
108#define APP_CFG_REQ BIT(0)
109#define APP_CPL_STATUS GENMASK(7, 5)
110
111#define CFG_WRRD_TYPE_0 4
112#define CFG_WR_FMT 2
113#define CFG_RD_FMT 0
114
115#define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0))
116#define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24))
117#define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29))
118#define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2))
119#define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16))
120#define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19))
121#define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24))
122#define CFG_HEADER_DW0(type, fmt) \
123 (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
124#define CFG_HEADER_DW1(where, size) \
125 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
126#define CFG_HEADER_DW2(regn, fun, dev, bus) \
127 (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
128 CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
129
130#define PCIE_RST_CTRL 0x510
131#define PCIE_PHY_RSTB BIT(0)
132#define PCIE_PIPE_SRSTB BIT(1)
133#define PCIE_MAC_SRSTB BIT(2)
134#define PCIE_CRSTB BIT(3)
135#define PCIE_PERSTB BIT(8)
136#define PCIE_LINKDOWN_RST_EN GENMASK(15, 13)
137#define PCIE_LINK_STATUS_V2 0x804
138#define PCIE_PORT_LINKUP_V2 BIT(10)
139
140struct mtk_pcie_port;
141
142/**
143 * struct mtk_pcie_soc - differentiate between host generations
144 * @need_fix_class_id: whether this host's class ID needed to be fixed or not
145 * @need_fix_device_id: whether this host's device ID needed to be fixed or not
146 * @device_id: device ID which this host need to be fixed
147 * @ops: pointer to configuration access functions
148 * @startup: pointer to controller setting functions
149 * @setup_irq: pointer to initialize IRQ functions
150 */
151struct mtk_pcie_soc {
152 bool need_fix_class_id;
153 bool need_fix_device_id;
154 unsigned int device_id;
155 struct pci_ops *ops;
156 int (*startup)(struct mtk_pcie_port *port);
157 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
158};
159
160/**
161 * struct mtk_pcie_port - PCIe port information
162 * @base: IO mapped register base
163 * @list: port list
164 * @pcie: pointer to PCIe host info
165 * @reset: pointer to port reset control
166 * @sys_ck: pointer to transaction/data link layer clock
167 * @ahb_ck: pointer to AHB slave interface operating clock for CSR access
168 * and RC initiated MMIO access
169 * @axi_ck: pointer to application layer MMIO channel operating clock
170 * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock
171 * when pcie_mac_ck/pcie_pipe_ck is turned off
172 * @obff_ck: pointer to OBFF functional block operating clock
173 * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock
174 * @phy: pointer to PHY control block
175 * @slot: port slot
176 * @irq: GIC irq
177 * @irq_domain: legacy INTx IRQ domain
178 * @inner_domain: inner IRQ domain
179 * @msi_domain: MSI IRQ domain
180 * @lock: protect the msi_irq_in_use bitmap
181 * @msi_irq_in_use: bit map for assigned MSI IRQ
182 */
183struct mtk_pcie_port {
184 void __iomem *base;
185 struct list_head list;
186 struct mtk_pcie *pcie;
187 struct reset_control *reset;
188 struct clk *sys_ck;
189 struct clk *ahb_ck;
190 struct clk *axi_ck;
191 struct clk *aux_ck;
192 struct clk *obff_ck;
193 struct clk *pipe_ck;
194 struct phy *phy;
195 u32 slot;
196 int irq;
197 struct irq_domain *irq_domain;
198 struct irq_domain *inner_domain;
199 struct irq_domain *msi_domain;
200 struct mutex lock;
201 DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM);
202};
203
204/**
205 * struct mtk_pcie - PCIe host information
206 * @dev: pointer to PCIe device
207 * @base: IO mapped register base
208 * @free_ck: free-run reference clock
209 * @mem: non-prefetchable memory resource
210 * @ports: pointer to PCIe port information
211 * @soc: pointer to SoC-dependent operations
212 * @busnr: root bus number
213 */
214struct mtk_pcie {
215 struct device *dev;
216 void __iomem *base;
217 struct clk *free_ck;
218
219 struct resource mem;
220 struct list_head ports;
221 const struct mtk_pcie_soc *soc;
222 unsigned int busnr;
223};
224
225static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)
226{
227 struct device *dev = pcie->dev;
228
229 clk_disable_unprepare(pcie->free_ck);
230
231 pm_runtime_put_sync(dev);
232 pm_runtime_disable(dev);
233}
234
235static void mtk_pcie_port_free(struct mtk_pcie_port *port)
236{
237 struct mtk_pcie *pcie = port->pcie;
238 struct device *dev = pcie->dev;
239
240 devm_iounmap(dev, port->base);
241 list_del(&port->list);
242 devm_kfree(dev, port);
243}
244
245static void mtk_pcie_put_resources(struct mtk_pcie *pcie)
246{
247 struct mtk_pcie_port *port, *tmp;
248
249 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
250 phy_power_off(port->phy);
251 phy_exit(port->phy);
252 clk_disable_unprepare(port->pipe_ck);
253 clk_disable_unprepare(port->obff_ck);
254 clk_disable_unprepare(port->axi_ck);
255 clk_disable_unprepare(port->aux_ck);
256 clk_disable_unprepare(port->ahb_ck);
257 clk_disable_unprepare(port->sys_ck);
258 mtk_pcie_port_free(port);
259 }
260
261 mtk_pcie_subsys_powerdown(pcie);
262}
263
264static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
265{
266 u32 val;
267 int err;
268
269 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val,
270 !(val & APP_CFG_REQ), 10,
271 100 * USEC_PER_MSEC);
272 if (err)
273 return PCIBIOS_SET_FAILED;
274
275 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
276 return PCIBIOS_SET_FAILED;
277
278 return PCIBIOS_SUCCESSFUL;
279}
280
281static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
282 int where, int size, u32 *val)
283{
284 u32 tmp;
285
286 /* Write PCIe configuration transaction header for Cfgrd */
287 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
288 port->base + PCIE_CFG_HEADER0);
289 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
290 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
291 port->base + PCIE_CFG_HEADER2);
292
293 /* Trigger h/w to transmit Cfgrd TLP */
294 tmp = readl(port->base + PCIE_APP_TLP_REQ);
295 tmp |= APP_CFG_REQ;
296 writel(tmp, port->base + PCIE_APP_TLP_REQ);
297
298 /* Check completion status */
299 if (mtk_pcie_check_cfg_cpld(port))
300 return PCIBIOS_SET_FAILED;
301
302 /* Read cpld payload of Cfgrd */
303 *val = readl(port->base + PCIE_CFG_RDATA);
304
305 if (size == 1)
306 *val = (*val >> (8 * (where & 3))) & 0xff;
307 else if (size == 2)
308 *val = (*val >> (8 * (where & 3))) & 0xffff;
309
310 return PCIBIOS_SUCCESSFUL;
311}
312
313static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
314 int where, int size, u32 val)
315{
316 /* Write PCIe configuration transaction header for Cfgwr */
317 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
318 port->base + PCIE_CFG_HEADER0);
319 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
320 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
321 port->base + PCIE_CFG_HEADER2);
322
323 /* Write Cfgwr data */
324 val = val << 8 * (where & 3);
325 writel(val, port->base + PCIE_CFG_WDATA);
326
327 /* Trigger h/w to transmit Cfgwr TLP */
328 val = readl(port->base + PCIE_APP_TLP_REQ);
329 val |= APP_CFG_REQ;
330 writel(val, port->base + PCIE_APP_TLP_REQ);
331
332 /* Check completion status */
333 return mtk_pcie_check_cfg_cpld(port);
334}
335
336static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus,
337 unsigned int devfn)
338{
339 struct mtk_pcie *pcie = bus->sysdata;
340 struct mtk_pcie_port *port;
341 struct pci_dev *dev = NULL;
342
343 /*
344 * Walk the bus hierarchy to get the devfn value
345 * of the port in the root bus.
346 */
347 while (bus && bus->number) {
348 dev = bus->self;
349 bus = dev->bus;
350 devfn = dev->devfn;
351 }
352
353 list_for_each_entry(port, &pcie->ports, list)
354 if (port->slot == PCI_SLOT(devfn))
355 return port;
356
357 return NULL;
358}
359
360static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
361 int where, int size, u32 *val)
362{
363 struct mtk_pcie_port *port;
364 u32 bn = bus->number;
365 int ret;
366
367 port = mtk_pcie_find_port(bus, devfn);
368 if (!port) {
369 *val = ~0;
370 return PCIBIOS_DEVICE_NOT_FOUND;
371 }
372
373 ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val);
374 if (ret)
375 *val = ~0;
376
377 return ret;
378}
379
380static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
381 int where, int size, u32 val)
382{
383 struct mtk_pcie_port *port;
384 u32 bn = bus->number;
385
386 port = mtk_pcie_find_port(bus, devfn);
387 if (!port)
388 return PCIBIOS_DEVICE_NOT_FOUND;
389
390 return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val);
391}
392
393static struct pci_ops mtk_pcie_ops_v2 = {
394 .read = mtk_pcie_config_read,
395 .write = mtk_pcie_config_write,
396};
397
398static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
399{
400 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
401 phys_addr_t addr;
402
403 /* MT2712/MT7622 only support 32-bit MSI addresses */
404 addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
405 msg->address_hi = 0;
406 msg->address_lo = lower_32_bits(addr);
407
408 msg->data = data->hwirq;
409
410 dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n",
411 (int)data->hwirq, msg->address_hi, msg->address_lo);
412}
413
414static int mtk_msi_set_affinity(struct irq_data *irq_data,
415 const struct cpumask *mask, bool force)
416{
417 return -EINVAL;
418}
419
420static void mtk_msi_ack_irq(struct irq_data *data)
421{
422 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
423 u32 hwirq = data->hwirq;
424
425 writel(1 << hwirq, port->base + PCIE_IMSI_STATUS);
426}
427
428static struct irq_chip mtk_msi_bottom_irq_chip = {
429 .name = "MTK MSI",
430 .irq_compose_msi_msg = mtk_compose_msi_msg,
431 .irq_set_affinity = mtk_msi_set_affinity,
432 .irq_ack = mtk_msi_ack_irq,
433};
434
435static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
436 unsigned int nr_irqs, void *args)
437{
438 struct mtk_pcie_port *port = domain->host_data;
439 unsigned long bit;
440
441 WARN_ON(nr_irqs != 1);
442 mutex_lock(&port->lock);
443
444 bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);
445 if (bit >= MTK_MSI_IRQS_NUM) {
446 mutex_unlock(&port->lock);
447 return -ENOSPC;
448 }
449
450 __set_bit(bit, port->msi_irq_in_use);
451
452 mutex_unlock(&port->lock);
453
454 irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip,
455 domain->host_data, handle_edge_irq,
456 NULL, NULL);
457
458 return 0;
459}
460
461static void mtk_pcie_irq_domain_free(struct irq_domain *domain,
462 unsigned int virq, unsigned int nr_irqs)
463{
464 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
465 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d);
466
467 mutex_lock(&port->lock);
468
469 if (!test_bit(d->hwirq, port->msi_irq_in_use))
470 dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n",
471 d->hwirq);
472 else
473 __clear_bit(d->hwirq, port->msi_irq_in_use);
474
475 mutex_unlock(&port->lock);
476
477 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
478}
479
480static const struct irq_domain_ops msi_domain_ops = {
481 .alloc = mtk_pcie_irq_domain_alloc,
482 .free = mtk_pcie_irq_domain_free,
483};
484
485static struct irq_chip mtk_msi_irq_chip = {
486 .name = "MTK PCIe MSI",
487 .irq_ack = irq_chip_ack_parent,
488 .irq_mask = pci_msi_mask_irq,
489 .irq_unmask = pci_msi_unmask_irq,
490};
491
492static struct msi_domain_info mtk_msi_domain_info = {
493 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
494 MSI_FLAG_PCI_MSIX),
495 .chip = &mtk_msi_irq_chip,
496};
497
498static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port)
499{
500 struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node);
501
502 mutex_init(&port->lock);
503
504 port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM,
505 &msi_domain_ops, port);
506 if (!port->inner_domain) {
507 dev_err(port->pcie->dev, "failed to create IRQ domain\n");
508 return -ENOMEM;
509 }
510
511 port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info,
512 port->inner_domain);
513 if (!port->msi_domain) {
514 dev_err(port->pcie->dev, "failed to create MSI domain\n");
515 irq_domain_remove(port->inner_domain);
516 return -ENOMEM;
517 }
518
519 return 0;
520}
521
522static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
523{
524 u32 val;
525 phys_addr_t msg_addr;
526
527 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
528 val = lower_32_bits(msg_addr);
529 writel(val, port->base + PCIE_IMSI_ADDR);
530
531 val = readl(port->base + PCIE_INT_MASK);
532 val &= ~MSI_MASK;
533 writel(val, port->base + PCIE_INT_MASK);
534}
535
536static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie)
537{
538 struct mtk_pcie_port *port, *tmp;
539
540 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
541 irq_set_chained_handler_and_data(port->irq, NULL, NULL);
542
543 if (port->irq_domain)
544 irq_domain_remove(port->irq_domain);
545
546 if (IS_ENABLED(CONFIG_PCI_MSI)) {
547 if (port->msi_domain)
548 irq_domain_remove(port->msi_domain);
549 if (port->inner_domain)
550 irq_domain_remove(port->inner_domain);
551 }
552
553 irq_dispose_mapping(port->irq);
554 }
555}
556
557static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
558 irq_hw_number_t hwirq)
559{
560 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
561 irq_set_chip_data(irq, domain->host_data);
562
563 return 0;
564}
565
566static const struct irq_domain_ops intx_domain_ops = {
567 .map = mtk_pcie_intx_map,
568};
569
570static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
571 struct device_node *node)
572{
573 struct device *dev = port->pcie->dev;
574 struct device_node *pcie_intc_node;
575 int ret;
576
577 /* Setup INTx */
578 pcie_intc_node = of_get_next_child(node, NULL);
579 if (!pcie_intc_node) {
580 dev_err(dev, "no PCIe Intc node found\n");
581 return -ENODEV;
582 }
583
584 port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
585 &intx_domain_ops, port);
586 of_node_put(pcie_intc_node);
587 if (!port->irq_domain) {
588 dev_err(dev, "failed to get INTx IRQ domain\n");
589 return -ENODEV;
590 }
591
592 if (IS_ENABLED(CONFIG_PCI_MSI)) {
593 ret = mtk_pcie_allocate_msi_domains(port);
594 if (ret)
595 return ret;
596 }
597
598 return 0;
599}
600
601static void mtk_pcie_intr_handler(struct irq_desc *desc)
602{
603 struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
604 struct irq_chip *irqchip = irq_desc_get_chip(desc);
605 unsigned long status;
606 u32 virq;
607 u32 bit = INTX_SHIFT;
608
609 chained_irq_enter(irqchip, desc);
610
611 status = readl(port->base + PCIE_INT_STATUS);
612 if (status & INTX_MASK) {
613 for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
614 /* Clear the INTx */
615 writel(1 << bit, port->base + PCIE_INT_STATUS);
616 virq = irq_find_mapping(port->irq_domain,
617 bit - INTX_SHIFT);
618 generic_handle_irq(virq);
619 }
620 }
621
622 if (IS_ENABLED(CONFIG_PCI_MSI)) {
623 if (status & MSI_STATUS){
624 unsigned long imsi_status;
625
626 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
627 for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) {
628 virq = irq_find_mapping(port->inner_domain, bit);
629 generic_handle_irq(virq);
630 }
631 }
632 /* Clear MSI interrupt status */
633 writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
634 }
635 }
636
637 chained_irq_exit(irqchip, desc);
638}
639
640static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
641 struct device_node *node)
642{
643 struct mtk_pcie *pcie = port->pcie;
644 struct device *dev = pcie->dev;
645 struct platform_device *pdev = to_platform_device(dev);
646 int err;
647
648 err = mtk_pcie_init_irq_domain(port, node);
649 if (err) {
650 dev_err(dev, "failed to init PCIe IRQ domain\n");
651 return err;
652 }
653
654 port->irq = platform_get_irq(pdev, port->slot);
655 irq_set_chained_handler_and_data(port->irq,
656 mtk_pcie_intr_handler, port);
657
658 return 0;
659}
660
661static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
662{
663 struct mtk_pcie *pcie = port->pcie;
664 struct resource *mem = &pcie->mem;
665 const struct mtk_pcie_soc *soc = port->pcie->soc;
666 u32 val;
667 int err;
668
669 /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
670 if (pcie->base) {
671 val = readl(pcie->base + PCIE_SYS_CFG_V2);
672 val |= PCIE_CSR_LTSSM_EN(port->slot) |
673 PCIE_CSR_ASPM_L1_EN(port->slot);
674 writel(val, pcie->base + PCIE_SYS_CFG_V2);
675 }
676
677 /* Assert all reset signals */
678 writel(0, port->base + PCIE_RST_CTRL);
679
680 /*
681 * Enable PCIe link down reset, if link status changed from link up to
682 * link down, this will reset MAC control registers and configuration
683 * space.
684 */
685 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
686
687 /* De-assert PHY, PE, PIPE, MAC and configuration reset */
688 val = readl(port->base + PCIE_RST_CTRL);
689 val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
690 PCIE_MAC_SRSTB | PCIE_CRSTB;
691 writel(val, port->base + PCIE_RST_CTRL);
692
693 /* Set up vendor ID and class code */
694 if (soc->need_fix_class_id) {
695 val = PCI_VENDOR_ID_MEDIATEK;
696 writew(val, port->base + PCIE_CONF_VEND_ID);
697
698 val = PCI_CLASS_BRIDGE_PCI;
699 writew(val, port->base + PCIE_CONF_CLASS_ID);
700 }
701
702 if (soc->need_fix_device_id)
703 writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID);
704
705 /* 100ms timeout value should be enough for Gen1/2 training */
706 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
707 !!(val & PCIE_PORT_LINKUP_V2), 20,
708 100 * USEC_PER_MSEC);
709 if (err)
710 return -ETIMEDOUT;
711
712 /* Set INTx mask */
713 val = readl(port->base + PCIE_INT_MASK);
714 val &= ~INTX_MASK;
715 writel(val, port->base + PCIE_INT_MASK);
716
717 if (IS_ENABLED(CONFIG_PCI_MSI))
718 mtk_pcie_enable_msi(port);
719
720 /* Set AHB to PCIe translation windows */
721 val = lower_32_bits(mem->start) |
722 AHB2PCIE_SIZE(fls(resource_size(mem)));
723 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
724
725 val = upper_32_bits(mem->start);
726 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
727
728 /* Set PCIe to AXI translation memory space.*/
729 val = PCIE2AHB_SIZE | WIN_ENABLE;
730 writel(val, port->base + PCIE_AXI_WINDOW0);
731
732 return 0;
733}
734
735static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
736 unsigned int devfn, int where)
737{
738 struct mtk_pcie *pcie = bus->sysdata;
739
740 writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn),
741 bus->number), pcie->base + PCIE_CFG_ADDR);
742
743 return pcie->base + PCIE_CFG_DATA + (where & 3);
744}
745
746static struct pci_ops mtk_pcie_ops = {
747 .map_bus = mtk_pcie_map_bus,
748 .read = pci_generic_config_read,
749 .write = pci_generic_config_write,
750};
751
752static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
753{
754 struct mtk_pcie *pcie = port->pcie;
755 u32 func = PCI_FUNC(port->slot << 3);
756 u32 slot = PCI_SLOT(port->slot << 3);
757 u32 val;
758 int err;
759
760 /* assert port PERST_N */
761 val = readl(pcie->base + PCIE_SYS_CFG);
762 val |= PCIE_PORT_PERST(port->slot);
763 writel(val, pcie->base + PCIE_SYS_CFG);
764
765 /* de-assert port PERST_N */
766 val = readl(pcie->base + PCIE_SYS_CFG);
767 val &= ~PCIE_PORT_PERST(port->slot);
768 writel(val, pcie->base + PCIE_SYS_CFG);
769
770 /* 100ms timeout value should be enough for Gen1/2 training */
771 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
772 !!(val & PCIE_PORT_LINKUP), 20,
773 100 * USEC_PER_MSEC);
774 if (err)
775 return -ETIMEDOUT;
776
777 /* enable interrupt */
778 val = readl(pcie->base + PCIE_INT_ENABLE);
779 val |= PCIE_PORT_INT_EN(port->slot);
780 writel(val, pcie->base + PCIE_INT_ENABLE);
781
782 /* map to all DDR region. We need to set it before cfg operation. */
783 writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
784 port->base + PCIE_BAR0_SETUP);
785
786 /* configure class code and revision ID */
787 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
788
789 /* configure FC credit */
790 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
791 pcie->base + PCIE_CFG_ADDR);
792 val = readl(pcie->base + PCIE_CFG_DATA);
793 val &= ~PCIE_FC_CREDIT_MASK;
794 val |= PCIE_FC_CREDIT_VAL(0x806c);
795 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
796 pcie->base + PCIE_CFG_ADDR);
797 writel(val, pcie->base + PCIE_CFG_DATA);
798
799 /* configure RC FTS number to 250 when it leaves L0s */
800 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
801 pcie->base + PCIE_CFG_ADDR);
802 val = readl(pcie->base + PCIE_CFG_DATA);
803 val &= ~PCIE_FTS_NUM_MASK;
804 val |= PCIE_FTS_NUM_L0(0x50);
805 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
806 pcie->base + PCIE_CFG_ADDR);
807 writel(val, pcie->base + PCIE_CFG_DATA);
808
809 return 0;
810}
811
812static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
813{
814 struct mtk_pcie *pcie = port->pcie;
815 struct device *dev = pcie->dev;
816 int err;
817
818 err = clk_prepare_enable(port->sys_ck);
819 if (err) {
820 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot);
821 goto err_sys_clk;
822 }
823
824 err = clk_prepare_enable(port->ahb_ck);
825 if (err) {
826 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot);
827 goto err_ahb_clk;
828 }
829
830 err = clk_prepare_enable(port->aux_ck);
831 if (err) {
832 dev_err(dev, "failed to enable aux_ck%d\n", port->slot);
833 goto err_aux_clk;
834 }
835
836 err = clk_prepare_enable(port->axi_ck);
837 if (err) {
838 dev_err(dev, "failed to enable axi_ck%d\n", port->slot);
839 goto err_axi_clk;
840 }
841
842 err = clk_prepare_enable(port->obff_ck);
843 if (err) {
844 dev_err(dev, "failed to enable obff_ck%d\n", port->slot);
845 goto err_obff_clk;
846 }
847
848 err = clk_prepare_enable(port->pipe_ck);
849 if (err) {
850 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot);
851 goto err_pipe_clk;
852 }
853
854 reset_control_assert(port->reset);
855 reset_control_deassert(port->reset);
856
857 err = phy_init(port->phy);
858 if (err) {
859 dev_err(dev, "failed to initialize port%d phy\n", port->slot);
860 goto err_phy_init;
861 }
862
863 err = phy_power_on(port->phy);
864 if (err) {
865 dev_err(dev, "failed to power on port%d phy\n", port->slot);
866 goto err_phy_on;
867 }
868
869 if (!pcie->soc->startup(port))
870 return;
871
872 dev_info(dev, "Port%d link down\n", port->slot);
873
874 phy_power_off(port->phy);
875err_phy_on:
876 phy_exit(port->phy);
877err_phy_init:
878 clk_disable_unprepare(port->pipe_ck);
879err_pipe_clk:
880 clk_disable_unprepare(port->obff_ck);
881err_obff_clk:
882 clk_disable_unprepare(port->axi_ck);
883err_axi_clk:
884 clk_disable_unprepare(port->aux_ck);
885err_aux_clk:
886 clk_disable_unprepare(port->ahb_ck);
887err_ahb_clk:
888 clk_disable_unprepare(port->sys_ck);
889err_sys_clk:
890 mtk_pcie_port_free(port);
891}
892
893static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
894 struct device_node *node,
895 int slot)
896{
897 struct mtk_pcie_port *port;
898 struct resource *regs;
899 struct device *dev = pcie->dev;
900 struct platform_device *pdev = to_platform_device(dev);
901 char name[10];
902 int err;
903
904 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
905 if (!port)
906 return -ENOMEM;
907
908 snprintf(name, sizeof(name), "port%d", slot);
909 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
910 port->base = devm_ioremap_resource(dev, regs);
911 if (IS_ERR(port->base)) {
912 dev_err(dev, "failed to map port%d base\n", slot);
913 return PTR_ERR(port->base);
914 }
915
916 snprintf(name, sizeof(name), "sys_ck%d", slot);
917 port->sys_ck = devm_clk_get(dev, name);
918 if (IS_ERR(port->sys_ck)) {
919 dev_err(dev, "failed to get sys_ck%d clock\n", slot);
920 return PTR_ERR(port->sys_ck);
921 }
922
923 /* sys_ck might be divided into the following parts in some chips */
924 snprintf(name, sizeof(name), "ahb_ck%d", slot);
925 port->ahb_ck = devm_clk_get_optional(dev, name);
926 if (IS_ERR(port->ahb_ck))
927 return PTR_ERR(port->ahb_ck);
928
929 snprintf(name, sizeof(name), "axi_ck%d", slot);
930 port->axi_ck = devm_clk_get_optional(dev, name);
931 if (IS_ERR(port->axi_ck))
932 return PTR_ERR(port->axi_ck);
933
934 snprintf(name, sizeof(name), "aux_ck%d", slot);
935 port->aux_ck = devm_clk_get_optional(dev, name);
936 if (IS_ERR(port->aux_ck))
937 return PTR_ERR(port->aux_ck);
938
939 snprintf(name, sizeof(name), "obff_ck%d", slot);
940 port->obff_ck = devm_clk_get_optional(dev, name);
941 if (IS_ERR(port->obff_ck))
942 return PTR_ERR(port->obff_ck);
943
944 snprintf(name, sizeof(name), "pipe_ck%d", slot);
945 port->pipe_ck = devm_clk_get_optional(dev, name);
946 if (IS_ERR(port->pipe_ck))
947 return PTR_ERR(port->pipe_ck);
948
949 snprintf(name, sizeof(name), "pcie-rst%d", slot);
950 port->reset = devm_reset_control_get_optional_exclusive(dev, name);
951 if (PTR_ERR(port->reset) == -EPROBE_DEFER)
952 return PTR_ERR(port->reset);
953
954 /* some platforms may use default PHY setting */
955 snprintf(name, sizeof(name), "pcie-phy%d", slot);
956 port->phy = devm_phy_optional_get(dev, name);
957 if (IS_ERR(port->phy))
958 return PTR_ERR(port->phy);
959
960 port->slot = slot;
961 port->pcie = pcie;
962
963 if (pcie->soc->setup_irq) {
964 err = pcie->soc->setup_irq(port, node);
965 if (err)
966 return err;
967 }
968
969 INIT_LIST_HEAD(&port->list);
970 list_add_tail(&port->list, &pcie->ports);
971
972 return 0;
973}
974
975static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
976{
977 struct device *dev = pcie->dev;
978 struct platform_device *pdev = to_platform_device(dev);
979 struct resource *regs;
980 int err;
981
982 /* get shared registers, which are optional */
983 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys");
984 if (regs) {
985 pcie->base = devm_ioremap_resource(dev, regs);
986 if (IS_ERR(pcie->base)) {
987 dev_err(dev, "failed to map shared register\n");
988 return PTR_ERR(pcie->base);
989 }
990 }
991
992 pcie->free_ck = devm_clk_get(dev, "free_ck");
993 if (IS_ERR(pcie->free_ck)) {
994 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
995 return -EPROBE_DEFER;
996
997 pcie->free_ck = NULL;
998 }
999
1000 pm_runtime_enable(dev);
1001 pm_runtime_get_sync(dev);
1002
1003 /* enable top level clock */
1004 err = clk_prepare_enable(pcie->free_ck);
1005 if (err) {
1006 dev_err(dev, "failed to enable free_ck\n");
1007 goto err_free_ck;
1008 }
1009
1010 return 0;
1011
1012err_free_ck:
1013 pm_runtime_put_sync(dev);
1014 pm_runtime_disable(dev);
1015
1016 return err;
1017}
1018
1019static int mtk_pcie_setup(struct mtk_pcie *pcie)
1020{
1021 struct device *dev = pcie->dev;
1022 struct device_node *node = dev->of_node, *child;
1023 struct mtk_pcie_port *port, *tmp;
1024 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1025 struct list_head *windows = &host->windows;
1026 struct resource_entry *win, *tmp_win;
1027 resource_size_t io_base;
1028 int err;
1029
1030 err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
1031 windows, &io_base);
1032 if (err)
1033 return err;
1034
1035 err = devm_request_pci_bus_resources(dev, windows);
1036 if (err < 0)
1037 return err;
1038
1039 /* Get the I/O and memory ranges from DT */
1040 resource_list_for_each_entry_safe(win, tmp_win, windows) {
1041 switch (resource_type(win->res)) {
1042 case IORESOURCE_IO:
1043 err = devm_pci_remap_iospace(dev, win->res, io_base);
1044 if (err) {
1045 dev_warn(dev, "error %d: failed to map resource %pR\n",
1046 err, win->res);
1047 resource_list_destroy_entry(win);
1048 }
1049 break;
1050 case IORESOURCE_MEM:
1051 memcpy(&pcie->mem, win->res, sizeof(*win->res));
1052 pcie->mem.name = "non-prefetchable";
1053 break;
1054 case IORESOURCE_BUS:
1055 pcie->busnr = win->res->start;
1056 break;
1057 }
1058 }
1059
1060 for_each_available_child_of_node(node, child) {
1061 int slot;
1062
1063 err = of_pci_get_devfn(child);
1064 if (err < 0) {
1065 dev_err(dev, "failed to parse devfn: %d\n", err);
1066 return err;
1067 }
1068
1069 slot = PCI_SLOT(err);
1070
1071 err = mtk_pcie_parse_port(pcie, child, slot);
1072 if (err)
1073 return err;
1074 }
1075
1076 err = mtk_pcie_subsys_powerup(pcie);
1077 if (err)
1078 return err;
1079
1080 /* enable each port, and then check link status */
1081 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1082 mtk_pcie_enable_port(port);
1083
1084 /* power down PCIe subsys if slots are all empty (link down) */
1085 if (list_empty(&pcie->ports))
1086 mtk_pcie_subsys_powerdown(pcie);
1087
1088 return 0;
1089}
1090
1091static int mtk_pcie_probe(struct platform_device *pdev)
1092{
1093 struct device *dev = &pdev->dev;
1094 struct mtk_pcie *pcie;
1095 struct pci_host_bridge *host;
1096 int err;
1097
1098 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
1099 if (!host)
1100 return -ENOMEM;
1101
1102 pcie = pci_host_bridge_priv(host);
1103
1104 pcie->dev = dev;
1105 pcie->soc = of_device_get_match_data(dev);
1106 platform_set_drvdata(pdev, pcie);
1107 INIT_LIST_HEAD(&pcie->ports);
1108
1109 err = mtk_pcie_setup(pcie);
1110 if (err)
1111 return err;
1112
1113 host->busnr = pcie->busnr;
1114 host->dev.parent = pcie->dev;
1115 host->ops = pcie->soc->ops;
1116 host->map_irq = of_irq_parse_and_map_pci;
1117 host->swizzle_irq = pci_common_swizzle;
1118 host->sysdata = pcie;
1119
1120 err = pci_host_probe(host);
1121 if (err)
1122 goto put_resources;
1123
1124 return 0;
1125
1126put_resources:
1127 if (!list_empty(&pcie->ports))
1128 mtk_pcie_put_resources(pcie);
1129
1130 return err;
1131}
1132
1133
1134static void mtk_pcie_free_resources(struct mtk_pcie *pcie)
1135{
1136 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1137 struct list_head *windows = &host->windows;
1138
1139 pci_free_resource_list(windows);
1140}
1141
1142static int mtk_pcie_remove(struct platform_device *pdev)
1143{
1144 struct mtk_pcie *pcie = platform_get_drvdata(pdev);
1145 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1146
1147 pci_stop_root_bus(host->bus);
1148 pci_remove_root_bus(host->bus);
1149 mtk_pcie_free_resources(pcie);
1150
1151 mtk_pcie_irq_teardown(pcie);
1152
1153 mtk_pcie_put_resources(pcie);
1154
1155 return 0;
1156}
1157
1158static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev)
1159{
1160 struct mtk_pcie *pcie = dev_get_drvdata(dev);
1161 struct mtk_pcie_port *port;
1162
1163 if (list_empty(&pcie->ports))
1164 return 0;
1165
1166 list_for_each_entry(port, &pcie->ports, list) {
1167 clk_disable_unprepare(port->pipe_ck);
1168 clk_disable_unprepare(port->obff_ck);
1169 clk_disable_unprepare(port->axi_ck);
1170 clk_disable_unprepare(port->aux_ck);
1171 clk_disable_unprepare(port->ahb_ck);
1172 clk_disable_unprepare(port->sys_ck);
1173 phy_power_off(port->phy);
1174 phy_exit(port->phy);
1175 }
1176
1177 clk_disable_unprepare(pcie->free_ck);
1178
1179 return 0;
1180}
1181
1182static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
1183{
1184 struct mtk_pcie *pcie = dev_get_drvdata(dev);
1185 struct mtk_pcie_port *port, *tmp;
1186
1187 if (list_empty(&pcie->ports))
1188 return 0;
1189
1190 clk_prepare_enable(pcie->free_ck);
1191
1192 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1193 mtk_pcie_enable_port(port);
1194
1195 /* In case of EP was removed while system suspend. */
1196 if (list_empty(&pcie->ports))
1197 clk_disable_unprepare(pcie->free_ck);
1198
1199 return 0;
1200}
1201
1202static const struct dev_pm_ops mtk_pcie_pm_ops = {
1203 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
1204 mtk_pcie_resume_noirq)
1205};
1206
1207static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
1208 .ops = &mtk_pcie_ops,
1209 .startup = mtk_pcie_startup_port,
1210};
1211
1212static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = {
1213 .ops = &mtk_pcie_ops_v2,
1214 .startup = mtk_pcie_startup_port_v2,
1215 .setup_irq = mtk_pcie_setup_irq,
1216};
1217
1218static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = {
1219 .need_fix_class_id = true,
1220 .ops = &mtk_pcie_ops_v2,
1221 .startup = mtk_pcie_startup_port_v2,
1222 .setup_irq = mtk_pcie_setup_irq,
1223};
1224
1225static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {
1226 .need_fix_class_id = true,
1227 .need_fix_device_id = true,
1228 .device_id = PCI_DEVICE_ID_MEDIATEK_7629,
1229 .ops = &mtk_pcie_ops_v2,
1230 .startup = mtk_pcie_startup_port_v2,
1231 .setup_irq = mtk_pcie_setup_irq,
1232};
1233
1234static const struct of_device_id mtk_pcie_ids[] = {
1235 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1236 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1237 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
1238 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
1239 { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
1240 {},
1241};
1242
1243static struct platform_driver mtk_pcie_driver = {
1244 .probe = mtk_pcie_probe,
1245 .remove = mtk_pcie_remove,
1246 .driver = {
1247 .name = "mtk-pcie",
1248 .of_match_table = mtk_pcie_ids,
1249 .suppress_bind_attrs = true,
1250 .pm = &mtk_pcie_pm_ops,
1251 },
1252};
1253module_platform_driver(mtk_pcie_driver);
1254MODULE_LICENSE("GPL v2");