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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*******************************************************************************
3 STMMAC Common Header File
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
7
8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9*******************************************************************************/
10
11#ifndef __COMMON_H__
12#define __COMMON_H__
13
14#include <linux/etherdevice.h>
15#include <linux/netdevice.h>
16#include <linux/stmmac.h>
17#include <linux/phy.h>
18#include <linux/pcs/pcs-xpcs.h>
19#include <linux/module.h>
20#if IS_ENABLED(CONFIG_VLAN_8021Q)
21#define STMMAC_VLAN_TAG_USED
22#include <linux/if_vlan.h>
23#endif
24
25#include "descs.h"
26#include "hwif.h"
27#include "mmc.h"
28
29/* Synopsys Core versions */
30#define DWMAC_CORE_3_40 0x34
31#define DWMAC_CORE_3_50 0x35
32#define DWMAC_CORE_4_00 0x40
33#define DWMAC_CORE_4_10 0x41
34#define DWMAC_CORE_5_00 0x50
35#define DWMAC_CORE_5_10 0x51
36#define DWMAC_CORE_5_20 0x52
37#define DWXGMAC_CORE_2_10 0x21
38#define DWXGMAC_CORE_2_20 0x22
39#define DWXLGMAC_CORE_2_00 0x20
40
41/* Device ID */
42#define DWXGMAC_ID 0x76
43#define DWXLGMAC_ID 0x27
44
45#define STMMAC_CHAN0 0 /* Always supported and default for all chips */
46
47/* TX and RX Descriptor Length, these need to be power of two.
48 * TX descriptor length less than 64 may cause transmit queue timed out error.
49 * RX descriptor length less than 64 may cause inconsistent Rx chain error.
50 */
51#define DMA_MIN_TX_SIZE 64
52#define DMA_MAX_TX_SIZE 1024
53#define DMA_DEFAULT_TX_SIZE 512
54#define DMA_MIN_RX_SIZE 64
55#define DMA_MAX_RX_SIZE 1024
56#define DMA_DEFAULT_RX_SIZE 512
57#define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
58
59#undef FRAME_FILTER_DEBUG
60/* #define FRAME_FILTER_DEBUG */
61
62struct stmmac_q_tx_stats {
63 u64_stats_t tx_bytes;
64 u64_stats_t tx_set_ic_bit;
65 u64_stats_t tx_tso_frames;
66 u64_stats_t tx_tso_nfrags;
67};
68
69struct stmmac_napi_tx_stats {
70 u64_stats_t tx_packets;
71 u64_stats_t tx_pkt_n;
72 u64_stats_t poll;
73 u64_stats_t tx_clean;
74 u64_stats_t tx_set_ic_bit;
75};
76
77struct stmmac_txq_stats {
78 /* Updates protected by tx queue lock. */
79 struct u64_stats_sync q_syncp;
80 struct stmmac_q_tx_stats q;
81
82 /* Updates protected by NAPI poll logic. */
83 struct u64_stats_sync napi_syncp;
84 struct stmmac_napi_tx_stats napi;
85} ____cacheline_aligned_in_smp;
86
87struct stmmac_napi_rx_stats {
88 u64_stats_t rx_bytes;
89 u64_stats_t rx_packets;
90 u64_stats_t rx_pkt_n;
91 u64_stats_t poll;
92};
93
94struct stmmac_rxq_stats {
95 /* Updates protected by NAPI poll logic. */
96 struct u64_stats_sync napi_syncp;
97 struct stmmac_napi_rx_stats napi;
98} ____cacheline_aligned_in_smp;
99
100/* Updates on each CPU protected by not allowing nested irqs. */
101struct stmmac_pcpu_stats {
102 struct u64_stats_sync syncp;
103 u64_stats_t rx_normal_irq_n[MTL_MAX_TX_QUEUES];
104 u64_stats_t tx_normal_irq_n[MTL_MAX_RX_QUEUES];
105};
106
107/* Extra statistic and debug information exposed by ethtool */
108struct stmmac_extra_stats {
109 /* Transmit errors */
110 unsigned long tx_underflow ____cacheline_aligned;
111 unsigned long tx_carrier;
112 unsigned long tx_losscarrier;
113 unsigned long vlan_tag;
114 unsigned long tx_deferred;
115 unsigned long tx_vlan;
116 unsigned long tx_jabber;
117 unsigned long tx_frame_flushed;
118 unsigned long tx_payload_error;
119 unsigned long tx_ip_header_error;
120 unsigned long tx_collision;
121 /* Receive errors */
122 unsigned long rx_desc;
123 unsigned long sa_filter_fail;
124 unsigned long overflow_error;
125 unsigned long ipc_csum_error;
126 unsigned long rx_collision;
127 unsigned long rx_crc_errors;
128 unsigned long dribbling_bit;
129 unsigned long rx_length;
130 unsigned long rx_mii;
131 unsigned long rx_multicast;
132 unsigned long rx_gmac_overflow;
133 unsigned long rx_watchdog;
134 unsigned long da_rx_filter_fail;
135 unsigned long sa_rx_filter_fail;
136 unsigned long rx_missed_cntr;
137 unsigned long rx_overflow_cntr;
138 unsigned long rx_vlan;
139 unsigned long rx_split_hdr_pkt_n;
140 /* Tx/Rx IRQ error info */
141 unsigned long tx_undeflow_irq;
142 unsigned long tx_process_stopped_irq;
143 unsigned long tx_jabber_irq;
144 unsigned long rx_overflow_irq;
145 unsigned long rx_buf_unav_irq;
146 unsigned long rx_process_stopped_irq;
147 unsigned long rx_watchdog_irq;
148 unsigned long tx_early_irq;
149 unsigned long fatal_bus_error_irq;
150 /* Tx/Rx IRQ Events */
151 unsigned long rx_early_irq;
152 unsigned long threshold;
153 unsigned long irq_receive_pmt_irq_n;
154 /* MMC info */
155 unsigned long mmc_tx_irq_n;
156 unsigned long mmc_rx_irq_n;
157 unsigned long mmc_rx_csum_offload_irq_n;
158 /* EEE */
159 unsigned long irq_tx_path_in_lpi_mode_n;
160 unsigned long irq_tx_path_exit_lpi_mode_n;
161 unsigned long irq_rx_path_in_lpi_mode_n;
162 unsigned long irq_rx_path_exit_lpi_mode_n;
163 unsigned long phy_eee_wakeup_error_n;
164 /* Extended RDES status */
165 unsigned long ip_hdr_err;
166 unsigned long ip_payload_err;
167 unsigned long ip_csum_bypassed;
168 unsigned long ipv4_pkt_rcvd;
169 unsigned long ipv6_pkt_rcvd;
170 unsigned long no_ptp_rx_msg_type_ext;
171 unsigned long ptp_rx_msg_type_sync;
172 unsigned long ptp_rx_msg_type_follow_up;
173 unsigned long ptp_rx_msg_type_delay_req;
174 unsigned long ptp_rx_msg_type_delay_resp;
175 unsigned long ptp_rx_msg_type_pdelay_req;
176 unsigned long ptp_rx_msg_type_pdelay_resp;
177 unsigned long ptp_rx_msg_type_pdelay_follow_up;
178 unsigned long ptp_rx_msg_type_announce;
179 unsigned long ptp_rx_msg_type_management;
180 unsigned long ptp_rx_msg_pkt_reserved_type;
181 unsigned long ptp_frame_type;
182 unsigned long ptp_ver;
183 unsigned long timestamp_dropped;
184 unsigned long av_pkt_rcvd;
185 unsigned long av_tagged_pkt_rcvd;
186 unsigned long vlan_tag_priority_val;
187 unsigned long l3_filter_match;
188 unsigned long l4_filter_match;
189 unsigned long l3_l4_filter_no_match;
190 /* PCS */
191 unsigned long irq_pcs_ane_n;
192 unsigned long irq_pcs_link_n;
193 unsigned long irq_rgmii_n;
194 unsigned long pcs_link;
195 unsigned long pcs_duplex;
196 unsigned long pcs_speed;
197 /* debug register */
198 unsigned long mtl_tx_status_fifo_full;
199 unsigned long mtl_tx_fifo_not_empty;
200 unsigned long mmtl_fifo_ctrl;
201 unsigned long mtl_tx_fifo_read_ctrl_write;
202 unsigned long mtl_tx_fifo_read_ctrl_wait;
203 unsigned long mtl_tx_fifo_read_ctrl_read;
204 unsigned long mtl_tx_fifo_read_ctrl_idle;
205 unsigned long mac_tx_in_pause;
206 unsigned long mac_tx_frame_ctrl_xfer;
207 unsigned long mac_tx_frame_ctrl_idle;
208 unsigned long mac_tx_frame_ctrl_wait;
209 unsigned long mac_tx_frame_ctrl_pause;
210 unsigned long mac_gmii_tx_proto_engine;
211 unsigned long mtl_rx_fifo_fill_level_full;
212 unsigned long mtl_rx_fifo_fill_above_thresh;
213 unsigned long mtl_rx_fifo_fill_below_thresh;
214 unsigned long mtl_rx_fifo_fill_level_empty;
215 unsigned long mtl_rx_fifo_read_ctrl_flush;
216 unsigned long mtl_rx_fifo_read_ctrl_read_data;
217 unsigned long mtl_rx_fifo_read_ctrl_status;
218 unsigned long mtl_rx_fifo_read_ctrl_idle;
219 unsigned long mtl_rx_fifo_ctrl_active;
220 unsigned long mac_rx_frame_ctrl_fifo;
221 unsigned long mac_gmii_rx_proto_engine;
222 /* EST */
223 unsigned long mtl_est_cgce;
224 unsigned long mtl_est_hlbs;
225 unsigned long mtl_est_hlbf;
226 unsigned long mtl_est_btre;
227 unsigned long mtl_est_btrlm;
228 /* per queue statistics */
229 struct stmmac_txq_stats txq_stats[MTL_MAX_TX_QUEUES];
230 struct stmmac_rxq_stats rxq_stats[MTL_MAX_RX_QUEUES];
231 struct stmmac_pcpu_stats __percpu *pcpu_stats;
232 unsigned long rx_dropped;
233 unsigned long rx_errors;
234 unsigned long tx_dropped;
235 unsigned long tx_errors;
236};
237
238/* Safety Feature statistics exposed by ethtool */
239struct stmmac_safety_stats {
240 unsigned long mac_errors[32];
241 unsigned long mtl_errors[32];
242 unsigned long dma_errors[32];
243 unsigned long dma_dpp_errors[32];
244};
245
246/* Number of fields in Safety Stats */
247#define STMMAC_SAFETY_FEAT_SIZE \
248 (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))
249
250/* CSR Frequency Access Defines*/
251#define CSR_F_35M 35000000
252#define CSR_F_60M 60000000
253#define CSR_F_100M 100000000
254#define CSR_F_150M 150000000
255#define CSR_F_250M 250000000
256#define CSR_F_300M 300000000
257
258#define MAC_CSR_H_FRQ_MASK 0x20
259
260#define HASH_TABLE_SIZE 64
261#define PAUSE_TIME 0xffff
262
263/* Flow Control defines */
264#define FLOW_OFF 0
265#define FLOW_RX 1
266#define FLOW_TX 2
267#define FLOW_AUTO (FLOW_TX | FLOW_RX)
268
269/* PCS defines */
270#define STMMAC_PCS_RGMII (1 << 0)
271#define STMMAC_PCS_SGMII (1 << 1)
272#define STMMAC_PCS_TBI (1 << 2)
273#define STMMAC_PCS_RTBI (1 << 3)
274
275#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
276
277/* DMA HW feature register fields */
278#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
279#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
280#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
281#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
282#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
283#define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
284#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
285#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
286#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
287#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
288#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
289#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
290#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
291#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
292#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
293#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
294#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
295#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
296#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
297#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
298#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
299#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
300#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
301/* Timestamping with Internal System Time */
302#define DMA_HW_FEAT_INTTSEN 0x02000000
303#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
304#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
305#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
306#define DEFAULT_DMA_PBL 8
307
308/* MSI defines */
309#define STMMAC_MSI_VEC_MAX 32
310
311/* PCS status and mask defines */
312#define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */
313#define PCS_LINK_IRQ BIT(1) /* PCS Link */
314#define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */
315
316/* Max/Min RI Watchdog Timer count value */
317#define MAX_DMA_RIWT 0xff
318#define MIN_DMA_RIWT 0x10
319#define DEF_DMA_RIWT 0xa0
320/* Tx coalesce parameters */
321#define STMMAC_COAL_TX_TIMER 5000
322#define STMMAC_MAX_COAL_TX_TICK 100000
323#define STMMAC_TX_MAX_FRAMES 256
324#define STMMAC_TX_FRAMES 25
325#define STMMAC_RX_FRAMES 0
326
327/* Packets types */
328enum packets_types {
329 PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */
330 PACKET_PTPQ = 0x2, /* PTP Packets */
331 PACKET_DCBCPQ = 0x3, /* DCB Control Packets */
332 PACKET_UPQ = 0x4, /* Untagged Packets */
333 PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */
334};
335
336/* Rx IPC status */
337enum rx_frame_status {
338 good_frame = 0x0,
339 discard_frame = 0x1,
340 csum_none = 0x2,
341 llc_snap = 0x4,
342 dma_own = 0x8,
343 rx_not_ls = 0x10,
344};
345
346/* Tx status */
347enum tx_frame_status {
348 tx_done = 0x0,
349 tx_not_ls = 0x1,
350 tx_err = 0x2,
351 tx_dma_own = 0x4,
352 tx_err_bump_tc = 0x8,
353};
354
355enum dma_irq_status {
356 tx_hard_error = 0x1,
357 tx_hard_error_bump_tc = 0x2,
358 handle_rx = 0x4,
359 handle_tx = 0x8,
360};
361
362enum dma_irq_dir {
363 DMA_DIR_RX = 0x1,
364 DMA_DIR_TX = 0x2,
365 DMA_DIR_RXTX = 0x3,
366};
367
368enum request_irq_err {
369 REQ_IRQ_ERR_ALL,
370 REQ_IRQ_ERR_TX,
371 REQ_IRQ_ERR_RX,
372 REQ_IRQ_ERR_SFTY_UE,
373 REQ_IRQ_ERR_SFTY_CE,
374 REQ_IRQ_ERR_LPI,
375 REQ_IRQ_ERR_WOL,
376 REQ_IRQ_ERR_MAC,
377 REQ_IRQ_ERR_NO,
378};
379
380/* EEE and LPI defines */
381#define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
382#define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
383#define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
384#define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
385
386/* FPE defines */
387#define FPE_EVENT_UNKNOWN 0
388#define FPE_EVENT_TRSP BIT(0)
389#define FPE_EVENT_TVER BIT(1)
390#define FPE_EVENT_RRSP BIT(2)
391#define FPE_EVENT_RVER BIT(3)
392
393#define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
394
395/* Physical Coding Sublayer */
396struct rgmii_adv {
397 unsigned int pause;
398 unsigned int duplex;
399 unsigned int lp_pause;
400 unsigned int lp_duplex;
401};
402
403#define STMMAC_PCS_PAUSE 1
404#define STMMAC_PCS_ASYM_PAUSE 2
405
406/* DMA HW capabilities */
407struct dma_features {
408 unsigned int mbps_10_100;
409 unsigned int mbps_1000;
410 unsigned int half_duplex;
411 unsigned int hash_filter;
412 unsigned int multi_addr;
413 unsigned int pcs;
414 unsigned int sma_mdio;
415 unsigned int pmt_remote_wake_up;
416 unsigned int pmt_magic_frame;
417 unsigned int rmon;
418 /* IEEE 1588-2002 */
419 unsigned int time_stamp;
420 /* IEEE 1588-2008 */
421 unsigned int atime_stamp;
422 /* 802.3az - Energy-Efficient Ethernet (EEE) */
423 unsigned int eee;
424 unsigned int av;
425 unsigned int hash_tb_sz;
426 unsigned int tsoen;
427 /* TX and RX csum */
428 unsigned int tx_coe;
429 unsigned int rx_coe;
430 unsigned int rx_coe_type1;
431 unsigned int rx_coe_type2;
432 unsigned int rxfifo_over_2048;
433 /* TX and RX number of channels */
434 unsigned int number_rx_channel;
435 unsigned int number_tx_channel;
436 /* TX and RX number of queues */
437 unsigned int number_rx_queues;
438 unsigned int number_tx_queues;
439 /* PPS output */
440 unsigned int pps_out_num;
441 /* Number of Traffic Classes */
442 unsigned int numtc;
443 /* DCB Feature Enable */
444 unsigned int dcben;
445 /* IEEE 1588 High Word Register Enable */
446 unsigned int advthword;
447 /* PTP Offload Enable */
448 unsigned int ptoen;
449 /* One-Step Timestamping Enable */
450 unsigned int osten;
451 /* Priority-Based Flow Control Enable */
452 unsigned int pfcen;
453 /* Alternate (enhanced) DESC mode */
454 unsigned int enh_desc;
455 /* TX and RX FIFO sizes */
456 unsigned int tx_fifo_size;
457 unsigned int rx_fifo_size;
458 /* Automotive Safety Package */
459 unsigned int asp;
460 /* RX Parser */
461 unsigned int frpsel;
462 unsigned int frpbs;
463 unsigned int frpes;
464 unsigned int addr64;
465 unsigned int host_dma_width;
466 unsigned int rssen;
467 unsigned int vlhash;
468 unsigned int sphen;
469 unsigned int vlins;
470 unsigned int dvlan;
471 unsigned int l3l4fnum;
472 unsigned int arpoffsel;
473 /* One Step for PTP over UDP/IP Feature Enable */
474 unsigned int pou_ost_en;
475 /* Tx Timestamp FIFO Depth */
476 unsigned int ttsfd;
477 /* Queue/Channel-Based VLAN tag insertion on Tx */
478 unsigned int cbtisel;
479 /* Supported Parallel Instruction Processor Engines */
480 unsigned int frppipe_num;
481 /* Number of Extended VLAN Tag Filters */
482 unsigned int nrvf_num;
483 /* TSN Features */
484 unsigned int estwid;
485 unsigned int estdep;
486 unsigned int estsel;
487 unsigned int fpesel;
488 unsigned int tbssel;
489 /* Number of DMA channels enabled for TBS */
490 unsigned int tbs_ch_num;
491 /* Per-Stream Filtering Enable */
492 unsigned int sgfsel;
493 /* Numbers of Auxiliary Snapshot Inputs */
494 unsigned int aux_snapshot_n;
495 /* Timestamp System Time Source */
496 unsigned int tssrc;
497 /* Enhanced DMA Enable */
498 unsigned int edma;
499 /* Different Descriptor Cache Enable */
500 unsigned int ediffc;
501 /* VxLAN/NVGRE Enable */
502 unsigned int vxn;
503 /* Debug Memory Interface Enable */
504 unsigned int dbgmem;
505 /* Number of Policing Counters */
506 unsigned int pcsel;
507};
508
509/* RX Buffer size must be multiple of 4/8/16 bytes */
510#define BUF_SIZE_16KiB 16368
511#define BUF_SIZE_8KiB 8188
512#define BUF_SIZE_4KiB 4096
513#define BUF_SIZE_2KiB 2048
514
515/* Power Down and WOL */
516#define PMT_NOT_SUPPORTED 0
517#define PMT_SUPPORTED 1
518
519/* Common MAC defines */
520#define MAC_CTRL_REG 0x00000000 /* MAC Control */
521#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
522#define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
523
524/* Default LPI timers */
525#define STMMAC_DEFAULT_LIT_LS 0x3E8
526#define STMMAC_DEFAULT_TWT_LS 0x1E
527#define STMMAC_ET_MAX 0xFFFFF
528
529#define STMMAC_CHAIN_MODE 0x1
530#define STMMAC_RING_MODE 0x2
531
532#define JUMBO_LEN 9000
533
534/* Receive Side Scaling */
535#define STMMAC_RSS_HASH_KEY_SIZE 40
536#define STMMAC_RSS_MAX_TABLE_SIZE 256
537
538/* VLAN */
539#define STMMAC_VLAN_NONE 0x0
540#define STMMAC_VLAN_REMOVE 0x1
541#define STMMAC_VLAN_INSERT 0x2
542#define STMMAC_VLAN_REPLACE 0x3
543
544extern const struct stmmac_desc_ops enh_desc_ops;
545extern const struct stmmac_desc_ops ndesc_ops;
546
547struct mac_device_info;
548
549extern const struct stmmac_hwtimestamp stmmac_ptp;
550extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
551
552struct mac_link {
553 u32 speed_mask;
554 u32 speed10;
555 u32 speed100;
556 u32 speed1000;
557 u32 speed2500;
558 u32 duplex;
559 struct {
560 u32 speed2500;
561 u32 speed5000;
562 u32 speed10000;
563 } xgmii;
564 struct {
565 u32 speed25000;
566 u32 speed40000;
567 u32 speed50000;
568 u32 speed100000;
569 } xlgmii;
570};
571
572struct mii_regs {
573 unsigned int addr; /* MII Address */
574 unsigned int data; /* MII Data */
575 unsigned int addr_shift; /* MII address shift */
576 unsigned int reg_shift; /* MII reg shift */
577 unsigned int addr_mask; /* MII address mask */
578 unsigned int reg_mask; /* MII reg mask */
579 unsigned int clk_csr_shift;
580 unsigned int clk_csr_mask;
581};
582
583struct mac_device_info {
584 const struct stmmac_ops *mac;
585 const struct stmmac_desc_ops *desc;
586 const struct stmmac_dma_ops *dma;
587 const struct stmmac_mode_ops *mode;
588 const struct stmmac_hwtimestamp *ptp;
589 const struct stmmac_tc_ops *tc;
590 const struct stmmac_mmc_ops *mmc;
591 const struct stmmac_est_ops *est;
592 struct dw_xpcs *xpcs;
593 struct phylink_pcs *lynx_pcs; /* Lynx external PCS */
594 struct mii_regs mii; /* MII register Addresses */
595 struct mac_link link;
596 void __iomem *pcsr; /* vpointer to device CSRs */
597 unsigned int multicast_filter_bins;
598 unsigned int unicast_filter_entries;
599 unsigned int mcast_bits_log2;
600 unsigned int rx_csum;
601 unsigned int pcs;
602 unsigned int pmt;
603 unsigned int ps;
604 unsigned int xlgmac;
605 unsigned int num_vlan;
606 u32 vlan_filter[32];
607 bool vlan_fail_q_en;
608 u8 vlan_fail_q;
609 bool hw_vlan_en;
610};
611
612struct stmmac_rx_routing {
613 u32 reg_mask;
614 u32 reg_shift;
615};
616
617int dwmac100_setup(struct stmmac_priv *priv);
618int dwmac1000_setup(struct stmmac_priv *priv);
619int dwmac4_setup(struct stmmac_priv *priv);
620int dwxgmac2_setup(struct stmmac_priv *priv);
621int dwxlgmac2_setup(struct stmmac_priv *priv);
622
623void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
624 unsigned int high, unsigned int low);
625void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
626 unsigned int high, unsigned int low);
627void stmmac_set_mac(void __iomem *ioaddr, bool enable);
628
629void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
630 unsigned int high, unsigned int low);
631void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
632 unsigned int high, unsigned int low);
633void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
634
635void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
636
637extern const struct stmmac_mode_ops ring_mode_ops;
638extern const struct stmmac_mode_ops chain_mode_ops;
639extern const struct stmmac_desc_ops dwmac4_desc_ops;
640
641#endif /* __COMMON_H__ */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*******************************************************************************
3 STMMAC Common Header File
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
7
8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9*******************************************************************************/
10
11#ifndef __COMMON_H__
12#define __COMMON_H__
13
14#include <linux/etherdevice.h>
15#include <linux/netdevice.h>
16#include <linux/stmmac.h>
17#include <linux/phy.h>
18#include <linux/module.h>
19#if IS_ENABLED(CONFIG_VLAN_8021Q)
20#define STMMAC_VLAN_TAG_USED
21#include <linux/if_vlan.h>
22#endif
23
24#include "descs.h"
25#include "hwif.h"
26#include "mmc.h"
27
28/* Synopsys Core versions */
29#define DWMAC_CORE_3_40 0x34
30#define DWMAC_CORE_3_50 0x35
31#define DWMAC_CORE_4_00 0x40
32#define DWMAC_CORE_4_10 0x41
33#define DWMAC_CORE_5_00 0x50
34#define DWMAC_CORE_5_10 0x51
35#define DWXGMAC_CORE_2_10 0x21
36
37#define STMMAC_CHAN0 0 /* Always supported and default for all chips */
38
39/* These need to be power of two, and >= 4 */
40#define DMA_TX_SIZE 512
41#define DMA_RX_SIZE 512
42#define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
43
44#undef FRAME_FILTER_DEBUG
45/* #define FRAME_FILTER_DEBUG */
46
47/* Extra statistic and debug information exposed by ethtool */
48struct stmmac_extra_stats {
49 /* Transmit errors */
50 unsigned long tx_underflow ____cacheline_aligned;
51 unsigned long tx_carrier;
52 unsigned long tx_losscarrier;
53 unsigned long vlan_tag;
54 unsigned long tx_deferred;
55 unsigned long tx_vlan;
56 unsigned long tx_jabber;
57 unsigned long tx_frame_flushed;
58 unsigned long tx_payload_error;
59 unsigned long tx_ip_header_error;
60 /* Receive errors */
61 unsigned long rx_desc;
62 unsigned long sa_filter_fail;
63 unsigned long overflow_error;
64 unsigned long ipc_csum_error;
65 unsigned long rx_collision;
66 unsigned long rx_crc_errors;
67 unsigned long dribbling_bit;
68 unsigned long rx_length;
69 unsigned long rx_mii;
70 unsigned long rx_multicast;
71 unsigned long rx_gmac_overflow;
72 unsigned long rx_watchdog;
73 unsigned long da_rx_filter_fail;
74 unsigned long sa_rx_filter_fail;
75 unsigned long rx_missed_cntr;
76 unsigned long rx_overflow_cntr;
77 unsigned long rx_vlan;
78 unsigned long rx_split_hdr_pkt_n;
79 /* Tx/Rx IRQ error info */
80 unsigned long tx_undeflow_irq;
81 unsigned long tx_process_stopped_irq;
82 unsigned long tx_jabber_irq;
83 unsigned long rx_overflow_irq;
84 unsigned long rx_buf_unav_irq;
85 unsigned long rx_process_stopped_irq;
86 unsigned long rx_watchdog_irq;
87 unsigned long tx_early_irq;
88 unsigned long fatal_bus_error_irq;
89 /* Tx/Rx IRQ Events */
90 unsigned long rx_early_irq;
91 unsigned long threshold;
92 unsigned long tx_pkt_n;
93 unsigned long rx_pkt_n;
94 unsigned long normal_irq_n;
95 unsigned long rx_normal_irq_n;
96 unsigned long napi_poll;
97 unsigned long tx_normal_irq_n;
98 unsigned long tx_clean;
99 unsigned long tx_set_ic_bit;
100 unsigned long irq_receive_pmt_irq_n;
101 /* MMC info */
102 unsigned long mmc_tx_irq_n;
103 unsigned long mmc_rx_irq_n;
104 unsigned long mmc_rx_csum_offload_irq_n;
105 /* EEE */
106 unsigned long irq_tx_path_in_lpi_mode_n;
107 unsigned long irq_tx_path_exit_lpi_mode_n;
108 unsigned long irq_rx_path_in_lpi_mode_n;
109 unsigned long irq_rx_path_exit_lpi_mode_n;
110 unsigned long phy_eee_wakeup_error_n;
111 /* Extended RDES status */
112 unsigned long ip_hdr_err;
113 unsigned long ip_payload_err;
114 unsigned long ip_csum_bypassed;
115 unsigned long ipv4_pkt_rcvd;
116 unsigned long ipv6_pkt_rcvd;
117 unsigned long no_ptp_rx_msg_type_ext;
118 unsigned long ptp_rx_msg_type_sync;
119 unsigned long ptp_rx_msg_type_follow_up;
120 unsigned long ptp_rx_msg_type_delay_req;
121 unsigned long ptp_rx_msg_type_delay_resp;
122 unsigned long ptp_rx_msg_type_pdelay_req;
123 unsigned long ptp_rx_msg_type_pdelay_resp;
124 unsigned long ptp_rx_msg_type_pdelay_follow_up;
125 unsigned long ptp_rx_msg_type_announce;
126 unsigned long ptp_rx_msg_type_management;
127 unsigned long ptp_rx_msg_pkt_reserved_type;
128 unsigned long ptp_frame_type;
129 unsigned long ptp_ver;
130 unsigned long timestamp_dropped;
131 unsigned long av_pkt_rcvd;
132 unsigned long av_tagged_pkt_rcvd;
133 unsigned long vlan_tag_priority_val;
134 unsigned long l3_filter_match;
135 unsigned long l4_filter_match;
136 unsigned long l3_l4_filter_no_match;
137 /* PCS */
138 unsigned long irq_pcs_ane_n;
139 unsigned long irq_pcs_link_n;
140 unsigned long irq_rgmii_n;
141 unsigned long pcs_link;
142 unsigned long pcs_duplex;
143 unsigned long pcs_speed;
144 /* debug register */
145 unsigned long mtl_tx_status_fifo_full;
146 unsigned long mtl_tx_fifo_not_empty;
147 unsigned long mmtl_fifo_ctrl;
148 unsigned long mtl_tx_fifo_read_ctrl_write;
149 unsigned long mtl_tx_fifo_read_ctrl_wait;
150 unsigned long mtl_tx_fifo_read_ctrl_read;
151 unsigned long mtl_tx_fifo_read_ctrl_idle;
152 unsigned long mac_tx_in_pause;
153 unsigned long mac_tx_frame_ctrl_xfer;
154 unsigned long mac_tx_frame_ctrl_idle;
155 unsigned long mac_tx_frame_ctrl_wait;
156 unsigned long mac_tx_frame_ctrl_pause;
157 unsigned long mac_gmii_tx_proto_engine;
158 unsigned long mtl_rx_fifo_fill_level_full;
159 unsigned long mtl_rx_fifo_fill_above_thresh;
160 unsigned long mtl_rx_fifo_fill_below_thresh;
161 unsigned long mtl_rx_fifo_fill_level_empty;
162 unsigned long mtl_rx_fifo_read_ctrl_flush;
163 unsigned long mtl_rx_fifo_read_ctrl_read_data;
164 unsigned long mtl_rx_fifo_read_ctrl_status;
165 unsigned long mtl_rx_fifo_read_ctrl_idle;
166 unsigned long mtl_rx_fifo_ctrl_active;
167 unsigned long mac_rx_frame_ctrl_fifo;
168 unsigned long mac_gmii_rx_proto_engine;
169 /* TSO */
170 unsigned long tx_tso_frames;
171 unsigned long tx_tso_nfrags;
172};
173
174/* Safety Feature statistics exposed by ethtool */
175struct stmmac_safety_stats {
176 unsigned long mac_errors[32];
177 unsigned long mtl_errors[32];
178 unsigned long dma_errors[32];
179};
180
181/* Number of fields in Safety Stats */
182#define STMMAC_SAFETY_FEAT_SIZE \
183 (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))
184
185/* CSR Frequency Access Defines*/
186#define CSR_F_35M 35000000
187#define CSR_F_60M 60000000
188#define CSR_F_100M 100000000
189#define CSR_F_150M 150000000
190#define CSR_F_250M 250000000
191#define CSR_F_300M 300000000
192
193#define MAC_CSR_H_FRQ_MASK 0x20
194
195#define HASH_TABLE_SIZE 64
196#define PAUSE_TIME 0xffff
197
198/* Flow Control defines */
199#define FLOW_OFF 0
200#define FLOW_RX 1
201#define FLOW_TX 2
202#define FLOW_AUTO (FLOW_TX | FLOW_RX)
203
204/* PCS defines */
205#define STMMAC_PCS_RGMII (1 << 0)
206#define STMMAC_PCS_SGMII (1 << 1)
207#define STMMAC_PCS_TBI (1 << 2)
208#define STMMAC_PCS_RTBI (1 << 3)
209
210#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
211
212/* DAM HW feature register fields */
213#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
214#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
215#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
216#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
217#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
218#define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
219#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
220#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
221#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
222#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
223#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
224#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
225#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
226#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
227#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
228#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
229#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
230#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
231#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
232#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
233#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
234#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
235#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
236/* Timestamping with Internal System Time */
237#define DMA_HW_FEAT_INTTSEN 0x02000000
238#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
239#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
240#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
241#define DEFAULT_DMA_PBL 8
242
243/* PCS status and mask defines */
244#define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */
245#define PCS_LINK_IRQ BIT(1) /* PCS Link */
246#define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */
247
248/* Max/Min RI Watchdog Timer count value */
249#define MAX_DMA_RIWT 0xff
250#define MIN_DMA_RIWT 0x10
251/* Tx coalesce parameters */
252#define STMMAC_COAL_TX_TIMER 1000
253#define STMMAC_MAX_COAL_TX_TICK 100000
254#define STMMAC_TX_MAX_FRAMES 256
255#define STMMAC_TX_FRAMES 1
256#define STMMAC_RX_FRAMES 25
257
258/* Packets types */
259enum packets_types {
260 PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */
261 PACKET_PTPQ = 0x2, /* PTP Packets */
262 PACKET_DCBCPQ = 0x3, /* DCB Control Packets */
263 PACKET_UPQ = 0x4, /* Untagged Packets */
264 PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */
265};
266
267/* Rx IPC status */
268enum rx_frame_status {
269 good_frame = 0x0,
270 discard_frame = 0x1,
271 csum_none = 0x2,
272 llc_snap = 0x4,
273 dma_own = 0x8,
274 rx_not_ls = 0x10,
275};
276
277/* Tx status */
278enum tx_frame_status {
279 tx_done = 0x0,
280 tx_not_ls = 0x1,
281 tx_err = 0x2,
282 tx_dma_own = 0x4,
283};
284
285enum dma_irq_status {
286 tx_hard_error = 0x1,
287 tx_hard_error_bump_tc = 0x2,
288 handle_rx = 0x4,
289 handle_tx = 0x8,
290};
291
292/* EEE and LPI defines */
293#define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
294#define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
295#define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
296#define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
297
298#define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
299
300/* Physical Coding Sublayer */
301struct rgmii_adv {
302 unsigned int pause;
303 unsigned int duplex;
304 unsigned int lp_pause;
305 unsigned int lp_duplex;
306};
307
308#define STMMAC_PCS_PAUSE 1
309#define STMMAC_PCS_ASYM_PAUSE 2
310
311/* DMA HW capabilities */
312struct dma_features {
313 unsigned int mbps_10_100;
314 unsigned int mbps_1000;
315 unsigned int half_duplex;
316 unsigned int hash_filter;
317 unsigned int multi_addr;
318 unsigned int pcs;
319 unsigned int sma_mdio;
320 unsigned int pmt_remote_wake_up;
321 unsigned int pmt_magic_frame;
322 unsigned int rmon;
323 /* IEEE 1588-2002 */
324 unsigned int time_stamp;
325 /* IEEE 1588-2008 */
326 unsigned int atime_stamp;
327 /* 802.3az - Energy-Efficient Ethernet (EEE) */
328 unsigned int eee;
329 unsigned int av;
330 unsigned int hash_tb_sz;
331 unsigned int tsoen;
332 /* TX and RX csum */
333 unsigned int tx_coe;
334 unsigned int rx_coe;
335 unsigned int rx_coe_type1;
336 unsigned int rx_coe_type2;
337 unsigned int rxfifo_over_2048;
338 /* TX and RX number of channels */
339 unsigned int number_rx_channel;
340 unsigned int number_tx_channel;
341 /* TX and RX number of queues */
342 unsigned int number_rx_queues;
343 unsigned int number_tx_queues;
344 /* PPS output */
345 unsigned int pps_out_num;
346 /* Alternate (enhanced) DESC mode */
347 unsigned int enh_desc;
348 /* TX and RX FIFO sizes */
349 unsigned int tx_fifo_size;
350 unsigned int rx_fifo_size;
351 /* Automotive Safety Package */
352 unsigned int asp;
353 /* RX Parser */
354 unsigned int frpsel;
355 unsigned int frpbs;
356 unsigned int frpes;
357 unsigned int addr64;
358 unsigned int rssen;
359 unsigned int vlhash;
360 unsigned int sphen;
361 unsigned int vlins;
362 unsigned int dvlan;
363 unsigned int l3l4fnum;
364 unsigned int arpoffsel;
365};
366
367/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
368#define BUF_SIZE_16KiB 16384
369/* RX Buffer size must be < 8191 and multiple of 4/8/16 bytes */
370#define BUF_SIZE_8KiB 8188
371#define BUF_SIZE_4KiB 4096
372#define BUF_SIZE_2KiB 2048
373
374/* Power Down and WOL */
375#define PMT_NOT_SUPPORTED 0
376#define PMT_SUPPORTED 1
377
378/* Common MAC defines */
379#define MAC_CTRL_REG 0x00000000 /* MAC Control */
380#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
381#define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
382
383/* Default LPI timers */
384#define STMMAC_DEFAULT_LIT_LS 0x3E8
385#define STMMAC_DEFAULT_TWT_LS 0x1E
386
387#define STMMAC_CHAIN_MODE 0x1
388#define STMMAC_RING_MODE 0x2
389
390#define JUMBO_LEN 9000
391
392/* Receive Side Scaling */
393#define STMMAC_RSS_HASH_KEY_SIZE 40
394#define STMMAC_RSS_MAX_TABLE_SIZE 256
395
396/* VLAN */
397#define STMMAC_VLAN_NONE 0x0
398#define STMMAC_VLAN_REMOVE 0x1
399#define STMMAC_VLAN_INSERT 0x2
400#define STMMAC_VLAN_REPLACE 0x3
401
402extern const struct stmmac_desc_ops enh_desc_ops;
403extern const struct stmmac_desc_ops ndesc_ops;
404
405struct mac_device_info;
406
407extern const struct stmmac_hwtimestamp stmmac_ptp;
408extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
409
410struct mac_link {
411 u32 speed_mask;
412 u32 speed10;
413 u32 speed100;
414 u32 speed1000;
415 u32 speed2500;
416 u32 duplex;
417 struct {
418 u32 speed2500;
419 u32 speed5000;
420 u32 speed10000;
421 } xgmii;
422};
423
424struct mii_regs {
425 unsigned int addr; /* MII Address */
426 unsigned int data; /* MII Data */
427 unsigned int addr_shift; /* MII address shift */
428 unsigned int reg_shift; /* MII reg shift */
429 unsigned int addr_mask; /* MII address mask */
430 unsigned int reg_mask; /* MII reg mask */
431 unsigned int clk_csr_shift;
432 unsigned int clk_csr_mask;
433};
434
435struct mac_device_info {
436 const struct stmmac_ops *mac;
437 const struct stmmac_desc_ops *desc;
438 const struct stmmac_dma_ops *dma;
439 const struct stmmac_mode_ops *mode;
440 const struct stmmac_hwtimestamp *ptp;
441 const struct stmmac_tc_ops *tc;
442 const struct stmmac_mmc_ops *mmc;
443 struct mii_regs mii; /* MII register Addresses */
444 struct mac_link link;
445 void __iomem *pcsr; /* vpointer to device CSRs */
446 unsigned int multicast_filter_bins;
447 unsigned int unicast_filter_entries;
448 unsigned int mcast_bits_log2;
449 unsigned int rx_csum;
450 unsigned int pcs;
451 unsigned int pmt;
452 unsigned int ps;
453};
454
455struct stmmac_rx_routing {
456 u32 reg_mask;
457 u32 reg_shift;
458};
459
460int dwmac100_setup(struct stmmac_priv *priv);
461int dwmac1000_setup(struct stmmac_priv *priv);
462int dwmac4_setup(struct stmmac_priv *priv);
463int dwxgmac2_setup(struct stmmac_priv *priv);
464
465void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
466 unsigned int high, unsigned int low);
467void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
468 unsigned int high, unsigned int low);
469void stmmac_set_mac(void __iomem *ioaddr, bool enable);
470
471void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
472 unsigned int high, unsigned int low);
473void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
474 unsigned int high, unsigned int low);
475void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
476
477void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
478
479extern const struct stmmac_mode_ops ring_mode_ops;
480extern const struct stmmac_mode_ops chain_mode_ops;
481extern const struct stmmac_desc_ops dwmac4_desc_ops;
482
483#endif /* __COMMON_H__ */