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1// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2/* Copyright (C) 2018 KVASER AB, Sweden. All rights reserved.
3 * Parts of this driver are based on the following:
4 * - Kvaser linux pciefd driver (version 5.42)
5 * - PEAK linux canfd driver
6 */
7
8#include <linux/bitfield.h>
9#include <linux/can/dev.h>
10#include <linux/device.h>
11#include <linux/ethtool.h>
12#include <linux/iopoll.h>
13#include <linux/kernel.h>
14#include <linux/minmax.h>
15#include <linux/module.h>
16#include <linux/netdevice.h>
17#include <linux/pci.h>
18#include <linux/timer.h>
19
20MODULE_LICENSE("Dual BSD/GPL");
21MODULE_AUTHOR("Kvaser AB <support@kvaser.com>");
22MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices");
23
24#define KVASER_PCIEFD_DRV_NAME "kvaser_pciefd"
25
26#define KVASER_PCIEFD_WAIT_TIMEOUT msecs_to_jiffies(1000)
27#define KVASER_PCIEFD_BEC_POLL_FREQ (jiffies + msecs_to_jiffies(200))
28#define KVASER_PCIEFD_MAX_ERR_REP 256U
29#define KVASER_PCIEFD_CAN_TX_MAX_COUNT 17U
30#define KVASER_PCIEFD_MAX_CAN_CHANNELS 4UL
31#define KVASER_PCIEFD_DMA_COUNT 2U
32
33#define KVASER_PCIEFD_DMA_SIZE (4U * 1024U)
34
35#define KVASER_PCIEFD_VENDOR 0x1a07
36/* Altera based devices */
37#define KVASER_PCIEFD_4HS_DEVICE_ID 0x000d
38#define KVASER_PCIEFD_2HS_V2_DEVICE_ID 0x000e
39#define KVASER_PCIEFD_HS_V2_DEVICE_ID 0x000f
40#define KVASER_PCIEFD_MINIPCIE_HS_V2_DEVICE_ID 0x0010
41#define KVASER_PCIEFD_MINIPCIE_2HS_V2_DEVICE_ID 0x0011
42
43/* SmartFusion2 based devices */
44#define KVASER_PCIEFD_2CAN_V3_DEVICE_ID 0x0012
45#define KVASER_PCIEFD_1CAN_V3_DEVICE_ID 0x0013
46#define KVASER_PCIEFD_4CAN_V2_DEVICE_ID 0x0014
47#define KVASER_PCIEFD_MINIPCIE_2CAN_V3_DEVICE_ID 0x0015
48#define KVASER_PCIEFD_MINIPCIE_1CAN_V3_DEVICE_ID 0x0016
49
50/* Altera SerDes Enable 64-bit DMA address translation */
51#define KVASER_PCIEFD_ALTERA_DMA_64BIT BIT(0)
52
53/* SmartFusion2 SerDes LSB address translation mask */
54#define KVASER_PCIEFD_SF2_DMA_LSB_MASK GENMASK(31, 12)
55
56/* Kvaser KCAN CAN controller registers */
57#define KVASER_PCIEFD_KCAN_FIFO_REG 0x100
58#define KVASER_PCIEFD_KCAN_FIFO_LAST_REG 0x180
59#define KVASER_PCIEFD_KCAN_CTRL_REG 0x2c0
60#define KVASER_PCIEFD_KCAN_CMD_REG 0x400
61#define KVASER_PCIEFD_KCAN_IEN_REG 0x408
62#define KVASER_PCIEFD_KCAN_IRQ_REG 0x410
63#define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG 0x414
64#define KVASER_PCIEFD_KCAN_STAT_REG 0x418
65#define KVASER_PCIEFD_KCAN_MODE_REG 0x41c
66#define KVASER_PCIEFD_KCAN_BTRN_REG 0x420
67#define KVASER_PCIEFD_KCAN_BUS_LOAD_REG 0x424
68#define KVASER_PCIEFD_KCAN_BTRD_REG 0x428
69#define KVASER_PCIEFD_KCAN_PWM_REG 0x430
70/* System identification and information registers */
71#define KVASER_PCIEFD_SYSID_VERSION_REG 0x8
72#define KVASER_PCIEFD_SYSID_CANFREQ_REG 0xc
73#define KVASER_PCIEFD_SYSID_BUSFREQ_REG 0x10
74#define KVASER_PCIEFD_SYSID_BUILD_REG 0x14
75/* Shared receive buffer FIFO registers */
76#define KVASER_PCIEFD_SRB_FIFO_LAST_REG 0x1f4
77/* Shared receive buffer registers */
78#define KVASER_PCIEFD_SRB_CMD_REG 0x0
79#define KVASER_PCIEFD_SRB_IEN_REG 0x04
80#define KVASER_PCIEFD_SRB_IRQ_REG 0x0c
81#define KVASER_PCIEFD_SRB_STAT_REG 0x10
82#define KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG 0x14
83#define KVASER_PCIEFD_SRB_CTRL_REG 0x18
84
85/* System build information fields */
86#define KVASER_PCIEFD_SYSID_VERSION_NR_CHAN_MASK GENMASK(31, 24)
87#define KVASER_PCIEFD_SYSID_VERSION_MAJOR_MASK GENMASK(23, 16)
88#define KVASER_PCIEFD_SYSID_VERSION_MINOR_MASK GENMASK(7, 0)
89#define KVASER_PCIEFD_SYSID_BUILD_SEQ_MASK GENMASK(15, 1)
90
91/* Reset DMA buffer 0, 1 and FIFO offset */
92#define KVASER_PCIEFD_SRB_CMD_RDB1 BIT(5)
93#define KVASER_PCIEFD_SRB_CMD_RDB0 BIT(4)
94#define KVASER_PCIEFD_SRB_CMD_FOR BIT(0)
95
96/* DMA underflow, buffer 0 and 1 */
97#define KVASER_PCIEFD_SRB_IRQ_DUF1 BIT(13)
98#define KVASER_PCIEFD_SRB_IRQ_DUF0 BIT(12)
99/* DMA overflow, buffer 0 and 1 */
100#define KVASER_PCIEFD_SRB_IRQ_DOF1 BIT(11)
101#define KVASER_PCIEFD_SRB_IRQ_DOF0 BIT(10)
102/* DMA packet done, buffer 0 and 1 */
103#define KVASER_PCIEFD_SRB_IRQ_DPD1 BIT(9)
104#define KVASER_PCIEFD_SRB_IRQ_DPD0 BIT(8)
105
106/* Got DMA support */
107#define KVASER_PCIEFD_SRB_STAT_DMA BIT(24)
108/* DMA idle */
109#define KVASER_PCIEFD_SRB_STAT_DI BIT(15)
110
111/* SRB current packet level */
112#define KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK GENMASK(7, 0)
113
114/* DMA Enable */
115#define KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE BIT(0)
116
117/* KCAN CTRL packet types */
118#define KVASER_PCIEFD_KCAN_CTRL_TYPE_MASK GENMASK(31, 29)
119#define KVASER_PCIEFD_KCAN_CTRL_TYPE_EFLUSH 0x4
120#define KVASER_PCIEFD_KCAN_CTRL_TYPE_EFRAME 0x5
121
122/* Command sequence number */
123#define KVASER_PCIEFD_KCAN_CMD_SEQ_MASK GENMASK(23, 16)
124/* Command bits */
125#define KVASER_PCIEFD_KCAN_CMD_MASK GENMASK(5, 0)
126/* Abort, flush and reset */
127#define KVASER_PCIEFD_KCAN_CMD_AT BIT(1)
128/* Request status packet */
129#define KVASER_PCIEFD_KCAN_CMD_SRQ BIT(0)
130
131/* Transmitter unaligned */
132#define KVASER_PCIEFD_KCAN_IRQ_TAL BIT(17)
133/* Tx FIFO empty */
134#define KVASER_PCIEFD_KCAN_IRQ_TE BIT(16)
135/* Tx FIFO overflow */
136#define KVASER_PCIEFD_KCAN_IRQ_TOF BIT(15)
137/* Tx buffer flush done */
138#define KVASER_PCIEFD_KCAN_IRQ_TFD BIT(14)
139/* Abort done */
140#define KVASER_PCIEFD_KCAN_IRQ_ABD BIT(13)
141/* Rx FIFO overflow */
142#define KVASER_PCIEFD_KCAN_IRQ_ROF BIT(5)
143/* FDF bit when controller is in classic CAN mode */
144#define KVASER_PCIEFD_KCAN_IRQ_FDIC BIT(3)
145/* Bus parameter protection error */
146#define KVASER_PCIEFD_KCAN_IRQ_BPP BIT(2)
147/* Tx FIFO unaligned end */
148#define KVASER_PCIEFD_KCAN_IRQ_TAE BIT(1)
149/* Tx FIFO unaligned read */
150#define KVASER_PCIEFD_KCAN_IRQ_TAR BIT(0)
151
152/* Tx FIFO size */
153#define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_MAX_MASK GENMASK(23, 16)
154/* Tx FIFO current packet level */
155#define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK GENMASK(7, 0)
156
157/* Current status packet sequence number */
158#define KVASER_PCIEFD_KCAN_STAT_SEQNO_MASK GENMASK(31, 24)
159/* Controller got CAN FD capability */
160#define KVASER_PCIEFD_KCAN_STAT_FD BIT(19)
161/* Controller got one-shot capability */
162#define KVASER_PCIEFD_KCAN_STAT_CAP BIT(16)
163/* Controller in reset mode */
164#define KVASER_PCIEFD_KCAN_STAT_IRM BIT(15)
165/* Reset mode request */
166#define KVASER_PCIEFD_KCAN_STAT_RMR BIT(14)
167/* Bus off */
168#define KVASER_PCIEFD_KCAN_STAT_BOFF BIT(11)
169/* Idle state. Controller in reset mode and no abort or flush pending */
170#define KVASER_PCIEFD_KCAN_STAT_IDLE BIT(10)
171/* Abort request */
172#define KVASER_PCIEFD_KCAN_STAT_AR BIT(7)
173/* Controller is bus off */
174#define KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MASK \
175 (KVASER_PCIEFD_KCAN_STAT_AR | KVASER_PCIEFD_KCAN_STAT_BOFF | \
176 KVASER_PCIEFD_KCAN_STAT_RMR | KVASER_PCIEFD_KCAN_STAT_IRM)
177
178/* Classic CAN mode */
179#define KVASER_PCIEFD_KCAN_MODE_CCM BIT(31)
180/* Active error flag enable. Clear to force error passive */
181#define KVASER_PCIEFD_KCAN_MODE_EEN BIT(23)
182/* Acknowledgment packet type */
183#define KVASER_PCIEFD_KCAN_MODE_APT BIT(20)
184/* CAN FD non-ISO */
185#define KVASER_PCIEFD_KCAN_MODE_NIFDEN BIT(15)
186/* Error packet enable */
187#define KVASER_PCIEFD_KCAN_MODE_EPEN BIT(12)
188/* Listen only mode */
189#define KVASER_PCIEFD_KCAN_MODE_LOM BIT(9)
190/* Reset mode */
191#define KVASER_PCIEFD_KCAN_MODE_RM BIT(8)
192
193/* BTRN and BTRD fields */
194#define KVASER_PCIEFD_KCAN_BTRN_TSEG2_MASK GENMASK(30, 26)
195#define KVASER_PCIEFD_KCAN_BTRN_TSEG1_MASK GENMASK(25, 17)
196#define KVASER_PCIEFD_KCAN_BTRN_SJW_MASK GENMASK(16, 13)
197#define KVASER_PCIEFD_KCAN_BTRN_BRP_MASK GENMASK(12, 0)
198
199/* PWM Control fields */
200#define KVASER_PCIEFD_KCAN_PWM_TOP_MASK GENMASK(23, 16)
201#define KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK GENMASK(7, 0)
202
203/* KCAN packet type IDs */
204#define KVASER_PCIEFD_PACK_TYPE_DATA 0x0
205#define KVASER_PCIEFD_PACK_TYPE_ACK 0x1
206#define KVASER_PCIEFD_PACK_TYPE_TXRQ 0x2
207#define KVASER_PCIEFD_PACK_TYPE_ERROR 0x3
208#define KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK 0x4
209#define KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK 0x5
210#define KVASER_PCIEFD_PACK_TYPE_ACK_DATA 0x6
211#define KVASER_PCIEFD_PACK_TYPE_STATUS 0x8
212#define KVASER_PCIEFD_PACK_TYPE_BUS_LOAD 0x9
213
214/* Common KCAN packet definitions, second word */
215#define KVASER_PCIEFD_PACKET_TYPE_MASK GENMASK(31, 28)
216#define KVASER_PCIEFD_PACKET_CHID_MASK GENMASK(27, 25)
217#define KVASER_PCIEFD_PACKET_SEQ_MASK GENMASK(7, 0)
218
219/* KCAN Transmit/Receive data packet, first word */
220#define KVASER_PCIEFD_RPACKET_IDE BIT(30)
221#define KVASER_PCIEFD_RPACKET_RTR BIT(29)
222#define KVASER_PCIEFD_RPACKET_ID_MASK GENMASK(28, 0)
223/* KCAN Transmit data packet, second word */
224#define KVASER_PCIEFD_TPACKET_AREQ BIT(31)
225#define KVASER_PCIEFD_TPACKET_SMS BIT(16)
226/* KCAN Transmit/Receive data packet, second word */
227#define KVASER_PCIEFD_RPACKET_FDF BIT(15)
228#define KVASER_PCIEFD_RPACKET_BRS BIT(14)
229#define KVASER_PCIEFD_RPACKET_ESI BIT(13)
230#define KVASER_PCIEFD_RPACKET_DLC_MASK GENMASK(11, 8)
231
232/* KCAN Transmit acknowledge packet, first word */
233#define KVASER_PCIEFD_APACKET_NACK BIT(11)
234#define KVASER_PCIEFD_APACKET_ABL BIT(10)
235#define KVASER_PCIEFD_APACKET_CT BIT(9)
236#define KVASER_PCIEFD_APACKET_FLU BIT(8)
237
238/* KCAN Status packet, first word */
239#define KVASER_PCIEFD_SPACK_RMCD BIT(22)
240#define KVASER_PCIEFD_SPACK_IRM BIT(21)
241#define KVASER_PCIEFD_SPACK_IDET BIT(20)
242#define KVASER_PCIEFD_SPACK_BOFF BIT(16)
243#define KVASER_PCIEFD_SPACK_RXERR_MASK GENMASK(15, 8)
244#define KVASER_PCIEFD_SPACK_TXERR_MASK GENMASK(7, 0)
245/* KCAN Status packet, second word */
246#define KVASER_PCIEFD_SPACK_EPLR BIT(24)
247#define KVASER_PCIEFD_SPACK_EWLR BIT(23)
248#define KVASER_PCIEFD_SPACK_AUTO BIT(21)
249
250/* KCAN Error detected packet, second word */
251#define KVASER_PCIEFD_EPACK_DIR_TX BIT(0)
252
253/* Macros for calculating addresses of registers */
254#define KVASER_PCIEFD_GET_BLOCK_ADDR(pcie, block) \
255 ((pcie)->reg_base + (pcie)->driver_data->address_offset->block)
256#define KVASER_PCIEFD_PCI_IEN_ADDR(pcie) \
257 (KVASER_PCIEFD_GET_BLOCK_ADDR((pcie), pci_ien))
258#define KVASER_PCIEFD_PCI_IRQ_ADDR(pcie) \
259 (KVASER_PCIEFD_GET_BLOCK_ADDR((pcie), pci_irq))
260#define KVASER_PCIEFD_SERDES_ADDR(pcie) \
261 (KVASER_PCIEFD_GET_BLOCK_ADDR((pcie), serdes))
262#define KVASER_PCIEFD_SYSID_ADDR(pcie) \
263 (KVASER_PCIEFD_GET_BLOCK_ADDR((pcie), sysid))
264#define KVASER_PCIEFD_LOOPBACK_ADDR(pcie) \
265 (KVASER_PCIEFD_GET_BLOCK_ADDR((pcie), loopback))
266#define KVASER_PCIEFD_SRB_FIFO_ADDR(pcie) \
267 (KVASER_PCIEFD_GET_BLOCK_ADDR((pcie), kcan_srb_fifo))
268#define KVASER_PCIEFD_SRB_ADDR(pcie) \
269 (KVASER_PCIEFD_GET_BLOCK_ADDR((pcie), kcan_srb))
270#define KVASER_PCIEFD_KCAN_CH0_ADDR(pcie) \
271 (KVASER_PCIEFD_GET_BLOCK_ADDR((pcie), kcan_ch0))
272#define KVASER_PCIEFD_KCAN_CH1_ADDR(pcie) \
273 (KVASER_PCIEFD_GET_BLOCK_ADDR((pcie), kcan_ch1))
274#define KVASER_PCIEFD_KCAN_CHANNEL_SPAN(pcie) \
275 (KVASER_PCIEFD_KCAN_CH1_ADDR((pcie)) - KVASER_PCIEFD_KCAN_CH0_ADDR((pcie)))
276#define KVASER_PCIEFD_KCAN_CHX_ADDR(pcie, i) \
277 (KVASER_PCIEFD_KCAN_CH0_ADDR((pcie)) + (i) * KVASER_PCIEFD_KCAN_CHANNEL_SPAN((pcie)))
278
279struct kvaser_pciefd;
280static void kvaser_pciefd_write_dma_map_altera(struct kvaser_pciefd *pcie,
281 dma_addr_t addr, int index);
282static void kvaser_pciefd_write_dma_map_sf2(struct kvaser_pciefd *pcie,
283 dma_addr_t addr, int index);
284
285struct kvaser_pciefd_address_offset {
286 u32 serdes;
287 u32 pci_ien;
288 u32 pci_irq;
289 u32 sysid;
290 u32 loopback;
291 u32 kcan_srb_fifo;
292 u32 kcan_srb;
293 u32 kcan_ch0;
294 u32 kcan_ch1;
295};
296
297struct kvaser_pciefd_dev_ops {
298 void (*kvaser_pciefd_write_dma_map)(struct kvaser_pciefd *pcie,
299 dma_addr_t addr, int index);
300};
301
302struct kvaser_pciefd_irq_mask {
303 u32 kcan_rx0;
304 u32 kcan_tx[KVASER_PCIEFD_MAX_CAN_CHANNELS];
305 u32 all;
306};
307
308struct kvaser_pciefd_driver_data {
309 const struct kvaser_pciefd_address_offset *address_offset;
310 const struct kvaser_pciefd_irq_mask *irq_mask;
311 const struct kvaser_pciefd_dev_ops *ops;
312};
313
314static const struct kvaser_pciefd_address_offset kvaser_pciefd_altera_address_offset = {
315 .serdes = 0x1000,
316 .pci_ien = 0x50,
317 .pci_irq = 0x40,
318 .sysid = 0x1f020,
319 .loopback = 0x1f000,
320 .kcan_srb_fifo = 0x1f200,
321 .kcan_srb = 0x1f400,
322 .kcan_ch0 = 0x10000,
323 .kcan_ch1 = 0x11000,
324};
325
326static const struct kvaser_pciefd_address_offset kvaser_pciefd_sf2_address_offset = {
327 .serdes = 0x280c8,
328 .pci_ien = 0x102004,
329 .pci_irq = 0x102008,
330 .sysid = 0x100000,
331 .loopback = 0x103000,
332 .kcan_srb_fifo = 0x120000,
333 .kcan_srb = 0x121000,
334 .kcan_ch0 = 0x140000,
335 .kcan_ch1 = 0x142000,
336};
337
338static const struct kvaser_pciefd_irq_mask kvaser_pciefd_altera_irq_mask = {
339 .kcan_rx0 = BIT(4),
340 .kcan_tx = { BIT(0), BIT(1), BIT(2), BIT(3) },
341 .all = GENMASK(4, 0),
342};
343
344static const struct kvaser_pciefd_irq_mask kvaser_pciefd_sf2_irq_mask = {
345 .kcan_rx0 = BIT(4),
346 .kcan_tx = { BIT(16), BIT(17), BIT(18), BIT(19) },
347 .all = GENMASK(19, 16) | BIT(4),
348};
349
350static const struct kvaser_pciefd_dev_ops kvaser_pciefd_altera_dev_ops = {
351 .kvaser_pciefd_write_dma_map = kvaser_pciefd_write_dma_map_altera,
352};
353
354static const struct kvaser_pciefd_dev_ops kvaser_pciefd_sf2_dev_ops = {
355 .kvaser_pciefd_write_dma_map = kvaser_pciefd_write_dma_map_sf2,
356};
357
358static const struct kvaser_pciefd_driver_data kvaser_pciefd_altera_driver_data = {
359 .address_offset = &kvaser_pciefd_altera_address_offset,
360 .irq_mask = &kvaser_pciefd_altera_irq_mask,
361 .ops = &kvaser_pciefd_altera_dev_ops,
362};
363
364static const struct kvaser_pciefd_driver_data kvaser_pciefd_sf2_driver_data = {
365 .address_offset = &kvaser_pciefd_sf2_address_offset,
366 .irq_mask = &kvaser_pciefd_sf2_irq_mask,
367 .ops = &kvaser_pciefd_sf2_dev_ops,
368};
369
370struct kvaser_pciefd_can {
371 struct can_priv can;
372 struct kvaser_pciefd *kv_pcie;
373 void __iomem *reg_base;
374 struct can_berr_counter bec;
375 u8 cmd_seq;
376 int err_rep_cnt;
377 int echo_idx;
378 spinlock_t lock; /* Locks sensitive registers (e.g. MODE) */
379 spinlock_t echo_lock; /* Locks the message echo buffer */
380 struct timer_list bec_poll_timer;
381 struct completion start_comp, flush_comp;
382};
383
384struct kvaser_pciefd {
385 struct pci_dev *pci;
386 void __iomem *reg_base;
387 struct kvaser_pciefd_can *can[KVASER_PCIEFD_MAX_CAN_CHANNELS];
388 const struct kvaser_pciefd_driver_data *driver_data;
389 void *dma_data[KVASER_PCIEFD_DMA_COUNT];
390 u8 nr_channels;
391 u32 bus_freq;
392 u32 freq;
393 u32 freq_to_ticks_div;
394};
395
396struct kvaser_pciefd_rx_packet {
397 u32 header[2];
398 u64 timestamp;
399};
400
401struct kvaser_pciefd_tx_packet {
402 u32 header[2];
403 u8 data[64];
404};
405
406static const struct can_bittiming_const kvaser_pciefd_bittiming_const = {
407 .name = KVASER_PCIEFD_DRV_NAME,
408 .tseg1_min = 1,
409 .tseg1_max = 512,
410 .tseg2_min = 1,
411 .tseg2_max = 32,
412 .sjw_max = 16,
413 .brp_min = 1,
414 .brp_max = 8192,
415 .brp_inc = 1,
416};
417
418static struct pci_device_id kvaser_pciefd_id_table[] = {
419 {
420 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_4HS_DEVICE_ID),
421 .driver_data = (kernel_ulong_t)&kvaser_pciefd_altera_driver_data,
422 },
423 {
424 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_2HS_V2_DEVICE_ID),
425 .driver_data = (kernel_ulong_t)&kvaser_pciefd_altera_driver_data,
426 },
427 {
428 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_HS_V2_DEVICE_ID),
429 .driver_data = (kernel_ulong_t)&kvaser_pciefd_altera_driver_data,
430 },
431 {
432 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_HS_V2_DEVICE_ID),
433 .driver_data = (kernel_ulong_t)&kvaser_pciefd_altera_driver_data,
434 },
435 {
436 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_2HS_V2_DEVICE_ID),
437 .driver_data = (kernel_ulong_t)&kvaser_pciefd_altera_driver_data,
438 },
439 {
440 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_2CAN_V3_DEVICE_ID),
441 .driver_data = (kernel_ulong_t)&kvaser_pciefd_sf2_driver_data,
442 },
443 {
444 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_1CAN_V3_DEVICE_ID),
445 .driver_data = (kernel_ulong_t)&kvaser_pciefd_sf2_driver_data,
446 },
447 {
448 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_4CAN_V2_DEVICE_ID),
449 .driver_data = (kernel_ulong_t)&kvaser_pciefd_sf2_driver_data,
450 },
451 {
452 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_2CAN_V3_DEVICE_ID),
453 .driver_data = (kernel_ulong_t)&kvaser_pciefd_sf2_driver_data,
454 },
455 {
456 PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_1CAN_V3_DEVICE_ID),
457 .driver_data = (kernel_ulong_t)&kvaser_pciefd_sf2_driver_data,
458 },
459 {
460 0,
461 },
462};
463MODULE_DEVICE_TABLE(pci, kvaser_pciefd_id_table);
464
465static inline void kvaser_pciefd_send_kcan_cmd(struct kvaser_pciefd_can *can, u32 cmd)
466{
467 iowrite32(FIELD_PREP(KVASER_PCIEFD_KCAN_CMD_MASK, cmd) |
468 FIELD_PREP(KVASER_PCIEFD_KCAN_CMD_SEQ_MASK, ++can->cmd_seq),
469 can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
470}
471
472static inline void kvaser_pciefd_request_status(struct kvaser_pciefd_can *can)
473{
474 kvaser_pciefd_send_kcan_cmd(can, KVASER_PCIEFD_KCAN_CMD_SRQ);
475}
476
477static inline void kvaser_pciefd_abort_flush_reset(struct kvaser_pciefd_can *can)
478{
479 kvaser_pciefd_send_kcan_cmd(can, KVASER_PCIEFD_KCAN_CMD_AT);
480}
481
482static void kvaser_pciefd_enable_err_gen(struct kvaser_pciefd_can *can)
483{
484 u32 mode;
485 unsigned long irq;
486
487 spin_lock_irqsave(&can->lock, irq);
488 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
489 if (!(mode & KVASER_PCIEFD_KCAN_MODE_EPEN)) {
490 mode |= KVASER_PCIEFD_KCAN_MODE_EPEN;
491 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
492 }
493 spin_unlock_irqrestore(&can->lock, irq);
494}
495
496static void kvaser_pciefd_disable_err_gen(struct kvaser_pciefd_can *can)
497{
498 u32 mode;
499 unsigned long irq;
500
501 spin_lock_irqsave(&can->lock, irq);
502 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
503 mode &= ~KVASER_PCIEFD_KCAN_MODE_EPEN;
504 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
505 spin_unlock_irqrestore(&can->lock, irq);
506}
507
508static void kvaser_pciefd_set_tx_irq(struct kvaser_pciefd_can *can)
509{
510 u32 msk;
511
512 msk = KVASER_PCIEFD_KCAN_IRQ_TE | KVASER_PCIEFD_KCAN_IRQ_ROF |
513 KVASER_PCIEFD_KCAN_IRQ_TOF | KVASER_PCIEFD_KCAN_IRQ_ABD |
514 KVASER_PCIEFD_KCAN_IRQ_TAE | KVASER_PCIEFD_KCAN_IRQ_TAL |
515 KVASER_PCIEFD_KCAN_IRQ_FDIC | KVASER_PCIEFD_KCAN_IRQ_BPP |
516 KVASER_PCIEFD_KCAN_IRQ_TAR;
517
518 iowrite32(msk, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
519}
520
521static inline void kvaser_pciefd_set_skb_timestamp(const struct kvaser_pciefd *pcie,
522 struct sk_buff *skb, u64 timestamp)
523{
524 skb_hwtstamps(skb)->hwtstamp =
525 ns_to_ktime(div_u64(timestamp * 1000, pcie->freq_to_ticks_div));
526}
527
528static void kvaser_pciefd_setup_controller(struct kvaser_pciefd_can *can)
529{
530 u32 mode;
531 unsigned long irq;
532
533 spin_lock_irqsave(&can->lock, irq);
534 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
535 if (can->can.ctrlmode & CAN_CTRLMODE_FD) {
536 mode &= ~KVASER_PCIEFD_KCAN_MODE_CCM;
537 if (can->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)
538 mode |= KVASER_PCIEFD_KCAN_MODE_NIFDEN;
539 else
540 mode &= ~KVASER_PCIEFD_KCAN_MODE_NIFDEN;
541 } else {
542 mode |= KVASER_PCIEFD_KCAN_MODE_CCM;
543 mode &= ~KVASER_PCIEFD_KCAN_MODE_NIFDEN;
544 }
545
546 if (can->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
547 mode |= KVASER_PCIEFD_KCAN_MODE_LOM;
548 else
549 mode &= ~KVASER_PCIEFD_KCAN_MODE_LOM;
550 mode |= KVASER_PCIEFD_KCAN_MODE_EEN;
551 mode |= KVASER_PCIEFD_KCAN_MODE_EPEN;
552 /* Use ACK packet type */
553 mode &= ~KVASER_PCIEFD_KCAN_MODE_APT;
554 mode &= ~KVASER_PCIEFD_KCAN_MODE_RM;
555 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
556
557 spin_unlock_irqrestore(&can->lock, irq);
558}
559
560static void kvaser_pciefd_start_controller_flush(struct kvaser_pciefd_can *can)
561{
562 u32 status;
563 unsigned long irq;
564
565 spin_lock_irqsave(&can->lock, irq);
566 iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
567 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
568 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
569 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
570 if (status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
571 /* If controller is already idle, run abort, flush and reset */
572 kvaser_pciefd_abort_flush_reset(can);
573 } else if (!(status & KVASER_PCIEFD_KCAN_STAT_RMR)) {
574 u32 mode;
575
576 /* Put controller in reset mode */
577 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
578 mode |= KVASER_PCIEFD_KCAN_MODE_RM;
579 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
580 }
581 spin_unlock_irqrestore(&can->lock, irq);
582}
583
584static int kvaser_pciefd_bus_on(struct kvaser_pciefd_can *can)
585{
586 u32 mode;
587 unsigned long irq;
588
589 del_timer(&can->bec_poll_timer);
590 if (!completion_done(&can->flush_comp))
591 kvaser_pciefd_start_controller_flush(can);
592
593 if (!wait_for_completion_timeout(&can->flush_comp,
594 KVASER_PCIEFD_WAIT_TIMEOUT)) {
595 netdev_err(can->can.dev, "Timeout during bus on flush\n");
596 return -ETIMEDOUT;
597 }
598
599 spin_lock_irqsave(&can->lock, irq);
600 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
601 iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
602 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
603 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
604 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
605 mode &= ~KVASER_PCIEFD_KCAN_MODE_RM;
606 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
607 spin_unlock_irqrestore(&can->lock, irq);
608
609 if (!wait_for_completion_timeout(&can->start_comp,
610 KVASER_PCIEFD_WAIT_TIMEOUT)) {
611 netdev_err(can->can.dev, "Timeout during bus on reset\n");
612 return -ETIMEDOUT;
613 }
614 /* Reset interrupt handling */
615 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
616 iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
617
618 kvaser_pciefd_set_tx_irq(can);
619 kvaser_pciefd_setup_controller(can);
620 can->can.state = CAN_STATE_ERROR_ACTIVE;
621 netif_wake_queue(can->can.dev);
622 can->bec.txerr = 0;
623 can->bec.rxerr = 0;
624 can->err_rep_cnt = 0;
625
626 return 0;
627}
628
629static void kvaser_pciefd_pwm_stop(struct kvaser_pciefd_can *can)
630{
631 u8 top;
632 u32 pwm_ctrl;
633 unsigned long irq;
634
635 spin_lock_irqsave(&can->lock, irq);
636 pwm_ctrl = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
637 top = FIELD_GET(KVASER_PCIEFD_KCAN_PWM_TOP_MASK, pwm_ctrl);
638 /* Set duty cycle to zero */
639 pwm_ctrl |= FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK, top);
640 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
641 spin_unlock_irqrestore(&can->lock, irq);
642}
643
644static void kvaser_pciefd_pwm_start(struct kvaser_pciefd_can *can)
645{
646 int top, trigger;
647 u32 pwm_ctrl;
648 unsigned long irq;
649
650 kvaser_pciefd_pwm_stop(can);
651 spin_lock_irqsave(&can->lock, irq);
652 /* Set frequency to 500 KHz */
653 top = can->kv_pcie->bus_freq / (2 * 500000) - 1;
654
655 pwm_ctrl = FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK, top);
656 pwm_ctrl |= FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TOP_MASK, top);
657 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
658
659 /* Set duty cycle to 95 */
660 trigger = (100 * top - 95 * (top + 1) + 50) / 100;
661 pwm_ctrl = FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK, trigger);
662 pwm_ctrl |= FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TOP_MASK, top);
663 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
664 spin_unlock_irqrestore(&can->lock, irq);
665}
666
667static int kvaser_pciefd_open(struct net_device *netdev)
668{
669 int err;
670 struct kvaser_pciefd_can *can = netdev_priv(netdev);
671
672 err = open_candev(netdev);
673 if (err)
674 return err;
675
676 err = kvaser_pciefd_bus_on(can);
677 if (err) {
678 close_candev(netdev);
679 return err;
680 }
681
682 return 0;
683}
684
685static int kvaser_pciefd_stop(struct net_device *netdev)
686{
687 struct kvaser_pciefd_can *can = netdev_priv(netdev);
688 int ret = 0;
689
690 /* Don't interrupt ongoing flush */
691 if (!completion_done(&can->flush_comp))
692 kvaser_pciefd_start_controller_flush(can);
693
694 if (!wait_for_completion_timeout(&can->flush_comp,
695 KVASER_PCIEFD_WAIT_TIMEOUT)) {
696 netdev_err(can->can.dev, "Timeout during stop\n");
697 ret = -ETIMEDOUT;
698 } else {
699 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
700 del_timer(&can->bec_poll_timer);
701 }
702 can->can.state = CAN_STATE_STOPPED;
703 close_candev(netdev);
704
705 return ret;
706}
707
708static int kvaser_pciefd_prepare_tx_packet(struct kvaser_pciefd_tx_packet *p,
709 struct kvaser_pciefd_can *can,
710 struct sk_buff *skb)
711{
712 struct canfd_frame *cf = (struct canfd_frame *)skb->data;
713 int packet_size;
714 int seq = can->echo_idx;
715
716 memset(p, 0, sizeof(*p));
717 if (can->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
718 p->header[1] |= KVASER_PCIEFD_TPACKET_SMS;
719
720 if (cf->can_id & CAN_RTR_FLAG)
721 p->header[0] |= KVASER_PCIEFD_RPACKET_RTR;
722
723 if (cf->can_id & CAN_EFF_FLAG)
724 p->header[0] |= KVASER_PCIEFD_RPACKET_IDE;
725
726 p->header[0] |= FIELD_PREP(KVASER_PCIEFD_RPACKET_ID_MASK, cf->can_id);
727 p->header[1] |= KVASER_PCIEFD_TPACKET_AREQ;
728
729 if (can_is_canfd_skb(skb)) {
730 p->header[1] |= FIELD_PREP(KVASER_PCIEFD_RPACKET_DLC_MASK,
731 can_fd_len2dlc(cf->len));
732 p->header[1] |= KVASER_PCIEFD_RPACKET_FDF;
733 if (cf->flags & CANFD_BRS)
734 p->header[1] |= KVASER_PCIEFD_RPACKET_BRS;
735 if (cf->flags & CANFD_ESI)
736 p->header[1] |= KVASER_PCIEFD_RPACKET_ESI;
737 } else {
738 p->header[1] |=
739 FIELD_PREP(KVASER_PCIEFD_RPACKET_DLC_MASK,
740 can_get_cc_dlc((struct can_frame *)cf, can->can.ctrlmode));
741 }
742
743 p->header[1] |= FIELD_PREP(KVASER_PCIEFD_PACKET_SEQ_MASK, seq);
744
745 packet_size = cf->len;
746 memcpy(p->data, cf->data, packet_size);
747
748 return DIV_ROUND_UP(packet_size, 4);
749}
750
751static netdev_tx_t kvaser_pciefd_start_xmit(struct sk_buff *skb,
752 struct net_device *netdev)
753{
754 struct kvaser_pciefd_can *can = netdev_priv(netdev);
755 unsigned long irq_flags;
756 struct kvaser_pciefd_tx_packet packet;
757 int nr_words;
758 u8 count;
759
760 if (can_dev_dropped_skb(netdev, skb))
761 return NETDEV_TX_OK;
762
763 nr_words = kvaser_pciefd_prepare_tx_packet(&packet, can, skb);
764
765 spin_lock_irqsave(&can->echo_lock, irq_flags);
766 /* Prepare and save echo skb in internal slot */
767 can_put_echo_skb(skb, netdev, can->echo_idx, 0);
768
769 /* Move echo index to the next slot */
770 can->echo_idx = (can->echo_idx + 1) % can->can.echo_skb_max;
771
772 /* Write header to fifo */
773 iowrite32(packet.header[0],
774 can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG);
775 iowrite32(packet.header[1],
776 can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG);
777
778 if (nr_words) {
779 u32 data_last = ((u32 *)packet.data)[nr_words - 1];
780
781 /* Write data to fifo, except last word */
782 iowrite32_rep(can->reg_base +
783 KVASER_PCIEFD_KCAN_FIFO_REG, packet.data,
784 nr_words - 1);
785 /* Write last word to end of fifo */
786 __raw_writel(data_last, can->reg_base +
787 KVASER_PCIEFD_KCAN_FIFO_LAST_REG);
788 } else {
789 /* Complete write to fifo */
790 __raw_writel(0, can->reg_base +
791 KVASER_PCIEFD_KCAN_FIFO_LAST_REG);
792 }
793
794 count = FIELD_GET(KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK,
795 ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG));
796 /* No room for a new message, stop the queue until at least one
797 * successful transmit
798 */
799 if (count >= can->can.echo_skb_max || can->can.echo_skb[can->echo_idx])
800 netif_stop_queue(netdev);
801 spin_unlock_irqrestore(&can->echo_lock, irq_flags);
802
803 return NETDEV_TX_OK;
804}
805
806static int kvaser_pciefd_set_bittiming(struct kvaser_pciefd_can *can, bool data)
807{
808 u32 mode, test, btrn;
809 unsigned long irq_flags;
810 int ret;
811 struct can_bittiming *bt;
812
813 if (data)
814 bt = &can->can.data_bittiming;
815 else
816 bt = &can->can.bittiming;
817
818 btrn = FIELD_PREP(KVASER_PCIEFD_KCAN_BTRN_TSEG2_MASK, bt->phase_seg2 - 1) |
819 FIELD_PREP(KVASER_PCIEFD_KCAN_BTRN_TSEG1_MASK, bt->prop_seg + bt->phase_seg1 - 1) |
820 FIELD_PREP(KVASER_PCIEFD_KCAN_BTRN_SJW_MASK, bt->sjw - 1) |
821 FIELD_PREP(KVASER_PCIEFD_KCAN_BTRN_BRP_MASK, bt->brp - 1);
822
823 spin_lock_irqsave(&can->lock, irq_flags);
824 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
825 /* Put the circuit in reset mode */
826 iowrite32(mode | KVASER_PCIEFD_KCAN_MODE_RM,
827 can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
828
829 /* Can only set bittiming if in reset mode */
830 ret = readl_poll_timeout(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG,
831 test, test & KVASER_PCIEFD_KCAN_MODE_RM, 0, 10);
832 if (ret) {
833 spin_unlock_irqrestore(&can->lock, irq_flags);
834 return -EBUSY;
835 }
836
837 if (data)
838 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRD_REG);
839 else
840 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRN_REG);
841 /* Restore previous reset mode status */
842 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
843 spin_unlock_irqrestore(&can->lock, irq_flags);
844
845 return 0;
846}
847
848static int kvaser_pciefd_set_nominal_bittiming(struct net_device *ndev)
849{
850 return kvaser_pciefd_set_bittiming(netdev_priv(ndev), false);
851}
852
853static int kvaser_pciefd_set_data_bittiming(struct net_device *ndev)
854{
855 return kvaser_pciefd_set_bittiming(netdev_priv(ndev), true);
856}
857
858static int kvaser_pciefd_set_mode(struct net_device *ndev, enum can_mode mode)
859{
860 struct kvaser_pciefd_can *can = netdev_priv(ndev);
861 int ret = 0;
862
863 switch (mode) {
864 case CAN_MODE_START:
865 if (!can->can.restart_ms)
866 ret = kvaser_pciefd_bus_on(can);
867 break;
868 default:
869 return -EOPNOTSUPP;
870 }
871
872 return ret;
873}
874
875static int kvaser_pciefd_get_berr_counter(const struct net_device *ndev,
876 struct can_berr_counter *bec)
877{
878 struct kvaser_pciefd_can *can = netdev_priv(ndev);
879
880 bec->rxerr = can->bec.rxerr;
881 bec->txerr = can->bec.txerr;
882
883 return 0;
884}
885
886static void kvaser_pciefd_bec_poll_timer(struct timer_list *data)
887{
888 struct kvaser_pciefd_can *can = from_timer(can, data, bec_poll_timer);
889
890 kvaser_pciefd_enable_err_gen(can);
891 kvaser_pciefd_request_status(can);
892 can->err_rep_cnt = 0;
893}
894
895static const struct net_device_ops kvaser_pciefd_netdev_ops = {
896 .ndo_open = kvaser_pciefd_open,
897 .ndo_stop = kvaser_pciefd_stop,
898 .ndo_eth_ioctl = can_eth_ioctl_hwts,
899 .ndo_start_xmit = kvaser_pciefd_start_xmit,
900 .ndo_change_mtu = can_change_mtu,
901};
902
903static const struct ethtool_ops kvaser_pciefd_ethtool_ops = {
904 .get_ts_info = can_ethtool_op_get_ts_info_hwts,
905};
906
907static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie)
908{
909 int i;
910
911 for (i = 0; i < pcie->nr_channels; i++) {
912 struct net_device *netdev;
913 struct kvaser_pciefd_can *can;
914 u32 status, tx_nr_packets_max;
915
916 netdev = alloc_candev(sizeof(struct kvaser_pciefd_can),
917 KVASER_PCIEFD_CAN_TX_MAX_COUNT);
918 if (!netdev)
919 return -ENOMEM;
920
921 can = netdev_priv(netdev);
922 netdev->netdev_ops = &kvaser_pciefd_netdev_ops;
923 netdev->ethtool_ops = &kvaser_pciefd_ethtool_ops;
924 can->reg_base = KVASER_PCIEFD_KCAN_CHX_ADDR(pcie, i);
925 can->kv_pcie = pcie;
926 can->cmd_seq = 0;
927 can->err_rep_cnt = 0;
928 can->bec.txerr = 0;
929 can->bec.rxerr = 0;
930
931 init_completion(&can->start_comp);
932 init_completion(&can->flush_comp);
933 timer_setup(&can->bec_poll_timer, kvaser_pciefd_bec_poll_timer, 0);
934
935 /* Disable Bus load reporting */
936 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_BUS_LOAD_REG);
937
938 tx_nr_packets_max =
939 FIELD_GET(KVASER_PCIEFD_KCAN_TX_NR_PACKETS_MAX_MASK,
940 ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG));
941
942 can->can.clock.freq = pcie->freq;
943 can->can.echo_skb_max = min(KVASER_PCIEFD_CAN_TX_MAX_COUNT, tx_nr_packets_max - 1);
944 can->echo_idx = 0;
945 spin_lock_init(&can->echo_lock);
946 spin_lock_init(&can->lock);
947
948 can->can.bittiming_const = &kvaser_pciefd_bittiming_const;
949 can->can.data_bittiming_const = &kvaser_pciefd_bittiming_const;
950 can->can.do_set_bittiming = kvaser_pciefd_set_nominal_bittiming;
951 can->can.do_set_data_bittiming = kvaser_pciefd_set_data_bittiming;
952 can->can.do_set_mode = kvaser_pciefd_set_mode;
953 can->can.do_get_berr_counter = kvaser_pciefd_get_berr_counter;
954 can->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
955 CAN_CTRLMODE_FD |
956 CAN_CTRLMODE_FD_NON_ISO |
957 CAN_CTRLMODE_CC_LEN8_DLC;
958
959 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
960 if (!(status & KVASER_PCIEFD_KCAN_STAT_FD)) {
961 dev_err(&pcie->pci->dev,
962 "CAN FD not supported as expected %d\n", i);
963
964 free_candev(netdev);
965 return -ENODEV;
966 }
967
968 if (status & KVASER_PCIEFD_KCAN_STAT_CAP)
969 can->can.ctrlmode_supported |= CAN_CTRLMODE_ONE_SHOT;
970
971 netdev->flags |= IFF_ECHO;
972 SET_NETDEV_DEV(netdev, &pcie->pci->dev);
973
974 iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
975 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
976 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
977
978 pcie->can[i] = can;
979 kvaser_pciefd_pwm_start(can);
980 }
981
982 return 0;
983}
984
985static int kvaser_pciefd_reg_candev(struct kvaser_pciefd *pcie)
986{
987 int i;
988
989 for (i = 0; i < pcie->nr_channels; i++) {
990 int err = register_candev(pcie->can[i]->can.dev);
991
992 if (err) {
993 int j;
994
995 /* Unregister all successfully registered devices. */
996 for (j = 0; j < i; j++)
997 unregister_candev(pcie->can[j]->can.dev);
998 return err;
999 }
1000 }
1001
1002 return 0;
1003}
1004
1005static void kvaser_pciefd_write_dma_map_altera(struct kvaser_pciefd *pcie,
1006 dma_addr_t addr, int index)
1007{
1008 void __iomem *serdes_base;
1009 u32 word1, word2;
1010
1011#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1012 word1 = addr | KVASER_PCIEFD_ALTERA_DMA_64BIT;
1013 word2 = addr >> 32;
1014#else
1015 word1 = addr;
1016 word2 = 0;
1017#endif
1018 serdes_base = KVASER_PCIEFD_SERDES_ADDR(pcie) + 0x8 * index;
1019 iowrite32(word1, serdes_base);
1020 iowrite32(word2, serdes_base + 0x4);
1021}
1022
1023static void kvaser_pciefd_write_dma_map_sf2(struct kvaser_pciefd *pcie,
1024 dma_addr_t addr, int index)
1025{
1026 void __iomem *serdes_base;
1027 u32 lsb = addr & KVASER_PCIEFD_SF2_DMA_LSB_MASK;
1028 u32 msb = 0x0;
1029
1030#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1031 msb = addr >> 32;
1032#endif
1033 serdes_base = KVASER_PCIEFD_SERDES_ADDR(pcie) + 0x10 * index;
1034 iowrite32(lsb, serdes_base);
1035 iowrite32(msb, serdes_base + 0x4);
1036}
1037
1038static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie)
1039{
1040 int i;
1041 u32 srb_status;
1042 u32 srb_packet_count;
1043 dma_addr_t dma_addr[KVASER_PCIEFD_DMA_COUNT];
1044
1045 /* Disable the DMA */
1046 iowrite32(0, KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CTRL_REG);
1047 for (i = 0; i < KVASER_PCIEFD_DMA_COUNT; i++) {
1048 pcie->dma_data[i] = dmam_alloc_coherent(&pcie->pci->dev,
1049 KVASER_PCIEFD_DMA_SIZE,
1050 &dma_addr[i],
1051 GFP_KERNEL);
1052
1053 if (!pcie->dma_data[i] || !dma_addr[i]) {
1054 dev_err(&pcie->pci->dev, "Rx dma_alloc(%u) failure\n",
1055 KVASER_PCIEFD_DMA_SIZE);
1056 return -ENOMEM;
1057 }
1058 pcie->driver_data->ops->kvaser_pciefd_write_dma_map(pcie, dma_addr[i], i);
1059 }
1060
1061 /* Reset Rx FIFO, and both DMA buffers */
1062 iowrite32(KVASER_PCIEFD_SRB_CMD_FOR | KVASER_PCIEFD_SRB_CMD_RDB0 |
1063 KVASER_PCIEFD_SRB_CMD_RDB1,
1064 KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CMD_REG);
1065 /* Empty Rx FIFO */
1066 srb_packet_count =
1067 FIELD_GET(KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK,
1068 ioread32(KVASER_PCIEFD_SRB_ADDR(pcie) +
1069 KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG));
1070 while (srb_packet_count) {
1071 /* Drop current packet in FIFO */
1072 ioread32(KVASER_PCIEFD_SRB_FIFO_ADDR(pcie) + KVASER_PCIEFD_SRB_FIFO_LAST_REG);
1073 srb_packet_count--;
1074 }
1075
1076 srb_status = ioread32(KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_STAT_REG);
1077 if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DI)) {
1078 dev_err(&pcie->pci->dev, "DMA not idle before enabling\n");
1079 return -EIO;
1080 }
1081
1082 /* Enable the DMA */
1083 iowrite32(KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE,
1084 KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CTRL_REG);
1085
1086 return 0;
1087}
1088
1089static int kvaser_pciefd_setup_board(struct kvaser_pciefd *pcie)
1090{
1091 u32 version, srb_status, build;
1092
1093 version = ioread32(KVASER_PCIEFD_SYSID_ADDR(pcie) + KVASER_PCIEFD_SYSID_VERSION_REG);
1094 pcie->nr_channels = min(KVASER_PCIEFD_MAX_CAN_CHANNELS,
1095 FIELD_GET(KVASER_PCIEFD_SYSID_VERSION_NR_CHAN_MASK, version));
1096
1097 build = ioread32(KVASER_PCIEFD_SYSID_ADDR(pcie) + KVASER_PCIEFD_SYSID_BUILD_REG);
1098 dev_dbg(&pcie->pci->dev, "Version %lu.%lu.%lu\n",
1099 FIELD_GET(KVASER_PCIEFD_SYSID_VERSION_MAJOR_MASK, version),
1100 FIELD_GET(KVASER_PCIEFD_SYSID_VERSION_MINOR_MASK, version),
1101 FIELD_GET(KVASER_PCIEFD_SYSID_BUILD_SEQ_MASK, build));
1102
1103 srb_status = ioread32(KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_STAT_REG);
1104 if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DMA)) {
1105 dev_err(&pcie->pci->dev, "Hardware without DMA is not supported\n");
1106 return -ENODEV;
1107 }
1108
1109 pcie->bus_freq = ioread32(KVASER_PCIEFD_SYSID_ADDR(pcie) + KVASER_PCIEFD_SYSID_BUSFREQ_REG);
1110 pcie->freq = ioread32(KVASER_PCIEFD_SYSID_ADDR(pcie) + KVASER_PCIEFD_SYSID_CANFREQ_REG);
1111 pcie->freq_to_ticks_div = pcie->freq / 1000000;
1112 if (pcie->freq_to_ticks_div == 0)
1113 pcie->freq_to_ticks_div = 1;
1114 /* Turn off all loopback functionality */
1115 iowrite32(0, KVASER_PCIEFD_LOOPBACK_ADDR(pcie));
1116
1117 return 0;
1118}
1119
1120static int kvaser_pciefd_handle_data_packet(struct kvaser_pciefd *pcie,
1121 struct kvaser_pciefd_rx_packet *p,
1122 __le32 *data)
1123{
1124 struct sk_buff *skb;
1125 struct canfd_frame *cf;
1126 struct can_priv *priv;
1127 u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
1128 u8 dlc;
1129
1130 if (ch_id >= pcie->nr_channels)
1131 return -EIO;
1132
1133 priv = &pcie->can[ch_id]->can;
1134 dlc = FIELD_GET(KVASER_PCIEFD_RPACKET_DLC_MASK, p->header[1]);
1135
1136 if (p->header[1] & KVASER_PCIEFD_RPACKET_FDF) {
1137 skb = alloc_canfd_skb(priv->dev, &cf);
1138 if (!skb) {
1139 priv->dev->stats.rx_dropped++;
1140 return -ENOMEM;
1141 }
1142
1143 cf->len = can_fd_dlc2len(dlc);
1144 if (p->header[1] & KVASER_PCIEFD_RPACKET_BRS)
1145 cf->flags |= CANFD_BRS;
1146 if (p->header[1] & KVASER_PCIEFD_RPACKET_ESI)
1147 cf->flags |= CANFD_ESI;
1148 } else {
1149 skb = alloc_can_skb(priv->dev, (struct can_frame **)&cf);
1150 if (!skb) {
1151 priv->dev->stats.rx_dropped++;
1152 return -ENOMEM;
1153 }
1154 can_frame_set_cc_len((struct can_frame *)cf, dlc, priv->ctrlmode);
1155 }
1156
1157 cf->can_id = FIELD_GET(KVASER_PCIEFD_RPACKET_ID_MASK, p->header[0]);
1158 if (p->header[0] & KVASER_PCIEFD_RPACKET_IDE)
1159 cf->can_id |= CAN_EFF_FLAG;
1160
1161 if (p->header[0] & KVASER_PCIEFD_RPACKET_RTR) {
1162 cf->can_id |= CAN_RTR_FLAG;
1163 } else {
1164 memcpy(cf->data, data, cf->len);
1165 priv->dev->stats.rx_bytes += cf->len;
1166 }
1167 priv->dev->stats.rx_packets++;
1168 kvaser_pciefd_set_skb_timestamp(pcie, skb, p->timestamp);
1169
1170 return netif_rx(skb);
1171}
1172
1173static void kvaser_pciefd_change_state(struct kvaser_pciefd_can *can,
1174 struct can_frame *cf,
1175 enum can_state new_state,
1176 enum can_state tx_state,
1177 enum can_state rx_state)
1178{
1179 can_change_state(can->can.dev, cf, tx_state, rx_state);
1180
1181 if (new_state == CAN_STATE_BUS_OFF) {
1182 struct net_device *ndev = can->can.dev;
1183 unsigned long irq_flags;
1184
1185 spin_lock_irqsave(&can->lock, irq_flags);
1186 netif_stop_queue(can->can.dev);
1187 spin_unlock_irqrestore(&can->lock, irq_flags);
1188 /* Prevent CAN controller from auto recover from bus off */
1189 if (!can->can.restart_ms) {
1190 kvaser_pciefd_start_controller_flush(can);
1191 can_bus_off(ndev);
1192 }
1193 }
1194}
1195
1196static void kvaser_pciefd_packet_to_state(struct kvaser_pciefd_rx_packet *p,
1197 struct can_berr_counter *bec,
1198 enum can_state *new_state,
1199 enum can_state *tx_state,
1200 enum can_state *rx_state)
1201{
1202 if (p->header[0] & KVASER_PCIEFD_SPACK_BOFF ||
1203 p->header[0] & KVASER_PCIEFD_SPACK_IRM)
1204 *new_state = CAN_STATE_BUS_OFF;
1205 else if (bec->txerr >= 255 || bec->rxerr >= 255)
1206 *new_state = CAN_STATE_BUS_OFF;
1207 else if (p->header[1] & KVASER_PCIEFD_SPACK_EPLR)
1208 *new_state = CAN_STATE_ERROR_PASSIVE;
1209 else if (bec->txerr >= 128 || bec->rxerr >= 128)
1210 *new_state = CAN_STATE_ERROR_PASSIVE;
1211 else if (p->header[1] & KVASER_PCIEFD_SPACK_EWLR)
1212 *new_state = CAN_STATE_ERROR_WARNING;
1213 else if (bec->txerr >= 96 || bec->rxerr >= 96)
1214 *new_state = CAN_STATE_ERROR_WARNING;
1215 else
1216 *new_state = CAN_STATE_ERROR_ACTIVE;
1217
1218 *tx_state = bec->txerr >= bec->rxerr ? *new_state : 0;
1219 *rx_state = bec->txerr <= bec->rxerr ? *new_state : 0;
1220}
1221
1222static int kvaser_pciefd_rx_error_frame(struct kvaser_pciefd_can *can,
1223 struct kvaser_pciefd_rx_packet *p)
1224{
1225 struct can_berr_counter bec;
1226 enum can_state old_state, new_state, tx_state, rx_state;
1227 struct net_device *ndev = can->can.dev;
1228 struct sk_buff *skb;
1229 struct can_frame *cf = NULL;
1230
1231 old_state = can->can.state;
1232
1233 bec.txerr = FIELD_GET(KVASER_PCIEFD_SPACK_TXERR_MASK, p->header[0]);
1234 bec.rxerr = FIELD_GET(KVASER_PCIEFD_SPACK_RXERR_MASK, p->header[0]);
1235
1236 kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state, &rx_state);
1237 skb = alloc_can_err_skb(ndev, &cf);
1238 if (new_state != old_state) {
1239 kvaser_pciefd_change_state(can, cf, new_state, tx_state, rx_state);
1240 if (old_state == CAN_STATE_BUS_OFF &&
1241 new_state == CAN_STATE_ERROR_ACTIVE &&
1242 can->can.restart_ms) {
1243 can->can.can_stats.restarts++;
1244 if (skb)
1245 cf->can_id |= CAN_ERR_RESTARTED;
1246 }
1247 }
1248
1249 can->err_rep_cnt++;
1250 can->can.can_stats.bus_error++;
1251 if (p->header[1] & KVASER_PCIEFD_EPACK_DIR_TX)
1252 ndev->stats.tx_errors++;
1253 else
1254 ndev->stats.rx_errors++;
1255
1256 can->bec.txerr = bec.txerr;
1257 can->bec.rxerr = bec.rxerr;
1258
1259 if (!skb) {
1260 ndev->stats.rx_dropped++;
1261 return -ENOMEM;
1262 }
1263
1264 kvaser_pciefd_set_skb_timestamp(can->kv_pcie, skb, p->timestamp);
1265 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_CNT;
1266 cf->data[6] = bec.txerr;
1267 cf->data[7] = bec.rxerr;
1268
1269 netif_rx(skb);
1270
1271 return 0;
1272}
1273
1274static int kvaser_pciefd_handle_error_packet(struct kvaser_pciefd *pcie,
1275 struct kvaser_pciefd_rx_packet *p)
1276{
1277 struct kvaser_pciefd_can *can;
1278 u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
1279
1280 if (ch_id >= pcie->nr_channels)
1281 return -EIO;
1282
1283 can = pcie->can[ch_id];
1284 kvaser_pciefd_rx_error_frame(can, p);
1285 if (can->err_rep_cnt >= KVASER_PCIEFD_MAX_ERR_REP)
1286 /* Do not report more errors, until bec_poll_timer expires */
1287 kvaser_pciefd_disable_err_gen(can);
1288 /* Start polling the error counters */
1289 mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ);
1290
1291 return 0;
1292}
1293
1294static int kvaser_pciefd_handle_status_resp(struct kvaser_pciefd_can *can,
1295 struct kvaser_pciefd_rx_packet *p)
1296{
1297 struct can_berr_counter bec;
1298 enum can_state old_state, new_state, tx_state, rx_state;
1299
1300 old_state = can->can.state;
1301
1302 bec.txerr = FIELD_GET(KVASER_PCIEFD_SPACK_TXERR_MASK, p->header[0]);
1303 bec.rxerr = FIELD_GET(KVASER_PCIEFD_SPACK_RXERR_MASK, p->header[0]);
1304
1305 kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state, &rx_state);
1306 if (new_state != old_state) {
1307 struct net_device *ndev = can->can.dev;
1308 struct sk_buff *skb;
1309 struct can_frame *cf;
1310
1311 skb = alloc_can_err_skb(ndev, &cf);
1312 if (!skb) {
1313 ndev->stats.rx_dropped++;
1314 return -ENOMEM;
1315 }
1316
1317 kvaser_pciefd_change_state(can, cf, new_state, tx_state, rx_state);
1318 if (old_state == CAN_STATE_BUS_OFF &&
1319 new_state == CAN_STATE_ERROR_ACTIVE &&
1320 can->can.restart_ms) {
1321 can->can.can_stats.restarts++;
1322 cf->can_id |= CAN_ERR_RESTARTED;
1323 }
1324
1325 kvaser_pciefd_set_skb_timestamp(can->kv_pcie, skb, p->timestamp);
1326
1327 cf->data[6] = bec.txerr;
1328 cf->data[7] = bec.rxerr;
1329
1330 netif_rx(skb);
1331 }
1332 can->bec.txerr = bec.txerr;
1333 can->bec.rxerr = bec.rxerr;
1334 /* Check if we need to poll the error counters */
1335 if (bec.txerr || bec.rxerr)
1336 mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ);
1337
1338 return 0;
1339}
1340
1341static int kvaser_pciefd_handle_status_packet(struct kvaser_pciefd *pcie,
1342 struct kvaser_pciefd_rx_packet *p)
1343{
1344 struct kvaser_pciefd_can *can;
1345 u8 cmdseq;
1346 u32 status;
1347 u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
1348
1349 if (ch_id >= pcie->nr_channels)
1350 return -EIO;
1351
1352 can = pcie->can[ch_id];
1353
1354 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
1355 cmdseq = FIELD_GET(KVASER_PCIEFD_KCAN_STAT_SEQNO_MASK, status);
1356
1357 /* Reset done, start abort and flush */
1358 if (p->header[0] & KVASER_PCIEFD_SPACK_IRM &&
1359 p->header[0] & KVASER_PCIEFD_SPACK_RMCD &&
1360 p->header[1] & KVASER_PCIEFD_SPACK_AUTO &&
1361 cmdseq == FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[1]) &&
1362 status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
1363 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
1364 can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1365 kvaser_pciefd_abort_flush_reset(can);
1366 } else if (p->header[0] & KVASER_PCIEFD_SPACK_IDET &&
1367 p->header[0] & KVASER_PCIEFD_SPACK_IRM &&
1368 cmdseq == FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[1]) &&
1369 status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
1370 /* Reset detected, send end of flush if no packet are in FIFO */
1371 u8 count;
1372
1373 count = FIELD_GET(KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK,
1374 ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG));
1375 if (!count)
1376 iowrite32(FIELD_PREP(KVASER_PCIEFD_KCAN_CTRL_TYPE_MASK,
1377 KVASER_PCIEFD_KCAN_CTRL_TYPE_EFLUSH),
1378 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG);
1379 } else if (!(p->header[1] & KVASER_PCIEFD_SPACK_AUTO) &&
1380 cmdseq == FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[1])) {
1381 /* Response to status request received */
1382 kvaser_pciefd_handle_status_resp(can, p);
1383 if (can->can.state != CAN_STATE_BUS_OFF &&
1384 can->can.state != CAN_STATE_ERROR_ACTIVE) {
1385 mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ);
1386 }
1387 } else if (p->header[0] & KVASER_PCIEFD_SPACK_RMCD &&
1388 !(status & KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MASK)) {
1389 /* Reset to bus on detected */
1390 if (!completion_done(&can->start_comp))
1391 complete(&can->start_comp);
1392 }
1393
1394 return 0;
1395}
1396
1397static void kvaser_pciefd_handle_nack_packet(struct kvaser_pciefd_can *can,
1398 struct kvaser_pciefd_rx_packet *p)
1399{
1400 struct sk_buff *skb;
1401 struct can_frame *cf;
1402
1403 skb = alloc_can_err_skb(can->can.dev, &cf);
1404 can->can.dev->stats.tx_errors++;
1405 if (p->header[0] & KVASER_PCIEFD_APACKET_ABL) {
1406 if (skb)
1407 cf->can_id |= CAN_ERR_LOSTARB;
1408 can->can.can_stats.arbitration_lost++;
1409 } else if (skb) {
1410 cf->can_id |= CAN_ERR_ACK;
1411 }
1412
1413 if (skb) {
1414 cf->can_id |= CAN_ERR_BUSERROR;
1415 kvaser_pciefd_set_skb_timestamp(can->kv_pcie, skb, p->timestamp);
1416 netif_rx(skb);
1417 } else {
1418 can->can.dev->stats.rx_dropped++;
1419 netdev_warn(can->can.dev, "No memory left for err_skb\n");
1420 }
1421}
1422
1423static int kvaser_pciefd_handle_ack_packet(struct kvaser_pciefd *pcie,
1424 struct kvaser_pciefd_rx_packet *p)
1425{
1426 struct kvaser_pciefd_can *can;
1427 bool one_shot_fail = false;
1428 u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
1429
1430 if (ch_id >= pcie->nr_channels)
1431 return -EIO;
1432
1433 can = pcie->can[ch_id];
1434 /* Ignore control packet ACK */
1435 if (p->header[0] & KVASER_PCIEFD_APACKET_CT)
1436 return 0;
1437
1438 if (p->header[0] & KVASER_PCIEFD_APACKET_NACK) {
1439 kvaser_pciefd_handle_nack_packet(can, p);
1440 one_shot_fail = true;
1441 }
1442
1443 if (p->header[0] & KVASER_PCIEFD_APACKET_FLU) {
1444 netdev_dbg(can->can.dev, "Packet was flushed\n");
1445 } else {
1446 int echo_idx = FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[0]);
1447 int len;
1448 u8 count;
1449 struct sk_buff *skb;
1450
1451 skb = can->can.echo_skb[echo_idx];
1452 if (skb)
1453 kvaser_pciefd_set_skb_timestamp(pcie, skb, p->timestamp);
1454 len = can_get_echo_skb(can->can.dev, echo_idx, NULL);
1455 count = FIELD_GET(KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK,
1456 ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG));
1457
1458 if (count < can->can.echo_skb_max && netif_queue_stopped(can->can.dev))
1459 netif_wake_queue(can->can.dev);
1460
1461 if (!one_shot_fail) {
1462 can->can.dev->stats.tx_bytes += len;
1463 can->can.dev->stats.tx_packets++;
1464 }
1465 }
1466
1467 return 0;
1468}
1469
1470static int kvaser_pciefd_handle_eflush_packet(struct kvaser_pciefd *pcie,
1471 struct kvaser_pciefd_rx_packet *p)
1472{
1473 struct kvaser_pciefd_can *can;
1474 u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
1475
1476 if (ch_id >= pcie->nr_channels)
1477 return -EIO;
1478
1479 can = pcie->can[ch_id];
1480
1481 if (!completion_done(&can->flush_comp))
1482 complete(&can->flush_comp);
1483
1484 return 0;
1485}
1486
1487static int kvaser_pciefd_read_packet(struct kvaser_pciefd *pcie, int *start_pos,
1488 int dma_buf)
1489{
1490 __le32 *buffer = pcie->dma_data[dma_buf];
1491 __le64 timestamp;
1492 struct kvaser_pciefd_rx_packet packet;
1493 struct kvaser_pciefd_rx_packet *p = &packet;
1494 u8 type;
1495 int pos = *start_pos;
1496 int size;
1497 int ret = 0;
1498
1499 size = le32_to_cpu(buffer[pos++]);
1500 if (!size) {
1501 *start_pos = 0;
1502 return 0;
1503 }
1504
1505 p->header[0] = le32_to_cpu(buffer[pos++]);
1506 p->header[1] = le32_to_cpu(buffer[pos++]);
1507
1508 /* Read 64-bit timestamp */
1509 memcpy(×tamp, &buffer[pos], sizeof(__le64));
1510 pos += 2;
1511 p->timestamp = le64_to_cpu(timestamp);
1512
1513 type = FIELD_GET(KVASER_PCIEFD_PACKET_TYPE_MASK, p->header[1]);
1514 switch (type) {
1515 case KVASER_PCIEFD_PACK_TYPE_DATA:
1516 ret = kvaser_pciefd_handle_data_packet(pcie, p, &buffer[pos]);
1517 if (!(p->header[0] & KVASER_PCIEFD_RPACKET_RTR)) {
1518 u8 data_len;
1519
1520 data_len = can_fd_dlc2len(FIELD_GET(KVASER_PCIEFD_RPACKET_DLC_MASK,
1521 p->header[1]));
1522 pos += DIV_ROUND_UP(data_len, 4);
1523 }
1524 break;
1525
1526 case KVASER_PCIEFD_PACK_TYPE_ACK:
1527 ret = kvaser_pciefd_handle_ack_packet(pcie, p);
1528 break;
1529
1530 case KVASER_PCIEFD_PACK_TYPE_STATUS:
1531 ret = kvaser_pciefd_handle_status_packet(pcie, p);
1532 break;
1533
1534 case KVASER_PCIEFD_PACK_TYPE_ERROR:
1535 ret = kvaser_pciefd_handle_error_packet(pcie, p);
1536 break;
1537
1538 case KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK:
1539 ret = kvaser_pciefd_handle_eflush_packet(pcie, p);
1540 break;
1541
1542 case KVASER_PCIEFD_PACK_TYPE_ACK_DATA:
1543 case KVASER_PCIEFD_PACK_TYPE_BUS_LOAD:
1544 case KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK:
1545 case KVASER_PCIEFD_PACK_TYPE_TXRQ:
1546 dev_info(&pcie->pci->dev,
1547 "Received unexpected packet type 0x%08X\n", type);
1548 break;
1549
1550 default:
1551 dev_err(&pcie->pci->dev, "Unknown packet type 0x%08X\n", type);
1552 ret = -EIO;
1553 break;
1554 }
1555
1556 if (ret)
1557 return ret;
1558
1559 /* Position does not point to the end of the package,
1560 * corrupted packet size?
1561 */
1562 if ((*start_pos + size) != pos)
1563 return -EIO;
1564
1565 /* Point to the next packet header, if any */
1566 *start_pos = pos;
1567
1568 return ret;
1569}
1570
1571static int kvaser_pciefd_read_buffer(struct kvaser_pciefd *pcie, int dma_buf)
1572{
1573 int pos = 0;
1574 int res = 0;
1575
1576 do {
1577 res = kvaser_pciefd_read_packet(pcie, &pos, dma_buf);
1578 } while (!res && pos > 0 && pos < KVASER_PCIEFD_DMA_SIZE);
1579
1580 return res;
1581}
1582
1583static void kvaser_pciefd_receive_irq(struct kvaser_pciefd *pcie)
1584{
1585 u32 irq = ioread32(KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_IRQ_REG);
1586
1587 if (irq & KVASER_PCIEFD_SRB_IRQ_DPD0) {
1588 kvaser_pciefd_read_buffer(pcie, 0);
1589 /* Reset DMA buffer 0 */
1590 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB0,
1591 KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CMD_REG);
1592 }
1593
1594 if (irq & KVASER_PCIEFD_SRB_IRQ_DPD1) {
1595 kvaser_pciefd_read_buffer(pcie, 1);
1596 /* Reset DMA buffer 1 */
1597 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB1,
1598 KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CMD_REG);
1599 }
1600
1601 if (irq & KVASER_PCIEFD_SRB_IRQ_DOF0 ||
1602 irq & KVASER_PCIEFD_SRB_IRQ_DOF1 ||
1603 irq & KVASER_PCIEFD_SRB_IRQ_DUF0 ||
1604 irq & KVASER_PCIEFD_SRB_IRQ_DUF1)
1605 dev_err(&pcie->pci->dev, "DMA IRQ error 0x%08X\n", irq);
1606
1607 iowrite32(irq, KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_IRQ_REG);
1608}
1609
1610static void kvaser_pciefd_transmit_irq(struct kvaser_pciefd_can *can)
1611{
1612 u32 irq = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1613
1614 if (irq & KVASER_PCIEFD_KCAN_IRQ_TOF)
1615 netdev_err(can->can.dev, "Tx FIFO overflow\n");
1616
1617 if (irq & KVASER_PCIEFD_KCAN_IRQ_BPP)
1618 netdev_err(can->can.dev,
1619 "Fail to change bittiming, when not in reset mode\n");
1620
1621 if (irq & KVASER_PCIEFD_KCAN_IRQ_FDIC)
1622 netdev_err(can->can.dev, "CAN FD frame in CAN mode\n");
1623
1624 if (irq & KVASER_PCIEFD_KCAN_IRQ_ROF)
1625 netdev_err(can->can.dev, "Rx FIFO overflow\n");
1626
1627 iowrite32(irq, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1628}
1629
1630static irqreturn_t kvaser_pciefd_irq_handler(int irq, void *dev)
1631{
1632 struct kvaser_pciefd *pcie = (struct kvaser_pciefd *)dev;
1633 const struct kvaser_pciefd_irq_mask *irq_mask = pcie->driver_data->irq_mask;
1634 u32 board_irq = ioread32(KVASER_PCIEFD_PCI_IRQ_ADDR(pcie));
1635 int i;
1636
1637 if (!(board_irq & irq_mask->all))
1638 return IRQ_NONE;
1639
1640 if (board_irq & irq_mask->kcan_rx0)
1641 kvaser_pciefd_receive_irq(pcie);
1642
1643 for (i = 0; i < pcie->nr_channels; i++) {
1644 if (!pcie->can[i]) {
1645 dev_err(&pcie->pci->dev,
1646 "IRQ mask points to unallocated controller\n");
1647 break;
1648 }
1649
1650 /* Check that mask matches channel (i) IRQ mask */
1651 if (board_irq & irq_mask->kcan_tx[i])
1652 kvaser_pciefd_transmit_irq(pcie->can[i]);
1653 }
1654
1655 return IRQ_HANDLED;
1656}
1657
1658static void kvaser_pciefd_teardown_can_ctrls(struct kvaser_pciefd *pcie)
1659{
1660 int i;
1661
1662 for (i = 0; i < pcie->nr_channels; i++) {
1663 struct kvaser_pciefd_can *can = pcie->can[i];
1664
1665 if (can) {
1666 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1667 kvaser_pciefd_pwm_stop(can);
1668 free_candev(can->can.dev);
1669 }
1670 }
1671}
1672
1673static int kvaser_pciefd_probe(struct pci_dev *pdev,
1674 const struct pci_device_id *id)
1675{
1676 int err;
1677 struct kvaser_pciefd *pcie;
1678 const struct kvaser_pciefd_irq_mask *irq_mask;
1679 void __iomem *irq_en_base;
1680
1681 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
1682 if (!pcie)
1683 return -ENOMEM;
1684
1685 pci_set_drvdata(pdev, pcie);
1686 pcie->pci = pdev;
1687 pcie->driver_data = (const struct kvaser_pciefd_driver_data *)id->driver_data;
1688 irq_mask = pcie->driver_data->irq_mask;
1689
1690 err = pci_enable_device(pdev);
1691 if (err)
1692 return err;
1693
1694 err = pci_request_regions(pdev, KVASER_PCIEFD_DRV_NAME);
1695 if (err)
1696 goto err_disable_pci;
1697
1698 pcie->reg_base = pci_iomap(pdev, 0, 0);
1699 if (!pcie->reg_base) {
1700 err = -ENOMEM;
1701 goto err_release_regions;
1702 }
1703
1704 err = kvaser_pciefd_setup_board(pcie);
1705 if (err)
1706 goto err_pci_iounmap;
1707
1708 err = kvaser_pciefd_setup_dma(pcie);
1709 if (err)
1710 goto err_pci_iounmap;
1711
1712 pci_set_master(pdev);
1713
1714 err = kvaser_pciefd_setup_can_ctrls(pcie);
1715 if (err)
1716 goto err_teardown_can_ctrls;
1717
1718 err = request_irq(pcie->pci->irq, kvaser_pciefd_irq_handler,
1719 IRQF_SHARED, KVASER_PCIEFD_DRV_NAME, pcie);
1720 if (err)
1721 goto err_teardown_can_ctrls;
1722
1723 iowrite32(KVASER_PCIEFD_SRB_IRQ_DPD0 | KVASER_PCIEFD_SRB_IRQ_DPD1,
1724 KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_IRQ_REG);
1725
1726 iowrite32(KVASER_PCIEFD_SRB_IRQ_DPD0 | KVASER_PCIEFD_SRB_IRQ_DPD1 |
1727 KVASER_PCIEFD_SRB_IRQ_DOF0 | KVASER_PCIEFD_SRB_IRQ_DOF1 |
1728 KVASER_PCIEFD_SRB_IRQ_DUF0 | KVASER_PCIEFD_SRB_IRQ_DUF1,
1729 KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_IEN_REG);
1730
1731 /* Enable PCI interrupts */
1732 irq_en_base = KVASER_PCIEFD_PCI_IEN_ADDR(pcie);
1733 iowrite32(irq_mask->all, irq_en_base);
1734 /* Ready the DMA buffers */
1735 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB0,
1736 KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CMD_REG);
1737 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB1,
1738 KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CMD_REG);
1739
1740 err = kvaser_pciefd_reg_candev(pcie);
1741 if (err)
1742 goto err_free_irq;
1743
1744 return 0;
1745
1746err_free_irq:
1747 /* Disable PCI interrupts */
1748 iowrite32(0, irq_en_base);
1749 free_irq(pcie->pci->irq, pcie);
1750
1751err_teardown_can_ctrls:
1752 kvaser_pciefd_teardown_can_ctrls(pcie);
1753 iowrite32(0, KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CTRL_REG);
1754 pci_clear_master(pdev);
1755
1756err_pci_iounmap:
1757 pci_iounmap(pdev, pcie->reg_base);
1758
1759err_release_regions:
1760 pci_release_regions(pdev);
1761
1762err_disable_pci:
1763 pci_disable_device(pdev);
1764
1765 return err;
1766}
1767
1768static void kvaser_pciefd_remove_all_ctrls(struct kvaser_pciefd *pcie)
1769{
1770 int i;
1771
1772 for (i = 0; i < pcie->nr_channels; i++) {
1773 struct kvaser_pciefd_can *can = pcie->can[i];
1774
1775 if (can) {
1776 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1777 unregister_candev(can->can.dev);
1778 del_timer(&can->bec_poll_timer);
1779 kvaser_pciefd_pwm_stop(can);
1780 free_candev(can->can.dev);
1781 }
1782 }
1783}
1784
1785static void kvaser_pciefd_remove(struct pci_dev *pdev)
1786{
1787 struct kvaser_pciefd *pcie = pci_get_drvdata(pdev);
1788
1789 kvaser_pciefd_remove_all_ctrls(pcie);
1790
1791 /* Disable interrupts */
1792 iowrite32(0, KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CTRL_REG);
1793 iowrite32(0, KVASER_PCIEFD_PCI_IEN_ADDR(pcie));
1794
1795 free_irq(pcie->pci->irq, pcie);
1796
1797 pci_iounmap(pdev, pcie->reg_base);
1798 pci_release_regions(pdev);
1799 pci_disable_device(pdev);
1800}
1801
1802static struct pci_driver kvaser_pciefd = {
1803 .name = KVASER_PCIEFD_DRV_NAME,
1804 .id_table = kvaser_pciefd_id_table,
1805 .probe = kvaser_pciefd_probe,
1806 .remove = kvaser_pciefd_remove,
1807};
1808
1809module_pci_driver(kvaser_pciefd)
1// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2/* Copyright (C) 2018 KVASER AB, Sweden. All rights reserved.
3 * Parts of this driver are based on the following:
4 * - Kvaser linux pciefd driver (version 5.25)
5 * - PEAK linux canfd driver
6 * - Altera Avalon EPCS flash controller driver
7 */
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/device.h>
12#include <linux/pci.h>
13#include <linux/can/dev.h>
14#include <linux/timer.h>
15#include <linux/netdevice.h>
16#include <linux/crc32.h>
17#include <linux/iopoll.h>
18
19MODULE_LICENSE("Dual BSD/GPL");
20MODULE_AUTHOR("Kvaser AB <support@kvaser.com>");
21MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices");
22
23#define KVASER_PCIEFD_DRV_NAME "kvaser_pciefd"
24
25#define KVASER_PCIEFD_WAIT_TIMEOUT msecs_to_jiffies(1000)
26#define KVASER_PCIEFD_BEC_POLL_FREQ (jiffies + msecs_to_jiffies(200))
27#define KVASER_PCIEFD_MAX_ERR_REP 256
28#define KVASER_PCIEFD_CAN_TX_MAX_COUNT 17
29#define KVASER_PCIEFD_MAX_CAN_CHANNELS 4
30#define KVASER_PCIEFD_DMA_COUNT 2
31
32#define KVASER_PCIEFD_DMA_SIZE (4 * 1024)
33#define KVASER_PCIEFD_64BIT_DMA_BIT BIT(0)
34
35#define KVASER_PCIEFD_VENDOR 0x1a07
36#define KVASER_PCIEFD_4HS_ID 0x0d
37#define KVASER_PCIEFD_2HS_ID 0x0e
38#define KVASER_PCIEFD_HS_ID 0x0f
39#define KVASER_PCIEFD_MINIPCIE_HS_ID 0x10
40#define KVASER_PCIEFD_MINIPCIE_2HS_ID 0x11
41
42/* PCIe IRQ registers */
43#define KVASER_PCIEFD_IRQ_REG 0x40
44#define KVASER_PCIEFD_IEN_REG 0x50
45/* DMA map */
46#define KVASER_PCIEFD_DMA_MAP_BASE 0x1000
47/* Kvaser KCAN CAN controller registers */
48#define KVASER_PCIEFD_KCAN0_BASE 0x10000
49#define KVASER_PCIEFD_KCAN_BASE_OFFSET 0x1000
50#define KVASER_PCIEFD_KCAN_FIFO_REG 0x100
51#define KVASER_PCIEFD_KCAN_FIFO_LAST_REG 0x180
52#define KVASER_PCIEFD_KCAN_CTRL_REG 0x2c0
53#define KVASER_PCIEFD_KCAN_CMD_REG 0x400
54#define KVASER_PCIEFD_KCAN_IEN_REG 0x408
55#define KVASER_PCIEFD_KCAN_IRQ_REG 0x410
56#define KVASER_PCIEFD_KCAN_TX_NPACKETS_REG 0x414
57#define KVASER_PCIEFD_KCAN_STAT_REG 0x418
58#define KVASER_PCIEFD_KCAN_MODE_REG 0x41c
59#define KVASER_PCIEFD_KCAN_BTRN_REG 0x420
60#define KVASER_PCIEFD_KCAN_BTRD_REG 0x428
61#define KVASER_PCIEFD_KCAN_PWM_REG 0x430
62/* Loopback control register */
63#define KVASER_PCIEFD_LOOP_REG 0x1f000
64/* System identification and information registers */
65#define KVASER_PCIEFD_SYSID_BASE 0x1f020
66#define KVASER_PCIEFD_SYSID_VERSION_REG (KVASER_PCIEFD_SYSID_BASE + 0x8)
67#define KVASER_PCIEFD_SYSID_CANFREQ_REG (KVASER_PCIEFD_SYSID_BASE + 0xc)
68#define KVASER_PCIEFD_SYSID_BUSFREQ_REG (KVASER_PCIEFD_SYSID_BASE + 0x10)
69#define KVASER_PCIEFD_SYSID_BUILD_REG (KVASER_PCIEFD_SYSID_BASE + 0x14)
70/* Shared receive buffer registers */
71#define KVASER_PCIEFD_SRB_BASE 0x1f200
72#define KVASER_PCIEFD_SRB_CMD_REG (KVASER_PCIEFD_SRB_BASE + 0x200)
73#define KVASER_PCIEFD_SRB_IEN_REG (KVASER_PCIEFD_SRB_BASE + 0x204)
74#define KVASER_PCIEFD_SRB_IRQ_REG (KVASER_PCIEFD_SRB_BASE + 0x20c)
75#define KVASER_PCIEFD_SRB_STAT_REG (KVASER_PCIEFD_SRB_BASE + 0x210)
76#define KVASER_PCIEFD_SRB_CTRL_REG (KVASER_PCIEFD_SRB_BASE + 0x218)
77/* EPCS flash controller registers */
78#define KVASER_PCIEFD_SPI_BASE 0x1fc00
79#define KVASER_PCIEFD_SPI_RX_REG KVASER_PCIEFD_SPI_BASE
80#define KVASER_PCIEFD_SPI_TX_REG (KVASER_PCIEFD_SPI_BASE + 0x4)
81#define KVASER_PCIEFD_SPI_STATUS_REG (KVASER_PCIEFD_SPI_BASE + 0x8)
82#define KVASER_PCIEFD_SPI_CTRL_REG (KVASER_PCIEFD_SPI_BASE + 0xc)
83#define KVASER_PCIEFD_SPI_SSEL_REG (KVASER_PCIEFD_SPI_BASE + 0x14)
84
85#define KVASER_PCIEFD_IRQ_ALL_MSK 0x1f
86#define KVASER_PCIEFD_IRQ_SRB BIT(4)
87
88#define KVASER_PCIEFD_SYSID_NRCHAN_SHIFT 24
89#define KVASER_PCIEFD_SYSID_MAJOR_VER_SHIFT 16
90#define KVASER_PCIEFD_SYSID_BUILD_VER_SHIFT 1
91
92/* Reset DMA buffer 0, 1 and FIFO offset */
93#define KVASER_PCIEFD_SRB_CMD_RDB0 BIT(4)
94#define KVASER_PCIEFD_SRB_CMD_RDB1 BIT(5)
95#define KVASER_PCIEFD_SRB_CMD_FOR BIT(0)
96
97/* DMA packet done, buffer 0 and 1 */
98#define KVASER_PCIEFD_SRB_IRQ_DPD0 BIT(8)
99#define KVASER_PCIEFD_SRB_IRQ_DPD1 BIT(9)
100/* DMA overflow, buffer 0 and 1 */
101#define KVASER_PCIEFD_SRB_IRQ_DOF0 BIT(10)
102#define KVASER_PCIEFD_SRB_IRQ_DOF1 BIT(11)
103/* DMA underflow, buffer 0 and 1 */
104#define KVASER_PCIEFD_SRB_IRQ_DUF0 BIT(12)
105#define KVASER_PCIEFD_SRB_IRQ_DUF1 BIT(13)
106
107/* DMA idle */
108#define KVASER_PCIEFD_SRB_STAT_DI BIT(15)
109/* DMA support */
110#define KVASER_PCIEFD_SRB_STAT_DMA BIT(24)
111
112/* DMA Enable */
113#define KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE BIT(0)
114
115/* EPCS flash controller definitions */
116#define KVASER_PCIEFD_CFG_IMG_SZ (64 * 1024)
117#define KVASER_PCIEFD_CFG_IMG_OFFSET (31 * 65536L)
118#define KVASER_PCIEFD_CFG_MAX_PARAMS 256
119#define KVASER_PCIEFD_CFG_MAGIC 0xcafef00d
120#define KVASER_PCIEFD_CFG_PARAM_MAX_SZ 24
121#define KVASER_PCIEFD_CFG_SYS_VER 1
122#define KVASER_PCIEFD_CFG_PARAM_NR_CHAN 130
123#define KVASER_PCIEFD_SPI_TMT BIT(5)
124#define KVASER_PCIEFD_SPI_TRDY BIT(6)
125#define KVASER_PCIEFD_SPI_RRDY BIT(7)
126#define KVASER_PCIEFD_FLASH_ID_EPCS16 0x14
127/* Commands for controlling the onboard flash */
128#define KVASER_PCIEFD_FLASH_RES_CMD 0xab
129#define KVASER_PCIEFD_FLASH_READ_CMD 0x3
130#define KVASER_PCIEFD_FLASH_STATUS_CMD 0x5
131
132/* Kvaser KCAN definitions */
133#define KVASER_PCIEFD_KCAN_CTRL_EFLUSH (4 << 29)
134#define KVASER_PCIEFD_KCAN_CTRL_EFRAME (5 << 29)
135
136#define KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT 16
137/* Request status packet */
138#define KVASER_PCIEFD_KCAN_CMD_SRQ BIT(0)
139/* Abort, flush and reset */
140#define KVASER_PCIEFD_KCAN_CMD_AT BIT(1)
141
142/* Tx FIFO unaligned read */
143#define KVASER_PCIEFD_KCAN_IRQ_TAR BIT(0)
144/* Tx FIFO unaligned end */
145#define KVASER_PCIEFD_KCAN_IRQ_TAE BIT(1)
146/* Bus parameter protection error */
147#define KVASER_PCIEFD_KCAN_IRQ_BPP BIT(2)
148/* FDF bit when controller is in classic mode */
149#define KVASER_PCIEFD_KCAN_IRQ_FDIC BIT(3)
150/* Rx FIFO overflow */
151#define KVASER_PCIEFD_KCAN_IRQ_ROF BIT(5)
152/* Abort done */
153#define KVASER_PCIEFD_KCAN_IRQ_ABD BIT(13)
154/* Tx buffer flush done */
155#define KVASER_PCIEFD_KCAN_IRQ_TFD BIT(14)
156/* Tx FIFO overflow */
157#define KVASER_PCIEFD_KCAN_IRQ_TOF BIT(15)
158/* Tx FIFO empty */
159#define KVASER_PCIEFD_KCAN_IRQ_TE BIT(16)
160/* Transmitter unaligned */
161#define KVASER_PCIEFD_KCAN_IRQ_TAL BIT(17)
162
163#define KVASER_PCIEFD_KCAN_TX_NPACKETS_MAX_SHIFT 16
164
165#define KVASER_PCIEFD_KCAN_STAT_SEQNO_SHIFT 24
166/* Abort request */
167#define KVASER_PCIEFD_KCAN_STAT_AR BIT(7)
168/* Idle state. Controller in reset mode and no abort or flush pending */
169#define KVASER_PCIEFD_KCAN_STAT_IDLE BIT(10)
170/* Bus off */
171#define KVASER_PCIEFD_KCAN_STAT_BOFF BIT(11)
172/* Reset mode request */
173#define KVASER_PCIEFD_KCAN_STAT_RMR BIT(14)
174/* Controller in reset mode */
175#define KVASER_PCIEFD_KCAN_STAT_IRM BIT(15)
176/* Controller got one-shot capability */
177#define KVASER_PCIEFD_KCAN_STAT_CAP BIT(16)
178/* Controller got CAN FD capability */
179#define KVASER_PCIEFD_KCAN_STAT_FD BIT(19)
180#define KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MSK (KVASER_PCIEFD_KCAN_STAT_AR | \
181 KVASER_PCIEFD_KCAN_STAT_BOFF | KVASER_PCIEFD_KCAN_STAT_RMR | \
182 KVASER_PCIEFD_KCAN_STAT_IRM)
183
184/* Reset mode */
185#define KVASER_PCIEFD_KCAN_MODE_RM BIT(8)
186/* Listen only mode */
187#define KVASER_PCIEFD_KCAN_MODE_LOM BIT(9)
188/* Error packet enable */
189#define KVASER_PCIEFD_KCAN_MODE_EPEN BIT(12)
190/* CAN FD non-ISO */
191#define KVASER_PCIEFD_KCAN_MODE_NIFDEN BIT(15)
192/* Acknowledgment packet type */
193#define KVASER_PCIEFD_KCAN_MODE_APT BIT(20)
194/* Active error flag enable. Clear to force error passive */
195#define KVASER_PCIEFD_KCAN_MODE_EEN BIT(23)
196/* Classic CAN mode */
197#define KVASER_PCIEFD_KCAN_MODE_CCM BIT(31)
198
199#define KVASER_PCIEFD_KCAN_BTRN_SJW_SHIFT 13
200#define KVASER_PCIEFD_KCAN_BTRN_TSEG1_SHIFT 17
201#define KVASER_PCIEFD_KCAN_BTRN_TSEG2_SHIFT 26
202
203#define KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT 16
204
205/* Kvaser KCAN packet types */
206#define KVASER_PCIEFD_PACK_TYPE_DATA 0
207#define KVASER_PCIEFD_PACK_TYPE_ACK 1
208#define KVASER_PCIEFD_PACK_TYPE_TXRQ 2
209#define KVASER_PCIEFD_PACK_TYPE_ERROR 3
210#define KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK 4
211#define KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK 5
212#define KVASER_PCIEFD_PACK_TYPE_ACK_DATA 6
213#define KVASER_PCIEFD_PACK_TYPE_STATUS 8
214#define KVASER_PCIEFD_PACK_TYPE_BUS_LOAD 9
215
216/* Kvaser KCAN packet common definitions */
217#define KVASER_PCIEFD_PACKET_SEQ_MSK 0xff
218#define KVASER_PCIEFD_PACKET_CHID_SHIFT 25
219#define KVASER_PCIEFD_PACKET_TYPE_SHIFT 28
220
221/* Kvaser KCAN TDATA and RDATA first word */
222#define KVASER_PCIEFD_RPACKET_IDE BIT(30)
223#define KVASER_PCIEFD_RPACKET_RTR BIT(29)
224/* Kvaser KCAN TDATA and RDATA second word */
225#define KVASER_PCIEFD_RPACKET_ESI BIT(13)
226#define KVASER_PCIEFD_RPACKET_BRS BIT(14)
227#define KVASER_PCIEFD_RPACKET_FDF BIT(15)
228#define KVASER_PCIEFD_RPACKET_DLC_SHIFT 8
229/* Kvaser KCAN TDATA second word */
230#define KVASER_PCIEFD_TPACKET_SMS BIT(16)
231#define KVASER_PCIEFD_TPACKET_AREQ BIT(31)
232
233/* Kvaser KCAN APACKET */
234#define KVASER_PCIEFD_APACKET_FLU BIT(8)
235#define KVASER_PCIEFD_APACKET_CT BIT(9)
236#define KVASER_PCIEFD_APACKET_ABL BIT(10)
237#define KVASER_PCIEFD_APACKET_NACK BIT(11)
238
239/* Kvaser KCAN SPACK first word */
240#define KVASER_PCIEFD_SPACK_RXERR_SHIFT 8
241#define KVASER_PCIEFD_SPACK_BOFF BIT(16)
242#define KVASER_PCIEFD_SPACK_IDET BIT(20)
243#define KVASER_PCIEFD_SPACK_IRM BIT(21)
244#define KVASER_PCIEFD_SPACK_RMCD BIT(22)
245/* Kvaser KCAN SPACK second word */
246#define KVASER_PCIEFD_SPACK_AUTO BIT(21)
247#define KVASER_PCIEFD_SPACK_EWLR BIT(23)
248#define KVASER_PCIEFD_SPACK_EPLR BIT(24)
249
250struct kvaser_pciefd;
251
252struct kvaser_pciefd_can {
253 struct can_priv can;
254 struct kvaser_pciefd *kv_pcie;
255 void __iomem *reg_base;
256 struct can_berr_counter bec;
257 u8 cmd_seq;
258 int err_rep_cnt;
259 int echo_idx;
260 spinlock_t lock; /* Locks sensitive registers (e.g. MODE) */
261 spinlock_t echo_lock; /* Locks the message echo buffer */
262 struct timer_list bec_poll_timer;
263 struct completion start_comp, flush_comp;
264};
265
266struct kvaser_pciefd {
267 struct pci_dev *pci;
268 void __iomem *reg_base;
269 struct kvaser_pciefd_can *can[KVASER_PCIEFD_MAX_CAN_CHANNELS];
270 void *dma_data[KVASER_PCIEFD_DMA_COUNT];
271 u8 nr_channels;
272 u32 bus_freq;
273 u32 freq;
274 u32 freq_to_ticks_div;
275};
276
277struct kvaser_pciefd_rx_packet {
278 u32 header[2];
279 u64 timestamp;
280};
281
282struct kvaser_pciefd_tx_packet {
283 u32 header[2];
284 u8 data[64];
285};
286
287static const struct can_bittiming_const kvaser_pciefd_bittiming_const = {
288 .name = KVASER_PCIEFD_DRV_NAME,
289 .tseg1_min = 1,
290 .tseg1_max = 255,
291 .tseg2_min = 1,
292 .tseg2_max = 32,
293 .sjw_max = 16,
294 .brp_min = 1,
295 .brp_max = 4096,
296 .brp_inc = 1,
297};
298
299struct kvaser_pciefd_cfg_param {
300 __le32 magic;
301 __le32 nr;
302 __le32 len;
303 u8 data[KVASER_PCIEFD_CFG_PARAM_MAX_SZ];
304};
305
306struct kvaser_pciefd_cfg_img {
307 __le32 version;
308 __le32 magic;
309 __le32 crc;
310 struct kvaser_pciefd_cfg_param params[KVASER_PCIEFD_CFG_MAX_PARAMS];
311};
312
313static struct pci_device_id kvaser_pciefd_id_table[] = {
314 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_4HS_ID), },
315 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_2HS_ID), },
316 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_HS_ID), },
317 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_HS_ID), },
318 { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_2HS_ID), },
319 { 0,},
320};
321MODULE_DEVICE_TABLE(pci, kvaser_pciefd_id_table);
322
323/* Onboard flash memory functions */
324static int kvaser_pciefd_spi_wait_loop(struct kvaser_pciefd *pcie, int msk)
325{
326 u32 res;
327 int ret;
328
329 ret = readl_poll_timeout(pcie->reg_base + KVASER_PCIEFD_SPI_STATUS_REG,
330 res, res & msk, 0, 10);
331
332 return ret;
333}
334
335static int kvaser_pciefd_spi_cmd(struct kvaser_pciefd *pcie, const u8 *tx,
336 u32 tx_len, u8 *rx, u32 rx_len)
337{
338 int c;
339
340 iowrite32(BIT(0), pcie->reg_base + KVASER_PCIEFD_SPI_SSEL_REG);
341 iowrite32(BIT(10), pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG);
342 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
343
344 c = tx_len;
345 while (c--) {
346 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TRDY))
347 return -EIO;
348
349 iowrite32(*tx++, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG);
350
351 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_RRDY))
352 return -EIO;
353
354 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
355 }
356
357 c = rx_len;
358 while (c-- > 0) {
359 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TRDY))
360 return -EIO;
361
362 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG);
363
364 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_RRDY))
365 return -EIO;
366
367 *rx++ = ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
368 }
369
370 if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TMT))
371 return -EIO;
372
373 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG);
374
375 if (c != -1) {
376 dev_err(&pcie->pci->dev, "Flash SPI transfer failed\n");
377 return -EIO;
378 }
379
380 return 0;
381}
382
383static int kvaser_pciefd_cfg_read_and_verify(struct kvaser_pciefd *pcie,
384 struct kvaser_pciefd_cfg_img *img)
385{
386 int offset = KVASER_PCIEFD_CFG_IMG_OFFSET;
387 int res, crc;
388 u8 *crc_buff;
389
390 u8 cmd[] = {
391 KVASER_PCIEFD_FLASH_READ_CMD,
392 (u8)((offset >> 16) & 0xff),
393 (u8)((offset >> 8) & 0xff),
394 (u8)(offset & 0xff)
395 };
396
397 res = kvaser_pciefd_spi_cmd(pcie, cmd, ARRAY_SIZE(cmd), (u8 *)img,
398 KVASER_PCIEFD_CFG_IMG_SZ);
399 if (res)
400 return res;
401
402 crc_buff = (u8 *)img->params;
403
404 if (le32_to_cpu(img->version) != KVASER_PCIEFD_CFG_SYS_VER) {
405 dev_err(&pcie->pci->dev,
406 "Config flash corrupted, version number is wrong\n");
407 return -ENODEV;
408 }
409
410 if (le32_to_cpu(img->magic) != KVASER_PCIEFD_CFG_MAGIC) {
411 dev_err(&pcie->pci->dev,
412 "Config flash corrupted, magic number is wrong\n");
413 return -ENODEV;
414 }
415
416 crc = ~crc32_be(0xffffffff, crc_buff, sizeof(img->params));
417 if (le32_to_cpu(img->crc) != crc) {
418 dev_err(&pcie->pci->dev,
419 "Stored CRC does not match flash image contents\n");
420 return -EIO;
421 }
422
423 return 0;
424}
425
426static void kvaser_pciefd_cfg_read_params(struct kvaser_pciefd *pcie,
427 struct kvaser_pciefd_cfg_img *img)
428{
429 struct kvaser_pciefd_cfg_param *param;
430
431 param = &img->params[KVASER_PCIEFD_CFG_PARAM_NR_CHAN];
432 memcpy(&pcie->nr_channels, param->data, le32_to_cpu(param->len));
433}
434
435static int kvaser_pciefd_read_cfg(struct kvaser_pciefd *pcie)
436{
437 int res;
438 struct kvaser_pciefd_cfg_img *img;
439
440 /* Read electronic signature */
441 u8 cmd[] = {KVASER_PCIEFD_FLASH_RES_CMD, 0, 0, 0};
442
443 res = kvaser_pciefd_spi_cmd(pcie, cmd, ARRAY_SIZE(cmd), cmd, 1);
444 if (res)
445 return -EIO;
446
447 img = kmalloc(KVASER_PCIEFD_CFG_IMG_SZ, GFP_KERNEL);
448 if (!img)
449 return -ENOMEM;
450
451 if (cmd[0] != KVASER_PCIEFD_FLASH_ID_EPCS16) {
452 dev_err(&pcie->pci->dev,
453 "Flash id is 0x%x instead of expected EPCS16 (0x%x)\n",
454 cmd[0], KVASER_PCIEFD_FLASH_ID_EPCS16);
455
456 res = -ENODEV;
457 goto image_free;
458 }
459
460 cmd[0] = KVASER_PCIEFD_FLASH_STATUS_CMD;
461 res = kvaser_pciefd_spi_cmd(pcie, cmd, 1, cmd, 1);
462 if (res) {
463 goto image_free;
464 } else if (cmd[0] & 1) {
465 res = -EIO;
466 /* No write is ever done, the WIP should never be set */
467 dev_err(&pcie->pci->dev, "Unexpected WIP bit set in flash\n");
468 goto image_free;
469 }
470
471 res = kvaser_pciefd_cfg_read_and_verify(pcie, img);
472 if (res) {
473 res = -EIO;
474 goto image_free;
475 }
476
477 kvaser_pciefd_cfg_read_params(pcie, img);
478
479image_free:
480 kfree(img);
481 return res;
482}
483
484static void kvaser_pciefd_request_status(struct kvaser_pciefd_can *can)
485{
486 u32 cmd;
487
488 cmd = KVASER_PCIEFD_KCAN_CMD_SRQ;
489 cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT;
490 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
491}
492
493static void kvaser_pciefd_enable_err_gen(struct kvaser_pciefd_can *can)
494{
495 u32 mode;
496 unsigned long irq;
497
498 spin_lock_irqsave(&can->lock, irq);
499 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
500 if (!(mode & KVASER_PCIEFD_KCAN_MODE_EPEN)) {
501 mode |= KVASER_PCIEFD_KCAN_MODE_EPEN;
502 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
503 }
504 spin_unlock_irqrestore(&can->lock, irq);
505}
506
507static void kvaser_pciefd_disable_err_gen(struct kvaser_pciefd_can *can)
508{
509 u32 mode;
510 unsigned long irq;
511
512 spin_lock_irqsave(&can->lock, irq);
513 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
514 mode &= ~KVASER_PCIEFD_KCAN_MODE_EPEN;
515 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
516 spin_unlock_irqrestore(&can->lock, irq);
517}
518
519static int kvaser_pciefd_set_tx_irq(struct kvaser_pciefd_can *can)
520{
521 u32 msk;
522
523 msk = KVASER_PCIEFD_KCAN_IRQ_TE | KVASER_PCIEFD_KCAN_IRQ_ROF |
524 KVASER_PCIEFD_KCAN_IRQ_TOF | KVASER_PCIEFD_KCAN_IRQ_ABD |
525 KVASER_PCIEFD_KCAN_IRQ_TAE | KVASER_PCIEFD_KCAN_IRQ_TAL |
526 KVASER_PCIEFD_KCAN_IRQ_FDIC | KVASER_PCIEFD_KCAN_IRQ_BPP |
527 KVASER_PCIEFD_KCAN_IRQ_TAR | KVASER_PCIEFD_KCAN_IRQ_TFD;
528
529 iowrite32(msk, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
530
531 return 0;
532}
533
534static void kvaser_pciefd_setup_controller(struct kvaser_pciefd_can *can)
535{
536 u32 mode;
537 unsigned long irq;
538
539 spin_lock_irqsave(&can->lock, irq);
540
541 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
542 if (can->can.ctrlmode & CAN_CTRLMODE_FD) {
543 mode &= ~KVASER_PCIEFD_KCAN_MODE_CCM;
544 if (can->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)
545 mode |= KVASER_PCIEFD_KCAN_MODE_NIFDEN;
546 else
547 mode &= ~KVASER_PCIEFD_KCAN_MODE_NIFDEN;
548 } else {
549 mode |= KVASER_PCIEFD_KCAN_MODE_CCM;
550 mode &= ~KVASER_PCIEFD_KCAN_MODE_NIFDEN;
551 }
552
553 if (can->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
554 mode |= KVASER_PCIEFD_KCAN_MODE_LOM;
555
556 mode |= KVASER_PCIEFD_KCAN_MODE_EEN;
557 mode |= KVASER_PCIEFD_KCAN_MODE_EPEN;
558 /* Use ACK packet type */
559 mode &= ~KVASER_PCIEFD_KCAN_MODE_APT;
560 mode &= ~KVASER_PCIEFD_KCAN_MODE_RM;
561 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
562
563 spin_unlock_irqrestore(&can->lock, irq);
564}
565
566static void kvaser_pciefd_start_controller_flush(struct kvaser_pciefd_can *can)
567{
568 u32 status;
569 unsigned long irq;
570
571 spin_lock_irqsave(&can->lock, irq);
572 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
573 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD | KVASER_PCIEFD_KCAN_IRQ_TFD,
574 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
575
576 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
577 if (status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
578 u32 cmd;
579
580 /* If controller is already idle, run abort, flush and reset */
581 cmd = KVASER_PCIEFD_KCAN_CMD_AT;
582 cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT;
583 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
584 } else if (!(status & KVASER_PCIEFD_KCAN_STAT_RMR)) {
585 u32 mode;
586
587 /* Put controller in reset mode */
588 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
589 mode |= KVASER_PCIEFD_KCAN_MODE_RM;
590 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
591 }
592
593 spin_unlock_irqrestore(&can->lock, irq);
594}
595
596static int kvaser_pciefd_bus_on(struct kvaser_pciefd_can *can)
597{
598 u32 mode;
599 unsigned long irq;
600
601 del_timer(&can->bec_poll_timer);
602
603 if (!completion_done(&can->flush_comp))
604 kvaser_pciefd_start_controller_flush(can);
605
606 if (!wait_for_completion_timeout(&can->flush_comp,
607 KVASER_PCIEFD_WAIT_TIMEOUT)) {
608 netdev_err(can->can.dev, "Timeout during bus on flush\n");
609 return -ETIMEDOUT;
610 }
611
612 spin_lock_irqsave(&can->lock, irq);
613 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
614 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
615
616 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD | KVASER_PCIEFD_KCAN_IRQ_TFD,
617 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
618
619 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
620 mode &= ~KVASER_PCIEFD_KCAN_MODE_RM;
621 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
622 spin_unlock_irqrestore(&can->lock, irq);
623
624 if (!wait_for_completion_timeout(&can->start_comp,
625 KVASER_PCIEFD_WAIT_TIMEOUT)) {
626 netdev_err(can->can.dev, "Timeout during bus on reset\n");
627 return -ETIMEDOUT;
628 }
629 /* Reset interrupt handling */
630 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
631 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
632
633 kvaser_pciefd_set_tx_irq(can);
634 kvaser_pciefd_setup_controller(can);
635
636 can->can.state = CAN_STATE_ERROR_ACTIVE;
637 netif_wake_queue(can->can.dev);
638 can->bec.txerr = 0;
639 can->bec.rxerr = 0;
640 can->err_rep_cnt = 0;
641
642 return 0;
643}
644
645static void kvaser_pciefd_pwm_stop(struct kvaser_pciefd_can *can)
646{
647 u8 top;
648 u32 pwm_ctrl;
649 unsigned long irq;
650
651 spin_lock_irqsave(&can->lock, irq);
652 pwm_ctrl = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
653 top = (pwm_ctrl >> KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT) & 0xff;
654
655 /* Set duty cycle to zero */
656 pwm_ctrl |= top;
657 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
658 spin_unlock_irqrestore(&can->lock, irq);
659}
660
661static void kvaser_pciefd_pwm_start(struct kvaser_pciefd_can *can)
662{
663 int top, trigger;
664 u32 pwm_ctrl;
665 unsigned long irq;
666
667 kvaser_pciefd_pwm_stop(can);
668 spin_lock_irqsave(&can->lock, irq);
669
670 /* Set frequency to 500 KHz*/
671 top = can->kv_pcie->bus_freq / (2 * 500000) - 1;
672
673 pwm_ctrl = top & 0xff;
674 pwm_ctrl |= (top & 0xff) << KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT;
675 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
676
677 /* Set duty cycle to 95 */
678 trigger = (100 * top - 95 * (top + 1) + 50) / 100;
679 pwm_ctrl = trigger & 0xff;
680 pwm_ctrl |= (top & 0xff) << KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT;
681 iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
682 spin_unlock_irqrestore(&can->lock, irq);
683}
684
685static int kvaser_pciefd_open(struct net_device *netdev)
686{
687 int err;
688 struct kvaser_pciefd_can *can = netdev_priv(netdev);
689
690 err = open_candev(netdev);
691 if (err)
692 return err;
693
694 err = kvaser_pciefd_bus_on(can);
695 if (err)
696 return err;
697
698 return 0;
699}
700
701static int kvaser_pciefd_stop(struct net_device *netdev)
702{
703 struct kvaser_pciefd_can *can = netdev_priv(netdev);
704 int ret = 0;
705
706 /* Don't interrupt ongoing flush */
707 if (!completion_done(&can->flush_comp))
708 kvaser_pciefd_start_controller_flush(can);
709
710 if (!wait_for_completion_timeout(&can->flush_comp,
711 KVASER_PCIEFD_WAIT_TIMEOUT)) {
712 netdev_err(can->can.dev, "Timeout during stop\n");
713 ret = -ETIMEDOUT;
714 } else {
715 iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
716 del_timer(&can->bec_poll_timer);
717 }
718 close_candev(netdev);
719
720 return ret;
721}
722
723static int kvaser_pciefd_prepare_tx_packet(struct kvaser_pciefd_tx_packet *p,
724 struct kvaser_pciefd_can *can,
725 struct sk_buff *skb)
726{
727 struct canfd_frame *cf = (struct canfd_frame *)skb->data;
728 int packet_size;
729 int seq = can->echo_idx;
730
731 memset(p, 0, sizeof(*p));
732
733 if (can->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
734 p->header[1] |= KVASER_PCIEFD_TPACKET_SMS;
735
736 if (cf->can_id & CAN_RTR_FLAG)
737 p->header[0] |= KVASER_PCIEFD_RPACKET_RTR;
738
739 if (cf->can_id & CAN_EFF_FLAG)
740 p->header[0] |= KVASER_PCIEFD_RPACKET_IDE;
741
742 p->header[0] |= cf->can_id & CAN_EFF_MASK;
743 p->header[1] |= can_len2dlc(cf->len) << KVASER_PCIEFD_RPACKET_DLC_SHIFT;
744 p->header[1] |= KVASER_PCIEFD_TPACKET_AREQ;
745
746 if (can_is_canfd_skb(skb)) {
747 p->header[1] |= KVASER_PCIEFD_RPACKET_FDF;
748 if (cf->flags & CANFD_BRS)
749 p->header[1] |= KVASER_PCIEFD_RPACKET_BRS;
750 if (cf->flags & CANFD_ESI)
751 p->header[1] |= KVASER_PCIEFD_RPACKET_ESI;
752 }
753
754 p->header[1] |= seq & KVASER_PCIEFD_PACKET_SEQ_MSK;
755
756 packet_size = cf->len;
757 memcpy(p->data, cf->data, packet_size);
758
759 return DIV_ROUND_UP(packet_size, 4);
760}
761
762static netdev_tx_t kvaser_pciefd_start_xmit(struct sk_buff *skb,
763 struct net_device *netdev)
764{
765 struct kvaser_pciefd_can *can = netdev_priv(netdev);
766 unsigned long irq_flags;
767 struct kvaser_pciefd_tx_packet packet;
768 int nwords;
769 u8 count;
770
771 if (can_dropped_invalid_skb(netdev, skb))
772 return NETDEV_TX_OK;
773
774 nwords = kvaser_pciefd_prepare_tx_packet(&packet, can, skb);
775
776 spin_lock_irqsave(&can->echo_lock, irq_flags);
777
778 /* Prepare and save echo skb in internal slot */
779 can_put_echo_skb(skb, netdev, can->echo_idx);
780
781 /* Move echo index to the next slot */
782 can->echo_idx = (can->echo_idx + 1) % can->can.echo_skb_max;
783
784 /* Write header to fifo */
785 iowrite32(packet.header[0],
786 can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG);
787 iowrite32(packet.header[1],
788 can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG);
789
790 if (nwords) {
791 u32 data_last = ((u32 *)packet.data)[nwords - 1];
792
793 /* Write data to fifo, except last word */
794 iowrite32_rep(can->reg_base +
795 KVASER_PCIEFD_KCAN_FIFO_REG, packet.data,
796 nwords - 1);
797 /* Write last word to end of fifo */
798 __raw_writel(data_last, can->reg_base +
799 KVASER_PCIEFD_KCAN_FIFO_LAST_REG);
800 } else {
801 /* Complete write to fifo */
802 __raw_writel(0, can->reg_base +
803 KVASER_PCIEFD_KCAN_FIFO_LAST_REG);
804 }
805
806 count = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NPACKETS_REG);
807 /* No room for a new message, stop the queue until at least one
808 * successful transmit
809 */
810 if (count >= KVASER_PCIEFD_CAN_TX_MAX_COUNT ||
811 can->can.echo_skb[can->echo_idx])
812 netif_stop_queue(netdev);
813
814 spin_unlock_irqrestore(&can->echo_lock, irq_flags);
815
816 return NETDEV_TX_OK;
817}
818
819static int kvaser_pciefd_set_bittiming(struct kvaser_pciefd_can *can, bool data)
820{
821 u32 mode, test, btrn;
822 unsigned long irq_flags;
823 int ret;
824 struct can_bittiming *bt;
825
826 if (data)
827 bt = &can->can.data_bittiming;
828 else
829 bt = &can->can.bittiming;
830
831 btrn = ((bt->phase_seg2 - 1) & 0x1f) <<
832 KVASER_PCIEFD_KCAN_BTRN_TSEG2_SHIFT |
833 (((bt->prop_seg + bt->phase_seg1) - 1) & 0x1ff) <<
834 KVASER_PCIEFD_KCAN_BTRN_TSEG1_SHIFT |
835 ((bt->sjw - 1) & 0xf) << KVASER_PCIEFD_KCAN_BTRN_SJW_SHIFT |
836 ((bt->brp - 1) & 0x1fff);
837
838 spin_lock_irqsave(&can->lock, irq_flags);
839 mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
840
841 /* Put the circuit in reset mode */
842 iowrite32(mode | KVASER_PCIEFD_KCAN_MODE_RM,
843 can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
844
845 /* Can only set bittiming if in reset mode */
846 ret = readl_poll_timeout(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG,
847 test, test & KVASER_PCIEFD_KCAN_MODE_RM,
848 0, 10);
849
850 if (ret) {
851 spin_unlock_irqrestore(&can->lock, irq_flags);
852 return -EBUSY;
853 }
854
855 if (data)
856 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRD_REG);
857 else
858 iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRN_REG);
859
860 /* Restore previous reset mode status */
861 iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
862
863 spin_unlock_irqrestore(&can->lock, irq_flags);
864 return 0;
865}
866
867static int kvaser_pciefd_set_nominal_bittiming(struct net_device *ndev)
868{
869 return kvaser_pciefd_set_bittiming(netdev_priv(ndev), false);
870}
871
872static int kvaser_pciefd_set_data_bittiming(struct net_device *ndev)
873{
874 return kvaser_pciefd_set_bittiming(netdev_priv(ndev), true);
875}
876
877static int kvaser_pciefd_set_mode(struct net_device *ndev, enum can_mode mode)
878{
879 struct kvaser_pciefd_can *can = netdev_priv(ndev);
880 int ret = 0;
881
882 switch (mode) {
883 case CAN_MODE_START:
884 if (!can->can.restart_ms)
885 ret = kvaser_pciefd_bus_on(can);
886 break;
887 default:
888 return -EOPNOTSUPP;
889 }
890
891 return ret;
892}
893
894static int kvaser_pciefd_get_berr_counter(const struct net_device *ndev,
895 struct can_berr_counter *bec)
896{
897 struct kvaser_pciefd_can *can = netdev_priv(ndev);
898
899 bec->rxerr = can->bec.rxerr;
900 bec->txerr = can->bec.txerr;
901 return 0;
902}
903
904static void kvaser_pciefd_bec_poll_timer(struct timer_list *data)
905{
906 struct kvaser_pciefd_can *can = from_timer(can, data, bec_poll_timer);
907
908 kvaser_pciefd_enable_err_gen(can);
909 kvaser_pciefd_request_status(can);
910 can->err_rep_cnt = 0;
911}
912
913static const struct net_device_ops kvaser_pciefd_netdev_ops = {
914 .ndo_open = kvaser_pciefd_open,
915 .ndo_stop = kvaser_pciefd_stop,
916 .ndo_start_xmit = kvaser_pciefd_start_xmit,
917 .ndo_change_mtu = can_change_mtu,
918};
919
920static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie)
921{
922 int i;
923
924 for (i = 0; i < pcie->nr_channels; i++) {
925 struct net_device *netdev;
926 struct kvaser_pciefd_can *can;
927 u32 status, tx_npackets;
928
929 netdev = alloc_candev(sizeof(struct kvaser_pciefd_can),
930 KVASER_PCIEFD_CAN_TX_MAX_COUNT);
931 if (!netdev)
932 return -ENOMEM;
933
934 can = netdev_priv(netdev);
935 netdev->netdev_ops = &kvaser_pciefd_netdev_ops;
936 can->reg_base = pcie->reg_base + KVASER_PCIEFD_KCAN0_BASE +
937 i * KVASER_PCIEFD_KCAN_BASE_OFFSET;
938
939 can->kv_pcie = pcie;
940 can->cmd_seq = 0;
941 can->err_rep_cnt = 0;
942 can->bec.txerr = 0;
943 can->bec.rxerr = 0;
944
945 init_completion(&can->start_comp);
946 init_completion(&can->flush_comp);
947 timer_setup(&can->bec_poll_timer, kvaser_pciefd_bec_poll_timer,
948 0);
949
950 tx_npackets = ioread32(can->reg_base +
951 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG);
952 if (((tx_npackets >> KVASER_PCIEFD_KCAN_TX_NPACKETS_MAX_SHIFT) &
953 0xff) < KVASER_PCIEFD_CAN_TX_MAX_COUNT) {
954 dev_err(&pcie->pci->dev,
955 "Max Tx count is smaller than expected\n");
956
957 free_candev(netdev);
958 return -ENODEV;
959 }
960
961 can->can.clock.freq = pcie->freq;
962 can->can.echo_skb_max = KVASER_PCIEFD_CAN_TX_MAX_COUNT;
963 can->echo_idx = 0;
964 spin_lock_init(&can->echo_lock);
965 spin_lock_init(&can->lock);
966 can->can.bittiming_const = &kvaser_pciefd_bittiming_const;
967 can->can.data_bittiming_const = &kvaser_pciefd_bittiming_const;
968
969 can->can.do_set_bittiming = kvaser_pciefd_set_nominal_bittiming;
970 can->can.do_set_data_bittiming =
971 kvaser_pciefd_set_data_bittiming;
972
973 can->can.do_set_mode = kvaser_pciefd_set_mode;
974 can->can.do_get_berr_counter = kvaser_pciefd_get_berr_counter;
975
976 can->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
977 CAN_CTRLMODE_FD |
978 CAN_CTRLMODE_FD_NON_ISO;
979
980 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
981 if (!(status & KVASER_PCIEFD_KCAN_STAT_FD)) {
982 dev_err(&pcie->pci->dev,
983 "CAN FD not supported as expected %d\n", i);
984
985 free_candev(netdev);
986 return -ENODEV;
987 }
988
989 if (status & KVASER_PCIEFD_KCAN_STAT_CAP)
990 can->can.ctrlmode_supported |= CAN_CTRLMODE_ONE_SHOT;
991
992 netdev->flags |= IFF_ECHO;
993
994 SET_NETDEV_DEV(netdev, &pcie->pci->dev);
995
996 iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
997 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD |
998 KVASER_PCIEFD_KCAN_IRQ_TFD,
999 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1000
1001 pcie->can[i] = can;
1002 kvaser_pciefd_pwm_start(can);
1003 }
1004
1005 return 0;
1006}
1007
1008static int kvaser_pciefd_reg_candev(struct kvaser_pciefd *pcie)
1009{
1010 int i;
1011
1012 for (i = 0; i < pcie->nr_channels; i++) {
1013 int err = register_candev(pcie->can[i]->can.dev);
1014
1015 if (err) {
1016 int j;
1017
1018 /* Unregister all successfully registered devices. */
1019 for (j = 0; j < i; j++)
1020 unregister_candev(pcie->can[j]->can.dev);
1021 return err;
1022 }
1023 }
1024
1025 return 0;
1026}
1027
1028static void kvaser_pciefd_write_dma_map(struct kvaser_pciefd *pcie,
1029 dma_addr_t addr, int offset)
1030{
1031 u32 word1, word2;
1032
1033#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1034 word1 = addr | KVASER_PCIEFD_64BIT_DMA_BIT;
1035 word2 = addr >> 32;
1036#else
1037 word1 = addr;
1038 word2 = 0;
1039#endif
1040 iowrite32(word1, pcie->reg_base + offset);
1041 iowrite32(word2, pcie->reg_base + offset + 4);
1042}
1043
1044static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie)
1045{
1046 int i;
1047 u32 srb_status;
1048 dma_addr_t dma_addr[KVASER_PCIEFD_DMA_COUNT];
1049
1050 /* Disable the DMA */
1051 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1052 for (i = 0; i < KVASER_PCIEFD_DMA_COUNT; i++) {
1053 unsigned int offset = KVASER_PCIEFD_DMA_MAP_BASE + 8 * i;
1054
1055 pcie->dma_data[i] =
1056 dmam_alloc_coherent(&pcie->pci->dev,
1057 KVASER_PCIEFD_DMA_SIZE,
1058 &dma_addr[i],
1059 GFP_KERNEL);
1060
1061 if (!pcie->dma_data[i] || !dma_addr[i]) {
1062 dev_err(&pcie->pci->dev, "Rx dma_alloc(%u) failure\n",
1063 KVASER_PCIEFD_DMA_SIZE);
1064 return -ENOMEM;
1065 }
1066
1067 kvaser_pciefd_write_dma_map(pcie, dma_addr[i], offset);
1068 }
1069
1070 /* Reset Rx FIFO, and both DMA buffers */
1071 iowrite32(KVASER_PCIEFD_SRB_CMD_FOR | KVASER_PCIEFD_SRB_CMD_RDB0 |
1072 KVASER_PCIEFD_SRB_CMD_RDB1,
1073 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1074
1075 srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG);
1076 if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DI)) {
1077 dev_err(&pcie->pci->dev, "DMA not idle before enabling\n");
1078 return -EIO;
1079 }
1080
1081 /* Enable the DMA */
1082 iowrite32(KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE,
1083 pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1084
1085 return 0;
1086}
1087
1088static int kvaser_pciefd_setup_board(struct kvaser_pciefd *pcie)
1089{
1090 u32 sysid, srb_status, build;
1091 u8 sysid_nr_chan;
1092 int ret;
1093
1094 ret = kvaser_pciefd_read_cfg(pcie);
1095 if (ret)
1096 return ret;
1097
1098 sysid = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_VERSION_REG);
1099 sysid_nr_chan = (sysid >> KVASER_PCIEFD_SYSID_NRCHAN_SHIFT) & 0xff;
1100 if (pcie->nr_channels != sysid_nr_chan) {
1101 dev_err(&pcie->pci->dev,
1102 "Number of channels does not match: %u vs %u\n",
1103 pcie->nr_channels,
1104 sysid_nr_chan);
1105 return -ENODEV;
1106 }
1107
1108 if (pcie->nr_channels > KVASER_PCIEFD_MAX_CAN_CHANNELS)
1109 pcie->nr_channels = KVASER_PCIEFD_MAX_CAN_CHANNELS;
1110
1111 build = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_BUILD_REG);
1112 dev_dbg(&pcie->pci->dev, "Version %u.%u.%u\n",
1113 (sysid >> KVASER_PCIEFD_SYSID_MAJOR_VER_SHIFT) & 0xff,
1114 sysid & 0xff,
1115 (build >> KVASER_PCIEFD_SYSID_BUILD_VER_SHIFT) & 0x7fff);
1116
1117 srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG);
1118 if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DMA)) {
1119 dev_err(&pcie->pci->dev,
1120 "Hardware without DMA is not supported\n");
1121 return -ENODEV;
1122 }
1123
1124 pcie->bus_freq = ioread32(pcie->reg_base +
1125 KVASER_PCIEFD_SYSID_BUSFREQ_REG);
1126 pcie->freq = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_CANFREQ_REG);
1127 pcie->freq_to_ticks_div = pcie->freq / 1000000;
1128 if (pcie->freq_to_ticks_div == 0)
1129 pcie->freq_to_ticks_div = 1;
1130
1131 /* Turn off all loopback functionality */
1132 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_LOOP_REG);
1133 return ret;
1134}
1135
1136static int kvaser_pciefd_handle_data_packet(struct kvaser_pciefd *pcie,
1137 struct kvaser_pciefd_rx_packet *p,
1138 __le32 *data)
1139{
1140 struct sk_buff *skb;
1141 struct canfd_frame *cf;
1142 struct can_priv *priv;
1143 struct net_device_stats *stats;
1144 struct skb_shared_hwtstamps *shhwtstamps;
1145 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1146
1147 if (ch_id >= pcie->nr_channels)
1148 return -EIO;
1149
1150 priv = &pcie->can[ch_id]->can;
1151 stats = &priv->dev->stats;
1152
1153 if (p->header[1] & KVASER_PCIEFD_RPACKET_FDF) {
1154 skb = alloc_canfd_skb(priv->dev, &cf);
1155 if (!skb) {
1156 stats->rx_dropped++;
1157 return -ENOMEM;
1158 }
1159
1160 if (p->header[1] & KVASER_PCIEFD_RPACKET_BRS)
1161 cf->flags |= CANFD_BRS;
1162
1163 if (p->header[1] & KVASER_PCIEFD_RPACKET_ESI)
1164 cf->flags |= CANFD_ESI;
1165 } else {
1166 skb = alloc_can_skb(priv->dev, (struct can_frame **)&cf);
1167 if (!skb) {
1168 stats->rx_dropped++;
1169 return -ENOMEM;
1170 }
1171 }
1172
1173 cf->can_id = p->header[0] & CAN_EFF_MASK;
1174 if (p->header[0] & KVASER_PCIEFD_RPACKET_IDE)
1175 cf->can_id |= CAN_EFF_FLAG;
1176
1177 cf->len = can_dlc2len(p->header[1] >> KVASER_PCIEFD_RPACKET_DLC_SHIFT);
1178
1179 if (p->header[0] & KVASER_PCIEFD_RPACKET_RTR)
1180 cf->can_id |= CAN_RTR_FLAG;
1181 else
1182 memcpy(cf->data, data, cf->len);
1183
1184 shhwtstamps = skb_hwtstamps(skb);
1185
1186 shhwtstamps->hwtstamp =
1187 ns_to_ktime(div_u64(p->timestamp * 1000,
1188 pcie->freq_to_ticks_div));
1189
1190 stats->rx_bytes += cf->len;
1191 stats->rx_packets++;
1192
1193 return netif_rx(skb);
1194}
1195
1196static void kvaser_pciefd_change_state(struct kvaser_pciefd_can *can,
1197 struct can_frame *cf,
1198 enum can_state new_state,
1199 enum can_state tx_state,
1200 enum can_state rx_state)
1201{
1202 can_change_state(can->can.dev, cf, tx_state, rx_state);
1203
1204 if (new_state == CAN_STATE_BUS_OFF) {
1205 struct net_device *ndev = can->can.dev;
1206 unsigned long irq_flags;
1207
1208 spin_lock_irqsave(&can->lock, irq_flags);
1209 netif_stop_queue(can->can.dev);
1210 spin_unlock_irqrestore(&can->lock, irq_flags);
1211
1212 /* Prevent CAN controller from auto recover from bus off */
1213 if (!can->can.restart_ms) {
1214 kvaser_pciefd_start_controller_flush(can);
1215 can_bus_off(ndev);
1216 }
1217 }
1218}
1219
1220static void kvaser_pciefd_packet_to_state(struct kvaser_pciefd_rx_packet *p,
1221 struct can_berr_counter *bec,
1222 enum can_state *new_state,
1223 enum can_state *tx_state,
1224 enum can_state *rx_state)
1225{
1226 if (p->header[0] & KVASER_PCIEFD_SPACK_BOFF ||
1227 p->header[0] & KVASER_PCIEFD_SPACK_IRM)
1228 *new_state = CAN_STATE_BUS_OFF;
1229 else if (bec->txerr >= 255 || bec->rxerr >= 255)
1230 *new_state = CAN_STATE_BUS_OFF;
1231 else if (p->header[1] & KVASER_PCIEFD_SPACK_EPLR)
1232 *new_state = CAN_STATE_ERROR_PASSIVE;
1233 else if (bec->txerr >= 128 || bec->rxerr >= 128)
1234 *new_state = CAN_STATE_ERROR_PASSIVE;
1235 else if (p->header[1] & KVASER_PCIEFD_SPACK_EWLR)
1236 *new_state = CAN_STATE_ERROR_WARNING;
1237 else if (bec->txerr >= 96 || bec->rxerr >= 96)
1238 *new_state = CAN_STATE_ERROR_WARNING;
1239 else
1240 *new_state = CAN_STATE_ERROR_ACTIVE;
1241
1242 *tx_state = bec->txerr >= bec->rxerr ? *new_state : 0;
1243 *rx_state = bec->txerr <= bec->rxerr ? *new_state : 0;
1244}
1245
1246static int kvaser_pciefd_rx_error_frame(struct kvaser_pciefd_can *can,
1247 struct kvaser_pciefd_rx_packet *p)
1248{
1249 struct can_berr_counter bec;
1250 enum can_state old_state, new_state, tx_state, rx_state;
1251 struct net_device *ndev = can->can.dev;
1252 struct sk_buff *skb;
1253 struct can_frame *cf = NULL;
1254 struct skb_shared_hwtstamps *shhwtstamps;
1255 struct net_device_stats *stats = &ndev->stats;
1256
1257 old_state = can->can.state;
1258
1259 bec.txerr = p->header[0] & 0xff;
1260 bec.rxerr = (p->header[0] >> KVASER_PCIEFD_SPACK_RXERR_SHIFT) & 0xff;
1261
1262 kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state,
1263 &rx_state);
1264
1265 skb = alloc_can_err_skb(ndev, &cf);
1266
1267 if (new_state != old_state) {
1268 kvaser_pciefd_change_state(can, cf, new_state, tx_state,
1269 rx_state);
1270
1271 if (old_state == CAN_STATE_BUS_OFF &&
1272 new_state == CAN_STATE_ERROR_ACTIVE &&
1273 can->can.restart_ms) {
1274 can->can.can_stats.restarts++;
1275 if (skb)
1276 cf->can_id |= CAN_ERR_RESTARTED;
1277 }
1278 }
1279
1280 can->err_rep_cnt++;
1281 can->can.can_stats.bus_error++;
1282 stats->rx_errors++;
1283
1284 can->bec.txerr = bec.txerr;
1285 can->bec.rxerr = bec.rxerr;
1286
1287 if (!skb) {
1288 stats->rx_dropped++;
1289 return -ENOMEM;
1290 }
1291
1292 shhwtstamps = skb_hwtstamps(skb);
1293 shhwtstamps->hwtstamp =
1294 ns_to_ktime(div_u64(p->timestamp * 1000,
1295 can->kv_pcie->freq_to_ticks_div));
1296 cf->can_id |= CAN_ERR_BUSERROR;
1297
1298 cf->data[6] = bec.txerr;
1299 cf->data[7] = bec.rxerr;
1300
1301 stats->rx_packets++;
1302 stats->rx_bytes += cf->can_dlc;
1303
1304 netif_rx(skb);
1305 return 0;
1306}
1307
1308static int kvaser_pciefd_handle_error_packet(struct kvaser_pciefd *pcie,
1309 struct kvaser_pciefd_rx_packet *p)
1310{
1311 struct kvaser_pciefd_can *can;
1312 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1313
1314 if (ch_id >= pcie->nr_channels)
1315 return -EIO;
1316
1317 can = pcie->can[ch_id];
1318
1319 kvaser_pciefd_rx_error_frame(can, p);
1320 if (can->err_rep_cnt >= KVASER_PCIEFD_MAX_ERR_REP)
1321 /* Do not report more errors, until bec_poll_timer expires */
1322 kvaser_pciefd_disable_err_gen(can);
1323 /* Start polling the error counters */
1324 mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ);
1325 return 0;
1326}
1327
1328static int kvaser_pciefd_handle_status_resp(struct kvaser_pciefd_can *can,
1329 struct kvaser_pciefd_rx_packet *p)
1330{
1331 struct can_berr_counter bec;
1332 enum can_state old_state, new_state, tx_state, rx_state;
1333
1334 old_state = can->can.state;
1335
1336 bec.txerr = p->header[0] & 0xff;
1337 bec.rxerr = (p->header[0] >> KVASER_PCIEFD_SPACK_RXERR_SHIFT) & 0xff;
1338
1339 kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state,
1340 &rx_state);
1341
1342 if (new_state != old_state) {
1343 struct net_device *ndev = can->can.dev;
1344 struct sk_buff *skb;
1345 struct can_frame *cf;
1346 struct skb_shared_hwtstamps *shhwtstamps;
1347
1348 skb = alloc_can_err_skb(ndev, &cf);
1349 if (!skb) {
1350 struct net_device_stats *stats = &ndev->stats;
1351
1352 stats->rx_dropped++;
1353 return -ENOMEM;
1354 }
1355
1356 kvaser_pciefd_change_state(can, cf, new_state, tx_state,
1357 rx_state);
1358
1359 if (old_state == CAN_STATE_BUS_OFF &&
1360 new_state == CAN_STATE_ERROR_ACTIVE &&
1361 can->can.restart_ms) {
1362 can->can.can_stats.restarts++;
1363 cf->can_id |= CAN_ERR_RESTARTED;
1364 }
1365
1366 shhwtstamps = skb_hwtstamps(skb);
1367 shhwtstamps->hwtstamp =
1368 ns_to_ktime(div_u64(p->timestamp * 1000,
1369 can->kv_pcie->freq_to_ticks_div));
1370
1371 cf->data[6] = bec.txerr;
1372 cf->data[7] = bec.rxerr;
1373
1374 netif_rx(skb);
1375 }
1376 can->bec.txerr = bec.txerr;
1377 can->bec.rxerr = bec.rxerr;
1378 /* Check if we need to poll the error counters */
1379 if (bec.txerr || bec.rxerr)
1380 mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ);
1381
1382 return 0;
1383}
1384
1385static int kvaser_pciefd_handle_status_packet(struct kvaser_pciefd *pcie,
1386 struct kvaser_pciefd_rx_packet *p)
1387{
1388 struct kvaser_pciefd_can *can;
1389 u8 cmdseq;
1390 u32 status;
1391 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1392
1393 if (ch_id >= pcie->nr_channels)
1394 return -EIO;
1395
1396 can = pcie->can[ch_id];
1397
1398 status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
1399 cmdseq = (status >> KVASER_PCIEFD_KCAN_STAT_SEQNO_SHIFT) & 0xff;
1400
1401 /* Reset done, start abort and flush */
1402 if (p->header[0] & KVASER_PCIEFD_SPACK_IRM &&
1403 p->header[0] & KVASER_PCIEFD_SPACK_RMCD &&
1404 p->header[1] & KVASER_PCIEFD_SPACK_AUTO &&
1405 cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK) &&
1406 status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
1407 u32 cmd;
1408
1409 iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
1410 can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1411 cmd = KVASER_PCIEFD_KCAN_CMD_AT;
1412 cmd |= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT;
1413 iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
1414
1415 iowrite32(KVASER_PCIEFD_KCAN_IRQ_TFD,
1416 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1417 } else if (p->header[0] & KVASER_PCIEFD_SPACK_IDET &&
1418 p->header[0] & KVASER_PCIEFD_SPACK_IRM &&
1419 cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK) &&
1420 status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
1421 /* Reset detected, send end of flush if no packet are in FIFO */
1422 u8 count = ioread32(can->reg_base +
1423 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff;
1424
1425 if (!count)
1426 iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH,
1427 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG);
1428 } else if (!(p->header[1] & KVASER_PCIEFD_SPACK_AUTO) &&
1429 cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK)) {
1430 /* Response to status request received */
1431 kvaser_pciefd_handle_status_resp(can, p);
1432 if (can->can.state != CAN_STATE_BUS_OFF &&
1433 can->can.state != CAN_STATE_ERROR_ACTIVE) {
1434 mod_timer(&can->bec_poll_timer,
1435 KVASER_PCIEFD_BEC_POLL_FREQ);
1436 }
1437 } else if (p->header[0] & KVASER_PCIEFD_SPACK_RMCD &&
1438 !(status & KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MSK)) {
1439 /* Reset to bus on detected */
1440 if (!completion_done(&can->start_comp))
1441 complete(&can->start_comp);
1442 }
1443
1444 return 0;
1445}
1446
1447static int kvaser_pciefd_handle_eack_packet(struct kvaser_pciefd *pcie,
1448 struct kvaser_pciefd_rx_packet *p)
1449{
1450 struct kvaser_pciefd_can *can;
1451 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1452
1453 if (ch_id >= pcie->nr_channels)
1454 return -EIO;
1455
1456 can = pcie->can[ch_id];
1457
1458 /* If this is the last flushed packet, send end of flush */
1459 if (p->header[0] & KVASER_PCIEFD_APACKET_FLU) {
1460 u8 count = ioread32(can->reg_base +
1461 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff;
1462
1463 if (count == 0)
1464 iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH,
1465 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG);
1466 } else {
1467 int echo_idx = p->header[0] & KVASER_PCIEFD_PACKET_SEQ_MSK;
1468 int dlc = can_get_echo_skb(can->can.dev, echo_idx);
1469 struct net_device_stats *stats = &can->can.dev->stats;
1470
1471 stats->tx_bytes += dlc;
1472 stats->tx_packets++;
1473
1474 if (netif_queue_stopped(can->can.dev))
1475 netif_wake_queue(can->can.dev);
1476 }
1477
1478 return 0;
1479}
1480
1481static void kvaser_pciefd_handle_nack_packet(struct kvaser_pciefd_can *can,
1482 struct kvaser_pciefd_rx_packet *p)
1483{
1484 struct sk_buff *skb;
1485 struct net_device_stats *stats = &can->can.dev->stats;
1486 struct can_frame *cf;
1487
1488 skb = alloc_can_err_skb(can->can.dev, &cf);
1489
1490 stats->tx_errors++;
1491 if (p->header[0] & KVASER_PCIEFD_APACKET_ABL) {
1492 if (skb)
1493 cf->can_id |= CAN_ERR_LOSTARB;
1494 can->can.can_stats.arbitration_lost++;
1495 } else if (skb) {
1496 cf->can_id |= CAN_ERR_ACK;
1497 }
1498
1499 if (skb) {
1500 cf->can_id |= CAN_ERR_BUSERROR;
1501 stats->rx_bytes += cf->can_dlc;
1502 stats->rx_packets++;
1503 netif_rx(skb);
1504 } else {
1505 stats->rx_dropped++;
1506 netdev_warn(can->can.dev, "No memory left for err_skb\n");
1507 }
1508}
1509
1510static int kvaser_pciefd_handle_ack_packet(struct kvaser_pciefd *pcie,
1511 struct kvaser_pciefd_rx_packet *p)
1512{
1513 struct kvaser_pciefd_can *can;
1514 bool one_shot_fail = false;
1515 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1516
1517 if (ch_id >= pcie->nr_channels)
1518 return -EIO;
1519
1520 can = pcie->can[ch_id];
1521 /* Ignore control packet ACK */
1522 if (p->header[0] & KVASER_PCIEFD_APACKET_CT)
1523 return 0;
1524
1525 if (p->header[0] & KVASER_PCIEFD_APACKET_NACK) {
1526 kvaser_pciefd_handle_nack_packet(can, p);
1527 one_shot_fail = true;
1528 }
1529
1530 if (p->header[0] & KVASER_PCIEFD_APACKET_FLU) {
1531 netdev_dbg(can->can.dev, "Packet was flushed\n");
1532 } else {
1533 int echo_idx = p->header[0] & KVASER_PCIEFD_PACKET_SEQ_MSK;
1534 int dlc = can_get_echo_skb(can->can.dev, echo_idx);
1535 u8 count = ioread32(can->reg_base +
1536 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff;
1537
1538 if (count < KVASER_PCIEFD_CAN_TX_MAX_COUNT &&
1539 netif_queue_stopped(can->can.dev))
1540 netif_wake_queue(can->can.dev);
1541
1542 if (!one_shot_fail) {
1543 struct net_device_stats *stats = &can->can.dev->stats;
1544
1545 stats->tx_bytes += dlc;
1546 stats->tx_packets++;
1547 }
1548 }
1549
1550 return 0;
1551}
1552
1553static int kvaser_pciefd_handle_eflush_packet(struct kvaser_pciefd *pcie,
1554 struct kvaser_pciefd_rx_packet *p)
1555{
1556 struct kvaser_pciefd_can *can;
1557 u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1558
1559 if (ch_id >= pcie->nr_channels)
1560 return -EIO;
1561
1562 can = pcie->can[ch_id];
1563
1564 if (!completion_done(&can->flush_comp))
1565 complete(&can->flush_comp);
1566
1567 return 0;
1568}
1569
1570static int kvaser_pciefd_read_packet(struct kvaser_pciefd *pcie, int *start_pos,
1571 int dma_buf)
1572{
1573 __le32 *buffer = pcie->dma_data[dma_buf];
1574 __le64 timestamp;
1575 struct kvaser_pciefd_rx_packet packet;
1576 struct kvaser_pciefd_rx_packet *p = &packet;
1577 u8 type;
1578 int pos = *start_pos;
1579 int size;
1580 int ret = 0;
1581
1582 size = le32_to_cpu(buffer[pos++]);
1583 if (!size) {
1584 *start_pos = 0;
1585 return 0;
1586 }
1587
1588 p->header[0] = le32_to_cpu(buffer[pos++]);
1589 p->header[1] = le32_to_cpu(buffer[pos++]);
1590
1591 /* Read 64-bit timestamp */
1592 memcpy(×tamp, &buffer[pos], sizeof(__le64));
1593 pos += 2;
1594 p->timestamp = le64_to_cpu(timestamp);
1595
1596 type = (p->header[1] >> KVASER_PCIEFD_PACKET_TYPE_SHIFT) & 0xf;
1597 switch (type) {
1598 case KVASER_PCIEFD_PACK_TYPE_DATA:
1599 ret = kvaser_pciefd_handle_data_packet(pcie, p, &buffer[pos]);
1600 if (!(p->header[0] & KVASER_PCIEFD_RPACKET_RTR)) {
1601 u8 data_len;
1602
1603 data_len = can_dlc2len(p->header[1] >>
1604 KVASER_PCIEFD_RPACKET_DLC_SHIFT);
1605 pos += DIV_ROUND_UP(data_len, 4);
1606 }
1607 break;
1608
1609 case KVASER_PCIEFD_PACK_TYPE_ACK:
1610 ret = kvaser_pciefd_handle_ack_packet(pcie, p);
1611 break;
1612
1613 case KVASER_PCIEFD_PACK_TYPE_STATUS:
1614 ret = kvaser_pciefd_handle_status_packet(pcie, p);
1615 break;
1616
1617 case KVASER_PCIEFD_PACK_TYPE_ERROR:
1618 ret = kvaser_pciefd_handle_error_packet(pcie, p);
1619 break;
1620
1621 case KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK:
1622 ret = kvaser_pciefd_handle_eack_packet(pcie, p);
1623 break;
1624
1625 case KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK:
1626 ret = kvaser_pciefd_handle_eflush_packet(pcie, p);
1627 break;
1628
1629 case KVASER_PCIEFD_PACK_TYPE_ACK_DATA:
1630 case KVASER_PCIEFD_PACK_TYPE_BUS_LOAD:
1631 case KVASER_PCIEFD_PACK_TYPE_TXRQ:
1632 dev_info(&pcie->pci->dev,
1633 "Received unexpected packet type 0x%08X\n", type);
1634 break;
1635
1636 default:
1637 dev_err(&pcie->pci->dev, "Unknown packet type 0x%08X\n", type);
1638 ret = -EIO;
1639 break;
1640 }
1641
1642 if (ret)
1643 return ret;
1644
1645 /* Position does not point to the end of the package,
1646 * corrupted packet size?
1647 */
1648 if ((*start_pos + size) != pos)
1649 return -EIO;
1650
1651 /* Point to the next packet header, if any */
1652 *start_pos = pos;
1653
1654 return ret;
1655}
1656
1657static int kvaser_pciefd_read_buffer(struct kvaser_pciefd *pcie, int dma_buf)
1658{
1659 int pos = 0;
1660 int res = 0;
1661
1662 do {
1663 res = kvaser_pciefd_read_packet(pcie, &pos, dma_buf);
1664 } while (!res && pos > 0 && pos < KVASER_PCIEFD_DMA_SIZE);
1665
1666 return res;
1667}
1668
1669static int kvaser_pciefd_receive_irq(struct kvaser_pciefd *pcie)
1670{
1671 u32 irq;
1672
1673 irq = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG);
1674 if (irq & KVASER_PCIEFD_SRB_IRQ_DPD0) {
1675 kvaser_pciefd_read_buffer(pcie, 0);
1676 /* Reset DMA buffer 0 */
1677 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB0,
1678 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1679 }
1680
1681 if (irq & KVASER_PCIEFD_SRB_IRQ_DPD1) {
1682 kvaser_pciefd_read_buffer(pcie, 1);
1683 /* Reset DMA buffer 1 */
1684 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB1,
1685 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1686 }
1687
1688 if (irq & KVASER_PCIEFD_SRB_IRQ_DOF0 ||
1689 irq & KVASER_PCIEFD_SRB_IRQ_DOF1 ||
1690 irq & KVASER_PCIEFD_SRB_IRQ_DUF0 ||
1691 irq & KVASER_PCIEFD_SRB_IRQ_DUF1)
1692 dev_err(&pcie->pci->dev, "DMA IRQ error 0x%08X\n", irq);
1693
1694 iowrite32(irq, pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG);
1695 return 0;
1696}
1697
1698static int kvaser_pciefd_transmit_irq(struct kvaser_pciefd_can *can)
1699{
1700 u32 irq = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1701
1702 if (irq & KVASER_PCIEFD_KCAN_IRQ_TOF)
1703 netdev_err(can->can.dev, "Tx FIFO overflow\n");
1704
1705 if (irq & KVASER_PCIEFD_KCAN_IRQ_TFD) {
1706 u8 count = ioread32(can->reg_base +
1707 KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff;
1708
1709 if (count == 0)
1710 iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH,
1711 can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG);
1712 }
1713
1714 if (irq & KVASER_PCIEFD_KCAN_IRQ_BPP)
1715 netdev_err(can->can.dev,
1716 "Fail to change bittiming, when not in reset mode\n");
1717
1718 if (irq & KVASER_PCIEFD_KCAN_IRQ_FDIC)
1719 netdev_err(can->can.dev, "CAN FD frame in CAN mode\n");
1720
1721 if (irq & KVASER_PCIEFD_KCAN_IRQ_ROF)
1722 netdev_err(can->can.dev, "Rx FIFO overflow\n");
1723
1724 iowrite32(irq, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1725 return 0;
1726}
1727
1728static irqreturn_t kvaser_pciefd_irq_handler(int irq, void *dev)
1729{
1730 struct kvaser_pciefd *pcie = (struct kvaser_pciefd *)dev;
1731 u32 board_irq;
1732 int i;
1733
1734 board_irq = ioread32(pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1735
1736 if (!(board_irq & KVASER_PCIEFD_IRQ_ALL_MSK))
1737 return IRQ_NONE;
1738
1739 if (board_irq & KVASER_PCIEFD_IRQ_SRB)
1740 kvaser_pciefd_receive_irq(pcie);
1741
1742 for (i = 0; i < pcie->nr_channels; i++) {
1743 if (!pcie->can[i]) {
1744 dev_err(&pcie->pci->dev,
1745 "IRQ mask points to unallocated controller\n");
1746 break;
1747 }
1748
1749 /* Check that mask matches channel (i) IRQ mask */
1750 if (board_irq & (1 << i))
1751 kvaser_pciefd_transmit_irq(pcie->can[i]);
1752 }
1753
1754 iowrite32(board_irq, pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1755 return IRQ_HANDLED;
1756}
1757
1758static void kvaser_pciefd_teardown_can_ctrls(struct kvaser_pciefd *pcie)
1759{
1760 int i;
1761 struct kvaser_pciefd_can *can;
1762
1763 for (i = 0; i < pcie->nr_channels; i++) {
1764 can = pcie->can[i];
1765 if (can) {
1766 iowrite32(0,
1767 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1768 kvaser_pciefd_pwm_stop(can);
1769 free_candev(can->can.dev);
1770 }
1771 }
1772}
1773
1774static int kvaser_pciefd_probe(struct pci_dev *pdev,
1775 const struct pci_device_id *id)
1776{
1777 int err;
1778 struct kvaser_pciefd *pcie;
1779
1780 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
1781 if (!pcie)
1782 return -ENOMEM;
1783
1784 pci_set_drvdata(pdev, pcie);
1785 pcie->pci = pdev;
1786
1787 err = pci_enable_device(pdev);
1788 if (err)
1789 return err;
1790
1791 err = pci_request_regions(pdev, KVASER_PCIEFD_DRV_NAME);
1792 if (err)
1793 goto err_disable_pci;
1794
1795 pcie->reg_base = pci_iomap(pdev, 0, 0);
1796 if (!pcie->reg_base) {
1797 err = -ENOMEM;
1798 goto err_release_regions;
1799 }
1800
1801 err = kvaser_pciefd_setup_board(pcie);
1802 if (err)
1803 goto err_pci_iounmap;
1804
1805 err = kvaser_pciefd_setup_dma(pcie);
1806 if (err)
1807 goto err_pci_iounmap;
1808
1809 pci_set_master(pdev);
1810
1811 err = kvaser_pciefd_setup_can_ctrls(pcie);
1812 if (err)
1813 goto err_teardown_can_ctrls;
1814
1815 iowrite32(KVASER_PCIEFD_SRB_IRQ_DPD0 | KVASER_PCIEFD_SRB_IRQ_DPD1,
1816 pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG);
1817
1818 iowrite32(KVASER_PCIEFD_SRB_IRQ_DPD0 | KVASER_PCIEFD_SRB_IRQ_DPD1 |
1819 KVASER_PCIEFD_SRB_IRQ_DOF0 | KVASER_PCIEFD_SRB_IRQ_DOF1 |
1820 KVASER_PCIEFD_SRB_IRQ_DUF0 | KVASER_PCIEFD_SRB_IRQ_DUF1,
1821 pcie->reg_base + KVASER_PCIEFD_SRB_IEN_REG);
1822
1823 /* Reset IRQ handling, expected to be off before */
1824 iowrite32(KVASER_PCIEFD_IRQ_ALL_MSK,
1825 pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1826 iowrite32(KVASER_PCIEFD_IRQ_ALL_MSK,
1827 pcie->reg_base + KVASER_PCIEFD_IEN_REG);
1828
1829 /* Ready the DMA buffers */
1830 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB0,
1831 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1832 iowrite32(KVASER_PCIEFD_SRB_CMD_RDB1,
1833 pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1834
1835 err = request_irq(pcie->pci->irq, kvaser_pciefd_irq_handler,
1836 IRQF_SHARED, KVASER_PCIEFD_DRV_NAME, pcie);
1837 if (err)
1838 goto err_teardown_can_ctrls;
1839
1840 err = kvaser_pciefd_reg_candev(pcie);
1841 if (err)
1842 goto err_free_irq;
1843
1844 return 0;
1845
1846err_free_irq:
1847 free_irq(pcie->pci->irq, pcie);
1848
1849err_teardown_can_ctrls:
1850 kvaser_pciefd_teardown_can_ctrls(pcie);
1851 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1852 pci_clear_master(pdev);
1853
1854err_pci_iounmap:
1855 pci_iounmap(pdev, pcie->reg_base);
1856
1857err_release_regions:
1858 pci_release_regions(pdev);
1859
1860err_disable_pci:
1861 pci_disable_device(pdev);
1862
1863 return err;
1864}
1865
1866static void kvaser_pciefd_remove_all_ctrls(struct kvaser_pciefd *pcie)
1867{
1868 struct kvaser_pciefd_can *can;
1869 int i;
1870
1871 for (i = 0; i < pcie->nr_channels; i++) {
1872 can = pcie->can[i];
1873 if (can) {
1874 iowrite32(0,
1875 can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1876 unregister_candev(can->can.dev);
1877 del_timer(&can->bec_poll_timer);
1878 kvaser_pciefd_pwm_stop(can);
1879 free_candev(can->can.dev);
1880 }
1881 }
1882}
1883
1884static void kvaser_pciefd_remove(struct pci_dev *pdev)
1885{
1886 struct kvaser_pciefd *pcie = pci_get_drvdata(pdev);
1887
1888 kvaser_pciefd_remove_all_ctrls(pcie);
1889
1890 /* Turn off IRQ generation */
1891 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1892 iowrite32(KVASER_PCIEFD_IRQ_ALL_MSK,
1893 pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1894 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_IEN_REG);
1895
1896 free_irq(pcie->pci->irq, pcie);
1897
1898 pci_clear_master(pdev);
1899 pci_iounmap(pdev, pcie->reg_base);
1900 pci_release_regions(pdev);
1901 pci_disable_device(pdev);
1902}
1903
1904static struct pci_driver kvaser_pciefd = {
1905 .name = KVASER_PCIEFD_DRV_NAME,
1906 .id_table = kvaser_pciefd_id_table,
1907 .probe = kvaser_pciefd_probe,
1908 .remove = kvaser_pciefd_remove,
1909};
1910
1911module_pci_driver(kvaser_pciefd)