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1// SPDX-License-Identifier: GPL-2.0-or-later
2/* Realtek PCI-Express SD/MMC Card Interface driver
3 *
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Wei WANG <wei_wang@realsil.com.cn>
8 */
9
10#include <linux/pci.h>
11#include <linux/module.h>
12#include <linux/slab.h>
13#include <linux/highmem.h>
14#include <linux/delay.h>
15#include <linux/platform_device.h>
16#include <linux/workqueue.h>
17#include <linux/mmc/host.h>
18#include <linux/mmc/mmc.h>
19#include <linux/mmc/sd.h>
20#include <linux/mmc/sdio.h>
21#include <linux/mmc/card.h>
22#include <linux/rtsx_pci.h>
23#include <asm/unaligned.h>
24#include <linux/pm_runtime.h>
25
26struct realtek_pci_sdmmc {
27 struct platform_device *pdev;
28 struct rtsx_pcr *pcr;
29 struct mmc_host *mmc;
30 struct mmc_request *mrq;
31#define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq"
32
33 struct work_struct work;
34 struct mutex host_mutex;
35
36 u8 ssc_depth;
37 unsigned int clock;
38 bool vpclk;
39 bool double_clk;
40 bool eject;
41 bool initial_mode;
42 int prev_power_state;
43 int sg_count;
44 s32 cookie;
45 int cookie_sg_count;
46 bool using_cookie;
47};
48
49static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios);
50
51static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
52{
53 return &(host->pdev->dev);
54}
55
56static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
57{
58 rtsx_pci_write_register(host->pcr, CARD_STOP,
59 SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
60}
61
62#ifdef DEBUG
63static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
64{
65 u16 len = end - start + 1;
66 int i;
67 u8 data[8];
68
69 for (i = 0; i < len; i += 8) {
70 int j;
71 int n = min(8, len - i);
72
73 memset(&data, 0, sizeof(data));
74 for (j = 0; j < n; j++)
75 rtsx_pci_read_register(host->pcr, start + i + j,
76 data + j);
77 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
78 start + i, n, data);
79 }
80}
81
82static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
83{
84 dump_reg_range(host, 0xFDA0, 0xFDB3);
85 dump_reg_range(host, 0xFD52, 0xFD69);
86}
87#else
88#define sd_print_debug_regs(host)
89#endif /* DEBUG */
90
91static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host)
92{
93 return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
94}
95
96static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
97{
98 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
99 SD_CMD_START | cmd->opcode);
100 rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
101}
102
103static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
104{
105 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
106 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
107 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
108 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
109}
110
111static int sd_response_type(struct mmc_command *cmd)
112{
113 switch (mmc_resp_type(cmd)) {
114 case MMC_RSP_NONE:
115 return SD_RSP_TYPE_R0;
116 case MMC_RSP_R1:
117 return SD_RSP_TYPE_R1;
118 case MMC_RSP_R1_NO_CRC:
119 return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
120 case MMC_RSP_R1B:
121 return SD_RSP_TYPE_R1b;
122 case MMC_RSP_R2:
123 return SD_RSP_TYPE_R2;
124 case MMC_RSP_R3:
125 return SD_RSP_TYPE_R3;
126 default:
127 return -EINVAL;
128 }
129}
130
131static int sd_status_index(int resp_type)
132{
133 if (resp_type == SD_RSP_TYPE_R0)
134 return 0;
135 else if (resp_type == SD_RSP_TYPE_R2)
136 return 16;
137
138 return 5;
139}
140/*
141 * sd_pre_dma_transfer - do dma_map_sg() or using cookie
142 *
143 * @pre: if called in pre_req()
144 * return:
145 * 0 - do dma_map_sg()
146 * 1 - using cookie
147 */
148static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
149 struct mmc_data *data, bool pre)
150{
151 struct rtsx_pcr *pcr = host->pcr;
152 int read = data->flags & MMC_DATA_READ;
153 int count = 0;
154 int using_cookie = 0;
155
156 if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
157 dev_err(sdmmc_dev(host),
158 "error: data->host_cookie = %d, host->cookie = %d\n",
159 data->host_cookie, host->cookie);
160 data->host_cookie = 0;
161 }
162
163 if (pre || data->host_cookie != host->cookie) {
164 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
165 } else {
166 count = host->cookie_sg_count;
167 using_cookie = 1;
168 }
169
170 if (pre) {
171 host->cookie_sg_count = count;
172 if (++host->cookie < 0)
173 host->cookie = 1;
174 data->host_cookie = host->cookie;
175 } else {
176 host->sg_count = count;
177 }
178
179 return using_cookie;
180}
181
182static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
183{
184 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
185 struct mmc_data *data = mrq->data;
186
187 if (data->host_cookie) {
188 dev_err(sdmmc_dev(host),
189 "error: reset data->host_cookie = %d\n",
190 data->host_cookie);
191 data->host_cookie = 0;
192 }
193
194 sd_pre_dma_transfer(host, data, true);
195 dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
196}
197
198static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
199 int err)
200{
201 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
202 struct rtsx_pcr *pcr = host->pcr;
203 struct mmc_data *data = mrq->data;
204 int read = data->flags & MMC_DATA_READ;
205
206 rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
207 data->host_cookie = 0;
208}
209
210static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
211 struct mmc_command *cmd)
212{
213 struct rtsx_pcr *pcr = host->pcr;
214 u8 cmd_idx = (u8)cmd->opcode;
215 u32 arg = cmd->arg;
216 int err = 0;
217 int timeout = 100;
218 int i;
219 u8 *ptr;
220 int rsp_type;
221 int stat_idx;
222 bool clock_toggled = false;
223
224 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
225 __func__, cmd_idx, arg);
226
227 rsp_type = sd_response_type(cmd);
228 if (rsp_type < 0)
229 goto out;
230
231 stat_idx = sd_status_index(rsp_type);
232
233 if (rsp_type == SD_RSP_TYPE_R1b)
234 timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000;
235
236 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
237 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
238 0xFF, SD_CLK_TOGGLE_EN);
239 if (err < 0)
240 goto out;
241
242 clock_toggled = true;
243 }
244
245 rtsx_pci_init_cmd(pcr);
246 sd_cmd_set_sd_cmd(pcr, cmd);
247 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
248 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
249 0x01, PINGPONG_BUFFER);
250 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
251 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
252 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
253 SD_TRANSFER_END | SD_STAT_IDLE,
254 SD_TRANSFER_END | SD_STAT_IDLE);
255
256 if (rsp_type == SD_RSP_TYPE_R2) {
257 /* Read data from ping-pong buffer */
258 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
259 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
260 } else if (rsp_type != SD_RSP_TYPE_R0) {
261 /* Read data from SD_CMDx registers */
262 for (i = SD_CMD0; i <= SD_CMD4; i++)
263 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
264 }
265
266 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
267
268 err = rtsx_pci_send_cmd(pcr, timeout);
269 if (err < 0) {
270 sd_print_debug_regs(host);
271 sd_clear_error(host);
272 dev_dbg(sdmmc_dev(host),
273 "rtsx_pci_send_cmd error (err = %d)\n", err);
274 goto out;
275 }
276
277 if (rsp_type == SD_RSP_TYPE_R0) {
278 err = 0;
279 goto out;
280 }
281
282 /* Eliminate returned value of CHECK_REG_CMD */
283 ptr = rtsx_pci_get_cmd_data(pcr) + 1;
284
285 /* Check (Start,Transmission) bit of Response */
286 if ((ptr[0] & 0xC0) != 0) {
287 err = -EILSEQ;
288 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
289 goto out;
290 }
291
292 /* Check CRC7 */
293 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
294 if (ptr[stat_idx] & SD_CRC7_ERR) {
295 err = -EILSEQ;
296 dev_dbg(sdmmc_dev(host), "CRC7 error\n");
297 goto out;
298 }
299 }
300
301 if (rsp_type == SD_RSP_TYPE_R2) {
302 /*
303 * The controller offloads the last byte {CRC-7, end bit 1'b1}
304 * of response type R2. Assign dummy CRC, 0, and end bit to the
305 * byte(ptr[16], goes into the LSB of resp[3] later).
306 */
307 ptr[16] = 1;
308
309 for (i = 0; i < 4; i++) {
310 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
311 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
312 i, cmd->resp[i]);
313 }
314 } else {
315 cmd->resp[0] = get_unaligned_be32(ptr + 1);
316 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
317 cmd->resp[0]);
318 }
319
320out:
321 cmd->error = err;
322
323 if (err && clock_toggled)
324 rtsx_pci_write_register(pcr, SD_BUS_STAT,
325 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
326}
327
328static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd,
329 u16 byte_cnt, u8 *buf, int buf_len, int timeout)
330{
331 struct rtsx_pcr *pcr = host->pcr;
332 int err;
333 u8 trans_mode;
334
335 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
336 __func__, cmd->opcode, cmd->arg);
337
338 if (!buf)
339 buf_len = 0;
340
341 if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
342 trans_mode = SD_TM_AUTO_TUNING;
343 else
344 trans_mode = SD_TM_NORMAL_READ;
345
346 rtsx_pci_init_cmd(pcr);
347 sd_cmd_set_sd_cmd(pcr, cmd);
348 sd_cmd_set_data_len(pcr, 1, byte_cnt);
349 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
350 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
351 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
352 if (trans_mode != SD_TM_AUTO_TUNING)
353 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
354 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
355
356 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
357 0xFF, trans_mode | SD_TRANSFER_START);
358 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
359 SD_TRANSFER_END, SD_TRANSFER_END);
360
361 err = rtsx_pci_send_cmd(pcr, timeout);
362 if (err < 0) {
363 sd_print_debug_regs(host);
364 dev_dbg(sdmmc_dev(host),
365 "rtsx_pci_send_cmd fail (err = %d)\n", err);
366 return err;
367 }
368
369 if (buf && buf_len) {
370 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
371 if (err < 0) {
372 dev_dbg(sdmmc_dev(host),
373 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
374 return err;
375 }
376 }
377
378 return 0;
379}
380
381static int sd_write_data(struct realtek_pci_sdmmc *host,
382 struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len,
383 int timeout)
384{
385 struct rtsx_pcr *pcr = host->pcr;
386 int err;
387
388 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
389 __func__, cmd->opcode, cmd->arg);
390
391 if (!buf)
392 buf_len = 0;
393
394 sd_send_cmd_get_rsp(host, cmd);
395 if (cmd->error)
396 return cmd->error;
397
398 if (buf && buf_len) {
399 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
400 if (err < 0) {
401 dev_dbg(sdmmc_dev(host),
402 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
403 return err;
404 }
405 }
406
407 rtsx_pci_init_cmd(pcr);
408 sd_cmd_set_data_len(pcr, 1, byte_cnt);
409 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
410 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
411 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0);
412 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
413 SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
414 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
415 SD_TRANSFER_END, SD_TRANSFER_END);
416
417 err = rtsx_pci_send_cmd(pcr, timeout);
418 if (err < 0) {
419 sd_print_debug_regs(host);
420 dev_dbg(sdmmc_dev(host),
421 "rtsx_pci_send_cmd fail (err = %d)\n", err);
422 return err;
423 }
424
425 return 0;
426}
427
428static int sd_read_long_data(struct realtek_pci_sdmmc *host,
429 struct mmc_request *mrq)
430{
431 struct rtsx_pcr *pcr = host->pcr;
432 struct mmc_host *mmc = host->mmc;
433 struct mmc_card *card = mmc->card;
434 struct mmc_command *cmd = mrq->cmd;
435 struct mmc_data *data = mrq->data;
436 int uhs = mmc_card_uhs(card);
437 u8 cfg2 = 0;
438 int err;
439 int resp_type;
440 size_t data_len = data->blksz * data->blocks;
441
442 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
443 __func__, cmd->opcode, cmd->arg);
444
445 resp_type = sd_response_type(cmd);
446 if (resp_type < 0)
447 return resp_type;
448
449 if (!uhs)
450 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
451
452 rtsx_pci_init_cmd(pcr);
453 sd_cmd_set_sd_cmd(pcr, cmd);
454 sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
455 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
456 DMA_DONE_INT, DMA_DONE_INT);
457 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
458 0xFF, (u8)(data_len >> 24));
459 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
460 0xFF, (u8)(data_len >> 16));
461 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
462 0xFF, (u8)(data_len >> 8));
463 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
464 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
465 0x03 | DMA_PACK_SIZE_MASK,
466 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
467 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
468 0x01, RING_BUFFER);
469 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
470 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
471 SD_TRANSFER_START | SD_TM_AUTO_READ_2);
472 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
473 SD_TRANSFER_END, SD_TRANSFER_END);
474 rtsx_pci_send_cmd_no_wait(pcr);
475
476 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
477 if (err < 0) {
478 sd_print_debug_regs(host);
479 sd_clear_error(host);
480 return err;
481 }
482
483 return 0;
484}
485
486static int sd_write_long_data(struct realtek_pci_sdmmc *host,
487 struct mmc_request *mrq)
488{
489 struct rtsx_pcr *pcr = host->pcr;
490 struct mmc_host *mmc = host->mmc;
491 struct mmc_card *card = mmc->card;
492 struct mmc_command *cmd = mrq->cmd;
493 struct mmc_data *data = mrq->data;
494 int uhs = mmc_card_uhs(card);
495 u8 cfg2;
496 int err;
497 size_t data_len = data->blksz * data->blocks;
498
499 sd_send_cmd_get_rsp(host, cmd);
500 if (cmd->error)
501 return cmd->error;
502
503 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
504 __func__, cmd->opcode, cmd->arg);
505
506 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
507 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
508
509 if (!uhs)
510 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
511
512 rtsx_pci_init_cmd(pcr);
513 sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
514 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
515 DMA_DONE_INT, DMA_DONE_INT);
516 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
517 0xFF, (u8)(data_len >> 24));
518 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
519 0xFF, (u8)(data_len >> 16));
520 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
521 0xFF, (u8)(data_len >> 8));
522 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
523 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
524 0x03 | DMA_PACK_SIZE_MASK,
525 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
526 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
527 0x01, RING_BUFFER);
528 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
529 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
530 SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
531 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
532 SD_TRANSFER_END, SD_TRANSFER_END);
533 rtsx_pci_send_cmd_no_wait(pcr);
534 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
535 if (err < 0) {
536 sd_clear_error(host);
537 return err;
538 }
539
540 return 0;
541}
542
543static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
544{
545 rtsx_pci_write_register(host->pcr, SD_CFG1,
546 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
547}
548
549static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
550{
551 rtsx_pci_write_register(host->pcr, SD_CFG1,
552 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
553}
554
555static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
556{
557 struct mmc_data *data = mrq->data;
558 int err;
559
560 if (host->sg_count < 0) {
561 data->error = host->sg_count;
562 dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n",
563 __func__, host->sg_count);
564 return data->error;
565 }
566
567 if (data->flags & MMC_DATA_READ) {
568 if (host->initial_mode)
569 sd_disable_initial_mode(host);
570
571 err = sd_read_long_data(host, mrq);
572
573 if (host->initial_mode)
574 sd_enable_initial_mode(host);
575
576 return err;
577 }
578
579 return sd_write_long_data(host, mrq);
580}
581
582static void sd_normal_rw(struct realtek_pci_sdmmc *host,
583 struct mmc_request *mrq)
584{
585 struct mmc_command *cmd = mrq->cmd;
586 struct mmc_data *data = mrq->data;
587 u8 *buf;
588
589 buf = kzalloc(data->blksz, GFP_NOIO);
590 if (!buf) {
591 cmd->error = -ENOMEM;
592 return;
593 }
594
595 if (data->flags & MMC_DATA_READ) {
596 if (host->initial_mode)
597 sd_disable_initial_mode(host);
598
599 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
600 data->blksz, 200);
601
602 if (host->initial_mode)
603 sd_enable_initial_mode(host);
604
605 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
606 } else {
607 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
608
609 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
610 data->blksz, 200);
611 }
612
613 kfree(buf);
614}
615
616static int sd_change_phase(struct realtek_pci_sdmmc *host,
617 u8 sample_point, bool rx)
618{
619 struct rtsx_pcr *pcr = host->pcr;
620 u16 SD_VP_CTL = 0;
621 dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
622 __func__, rx ? "RX" : "TX", sample_point);
623
624 rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
625 if (rx) {
626 SD_VP_CTL = SD_VPRX_CTL;
627 rtsx_pci_write_register(pcr, SD_VPRX_CTL,
628 PHASE_SELECT_MASK, sample_point);
629 } else {
630 SD_VP_CTL = SD_VPTX_CTL;
631 rtsx_pci_write_register(pcr, SD_VPTX_CTL,
632 PHASE_SELECT_MASK, sample_point);
633 }
634 rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 0);
635 rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET,
636 PHASE_NOT_RESET);
637 rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);
638 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
639
640 return 0;
641}
642
643static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
644{
645 bit %= RTSX_PHASE_MAX;
646 return phase_map & (1 << bit);
647}
648
649static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
650{
651 int i;
652
653 for (i = 0; i < RTSX_PHASE_MAX; i++) {
654 if (test_phase_bit(phase_map, start_bit + i) == 0)
655 return i;
656 }
657 return RTSX_PHASE_MAX;
658}
659
660static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
661{
662 int start = 0, len = 0;
663 int start_final = 0, len_final = 0;
664 u8 final_phase = 0xFF;
665
666 if (phase_map == 0) {
667 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
668 return final_phase;
669 }
670
671 while (start < RTSX_PHASE_MAX) {
672 len = sd_get_phase_len(phase_map, start);
673 if (len_final < len) {
674 start_final = start;
675 len_final = len;
676 }
677 start += len ? len : 1;
678 }
679
680 final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
681 dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
682 phase_map, len_final, final_phase);
683
684 return final_phase;
685}
686
687static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
688{
689 int i;
690 u8 val = 0;
691
692 for (i = 0; i < 100; i++) {
693 rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
694 if (val & SD_DATA_IDLE)
695 return;
696
697 udelay(100);
698 }
699}
700
701static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
702 u8 opcode, u8 sample_point)
703{
704 int err;
705 struct mmc_command cmd = {};
706 struct rtsx_pcr *pcr = host->pcr;
707
708 sd_change_phase(host, sample_point, true);
709
710 rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
711 SD_RSP_80CLK_TIMEOUT_EN);
712
713 cmd.opcode = opcode;
714 err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
715 if (err < 0) {
716 /* Wait till SD DATA IDLE */
717 sd_wait_data_idle(host);
718 sd_clear_error(host);
719 rtsx_pci_write_register(pcr, SD_CFG3,
720 SD_RSP_80CLK_TIMEOUT_EN, 0);
721 return err;
722 }
723
724 rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
725 return 0;
726}
727
728static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
729 u8 opcode, u32 *phase_map)
730{
731 int err, i;
732 u32 raw_phase_map = 0;
733
734 for (i = 0; i < RTSX_PHASE_MAX; i++) {
735 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
736 if (err == 0)
737 raw_phase_map |= 1 << i;
738 }
739
740 if (phase_map)
741 *phase_map = raw_phase_map;
742
743 return 0;
744}
745
746static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
747{
748 int err, i;
749 u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
750 u8 final_phase;
751
752 for (i = 0; i < RX_TUNING_CNT; i++) {
753 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
754 if (err < 0)
755 return err;
756
757 if (raw_phase_map[i] == 0)
758 break;
759 }
760
761 phase_map = 0xFFFFFFFF;
762 for (i = 0; i < RX_TUNING_CNT; i++) {
763 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
764 i, raw_phase_map[i]);
765 phase_map &= raw_phase_map[i];
766 }
767 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
768
769 if (phase_map) {
770 final_phase = sd_search_final_phase(host, phase_map);
771 if (final_phase == 0xFF)
772 return -EINVAL;
773
774 err = sd_change_phase(host, final_phase, true);
775 if (err < 0)
776 return err;
777 } else {
778 return -EINVAL;
779 }
780
781 return 0;
782}
783
784static inline int sdio_extblock_cmd(struct mmc_command *cmd,
785 struct mmc_data *data)
786{
787 return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512);
788}
789
790static inline int sd_rw_cmd(struct mmc_command *cmd)
791{
792 return mmc_op_multi(cmd->opcode) ||
793 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
794 (cmd->opcode == MMC_WRITE_BLOCK);
795}
796
797static void sd_request(struct work_struct *work)
798{
799 struct realtek_pci_sdmmc *host = container_of(work,
800 struct realtek_pci_sdmmc, work);
801 struct rtsx_pcr *pcr = host->pcr;
802
803 struct mmc_host *mmc = host->mmc;
804 struct mmc_request *mrq = host->mrq;
805 struct mmc_command *cmd = mrq->cmd;
806 struct mmc_data *data = mrq->data;
807
808 unsigned int data_size = 0;
809 int err;
810
811 if (host->eject || !sd_get_cd_int(host)) {
812 cmd->error = -ENOMEDIUM;
813 goto finish;
814 }
815
816 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
817 if (err) {
818 cmd->error = err;
819 goto finish;
820 }
821
822 mutex_lock(&pcr->pcr_mutex);
823
824 rtsx_pci_start_run(pcr);
825
826 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
827 host->initial_mode, host->double_clk, host->vpclk);
828 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
829 rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
830 CARD_SHARE_MASK, CARD_SHARE_48_SD);
831
832 mutex_lock(&host->host_mutex);
833 host->mrq = mrq;
834 mutex_unlock(&host->host_mutex);
835
836 if (mrq->data)
837 data_size = data->blocks * data->blksz;
838
839 if (!data_size) {
840 sd_send_cmd_get_rsp(host, cmd);
841 } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) {
842 cmd->error = sd_rw_multi(host, mrq);
843 if (!host->using_cookie)
844 sdmmc_post_req(host->mmc, host->mrq, 0);
845
846 if (mmc_op_multi(cmd->opcode) && mrq->stop)
847 sd_send_cmd_get_rsp(host, mrq->stop);
848 } else {
849 sd_normal_rw(host, mrq);
850 }
851
852 if (mrq->data) {
853 if (cmd->error || data->error)
854 data->bytes_xfered = 0;
855 else
856 data->bytes_xfered = data->blocks * data->blksz;
857 }
858
859 mutex_unlock(&pcr->pcr_mutex);
860
861finish:
862 if (cmd->error) {
863 dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n",
864 cmd->opcode, cmd->arg, cmd->error);
865 }
866
867 mutex_lock(&host->host_mutex);
868 host->mrq = NULL;
869 mutex_unlock(&host->host_mutex);
870
871 mmc_request_done(mmc, mrq);
872}
873
874static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
875{
876 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
877 struct mmc_data *data = mrq->data;
878
879 mutex_lock(&host->host_mutex);
880 host->mrq = mrq;
881 mutex_unlock(&host->host_mutex);
882
883 if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
884 host->using_cookie = sd_pre_dma_transfer(host, data, false);
885
886 schedule_work(&host->work);
887}
888
889static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
890 unsigned char bus_width)
891{
892 int err = 0;
893 u8 width[] = {
894 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
895 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
896 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
897 };
898
899 if (bus_width <= MMC_BUS_WIDTH_8)
900 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
901 0x03, width[bus_width]);
902
903 return err;
904}
905
906static int sd_power_on(struct realtek_pci_sdmmc *host, unsigned char power_mode)
907{
908 struct rtsx_pcr *pcr = host->pcr;
909 struct mmc_host *mmc = host->mmc;
910 int err;
911 u32 val;
912 u8 test_mode;
913
914 if (host->prev_power_state == MMC_POWER_ON)
915 return 0;
916
917 if (host->prev_power_state == MMC_POWER_UP) {
918 rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0);
919 goto finish;
920 }
921
922 msleep(100);
923
924 rtsx_pci_init_cmd(pcr);
925 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
926 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
927 CARD_SHARE_MASK, CARD_SHARE_48_SD);
928 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
929 SD_CLK_EN, SD_CLK_EN);
930 err = rtsx_pci_send_cmd(pcr, 100);
931 if (err < 0)
932 return err;
933
934 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
935 if (err < 0)
936 return err;
937
938 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
939 if (err < 0)
940 return err;
941
942 mdelay(1);
943
944 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
945 if (err < 0)
946 return err;
947
948 /* send at least 74 clocks */
949 rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN);
950
951 if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5264)) {
952 /*
953 * If test mode is set switch to SD Express mandatorily,
954 * this is only for factory testing.
955 */
956 rtsx_pci_read_register(pcr, RTS5261_FW_CFG_INFO0, &test_mode);
957 if (test_mode & RTS5261_FW_EXPRESS_TEST_MASK) {
958 sdmmc_init_sd_express(mmc, NULL);
959 return 0;
960 }
961 if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS)
962 mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V;
963 /*
964 * HW read wp status when resuming from S3/S4,
965 * and then picks SD legacy interface if it's set
966 * in read-only mode.
967 */
968 val = rtsx_pci_readl(pcr, RTSX_BIPR);
969 if (val & SD_WRITE_PROTECT) {
970 pcr->extra_caps &= ~EXTRA_CAPS_SD_EXPRESS;
971 mmc->caps2 &= ~(MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V);
972 }
973 }
974
975finish:
976 host->prev_power_state = power_mode;
977 return 0;
978}
979
980static int sd_power_off(struct realtek_pci_sdmmc *host)
981{
982 struct rtsx_pcr *pcr = host->pcr;
983 int err;
984
985 host->prev_power_state = MMC_POWER_OFF;
986
987 rtsx_pci_init_cmd(pcr);
988
989 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
990 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
991
992 err = rtsx_pci_send_cmd(pcr, 100);
993 if (err < 0)
994 return err;
995
996 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
997 if (err < 0)
998 return err;
999
1000 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
1001}
1002
1003static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
1004 unsigned char power_mode)
1005{
1006 int err;
1007
1008 if (power_mode == MMC_POWER_OFF)
1009 err = sd_power_off(host);
1010 else
1011 err = sd_power_on(host, power_mode);
1012
1013 return err;
1014}
1015
1016static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
1017{
1018 struct rtsx_pcr *pcr = host->pcr;
1019 int err = 0;
1020
1021 rtsx_pci_init_cmd(pcr);
1022
1023 switch (timing) {
1024 case MMC_TIMING_UHS_SDR104:
1025 case MMC_TIMING_UHS_SDR50:
1026 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1027 0x0C | SD_ASYNC_FIFO_NOT_RST,
1028 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
1029 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1030 CLK_LOW_FREQ, CLK_LOW_FREQ);
1031 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1032 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1033 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1034 break;
1035
1036 case MMC_TIMING_MMC_DDR52:
1037 case MMC_TIMING_UHS_DDR50:
1038 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1039 0x0C | SD_ASYNC_FIFO_NOT_RST,
1040 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
1041 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1042 CLK_LOW_FREQ, CLK_LOW_FREQ);
1043 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1044 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
1045 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1046 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1047 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
1048 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1049 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
1050 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
1051 break;
1052
1053 case MMC_TIMING_MMC_HS:
1054 case MMC_TIMING_SD_HS:
1055 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1056 0x0C, SD_20_MODE);
1057 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1058 CLK_LOW_FREQ, CLK_LOW_FREQ);
1059 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1060 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1061 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1062 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1063 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1064 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1065 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1066 break;
1067
1068 default:
1069 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1070 SD_CFG1, 0x0C, SD_20_MODE);
1071 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1072 CLK_LOW_FREQ, CLK_LOW_FREQ);
1073 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1074 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1075 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1076 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1077 SD_PUSH_POINT_CTL, 0xFF, 0);
1078 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1079 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1080 break;
1081 }
1082
1083 err = rtsx_pci_send_cmd(pcr, 100);
1084
1085 return err;
1086}
1087
1088static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1089{
1090 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1091 struct rtsx_pcr *pcr = host->pcr;
1092
1093 if (host->eject)
1094 return;
1095
1096 if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1097 return;
1098
1099 mutex_lock(&pcr->pcr_mutex);
1100
1101 rtsx_pci_start_run(pcr);
1102
1103 sd_set_bus_width(host, ios->bus_width);
1104 sd_set_power_mode(host, ios->power_mode);
1105 sd_set_timing(host, ios->timing);
1106
1107 host->vpclk = false;
1108 host->double_clk = true;
1109
1110 switch (ios->timing) {
1111 case MMC_TIMING_UHS_SDR104:
1112 case MMC_TIMING_UHS_SDR50:
1113 host->ssc_depth = RTSX_SSC_DEPTH_2M;
1114 host->vpclk = true;
1115 host->double_clk = false;
1116 break;
1117 case MMC_TIMING_MMC_DDR52:
1118 case MMC_TIMING_UHS_DDR50:
1119 case MMC_TIMING_UHS_SDR25:
1120 host->ssc_depth = RTSX_SSC_DEPTH_1M;
1121 break;
1122 default:
1123 host->ssc_depth = RTSX_SSC_DEPTH_500K;
1124 break;
1125 }
1126
1127 host->initial_mode = (ios->clock <= 1000000) ? true : false;
1128
1129 host->clock = ios->clock;
1130 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1131 host->initial_mode, host->double_clk, host->vpclk);
1132
1133 mutex_unlock(&pcr->pcr_mutex);
1134}
1135
1136static int sdmmc_get_ro(struct mmc_host *mmc)
1137{
1138 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1139 struct rtsx_pcr *pcr = host->pcr;
1140 int ro = 0;
1141 u32 val;
1142
1143 if (host->eject)
1144 return -ENOMEDIUM;
1145
1146 mutex_lock(&pcr->pcr_mutex);
1147
1148 rtsx_pci_start_run(pcr);
1149
1150 /* Check SD mechanical write-protect switch */
1151 val = rtsx_pci_readl(pcr, RTSX_BIPR);
1152 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1153 if (val & SD_WRITE_PROTECT)
1154 ro = 1;
1155
1156 mutex_unlock(&pcr->pcr_mutex);
1157
1158 return ro;
1159}
1160
1161static int sdmmc_get_cd(struct mmc_host *mmc)
1162{
1163 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1164 struct rtsx_pcr *pcr = host->pcr;
1165 int cd = 0;
1166 u32 val;
1167
1168 if (host->eject)
1169 return cd;
1170
1171 mutex_lock(&pcr->pcr_mutex);
1172
1173 rtsx_pci_start_run(pcr);
1174
1175 /* Check SD card detect */
1176 val = rtsx_pci_card_exist(pcr);
1177 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1178 if (val & SD_EXIST)
1179 cd = 1;
1180
1181 mutex_unlock(&pcr->pcr_mutex);
1182
1183 return cd;
1184}
1185
1186static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1187{
1188 struct rtsx_pcr *pcr = host->pcr;
1189 int err;
1190 u8 stat;
1191
1192 /* Reference to Signal Voltage Switch Sequence in SD spec.
1193 * Wait for a period of time so that the card can drive SD_CMD and
1194 * SD_DAT[3:0] to low after sending back CMD11 response.
1195 */
1196 mdelay(1);
1197
1198 /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1199 * If either one of SD_CMD,SD_DAT[3:0] is not low,
1200 * abort the voltage switch sequence;
1201 */
1202 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1203 if (err < 0)
1204 return err;
1205
1206 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1207 SD_DAT1_STATUS | SD_DAT0_STATUS))
1208 return -EINVAL;
1209
1210 /* Stop toggle SD clock */
1211 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1212 0xFF, SD_CLK_FORCE_STOP);
1213 if (err < 0)
1214 return err;
1215
1216 return 0;
1217}
1218
1219static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1220{
1221 struct rtsx_pcr *pcr = host->pcr;
1222 int err;
1223 u8 stat, mask, val;
1224
1225 /* Wait 1.8V output of voltage regulator in card stable */
1226 msleep(50);
1227
1228 /* Toggle SD clock again */
1229 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1230 if (err < 0)
1231 return err;
1232
1233 /* Wait for a period of time so that the card can drive
1234 * SD_DAT[3:0] to high at 1.8V
1235 */
1236 msleep(20);
1237
1238 /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1239 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1240 if (err < 0)
1241 return err;
1242
1243 mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1244 SD_DAT1_STATUS | SD_DAT0_STATUS;
1245 val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1246 SD_DAT1_STATUS | SD_DAT0_STATUS;
1247 if ((stat & mask) != val) {
1248 dev_dbg(sdmmc_dev(host),
1249 "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1250 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1251 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1252 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1253 return -EINVAL;
1254 }
1255
1256 return 0;
1257}
1258
1259static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1260{
1261 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1262 struct rtsx_pcr *pcr = host->pcr;
1263 int err = 0;
1264 u8 voltage;
1265
1266 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1267 __func__, ios->signal_voltage);
1268
1269 if (host->eject)
1270 return -ENOMEDIUM;
1271
1272 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1273 if (err)
1274 return err;
1275
1276 mutex_lock(&pcr->pcr_mutex);
1277
1278 rtsx_pci_start_run(pcr);
1279
1280 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1281 voltage = OUTPUT_3V3;
1282 else
1283 voltage = OUTPUT_1V8;
1284
1285 if (voltage == OUTPUT_1V8) {
1286 err = sd_wait_voltage_stable_1(host);
1287 if (err < 0)
1288 goto out;
1289 }
1290
1291 err = rtsx_pci_switch_output_voltage(pcr, voltage);
1292 if (err < 0)
1293 goto out;
1294
1295 if (voltage == OUTPUT_1V8) {
1296 err = sd_wait_voltage_stable_2(host);
1297 if (err < 0)
1298 goto out;
1299 }
1300
1301out:
1302 /* Stop toggle SD clock in idle */
1303 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1304 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1305
1306 mutex_unlock(&pcr->pcr_mutex);
1307
1308 return err;
1309}
1310
1311static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1312{
1313 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1314 struct rtsx_pcr *pcr = host->pcr;
1315 int err = 0;
1316
1317 if (host->eject)
1318 return -ENOMEDIUM;
1319
1320 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1321 if (err)
1322 return err;
1323
1324 mutex_lock(&pcr->pcr_mutex);
1325
1326 rtsx_pci_start_run(pcr);
1327
1328 /* Set initial TX phase */
1329 switch (mmc->ios.timing) {
1330 case MMC_TIMING_UHS_SDR104:
1331 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1332 break;
1333
1334 case MMC_TIMING_UHS_SDR50:
1335 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1336 break;
1337
1338 case MMC_TIMING_UHS_DDR50:
1339 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1340 break;
1341
1342 default:
1343 err = 0;
1344 }
1345
1346 if (err)
1347 goto out;
1348
1349 /* Tuning RX phase */
1350 if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1351 (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1352 err = sd_tuning_rx(host, opcode);
1353 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1354 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1355
1356out:
1357 mutex_unlock(&pcr->pcr_mutex);
1358
1359 return err;
1360}
1361
1362static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios)
1363{
1364 u32 relink_time;
1365 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1366 struct rtsx_pcr *pcr = host->pcr;
1367
1368 if (PCI_PID(pcr) == PID_5264) {
1369 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL2,
1370 PCI_EXP_LNKCTL2_TLS, PCI_EXP_LNKCTL2_TLS_2_5GT);
1371 pci_write_config_byte(pcr->pci, 0x80e, 0x02);
1372 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL2,
1373 PCI_EXP_LNKCTL2_TLS, PCI_EXP_LNKCTL2_TLS_5_0GT);
1374 }
1375
1376 /* Set relink_time for changing to PCIe card */
1377 relink_time = 0x8FFF;
1378
1379 rtsx_pci_write_register(pcr, 0xFF01, 0xFF, relink_time);
1380 rtsx_pci_write_register(pcr, 0xFF02, 0xFF, relink_time >> 8);
1381 rtsx_pci_write_register(pcr, 0xFF03, 0x01, relink_time >> 16);
1382
1383 rtsx_pci_write_register(pcr, PETXCFG, 0x80, 0x80);
1384 rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
1385 RTS5261_LDO1_OCP_THD_MASK,
1386 pcr->option.sd_800mA_ocp_thd);
1387
1388 if (pcr->ops->disable_auto_blink)
1389 pcr->ops->disable_auto_blink(pcr);
1390
1391 if (PCI_PID(pcr) == PID_5264) {
1392 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG2,
1393 RTS5264_CHIP_RST_N_SEL, RTS5264_CHIP_RST_N_SEL);
1394 rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
1395 }
1396
1397 /* For PCIe/NVMe mode can't enter delink issue */
1398 pcr->hw_param.interrupt_en &= ~(SD_INT_EN);
1399 rtsx_pci_writel(pcr, RTSX_BIER, pcr->hw_param.interrupt_en);
1400
1401 rtsx_pci_write_register(pcr, RTS5260_AUTOLOAD_CFG4,
1402 RTS5261_AUX_CLK_16M_EN, RTS5261_AUX_CLK_16M_EN);
1403 rtsx_pci_write_register(pcr, RTS5261_FW_CFG0,
1404 RTS5261_FW_ENTER_EXPRESS, RTS5261_FW_ENTER_EXPRESS);
1405 rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
1406 RTS5261_MCU_CLOCK_GATING, RTS5261_MCU_CLOCK_GATING);
1407 rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
1408 RTS5261_MCU_BUS_SEL_MASK | RTS5261_MCU_CLOCK_SEL_MASK
1409 | RTS5261_DRIVER_ENABLE_FW,
1410 RTS5261_MCU_CLOCK_SEL_16M | RTS5261_DRIVER_ENABLE_FW);
1411 host->eject = true;
1412 return 0;
1413}
1414
1415static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1416 .pre_req = sdmmc_pre_req,
1417 .post_req = sdmmc_post_req,
1418 .request = sdmmc_request,
1419 .set_ios = sdmmc_set_ios,
1420 .get_ro = sdmmc_get_ro,
1421 .get_cd = sdmmc_get_cd,
1422 .start_signal_voltage_switch = sdmmc_switch_voltage,
1423 .execute_tuning = sdmmc_execute_tuning,
1424 .init_sd_express = sdmmc_init_sd_express,
1425};
1426
1427static void init_extra_caps(struct realtek_pci_sdmmc *host)
1428{
1429 struct mmc_host *mmc = host->mmc;
1430 struct rtsx_pcr *pcr = host->pcr;
1431
1432 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1433
1434 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1435 mmc->caps |= MMC_CAP_UHS_SDR50;
1436 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1437 mmc->caps |= MMC_CAP_UHS_SDR104;
1438 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1439 mmc->caps |= MMC_CAP_UHS_DDR50;
1440 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1441 mmc->caps |= MMC_CAP_1_8V_DDR;
1442 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1443 mmc->caps |= MMC_CAP_8_BIT_DATA;
1444 if (pcr->extra_caps & EXTRA_CAPS_NO_MMC)
1445 mmc->caps2 |= MMC_CAP2_NO_MMC;
1446 if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS)
1447 mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V;
1448}
1449
1450static void realtek_init_host(struct realtek_pci_sdmmc *host)
1451{
1452 struct mmc_host *mmc = host->mmc;
1453 struct rtsx_pcr *pcr = host->pcr;
1454
1455 mmc->f_min = 250000;
1456 mmc->f_max = 208000000;
1457 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1458 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1459 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1460 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
1461 if (pcr->rtd3_en)
1462 mmc->caps = mmc->caps | MMC_CAP_AGGRESSIVE_PM;
1463 mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE |
1464 MMC_CAP2_NO_SDIO;
1465 mmc->max_current_330 = 400;
1466 mmc->max_current_180 = 800;
1467 mmc->ops = &realtek_pci_sdmmc_ops;
1468
1469 init_extra_caps(host);
1470
1471 mmc->max_segs = 256;
1472 mmc->max_seg_size = 65536;
1473 mmc->max_blk_size = 512;
1474 mmc->max_blk_count = 65535;
1475 mmc->max_req_size = 524288;
1476}
1477
1478static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1479{
1480 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1481
1482 host->cookie = -1;
1483 mmc_detect_change(host->mmc, 0);
1484}
1485
1486static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1487{
1488 struct mmc_host *mmc;
1489 struct realtek_pci_sdmmc *host;
1490 struct rtsx_pcr *pcr;
1491 struct pcr_handle *handle = pdev->dev.platform_data;
1492 int ret;
1493
1494 if (!handle)
1495 return -ENXIO;
1496
1497 pcr = handle->pcr;
1498 if (!pcr)
1499 return -ENXIO;
1500
1501 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1502
1503 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1504 if (!mmc)
1505 return -ENOMEM;
1506
1507 host = mmc_priv(mmc);
1508 host->pcr = pcr;
1509 mmc->ios.power_delay_ms = 5;
1510 host->mmc = mmc;
1511 host->pdev = pdev;
1512 host->cookie = -1;
1513 host->prev_power_state = MMC_POWER_OFF;
1514 INIT_WORK(&host->work, sd_request);
1515 platform_set_drvdata(pdev, host);
1516 pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1517 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1518
1519 mutex_init(&host->host_mutex);
1520
1521 realtek_init_host(host);
1522
1523 pm_runtime_no_callbacks(&pdev->dev);
1524 pm_runtime_set_active(&pdev->dev);
1525 pm_runtime_enable(&pdev->dev);
1526 pm_runtime_set_autosuspend_delay(&pdev->dev, 200);
1527 pm_runtime_mark_last_busy(&pdev->dev);
1528 pm_runtime_use_autosuspend(&pdev->dev);
1529
1530 ret = mmc_add_host(mmc);
1531 if (ret) {
1532 pm_runtime_dont_use_autosuspend(&pdev->dev);
1533 pm_runtime_disable(&pdev->dev);
1534 mmc_free_host(mmc);
1535 return ret;
1536 }
1537
1538 return 0;
1539}
1540
1541static void rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1542{
1543 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1544 struct rtsx_pcr *pcr;
1545 struct mmc_host *mmc;
1546
1547 pcr = host->pcr;
1548 pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1549 pcr->slots[RTSX_SD_CARD].card_event = NULL;
1550 mmc = host->mmc;
1551
1552 cancel_work_sync(&host->work);
1553
1554 mutex_lock(&host->host_mutex);
1555 if (host->mrq) {
1556 dev_dbg(&(pdev->dev),
1557 "%s: Controller removed during transfer\n",
1558 mmc_hostname(mmc));
1559
1560 rtsx_pci_complete_unfinished_transfer(pcr);
1561
1562 host->mrq->cmd->error = -ENOMEDIUM;
1563 if (host->mrq->stop)
1564 host->mrq->stop->error = -ENOMEDIUM;
1565 mmc_request_done(mmc, host->mrq);
1566 }
1567 mutex_unlock(&host->host_mutex);
1568
1569 mmc_remove_host(mmc);
1570 host->eject = true;
1571
1572 flush_work(&host->work);
1573
1574 pm_runtime_dont_use_autosuspend(&pdev->dev);
1575 pm_runtime_disable(&pdev->dev);
1576
1577 mmc_free_host(mmc);
1578
1579 dev_dbg(&(pdev->dev),
1580 ": Realtek PCI-E SDMMC controller has been removed\n");
1581}
1582
1583static const struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1584 {
1585 .name = DRV_NAME_RTSX_PCI_SDMMC,
1586 }, {
1587 /* sentinel */
1588 }
1589};
1590MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1591
1592static struct platform_driver rtsx_pci_sdmmc_driver = {
1593 .probe = rtsx_pci_sdmmc_drv_probe,
1594 .remove_new = rtsx_pci_sdmmc_drv_remove,
1595 .id_table = rtsx_pci_sdmmc_ids,
1596 .driver = {
1597 .name = DRV_NAME_RTSX_PCI_SDMMC,
1598 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1599 },
1600};
1601module_platform_driver(rtsx_pci_sdmmc_driver);
1602
1603MODULE_LICENSE("GPL");
1604MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1605MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/* Realtek PCI-Express SD/MMC Card Interface driver
3 *
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Wei WANG <wei_wang@realsil.com.cn>
8 */
9
10#include <linux/module.h>
11#include <linux/slab.h>
12#include <linux/highmem.h>
13#include <linux/delay.h>
14#include <linux/platform_device.h>
15#include <linux/workqueue.h>
16#include <linux/mmc/host.h>
17#include <linux/mmc/mmc.h>
18#include <linux/mmc/sd.h>
19#include <linux/mmc/sdio.h>
20#include <linux/mmc/card.h>
21#include <linux/rtsx_pci.h>
22#include <asm/unaligned.h>
23
24struct realtek_pci_sdmmc {
25 struct platform_device *pdev;
26 struct rtsx_pcr *pcr;
27 struct mmc_host *mmc;
28 struct mmc_request *mrq;
29#define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq"
30
31 struct work_struct work;
32 struct mutex host_mutex;
33
34 u8 ssc_depth;
35 unsigned int clock;
36 bool vpclk;
37 bool double_clk;
38 bool eject;
39 bool initial_mode;
40 int power_state;
41#define SDMMC_POWER_ON 1
42#define SDMMC_POWER_OFF 0
43
44 int sg_count;
45 s32 cookie;
46 int cookie_sg_count;
47 bool using_cookie;
48};
49
50static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
51{
52 return &(host->pdev->dev);
53}
54
55static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
56{
57 rtsx_pci_write_register(host->pcr, CARD_STOP,
58 SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
59}
60
61#ifdef DEBUG
62static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
63{
64 u16 len = end - start + 1;
65 int i;
66 u8 data[8];
67
68 for (i = 0; i < len; i += 8) {
69 int j;
70 int n = min(8, len - i);
71
72 memset(&data, 0, sizeof(data));
73 for (j = 0; j < n; j++)
74 rtsx_pci_read_register(host->pcr, start + i + j,
75 data + j);
76 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
77 start + i, n, data);
78 }
79}
80
81static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
82{
83 dump_reg_range(host, 0xFDA0, 0xFDB3);
84 dump_reg_range(host, 0xFD52, 0xFD69);
85}
86#else
87#define sd_print_debug_regs(host)
88#endif /* DEBUG */
89
90static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host)
91{
92 return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
93}
94
95static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
96{
97 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
98 SD_CMD_START | cmd->opcode);
99 rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
100}
101
102static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
103{
104 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
105 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
106 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
107 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
108}
109
110static int sd_response_type(struct mmc_command *cmd)
111{
112 switch (mmc_resp_type(cmd)) {
113 case MMC_RSP_NONE:
114 return SD_RSP_TYPE_R0;
115 case MMC_RSP_R1:
116 return SD_RSP_TYPE_R1;
117 case MMC_RSP_R1_NO_CRC:
118 return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
119 case MMC_RSP_R1B:
120 return SD_RSP_TYPE_R1b;
121 case MMC_RSP_R2:
122 return SD_RSP_TYPE_R2;
123 case MMC_RSP_R3:
124 return SD_RSP_TYPE_R3;
125 default:
126 return -EINVAL;
127 }
128}
129
130static int sd_status_index(int resp_type)
131{
132 if (resp_type == SD_RSP_TYPE_R0)
133 return 0;
134 else if (resp_type == SD_RSP_TYPE_R2)
135 return 16;
136
137 return 5;
138}
139/*
140 * sd_pre_dma_transfer - do dma_map_sg() or using cookie
141 *
142 * @pre: if called in pre_req()
143 * return:
144 * 0 - do dma_map_sg()
145 * 1 - using cookie
146 */
147static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
148 struct mmc_data *data, bool pre)
149{
150 struct rtsx_pcr *pcr = host->pcr;
151 int read = data->flags & MMC_DATA_READ;
152 int count = 0;
153 int using_cookie = 0;
154
155 if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
156 dev_err(sdmmc_dev(host),
157 "error: data->host_cookie = %d, host->cookie = %d\n",
158 data->host_cookie, host->cookie);
159 data->host_cookie = 0;
160 }
161
162 if (pre || data->host_cookie != host->cookie) {
163 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
164 } else {
165 count = host->cookie_sg_count;
166 using_cookie = 1;
167 }
168
169 if (pre) {
170 host->cookie_sg_count = count;
171 if (++host->cookie < 0)
172 host->cookie = 1;
173 data->host_cookie = host->cookie;
174 } else {
175 host->sg_count = count;
176 }
177
178 return using_cookie;
179}
180
181static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
182{
183 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
184 struct mmc_data *data = mrq->data;
185
186 if (data->host_cookie) {
187 dev_err(sdmmc_dev(host),
188 "error: reset data->host_cookie = %d\n",
189 data->host_cookie);
190 data->host_cookie = 0;
191 }
192
193 sd_pre_dma_transfer(host, data, true);
194 dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
195}
196
197static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
198 int err)
199{
200 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
201 struct rtsx_pcr *pcr = host->pcr;
202 struct mmc_data *data = mrq->data;
203 int read = data->flags & MMC_DATA_READ;
204
205 rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
206 data->host_cookie = 0;
207}
208
209static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
210 struct mmc_command *cmd)
211{
212 struct rtsx_pcr *pcr = host->pcr;
213 u8 cmd_idx = (u8)cmd->opcode;
214 u32 arg = cmd->arg;
215 int err = 0;
216 int timeout = 100;
217 int i;
218 u8 *ptr;
219 int rsp_type;
220 int stat_idx;
221 bool clock_toggled = false;
222
223 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
224 __func__, cmd_idx, arg);
225
226 rsp_type = sd_response_type(cmd);
227 if (rsp_type < 0)
228 goto out;
229
230 stat_idx = sd_status_index(rsp_type);
231
232 if (rsp_type == SD_RSP_TYPE_R1b)
233 timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000;
234
235 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
236 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
237 0xFF, SD_CLK_TOGGLE_EN);
238 if (err < 0)
239 goto out;
240
241 clock_toggled = true;
242 }
243
244 rtsx_pci_init_cmd(pcr);
245 sd_cmd_set_sd_cmd(pcr, cmd);
246 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
247 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
248 0x01, PINGPONG_BUFFER);
249 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
250 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
251 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
252 SD_TRANSFER_END | SD_STAT_IDLE,
253 SD_TRANSFER_END | SD_STAT_IDLE);
254
255 if (rsp_type == SD_RSP_TYPE_R2) {
256 /* Read data from ping-pong buffer */
257 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
258 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
259 } else if (rsp_type != SD_RSP_TYPE_R0) {
260 /* Read data from SD_CMDx registers */
261 for (i = SD_CMD0; i <= SD_CMD4; i++)
262 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
263 }
264
265 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
266
267 err = rtsx_pci_send_cmd(pcr, timeout);
268 if (err < 0) {
269 sd_print_debug_regs(host);
270 sd_clear_error(host);
271 dev_dbg(sdmmc_dev(host),
272 "rtsx_pci_send_cmd error (err = %d)\n", err);
273 goto out;
274 }
275
276 if (rsp_type == SD_RSP_TYPE_R0) {
277 err = 0;
278 goto out;
279 }
280
281 /* Eliminate returned value of CHECK_REG_CMD */
282 ptr = rtsx_pci_get_cmd_data(pcr) + 1;
283
284 /* Check (Start,Transmission) bit of Response */
285 if ((ptr[0] & 0xC0) != 0) {
286 err = -EILSEQ;
287 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
288 goto out;
289 }
290
291 /* Check CRC7 */
292 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
293 if (ptr[stat_idx] & SD_CRC7_ERR) {
294 err = -EILSEQ;
295 dev_dbg(sdmmc_dev(host), "CRC7 error\n");
296 goto out;
297 }
298 }
299
300 if (rsp_type == SD_RSP_TYPE_R2) {
301 /*
302 * The controller offloads the last byte {CRC-7, end bit 1'b1}
303 * of response type R2. Assign dummy CRC, 0, and end bit to the
304 * byte(ptr[16], goes into the LSB of resp[3] later).
305 */
306 ptr[16] = 1;
307
308 for (i = 0; i < 4; i++) {
309 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
310 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
311 i, cmd->resp[i]);
312 }
313 } else {
314 cmd->resp[0] = get_unaligned_be32(ptr + 1);
315 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
316 cmd->resp[0]);
317 }
318
319out:
320 cmd->error = err;
321
322 if (err && clock_toggled)
323 rtsx_pci_write_register(pcr, SD_BUS_STAT,
324 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
325}
326
327static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd,
328 u16 byte_cnt, u8 *buf, int buf_len, int timeout)
329{
330 struct rtsx_pcr *pcr = host->pcr;
331 int err;
332 u8 trans_mode;
333
334 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
335 __func__, cmd->opcode, cmd->arg);
336
337 if (!buf)
338 buf_len = 0;
339
340 if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
341 trans_mode = SD_TM_AUTO_TUNING;
342 else
343 trans_mode = SD_TM_NORMAL_READ;
344
345 rtsx_pci_init_cmd(pcr);
346 sd_cmd_set_sd_cmd(pcr, cmd);
347 sd_cmd_set_data_len(pcr, 1, byte_cnt);
348 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
349 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
350 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
351 if (trans_mode != SD_TM_AUTO_TUNING)
352 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
353 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
354
355 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
356 0xFF, trans_mode | SD_TRANSFER_START);
357 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
358 SD_TRANSFER_END, SD_TRANSFER_END);
359
360 err = rtsx_pci_send_cmd(pcr, timeout);
361 if (err < 0) {
362 sd_print_debug_regs(host);
363 dev_dbg(sdmmc_dev(host),
364 "rtsx_pci_send_cmd fail (err = %d)\n", err);
365 return err;
366 }
367
368 if (buf && buf_len) {
369 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
370 if (err < 0) {
371 dev_dbg(sdmmc_dev(host),
372 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
373 return err;
374 }
375 }
376
377 return 0;
378}
379
380static int sd_write_data(struct realtek_pci_sdmmc *host,
381 struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len,
382 int timeout)
383{
384 struct rtsx_pcr *pcr = host->pcr;
385 int err;
386
387 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
388 __func__, cmd->opcode, cmd->arg);
389
390 if (!buf)
391 buf_len = 0;
392
393 sd_send_cmd_get_rsp(host, cmd);
394 if (cmd->error)
395 return cmd->error;
396
397 if (buf && buf_len) {
398 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
399 if (err < 0) {
400 dev_dbg(sdmmc_dev(host),
401 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
402 return err;
403 }
404 }
405
406 rtsx_pci_init_cmd(pcr);
407 sd_cmd_set_data_len(pcr, 1, byte_cnt);
408 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
409 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
410 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0);
411 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
412 SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
413 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
414 SD_TRANSFER_END, SD_TRANSFER_END);
415
416 err = rtsx_pci_send_cmd(pcr, timeout);
417 if (err < 0) {
418 sd_print_debug_regs(host);
419 dev_dbg(sdmmc_dev(host),
420 "rtsx_pci_send_cmd fail (err = %d)\n", err);
421 return err;
422 }
423
424 return 0;
425}
426
427static int sd_read_long_data(struct realtek_pci_sdmmc *host,
428 struct mmc_request *mrq)
429{
430 struct rtsx_pcr *pcr = host->pcr;
431 struct mmc_host *mmc = host->mmc;
432 struct mmc_card *card = mmc->card;
433 struct mmc_command *cmd = mrq->cmd;
434 struct mmc_data *data = mrq->data;
435 int uhs = mmc_card_uhs(card);
436 u8 cfg2 = 0;
437 int err;
438 int resp_type;
439 size_t data_len = data->blksz * data->blocks;
440
441 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
442 __func__, cmd->opcode, cmd->arg);
443
444 resp_type = sd_response_type(cmd);
445 if (resp_type < 0)
446 return resp_type;
447
448 if (!uhs)
449 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
450
451 rtsx_pci_init_cmd(pcr);
452 sd_cmd_set_sd_cmd(pcr, cmd);
453 sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
454 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
455 DMA_DONE_INT, DMA_DONE_INT);
456 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
457 0xFF, (u8)(data_len >> 24));
458 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
459 0xFF, (u8)(data_len >> 16));
460 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
461 0xFF, (u8)(data_len >> 8));
462 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
463 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
464 0x03 | DMA_PACK_SIZE_MASK,
465 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
466 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
467 0x01, RING_BUFFER);
468 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
469 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
470 SD_TRANSFER_START | SD_TM_AUTO_READ_2);
471 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
472 SD_TRANSFER_END, SD_TRANSFER_END);
473 rtsx_pci_send_cmd_no_wait(pcr);
474
475 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
476 if (err < 0) {
477 sd_print_debug_regs(host);
478 sd_clear_error(host);
479 return err;
480 }
481
482 return 0;
483}
484
485static int sd_write_long_data(struct realtek_pci_sdmmc *host,
486 struct mmc_request *mrq)
487{
488 struct rtsx_pcr *pcr = host->pcr;
489 struct mmc_host *mmc = host->mmc;
490 struct mmc_card *card = mmc->card;
491 struct mmc_command *cmd = mrq->cmd;
492 struct mmc_data *data = mrq->data;
493 int uhs = mmc_card_uhs(card);
494 u8 cfg2;
495 int err;
496 size_t data_len = data->blksz * data->blocks;
497
498 sd_send_cmd_get_rsp(host, cmd);
499 if (cmd->error)
500 return cmd->error;
501
502 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
503 __func__, cmd->opcode, cmd->arg);
504
505 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
506 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
507
508 if (!uhs)
509 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
510
511 rtsx_pci_init_cmd(pcr);
512 sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
513 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
514 DMA_DONE_INT, DMA_DONE_INT);
515 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
516 0xFF, (u8)(data_len >> 24));
517 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
518 0xFF, (u8)(data_len >> 16));
519 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
520 0xFF, (u8)(data_len >> 8));
521 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
522 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
523 0x03 | DMA_PACK_SIZE_MASK,
524 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
525 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
526 0x01, RING_BUFFER);
527 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
528 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
529 SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
530 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
531 SD_TRANSFER_END, SD_TRANSFER_END);
532 rtsx_pci_send_cmd_no_wait(pcr);
533 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
534 if (err < 0) {
535 sd_clear_error(host);
536 return err;
537 }
538
539 return 0;
540}
541
542static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
543{
544 struct mmc_data *data = mrq->data;
545
546 if (host->sg_count < 0) {
547 data->error = host->sg_count;
548 dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n",
549 __func__, host->sg_count);
550 return data->error;
551 }
552
553 if (data->flags & MMC_DATA_READ)
554 return sd_read_long_data(host, mrq);
555
556 return sd_write_long_data(host, mrq);
557}
558
559static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
560{
561 rtsx_pci_write_register(host->pcr, SD_CFG1,
562 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
563}
564
565static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
566{
567 rtsx_pci_write_register(host->pcr, SD_CFG1,
568 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
569}
570
571static void sd_normal_rw(struct realtek_pci_sdmmc *host,
572 struct mmc_request *mrq)
573{
574 struct mmc_command *cmd = mrq->cmd;
575 struct mmc_data *data = mrq->data;
576 u8 *buf;
577
578 buf = kzalloc(data->blksz, GFP_NOIO);
579 if (!buf) {
580 cmd->error = -ENOMEM;
581 return;
582 }
583
584 if (data->flags & MMC_DATA_READ) {
585 if (host->initial_mode)
586 sd_disable_initial_mode(host);
587
588 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
589 data->blksz, 200);
590
591 if (host->initial_mode)
592 sd_enable_initial_mode(host);
593
594 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
595 } else {
596 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
597
598 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
599 data->blksz, 200);
600 }
601
602 kfree(buf);
603}
604
605static int sd_change_phase(struct realtek_pci_sdmmc *host,
606 u8 sample_point, bool rx)
607{
608 struct rtsx_pcr *pcr = host->pcr;
609
610 dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
611 __func__, rx ? "RX" : "TX", sample_point);
612
613 rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
614 if (rx)
615 rtsx_pci_write_register(pcr, SD_VPRX_CTL,
616 PHASE_SELECT_MASK, sample_point);
617 else
618 rtsx_pci_write_register(pcr, SD_VPTX_CTL,
619 PHASE_SELECT_MASK, sample_point);
620 rtsx_pci_write_register(pcr, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
621 rtsx_pci_write_register(pcr, SD_VPCLK0_CTL, PHASE_NOT_RESET,
622 PHASE_NOT_RESET);
623 rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);
624 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
625
626 return 0;
627}
628
629static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
630{
631 bit %= RTSX_PHASE_MAX;
632 return phase_map & (1 << bit);
633}
634
635static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
636{
637 int i;
638
639 for (i = 0; i < RTSX_PHASE_MAX; i++) {
640 if (test_phase_bit(phase_map, start_bit + i) == 0)
641 return i;
642 }
643 return RTSX_PHASE_MAX;
644}
645
646static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
647{
648 int start = 0, len = 0;
649 int start_final = 0, len_final = 0;
650 u8 final_phase = 0xFF;
651
652 if (phase_map == 0) {
653 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
654 return final_phase;
655 }
656
657 while (start < RTSX_PHASE_MAX) {
658 len = sd_get_phase_len(phase_map, start);
659 if (len_final < len) {
660 start_final = start;
661 len_final = len;
662 }
663 start += len ? len : 1;
664 }
665
666 final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
667 dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
668 phase_map, len_final, final_phase);
669
670 return final_phase;
671}
672
673static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
674{
675 int err, i;
676 u8 val = 0;
677
678 for (i = 0; i < 100; i++) {
679 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
680 if (val & SD_DATA_IDLE)
681 return;
682
683 udelay(100);
684 }
685}
686
687static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
688 u8 opcode, u8 sample_point)
689{
690 int err;
691 struct mmc_command cmd = {};
692 struct rtsx_pcr *pcr = host->pcr;
693
694 sd_change_phase(host, sample_point, true);
695
696 rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
697 SD_RSP_80CLK_TIMEOUT_EN);
698
699 cmd.opcode = opcode;
700 err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
701 if (err < 0) {
702 /* Wait till SD DATA IDLE */
703 sd_wait_data_idle(host);
704 sd_clear_error(host);
705 rtsx_pci_write_register(pcr, SD_CFG3,
706 SD_RSP_80CLK_TIMEOUT_EN, 0);
707 return err;
708 }
709
710 rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
711 return 0;
712}
713
714static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
715 u8 opcode, u32 *phase_map)
716{
717 int err, i;
718 u32 raw_phase_map = 0;
719
720 for (i = 0; i < RTSX_PHASE_MAX; i++) {
721 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
722 if (err == 0)
723 raw_phase_map |= 1 << i;
724 }
725
726 if (phase_map)
727 *phase_map = raw_phase_map;
728
729 return 0;
730}
731
732static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
733{
734 int err, i;
735 u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
736 u8 final_phase;
737
738 for (i = 0; i < RX_TUNING_CNT; i++) {
739 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
740 if (err < 0)
741 return err;
742
743 if (raw_phase_map[i] == 0)
744 break;
745 }
746
747 phase_map = 0xFFFFFFFF;
748 for (i = 0; i < RX_TUNING_CNT; i++) {
749 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
750 i, raw_phase_map[i]);
751 phase_map &= raw_phase_map[i];
752 }
753 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
754
755 if (phase_map) {
756 final_phase = sd_search_final_phase(host, phase_map);
757 if (final_phase == 0xFF)
758 return -EINVAL;
759
760 err = sd_change_phase(host, final_phase, true);
761 if (err < 0)
762 return err;
763 } else {
764 return -EINVAL;
765 }
766
767 return 0;
768}
769
770static inline int sdio_extblock_cmd(struct mmc_command *cmd,
771 struct mmc_data *data)
772{
773 return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512);
774}
775
776static inline int sd_rw_cmd(struct mmc_command *cmd)
777{
778 return mmc_op_multi(cmd->opcode) ||
779 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
780 (cmd->opcode == MMC_WRITE_BLOCK);
781}
782
783static void sd_request(struct work_struct *work)
784{
785 struct realtek_pci_sdmmc *host = container_of(work,
786 struct realtek_pci_sdmmc, work);
787 struct rtsx_pcr *pcr = host->pcr;
788
789 struct mmc_host *mmc = host->mmc;
790 struct mmc_request *mrq = host->mrq;
791 struct mmc_command *cmd = mrq->cmd;
792 struct mmc_data *data = mrq->data;
793
794 unsigned int data_size = 0;
795 int err;
796
797 if (host->eject || !sd_get_cd_int(host)) {
798 cmd->error = -ENOMEDIUM;
799 goto finish;
800 }
801
802 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
803 if (err) {
804 cmd->error = err;
805 goto finish;
806 }
807
808 mutex_lock(&pcr->pcr_mutex);
809
810 rtsx_pci_start_run(pcr);
811
812 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
813 host->initial_mode, host->double_clk, host->vpclk);
814 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
815 rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
816 CARD_SHARE_MASK, CARD_SHARE_48_SD);
817
818 mutex_lock(&host->host_mutex);
819 host->mrq = mrq;
820 mutex_unlock(&host->host_mutex);
821
822 if (mrq->data)
823 data_size = data->blocks * data->blksz;
824
825 if (!data_size) {
826 sd_send_cmd_get_rsp(host, cmd);
827 } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) {
828 cmd->error = sd_rw_multi(host, mrq);
829 if (!host->using_cookie)
830 sdmmc_post_req(host->mmc, host->mrq, 0);
831
832 if (mmc_op_multi(cmd->opcode) && mrq->stop)
833 sd_send_cmd_get_rsp(host, mrq->stop);
834 } else {
835 sd_normal_rw(host, mrq);
836 }
837
838 if (mrq->data) {
839 if (cmd->error || data->error)
840 data->bytes_xfered = 0;
841 else
842 data->bytes_xfered = data->blocks * data->blksz;
843 }
844
845 mutex_unlock(&pcr->pcr_mutex);
846
847finish:
848 if (cmd->error) {
849 dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n",
850 cmd->opcode, cmd->arg, cmd->error);
851 }
852
853 mutex_lock(&host->host_mutex);
854 host->mrq = NULL;
855 mutex_unlock(&host->host_mutex);
856
857 mmc_request_done(mmc, mrq);
858}
859
860static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
861{
862 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
863 struct mmc_data *data = mrq->data;
864
865 mutex_lock(&host->host_mutex);
866 host->mrq = mrq;
867 mutex_unlock(&host->host_mutex);
868
869 if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
870 host->using_cookie = sd_pre_dma_transfer(host, data, false);
871
872 schedule_work(&host->work);
873}
874
875static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
876 unsigned char bus_width)
877{
878 int err = 0;
879 u8 width[] = {
880 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
881 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
882 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
883 };
884
885 if (bus_width <= MMC_BUS_WIDTH_8)
886 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
887 0x03, width[bus_width]);
888
889 return err;
890}
891
892static int sd_power_on(struct realtek_pci_sdmmc *host)
893{
894 struct rtsx_pcr *pcr = host->pcr;
895 int err;
896
897 if (host->power_state == SDMMC_POWER_ON)
898 return 0;
899
900 rtsx_pci_init_cmd(pcr);
901 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
902 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
903 CARD_SHARE_MASK, CARD_SHARE_48_SD);
904 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
905 SD_CLK_EN, SD_CLK_EN);
906 err = rtsx_pci_send_cmd(pcr, 100);
907 if (err < 0)
908 return err;
909
910 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
911 if (err < 0)
912 return err;
913
914 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
915 if (err < 0)
916 return err;
917
918 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
919 if (err < 0)
920 return err;
921
922 host->power_state = SDMMC_POWER_ON;
923 return 0;
924}
925
926static int sd_power_off(struct realtek_pci_sdmmc *host)
927{
928 struct rtsx_pcr *pcr = host->pcr;
929 int err;
930
931 host->power_state = SDMMC_POWER_OFF;
932
933 rtsx_pci_init_cmd(pcr);
934
935 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
936 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
937
938 err = rtsx_pci_send_cmd(pcr, 100);
939 if (err < 0)
940 return err;
941
942 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
943 if (err < 0)
944 return err;
945
946 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
947}
948
949static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
950 unsigned char power_mode)
951{
952 int err;
953
954 if (power_mode == MMC_POWER_OFF)
955 err = sd_power_off(host);
956 else
957 err = sd_power_on(host);
958
959 return err;
960}
961
962static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
963{
964 struct rtsx_pcr *pcr = host->pcr;
965 int err = 0;
966
967 rtsx_pci_init_cmd(pcr);
968
969 switch (timing) {
970 case MMC_TIMING_UHS_SDR104:
971 case MMC_TIMING_UHS_SDR50:
972 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
973 0x0C | SD_ASYNC_FIFO_NOT_RST,
974 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
975 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
976 CLK_LOW_FREQ, CLK_LOW_FREQ);
977 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
978 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
979 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
980 break;
981
982 case MMC_TIMING_MMC_DDR52:
983 case MMC_TIMING_UHS_DDR50:
984 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
985 0x0C | SD_ASYNC_FIFO_NOT_RST,
986 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
987 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
988 CLK_LOW_FREQ, CLK_LOW_FREQ);
989 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
990 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
991 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
992 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
993 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
994 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
995 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
996 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
997 break;
998
999 case MMC_TIMING_MMC_HS:
1000 case MMC_TIMING_SD_HS:
1001 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1002 0x0C, SD_20_MODE);
1003 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1004 CLK_LOW_FREQ, CLK_LOW_FREQ);
1005 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1006 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1007 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1008 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1009 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1010 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1011 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1012 break;
1013
1014 default:
1015 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1016 SD_CFG1, 0x0C, SD_20_MODE);
1017 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1018 CLK_LOW_FREQ, CLK_LOW_FREQ);
1019 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1020 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1021 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1022 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1023 SD_PUSH_POINT_CTL, 0xFF, 0);
1024 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1025 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1026 break;
1027 }
1028
1029 err = rtsx_pci_send_cmd(pcr, 100);
1030
1031 return err;
1032}
1033
1034static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1035{
1036 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1037 struct rtsx_pcr *pcr = host->pcr;
1038
1039 if (host->eject)
1040 return;
1041
1042 if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1043 return;
1044
1045 mutex_lock(&pcr->pcr_mutex);
1046
1047 rtsx_pci_start_run(pcr);
1048
1049 sd_set_bus_width(host, ios->bus_width);
1050 sd_set_power_mode(host, ios->power_mode);
1051 sd_set_timing(host, ios->timing);
1052
1053 host->vpclk = false;
1054 host->double_clk = true;
1055
1056 switch (ios->timing) {
1057 case MMC_TIMING_UHS_SDR104:
1058 case MMC_TIMING_UHS_SDR50:
1059 host->ssc_depth = RTSX_SSC_DEPTH_2M;
1060 host->vpclk = true;
1061 host->double_clk = false;
1062 break;
1063 case MMC_TIMING_MMC_DDR52:
1064 case MMC_TIMING_UHS_DDR50:
1065 case MMC_TIMING_UHS_SDR25:
1066 host->ssc_depth = RTSX_SSC_DEPTH_1M;
1067 break;
1068 default:
1069 host->ssc_depth = RTSX_SSC_DEPTH_500K;
1070 break;
1071 }
1072
1073 host->initial_mode = (ios->clock <= 1000000) ? true : false;
1074
1075 host->clock = ios->clock;
1076 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1077 host->initial_mode, host->double_clk, host->vpclk);
1078
1079 mutex_unlock(&pcr->pcr_mutex);
1080}
1081
1082static int sdmmc_get_ro(struct mmc_host *mmc)
1083{
1084 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1085 struct rtsx_pcr *pcr = host->pcr;
1086 int ro = 0;
1087 u32 val;
1088
1089 if (host->eject)
1090 return -ENOMEDIUM;
1091
1092 mutex_lock(&pcr->pcr_mutex);
1093
1094 rtsx_pci_start_run(pcr);
1095
1096 /* Check SD mechanical write-protect switch */
1097 val = rtsx_pci_readl(pcr, RTSX_BIPR);
1098 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1099 if (val & SD_WRITE_PROTECT)
1100 ro = 1;
1101
1102 mutex_unlock(&pcr->pcr_mutex);
1103
1104 return ro;
1105}
1106
1107static int sdmmc_get_cd(struct mmc_host *mmc)
1108{
1109 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1110 struct rtsx_pcr *pcr = host->pcr;
1111 int cd = 0;
1112 u32 val;
1113
1114 if (host->eject)
1115 return cd;
1116
1117 mutex_lock(&pcr->pcr_mutex);
1118
1119 rtsx_pci_start_run(pcr);
1120
1121 /* Check SD card detect */
1122 val = rtsx_pci_card_exist(pcr);
1123 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1124 if (val & SD_EXIST)
1125 cd = 1;
1126
1127 mutex_unlock(&pcr->pcr_mutex);
1128
1129 return cd;
1130}
1131
1132static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1133{
1134 struct rtsx_pcr *pcr = host->pcr;
1135 int err;
1136 u8 stat;
1137
1138 /* Reference to Signal Voltage Switch Sequence in SD spec.
1139 * Wait for a period of time so that the card can drive SD_CMD and
1140 * SD_DAT[3:0] to low after sending back CMD11 response.
1141 */
1142 mdelay(1);
1143
1144 /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1145 * If either one of SD_CMD,SD_DAT[3:0] is not low,
1146 * abort the voltage switch sequence;
1147 */
1148 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1149 if (err < 0)
1150 return err;
1151
1152 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1153 SD_DAT1_STATUS | SD_DAT0_STATUS))
1154 return -EINVAL;
1155
1156 /* Stop toggle SD clock */
1157 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1158 0xFF, SD_CLK_FORCE_STOP);
1159 if (err < 0)
1160 return err;
1161
1162 return 0;
1163}
1164
1165static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1166{
1167 struct rtsx_pcr *pcr = host->pcr;
1168 int err;
1169 u8 stat, mask, val;
1170
1171 /* Wait 1.8V output of voltage regulator in card stable */
1172 msleep(50);
1173
1174 /* Toggle SD clock again */
1175 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1176 if (err < 0)
1177 return err;
1178
1179 /* Wait for a period of time so that the card can drive
1180 * SD_DAT[3:0] to high at 1.8V
1181 */
1182 msleep(20);
1183
1184 /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1185 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1186 if (err < 0)
1187 return err;
1188
1189 mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1190 SD_DAT1_STATUS | SD_DAT0_STATUS;
1191 val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1192 SD_DAT1_STATUS | SD_DAT0_STATUS;
1193 if ((stat & mask) != val) {
1194 dev_dbg(sdmmc_dev(host),
1195 "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1196 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1197 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1198 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1199 return -EINVAL;
1200 }
1201
1202 return 0;
1203}
1204
1205static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1206{
1207 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1208 struct rtsx_pcr *pcr = host->pcr;
1209 int err = 0;
1210 u8 voltage;
1211
1212 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1213 __func__, ios->signal_voltage);
1214
1215 if (host->eject)
1216 return -ENOMEDIUM;
1217
1218 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1219 if (err)
1220 return err;
1221
1222 mutex_lock(&pcr->pcr_mutex);
1223
1224 rtsx_pci_start_run(pcr);
1225
1226 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1227 voltage = OUTPUT_3V3;
1228 else
1229 voltage = OUTPUT_1V8;
1230
1231 if (voltage == OUTPUT_1V8) {
1232 err = sd_wait_voltage_stable_1(host);
1233 if (err < 0)
1234 goto out;
1235 }
1236
1237 err = rtsx_pci_switch_output_voltage(pcr, voltage);
1238 if (err < 0)
1239 goto out;
1240
1241 if (voltage == OUTPUT_1V8) {
1242 err = sd_wait_voltage_stable_2(host);
1243 if (err < 0)
1244 goto out;
1245 }
1246
1247out:
1248 /* Stop toggle SD clock in idle */
1249 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1250 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1251
1252 mutex_unlock(&pcr->pcr_mutex);
1253
1254 return err;
1255}
1256
1257static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1258{
1259 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1260 struct rtsx_pcr *pcr = host->pcr;
1261 int err = 0;
1262
1263 if (host->eject)
1264 return -ENOMEDIUM;
1265
1266 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1267 if (err)
1268 return err;
1269
1270 mutex_lock(&pcr->pcr_mutex);
1271
1272 rtsx_pci_start_run(pcr);
1273
1274 /* Set initial TX phase */
1275 switch (mmc->ios.timing) {
1276 case MMC_TIMING_UHS_SDR104:
1277 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1278 break;
1279
1280 case MMC_TIMING_UHS_SDR50:
1281 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1282 break;
1283
1284 case MMC_TIMING_UHS_DDR50:
1285 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1286 break;
1287
1288 default:
1289 err = 0;
1290 }
1291
1292 if (err)
1293 goto out;
1294
1295 /* Tuning RX phase */
1296 if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1297 (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1298 err = sd_tuning_rx(host, opcode);
1299 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1300 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1301
1302out:
1303 mutex_unlock(&pcr->pcr_mutex);
1304
1305 return err;
1306}
1307
1308static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1309 .pre_req = sdmmc_pre_req,
1310 .post_req = sdmmc_post_req,
1311 .request = sdmmc_request,
1312 .set_ios = sdmmc_set_ios,
1313 .get_ro = sdmmc_get_ro,
1314 .get_cd = sdmmc_get_cd,
1315 .start_signal_voltage_switch = sdmmc_switch_voltage,
1316 .execute_tuning = sdmmc_execute_tuning,
1317};
1318
1319static void init_extra_caps(struct realtek_pci_sdmmc *host)
1320{
1321 struct mmc_host *mmc = host->mmc;
1322 struct rtsx_pcr *pcr = host->pcr;
1323
1324 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1325
1326 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1327 mmc->caps |= MMC_CAP_UHS_SDR50;
1328 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1329 mmc->caps |= MMC_CAP_UHS_SDR104;
1330 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1331 mmc->caps |= MMC_CAP_UHS_DDR50;
1332 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1333 mmc->caps |= MMC_CAP_1_8V_DDR;
1334 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1335 mmc->caps |= MMC_CAP_8_BIT_DATA;
1336}
1337
1338static void realtek_init_host(struct realtek_pci_sdmmc *host)
1339{
1340 struct mmc_host *mmc = host->mmc;
1341
1342 mmc->f_min = 250000;
1343 mmc->f_max = 208000000;
1344 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1345 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1346 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1347 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_ERASE;
1348 mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE;
1349 mmc->max_current_330 = 400;
1350 mmc->max_current_180 = 800;
1351 mmc->ops = &realtek_pci_sdmmc_ops;
1352
1353 init_extra_caps(host);
1354
1355 mmc->max_segs = 256;
1356 mmc->max_seg_size = 65536;
1357 mmc->max_blk_size = 512;
1358 mmc->max_blk_count = 65535;
1359 mmc->max_req_size = 524288;
1360}
1361
1362static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1363{
1364 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1365
1366 host->cookie = -1;
1367 mmc_detect_change(host->mmc, 0);
1368}
1369
1370static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1371{
1372 struct mmc_host *mmc;
1373 struct realtek_pci_sdmmc *host;
1374 struct rtsx_pcr *pcr;
1375 struct pcr_handle *handle = pdev->dev.platform_data;
1376
1377 if (!handle)
1378 return -ENXIO;
1379
1380 pcr = handle->pcr;
1381 if (!pcr)
1382 return -ENXIO;
1383
1384 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1385
1386 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1387 if (!mmc)
1388 return -ENOMEM;
1389
1390 host = mmc_priv(mmc);
1391 host->pcr = pcr;
1392 host->mmc = mmc;
1393 host->pdev = pdev;
1394 host->cookie = -1;
1395 host->power_state = SDMMC_POWER_OFF;
1396 INIT_WORK(&host->work, sd_request);
1397 platform_set_drvdata(pdev, host);
1398 pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1399 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1400
1401 mutex_init(&host->host_mutex);
1402
1403 realtek_init_host(host);
1404
1405 mmc_add_host(mmc);
1406
1407 return 0;
1408}
1409
1410static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1411{
1412 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1413 struct rtsx_pcr *pcr;
1414 struct mmc_host *mmc;
1415
1416 if (!host)
1417 return 0;
1418
1419 pcr = host->pcr;
1420 pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1421 pcr->slots[RTSX_SD_CARD].card_event = NULL;
1422 mmc = host->mmc;
1423
1424 cancel_work_sync(&host->work);
1425
1426 mutex_lock(&host->host_mutex);
1427 if (host->mrq) {
1428 dev_dbg(&(pdev->dev),
1429 "%s: Controller removed during transfer\n",
1430 mmc_hostname(mmc));
1431
1432 rtsx_pci_complete_unfinished_transfer(pcr);
1433
1434 host->mrq->cmd->error = -ENOMEDIUM;
1435 if (host->mrq->stop)
1436 host->mrq->stop->error = -ENOMEDIUM;
1437 mmc_request_done(mmc, host->mrq);
1438 }
1439 mutex_unlock(&host->host_mutex);
1440
1441 mmc_remove_host(mmc);
1442 host->eject = true;
1443
1444 flush_work(&host->work);
1445
1446 mmc_free_host(mmc);
1447
1448 dev_dbg(&(pdev->dev),
1449 ": Realtek PCI-E SDMMC controller has been removed\n");
1450
1451 return 0;
1452}
1453
1454static const struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1455 {
1456 .name = DRV_NAME_RTSX_PCI_SDMMC,
1457 }, {
1458 /* sentinel */
1459 }
1460};
1461MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1462
1463static struct platform_driver rtsx_pci_sdmmc_driver = {
1464 .probe = rtsx_pci_sdmmc_drv_probe,
1465 .remove = rtsx_pci_sdmmc_drv_remove,
1466 .id_table = rtsx_pci_sdmmc_ids,
1467 .driver = {
1468 .name = DRV_NAME_RTSX_PCI_SDMMC,
1469 },
1470};
1471module_platform_driver(rtsx_pci_sdmmc_driver);
1472
1473MODULE_LICENSE("GPL");
1474MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1475MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");