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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Azoteq IQS7222A/B/C/D Capacitive Touch Controller
4 *
5 * Copyright (C) 2022 Jeff LaBundy <jeff@labundy.com>
6 */
7
8#include <linux/bits.h>
9#include <linux/delay.h>
10#include <linux/device.h>
11#include <linux/err.h>
12#include <linux/gpio/consumer.h>
13#include <linux/i2c.h>
14#include <linux/input.h>
15#include <linux/input/touchscreen.h>
16#include <linux/interrupt.h>
17#include <linux/kernel.h>
18#include <linux/ktime.h>
19#include <linux/mod_devicetable.h>
20#include <linux/module.h>
21#include <linux/property.h>
22#include <linux/slab.h>
23#include <asm/unaligned.h>
24
25#define IQS7222_PROD_NUM 0x00
26#define IQS7222_PROD_NUM_A 840
27#define IQS7222_PROD_NUM_B 698
28#define IQS7222_PROD_NUM_C 863
29#define IQS7222_PROD_NUM_D 1046
30
31#define IQS7222_SYS_STATUS 0x10
32#define IQS7222_SYS_STATUS_RESET BIT(3)
33#define IQS7222_SYS_STATUS_ATI_ERROR BIT(1)
34#define IQS7222_SYS_STATUS_ATI_ACTIVE BIT(0)
35
36#define IQS7222_CHAN_SETUP_0_REF_MODE_MASK GENMASK(15, 14)
37#define IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW BIT(15)
38#define IQS7222_CHAN_SETUP_0_REF_MODE_REF BIT(14)
39#define IQS7222_CHAN_SETUP_0_CHAN_EN BIT(8)
40
41#define IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK GENMASK(2, 0)
42#define IQS7222_SLDR_SETUP_2_RES_MASK GENMASK(15, 8)
43#define IQS7222_SLDR_SETUP_2_RES_SHIFT 8
44#define IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK GENMASK(7, 0)
45
46#define IQS7222_GPIO_SETUP_0_GPIO_EN BIT(0)
47
48#define IQS7222_SYS_SETUP 0xD0
49#define IQS7222_SYS_SETUP_INTF_MODE_MASK GENMASK(7, 6)
50#define IQS7222_SYS_SETUP_INTF_MODE_TOUCH BIT(7)
51#define IQS7222_SYS_SETUP_INTF_MODE_EVENT BIT(6)
52#define IQS7222_SYS_SETUP_PWR_MODE_MASK GENMASK(5, 4)
53#define IQS7222_SYS_SETUP_PWR_MODE_AUTO IQS7222_SYS_SETUP_PWR_MODE_MASK
54#define IQS7222_SYS_SETUP_REDO_ATI BIT(2)
55#define IQS7222_SYS_SETUP_ACK_RESET BIT(0)
56
57#define IQS7222_EVENT_MASK_ATI BIT(12)
58#define IQS7222_EVENT_MASK_SLDR BIT(10)
59#define IQS7222_EVENT_MASK_TPAD IQS7222_EVENT_MASK_SLDR
60#define IQS7222_EVENT_MASK_TOUCH BIT(1)
61#define IQS7222_EVENT_MASK_PROX BIT(0)
62
63#define IQS7222_COMMS_HOLD BIT(0)
64#define IQS7222_COMMS_ERROR 0xEEEE
65#define IQS7222_COMMS_RETRY_MS 50
66#define IQS7222_COMMS_TIMEOUT_MS 100
67#define IQS7222_RESET_TIMEOUT_MS 250
68#define IQS7222_ATI_TIMEOUT_MS 2000
69
70#define IQS7222_MAX_COLS_STAT 8
71#define IQS7222_MAX_COLS_CYCLE 3
72#define IQS7222_MAX_COLS_GLBL 3
73#define IQS7222_MAX_COLS_BTN 3
74#define IQS7222_MAX_COLS_CHAN 6
75#define IQS7222_MAX_COLS_FILT 2
76#define IQS7222_MAX_COLS_SLDR 11
77#define IQS7222_MAX_COLS_TPAD 24
78#define IQS7222_MAX_COLS_GPIO 3
79#define IQS7222_MAX_COLS_SYS 13
80
81#define IQS7222_MAX_CHAN 20
82#define IQS7222_MAX_SLDR 2
83
84#define IQS7222_NUM_RETRIES 5
85#define IQS7222_REG_OFFSET 0x100
86
87enum iqs7222_reg_key_id {
88 IQS7222_REG_KEY_NONE,
89 IQS7222_REG_KEY_PROX,
90 IQS7222_REG_KEY_TOUCH,
91 IQS7222_REG_KEY_DEBOUNCE,
92 IQS7222_REG_KEY_TAP,
93 IQS7222_REG_KEY_TAP_LEGACY,
94 IQS7222_REG_KEY_AXIAL,
95 IQS7222_REG_KEY_AXIAL_LEGACY,
96 IQS7222_REG_KEY_WHEEL,
97 IQS7222_REG_KEY_NO_WHEEL,
98 IQS7222_REG_KEY_RESERVED
99};
100
101enum iqs7222_reg_grp_id {
102 IQS7222_REG_GRP_STAT,
103 IQS7222_REG_GRP_FILT,
104 IQS7222_REG_GRP_CYCLE,
105 IQS7222_REG_GRP_GLBL,
106 IQS7222_REG_GRP_BTN,
107 IQS7222_REG_GRP_CHAN,
108 IQS7222_REG_GRP_SLDR,
109 IQS7222_REG_GRP_TPAD,
110 IQS7222_REG_GRP_GPIO,
111 IQS7222_REG_GRP_SYS,
112 IQS7222_NUM_REG_GRPS
113};
114
115static const char * const iqs7222_reg_grp_names[IQS7222_NUM_REG_GRPS] = {
116 [IQS7222_REG_GRP_CYCLE] = "cycle-%d",
117 [IQS7222_REG_GRP_CHAN] = "channel-%d",
118 [IQS7222_REG_GRP_SLDR] = "slider-%d",
119 [IQS7222_REG_GRP_TPAD] = "trackpad",
120 [IQS7222_REG_GRP_GPIO] = "gpio-%d",
121};
122
123static const unsigned int iqs7222_max_cols[IQS7222_NUM_REG_GRPS] = {
124 [IQS7222_REG_GRP_STAT] = IQS7222_MAX_COLS_STAT,
125 [IQS7222_REG_GRP_CYCLE] = IQS7222_MAX_COLS_CYCLE,
126 [IQS7222_REG_GRP_GLBL] = IQS7222_MAX_COLS_GLBL,
127 [IQS7222_REG_GRP_BTN] = IQS7222_MAX_COLS_BTN,
128 [IQS7222_REG_GRP_CHAN] = IQS7222_MAX_COLS_CHAN,
129 [IQS7222_REG_GRP_FILT] = IQS7222_MAX_COLS_FILT,
130 [IQS7222_REG_GRP_SLDR] = IQS7222_MAX_COLS_SLDR,
131 [IQS7222_REG_GRP_TPAD] = IQS7222_MAX_COLS_TPAD,
132 [IQS7222_REG_GRP_GPIO] = IQS7222_MAX_COLS_GPIO,
133 [IQS7222_REG_GRP_SYS] = IQS7222_MAX_COLS_SYS,
134};
135
136static const unsigned int iqs7222_gpio_links[] = { 2, 5, 6, };
137
138struct iqs7222_event_desc {
139 const char *name;
140 u16 link;
141 u16 mask;
142 u16 val;
143 u16 strict;
144 u16 enable;
145 enum iqs7222_reg_key_id reg_key;
146};
147
148static const struct iqs7222_event_desc iqs7222_kp_events[] = {
149 {
150 .name = "event-prox",
151 .enable = IQS7222_EVENT_MASK_PROX,
152 .reg_key = IQS7222_REG_KEY_PROX,
153 },
154 {
155 .name = "event-touch",
156 .enable = IQS7222_EVENT_MASK_TOUCH,
157 .reg_key = IQS7222_REG_KEY_TOUCH,
158 },
159};
160
161static const struct iqs7222_event_desc iqs7222_sl_events[] = {
162 { .name = "event-press", },
163 {
164 .name = "event-tap",
165 .mask = BIT(0),
166 .val = BIT(0),
167 .enable = BIT(0),
168 .reg_key = IQS7222_REG_KEY_TAP,
169 },
170 {
171 .name = "event-swipe-pos",
172 .mask = BIT(5) | BIT(1),
173 .val = BIT(1),
174 .enable = BIT(1),
175 .reg_key = IQS7222_REG_KEY_AXIAL,
176 },
177 {
178 .name = "event-swipe-neg",
179 .mask = BIT(5) | BIT(1),
180 .val = BIT(5) | BIT(1),
181 .enable = BIT(1),
182 .reg_key = IQS7222_REG_KEY_AXIAL,
183 },
184 {
185 .name = "event-flick-pos",
186 .mask = BIT(5) | BIT(2),
187 .val = BIT(2),
188 .enable = BIT(2),
189 .reg_key = IQS7222_REG_KEY_AXIAL,
190 },
191 {
192 .name = "event-flick-neg",
193 .mask = BIT(5) | BIT(2),
194 .val = BIT(5) | BIT(2),
195 .enable = BIT(2),
196 .reg_key = IQS7222_REG_KEY_AXIAL,
197 },
198};
199
200static const struct iqs7222_event_desc iqs7222_tp_events[] = {
201 {
202 .name = "event-press",
203 .link = BIT(7),
204 },
205 {
206 .name = "event-tap",
207 .link = BIT(0),
208 .mask = BIT(0),
209 .val = BIT(0),
210 .enable = BIT(0),
211 .reg_key = IQS7222_REG_KEY_TAP,
212 },
213 {
214 .name = "event-swipe-x-pos",
215 .link = BIT(2),
216 .mask = BIT(2) | BIT(1),
217 .val = BIT(2),
218 .strict = BIT(4),
219 .enable = BIT(1),
220 .reg_key = IQS7222_REG_KEY_AXIAL,
221 },
222 {
223 .name = "event-swipe-y-pos",
224 .link = BIT(3),
225 .mask = BIT(3) | BIT(1),
226 .val = BIT(3),
227 .strict = BIT(3),
228 .enable = BIT(1),
229 .reg_key = IQS7222_REG_KEY_AXIAL,
230 },
231 {
232 .name = "event-swipe-x-neg",
233 .link = BIT(4),
234 .mask = BIT(4) | BIT(1),
235 .val = BIT(4),
236 .strict = BIT(4),
237 .enable = BIT(1),
238 .reg_key = IQS7222_REG_KEY_AXIAL,
239 },
240 {
241 .name = "event-swipe-y-neg",
242 .link = BIT(5),
243 .mask = BIT(5) | BIT(1),
244 .val = BIT(5),
245 .strict = BIT(3),
246 .enable = BIT(1),
247 .reg_key = IQS7222_REG_KEY_AXIAL,
248 },
249 {
250 .name = "event-flick-x-pos",
251 .link = BIT(2),
252 .mask = BIT(2) | BIT(1),
253 .val = BIT(2) | BIT(1),
254 .strict = BIT(4),
255 .enable = BIT(2),
256 .reg_key = IQS7222_REG_KEY_AXIAL,
257 },
258 {
259 .name = "event-flick-y-pos",
260 .link = BIT(3),
261 .mask = BIT(3) | BIT(1),
262 .val = BIT(3) | BIT(1),
263 .strict = BIT(3),
264 .enable = BIT(2),
265 .reg_key = IQS7222_REG_KEY_AXIAL,
266 },
267 {
268 .name = "event-flick-x-neg",
269 .link = BIT(4),
270 .mask = BIT(4) | BIT(1),
271 .val = BIT(4) | BIT(1),
272 .strict = BIT(4),
273 .enable = BIT(2),
274 .reg_key = IQS7222_REG_KEY_AXIAL,
275 },
276 {
277 .name = "event-flick-y-neg",
278 .link = BIT(5),
279 .mask = BIT(5) | BIT(1),
280 .val = BIT(5) | BIT(1),
281 .strict = BIT(3),
282 .enable = BIT(2),
283 .reg_key = IQS7222_REG_KEY_AXIAL,
284 },
285};
286
287struct iqs7222_reg_grp_desc {
288 u16 base;
289 int num_row;
290 int num_col;
291};
292
293struct iqs7222_dev_desc {
294 u16 prod_num;
295 u16 fw_major;
296 u16 fw_minor;
297 u16 sldr_res;
298 u16 touch_link;
299 u16 wheel_enable;
300 int allow_offset;
301 int event_offset;
302 int comms_offset;
303 bool legacy_gesture;
304 struct iqs7222_reg_grp_desc reg_grps[IQS7222_NUM_REG_GRPS];
305};
306
307static const struct iqs7222_dev_desc iqs7222_devs[] = {
308 {
309 .prod_num = IQS7222_PROD_NUM_A,
310 .fw_major = 1,
311 .fw_minor = 13,
312 .sldr_res = U8_MAX * 16,
313 .touch_link = 1768,
314 .allow_offset = 9,
315 .event_offset = 10,
316 .comms_offset = 12,
317 .reg_grps = {
318 [IQS7222_REG_GRP_STAT] = {
319 .base = IQS7222_SYS_STATUS,
320 .num_row = 1,
321 .num_col = 8,
322 },
323 [IQS7222_REG_GRP_CYCLE] = {
324 .base = 0x8000,
325 .num_row = 7,
326 .num_col = 3,
327 },
328 [IQS7222_REG_GRP_GLBL] = {
329 .base = 0x8700,
330 .num_row = 1,
331 .num_col = 3,
332 },
333 [IQS7222_REG_GRP_BTN] = {
334 .base = 0x9000,
335 .num_row = 12,
336 .num_col = 3,
337 },
338 [IQS7222_REG_GRP_CHAN] = {
339 .base = 0xA000,
340 .num_row = 12,
341 .num_col = 6,
342 },
343 [IQS7222_REG_GRP_FILT] = {
344 .base = 0xAC00,
345 .num_row = 1,
346 .num_col = 2,
347 },
348 [IQS7222_REG_GRP_SLDR] = {
349 .base = 0xB000,
350 .num_row = 2,
351 .num_col = 11,
352 },
353 [IQS7222_REG_GRP_GPIO] = {
354 .base = 0xC000,
355 .num_row = 1,
356 .num_col = 3,
357 },
358 [IQS7222_REG_GRP_SYS] = {
359 .base = IQS7222_SYS_SETUP,
360 .num_row = 1,
361 .num_col = 13,
362 },
363 },
364 },
365 {
366 .prod_num = IQS7222_PROD_NUM_A,
367 .fw_major = 1,
368 .fw_minor = 12,
369 .sldr_res = U8_MAX * 16,
370 .touch_link = 1768,
371 .allow_offset = 9,
372 .event_offset = 10,
373 .comms_offset = 12,
374 .legacy_gesture = true,
375 .reg_grps = {
376 [IQS7222_REG_GRP_STAT] = {
377 .base = IQS7222_SYS_STATUS,
378 .num_row = 1,
379 .num_col = 8,
380 },
381 [IQS7222_REG_GRP_CYCLE] = {
382 .base = 0x8000,
383 .num_row = 7,
384 .num_col = 3,
385 },
386 [IQS7222_REG_GRP_GLBL] = {
387 .base = 0x8700,
388 .num_row = 1,
389 .num_col = 3,
390 },
391 [IQS7222_REG_GRP_BTN] = {
392 .base = 0x9000,
393 .num_row = 12,
394 .num_col = 3,
395 },
396 [IQS7222_REG_GRP_CHAN] = {
397 .base = 0xA000,
398 .num_row = 12,
399 .num_col = 6,
400 },
401 [IQS7222_REG_GRP_FILT] = {
402 .base = 0xAC00,
403 .num_row = 1,
404 .num_col = 2,
405 },
406 [IQS7222_REG_GRP_SLDR] = {
407 .base = 0xB000,
408 .num_row = 2,
409 .num_col = 11,
410 },
411 [IQS7222_REG_GRP_GPIO] = {
412 .base = 0xC000,
413 .num_row = 1,
414 .num_col = 3,
415 },
416 [IQS7222_REG_GRP_SYS] = {
417 .base = IQS7222_SYS_SETUP,
418 .num_row = 1,
419 .num_col = 13,
420 },
421 },
422 },
423 {
424 .prod_num = IQS7222_PROD_NUM_B,
425 .fw_major = 1,
426 .fw_minor = 43,
427 .event_offset = 10,
428 .comms_offset = 11,
429 .reg_grps = {
430 [IQS7222_REG_GRP_STAT] = {
431 .base = IQS7222_SYS_STATUS,
432 .num_row = 1,
433 .num_col = 6,
434 },
435 [IQS7222_REG_GRP_CYCLE] = {
436 .base = 0x8000,
437 .num_row = 10,
438 .num_col = 2,
439 },
440 [IQS7222_REG_GRP_GLBL] = {
441 .base = 0x8A00,
442 .num_row = 1,
443 .num_col = 3,
444 },
445 [IQS7222_REG_GRP_BTN] = {
446 .base = 0x9000,
447 .num_row = 20,
448 .num_col = 2,
449 },
450 [IQS7222_REG_GRP_CHAN] = {
451 .base = 0xB000,
452 .num_row = 20,
453 .num_col = 4,
454 },
455 [IQS7222_REG_GRP_FILT] = {
456 .base = 0xC400,
457 .num_row = 1,
458 .num_col = 2,
459 },
460 [IQS7222_REG_GRP_SYS] = {
461 .base = IQS7222_SYS_SETUP,
462 .num_row = 1,
463 .num_col = 13,
464 },
465 },
466 },
467 {
468 .prod_num = IQS7222_PROD_NUM_B,
469 .fw_major = 1,
470 .fw_minor = 27,
471 .reg_grps = {
472 [IQS7222_REG_GRP_STAT] = {
473 .base = IQS7222_SYS_STATUS,
474 .num_row = 1,
475 .num_col = 6,
476 },
477 [IQS7222_REG_GRP_CYCLE] = {
478 .base = 0x8000,
479 .num_row = 10,
480 .num_col = 2,
481 },
482 [IQS7222_REG_GRP_GLBL] = {
483 .base = 0x8A00,
484 .num_row = 1,
485 .num_col = 3,
486 },
487 [IQS7222_REG_GRP_BTN] = {
488 .base = 0x9000,
489 .num_row = 20,
490 .num_col = 2,
491 },
492 [IQS7222_REG_GRP_CHAN] = {
493 .base = 0xB000,
494 .num_row = 20,
495 .num_col = 4,
496 },
497 [IQS7222_REG_GRP_FILT] = {
498 .base = 0xC400,
499 .num_row = 1,
500 .num_col = 2,
501 },
502 [IQS7222_REG_GRP_SYS] = {
503 .base = IQS7222_SYS_SETUP,
504 .num_row = 1,
505 .num_col = 10,
506 },
507 },
508 },
509 {
510 .prod_num = IQS7222_PROD_NUM_C,
511 .fw_major = 2,
512 .fw_minor = 6,
513 .sldr_res = U16_MAX,
514 .touch_link = 1686,
515 .wheel_enable = BIT(3),
516 .event_offset = 9,
517 .comms_offset = 10,
518 .reg_grps = {
519 [IQS7222_REG_GRP_STAT] = {
520 .base = IQS7222_SYS_STATUS,
521 .num_row = 1,
522 .num_col = 6,
523 },
524 [IQS7222_REG_GRP_CYCLE] = {
525 .base = 0x8000,
526 .num_row = 5,
527 .num_col = 3,
528 },
529 [IQS7222_REG_GRP_GLBL] = {
530 .base = 0x8500,
531 .num_row = 1,
532 .num_col = 3,
533 },
534 [IQS7222_REG_GRP_BTN] = {
535 .base = 0x9000,
536 .num_row = 10,
537 .num_col = 3,
538 },
539 [IQS7222_REG_GRP_CHAN] = {
540 .base = 0xA000,
541 .num_row = 10,
542 .num_col = 6,
543 },
544 [IQS7222_REG_GRP_FILT] = {
545 .base = 0xAA00,
546 .num_row = 1,
547 .num_col = 2,
548 },
549 [IQS7222_REG_GRP_SLDR] = {
550 .base = 0xB000,
551 .num_row = 2,
552 .num_col = 10,
553 },
554 [IQS7222_REG_GRP_GPIO] = {
555 .base = 0xC000,
556 .num_row = 3,
557 .num_col = 3,
558 },
559 [IQS7222_REG_GRP_SYS] = {
560 .base = IQS7222_SYS_SETUP,
561 .num_row = 1,
562 .num_col = 12,
563 },
564 },
565 },
566 {
567 .prod_num = IQS7222_PROD_NUM_C,
568 .fw_major = 1,
569 .fw_minor = 13,
570 .sldr_res = U16_MAX,
571 .touch_link = 1674,
572 .wheel_enable = BIT(3),
573 .event_offset = 9,
574 .comms_offset = 10,
575 .reg_grps = {
576 [IQS7222_REG_GRP_STAT] = {
577 .base = IQS7222_SYS_STATUS,
578 .num_row = 1,
579 .num_col = 6,
580 },
581 [IQS7222_REG_GRP_CYCLE] = {
582 .base = 0x8000,
583 .num_row = 5,
584 .num_col = 3,
585 },
586 [IQS7222_REG_GRP_GLBL] = {
587 .base = 0x8500,
588 .num_row = 1,
589 .num_col = 3,
590 },
591 [IQS7222_REG_GRP_BTN] = {
592 .base = 0x9000,
593 .num_row = 10,
594 .num_col = 3,
595 },
596 [IQS7222_REG_GRP_CHAN] = {
597 .base = 0xA000,
598 .num_row = 10,
599 .num_col = 6,
600 },
601 [IQS7222_REG_GRP_FILT] = {
602 .base = 0xAA00,
603 .num_row = 1,
604 .num_col = 2,
605 },
606 [IQS7222_REG_GRP_SLDR] = {
607 .base = 0xB000,
608 .num_row = 2,
609 .num_col = 10,
610 },
611 [IQS7222_REG_GRP_GPIO] = {
612 .base = 0xC000,
613 .num_row = 1,
614 .num_col = 3,
615 },
616 [IQS7222_REG_GRP_SYS] = {
617 .base = IQS7222_SYS_SETUP,
618 .num_row = 1,
619 .num_col = 11,
620 },
621 },
622 },
623 {
624 .prod_num = IQS7222_PROD_NUM_D,
625 .fw_major = 0,
626 .fw_minor = 37,
627 .touch_link = 1770,
628 .allow_offset = 9,
629 .event_offset = 10,
630 .comms_offset = 11,
631 .reg_grps = {
632 [IQS7222_REG_GRP_STAT] = {
633 .base = IQS7222_SYS_STATUS,
634 .num_row = 1,
635 .num_col = 7,
636 },
637 [IQS7222_REG_GRP_CYCLE] = {
638 .base = 0x8000,
639 .num_row = 7,
640 .num_col = 2,
641 },
642 [IQS7222_REG_GRP_GLBL] = {
643 .base = 0x8700,
644 .num_row = 1,
645 .num_col = 3,
646 },
647 [IQS7222_REG_GRP_BTN] = {
648 .base = 0x9000,
649 .num_row = 14,
650 .num_col = 3,
651 },
652 [IQS7222_REG_GRP_CHAN] = {
653 .base = 0xA000,
654 .num_row = 14,
655 .num_col = 4,
656 },
657 [IQS7222_REG_GRP_FILT] = {
658 .base = 0xAE00,
659 .num_row = 1,
660 .num_col = 2,
661 },
662 [IQS7222_REG_GRP_TPAD] = {
663 .base = 0xB000,
664 .num_row = 1,
665 .num_col = 24,
666 },
667 [IQS7222_REG_GRP_GPIO] = {
668 .base = 0xC000,
669 .num_row = 3,
670 .num_col = 3,
671 },
672 [IQS7222_REG_GRP_SYS] = {
673 .base = IQS7222_SYS_SETUP,
674 .num_row = 1,
675 .num_col = 12,
676 },
677 },
678 },
679};
680
681struct iqs7222_prop_desc {
682 const char *name;
683 enum iqs7222_reg_grp_id reg_grp;
684 enum iqs7222_reg_key_id reg_key;
685 int reg_offset;
686 int reg_shift;
687 int reg_width;
688 int val_pitch;
689 int val_min;
690 int val_max;
691 bool invert;
692 const char *label;
693};
694
695static const struct iqs7222_prop_desc iqs7222_props[] = {
696 {
697 .name = "azoteq,conv-period",
698 .reg_grp = IQS7222_REG_GRP_CYCLE,
699 .reg_offset = 0,
700 .reg_shift = 8,
701 .reg_width = 8,
702 .label = "conversion period",
703 },
704 {
705 .name = "azoteq,conv-frac",
706 .reg_grp = IQS7222_REG_GRP_CYCLE,
707 .reg_offset = 0,
708 .reg_shift = 0,
709 .reg_width = 8,
710 .label = "conversion frequency fractional divider",
711 },
712 {
713 .name = "azoteq,rx-float-inactive",
714 .reg_grp = IQS7222_REG_GRP_CYCLE,
715 .reg_offset = 1,
716 .reg_shift = 6,
717 .reg_width = 1,
718 .invert = true,
719 },
720 {
721 .name = "azoteq,dead-time-enable",
722 .reg_grp = IQS7222_REG_GRP_CYCLE,
723 .reg_offset = 1,
724 .reg_shift = 5,
725 .reg_width = 1,
726 },
727 {
728 .name = "azoteq,tx-freq-fosc",
729 .reg_grp = IQS7222_REG_GRP_CYCLE,
730 .reg_offset = 1,
731 .reg_shift = 4,
732 .reg_width = 1,
733 },
734 {
735 .name = "azoteq,vbias-enable",
736 .reg_grp = IQS7222_REG_GRP_CYCLE,
737 .reg_offset = 1,
738 .reg_shift = 3,
739 .reg_width = 1,
740 },
741 {
742 .name = "azoteq,sense-mode",
743 .reg_grp = IQS7222_REG_GRP_CYCLE,
744 .reg_offset = 1,
745 .reg_shift = 0,
746 .reg_width = 3,
747 .val_max = 3,
748 .label = "sensing mode",
749 },
750 {
751 .name = "azoteq,iref-enable",
752 .reg_grp = IQS7222_REG_GRP_CYCLE,
753 .reg_offset = 2,
754 .reg_shift = 10,
755 .reg_width = 1,
756 },
757 {
758 .name = "azoteq,iref-level",
759 .reg_grp = IQS7222_REG_GRP_CYCLE,
760 .reg_offset = 2,
761 .reg_shift = 4,
762 .reg_width = 4,
763 .label = "current reference level",
764 },
765 {
766 .name = "azoteq,iref-trim",
767 .reg_grp = IQS7222_REG_GRP_CYCLE,
768 .reg_offset = 2,
769 .reg_shift = 0,
770 .reg_width = 4,
771 .label = "current reference trim",
772 },
773 {
774 .name = "azoteq,max-counts",
775 .reg_grp = IQS7222_REG_GRP_GLBL,
776 .reg_offset = 0,
777 .reg_shift = 13,
778 .reg_width = 2,
779 .label = "maximum counts",
780 },
781 {
782 .name = "azoteq,auto-mode",
783 .reg_grp = IQS7222_REG_GRP_GLBL,
784 .reg_offset = 0,
785 .reg_shift = 2,
786 .reg_width = 2,
787 .label = "number of conversions",
788 },
789 {
790 .name = "azoteq,ati-frac-div-fine",
791 .reg_grp = IQS7222_REG_GRP_GLBL,
792 .reg_offset = 1,
793 .reg_shift = 9,
794 .reg_width = 5,
795 .label = "ATI fine fractional divider",
796 },
797 {
798 .name = "azoteq,ati-frac-div-coarse",
799 .reg_grp = IQS7222_REG_GRP_GLBL,
800 .reg_offset = 1,
801 .reg_shift = 0,
802 .reg_width = 5,
803 .label = "ATI coarse fractional divider",
804 },
805 {
806 .name = "azoteq,ati-comp-select",
807 .reg_grp = IQS7222_REG_GRP_GLBL,
808 .reg_offset = 2,
809 .reg_shift = 0,
810 .reg_width = 10,
811 .label = "ATI compensation selection",
812 },
813 {
814 .name = "azoteq,ati-band",
815 .reg_grp = IQS7222_REG_GRP_CHAN,
816 .reg_offset = 0,
817 .reg_shift = 12,
818 .reg_width = 2,
819 .label = "ATI band",
820 },
821 {
822 .name = "azoteq,global-halt",
823 .reg_grp = IQS7222_REG_GRP_CHAN,
824 .reg_offset = 0,
825 .reg_shift = 11,
826 .reg_width = 1,
827 },
828 {
829 .name = "azoteq,invert-enable",
830 .reg_grp = IQS7222_REG_GRP_CHAN,
831 .reg_offset = 0,
832 .reg_shift = 10,
833 .reg_width = 1,
834 },
835 {
836 .name = "azoteq,dual-direction",
837 .reg_grp = IQS7222_REG_GRP_CHAN,
838 .reg_offset = 0,
839 .reg_shift = 9,
840 .reg_width = 1,
841 },
842 {
843 .name = "azoteq,samp-cap-double",
844 .reg_grp = IQS7222_REG_GRP_CHAN,
845 .reg_offset = 0,
846 .reg_shift = 3,
847 .reg_width = 1,
848 },
849 {
850 .name = "azoteq,vref-half",
851 .reg_grp = IQS7222_REG_GRP_CHAN,
852 .reg_offset = 0,
853 .reg_shift = 2,
854 .reg_width = 1,
855 },
856 {
857 .name = "azoteq,proj-bias",
858 .reg_grp = IQS7222_REG_GRP_CHAN,
859 .reg_offset = 0,
860 .reg_shift = 0,
861 .reg_width = 2,
862 .label = "projected bias current",
863 },
864 {
865 .name = "azoteq,ati-target",
866 .reg_grp = IQS7222_REG_GRP_CHAN,
867 .reg_offset = 1,
868 .reg_shift = 8,
869 .reg_width = 8,
870 .val_pitch = 8,
871 .label = "ATI target",
872 },
873 {
874 .name = "azoteq,ati-base",
875 .reg_grp = IQS7222_REG_GRP_CHAN,
876 .reg_offset = 1,
877 .reg_shift = 3,
878 .reg_width = 5,
879 .val_pitch = 16,
880 .label = "ATI base",
881 },
882 {
883 .name = "azoteq,ati-mode",
884 .reg_grp = IQS7222_REG_GRP_CHAN,
885 .reg_offset = 1,
886 .reg_shift = 0,
887 .reg_width = 3,
888 .val_max = 5,
889 .label = "ATI mode",
890 },
891 {
892 .name = "azoteq,ati-frac-div-fine",
893 .reg_grp = IQS7222_REG_GRP_CHAN,
894 .reg_offset = 2,
895 .reg_shift = 9,
896 .reg_width = 5,
897 .label = "ATI fine fractional divider",
898 },
899 {
900 .name = "azoteq,ati-frac-mult-coarse",
901 .reg_grp = IQS7222_REG_GRP_CHAN,
902 .reg_offset = 2,
903 .reg_shift = 5,
904 .reg_width = 4,
905 .label = "ATI coarse fractional multiplier",
906 },
907 {
908 .name = "azoteq,ati-frac-div-coarse",
909 .reg_grp = IQS7222_REG_GRP_CHAN,
910 .reg_offset = 2,
911 .reg_shift = 0,
912 .reg_width = 5,
913 .label = "ATI coarse fractional divider",
914 },
915 {
916 .name = "azoteq,ati-comp-div",
917 .reg_grp = IQS7222_REG_GRP_CHAN,
918 .reg_offset = 3,
919 .reg_shift = 11,
920 .reg_width = 5,
921 .label = "ATI compensation divider",
922 },
923 {
924 .name = "azoteq,ati-comp-select",
925 .reg_grp = IQS7222_REG_GRP_CHAN,
926 .reg_offset = 3,
927 .reg_shift = 0,
928 .reg_width = 10,
929 .label = "ATI compensation selection",
930 },
931 {
932 .name = "azoteq,debounce-exit",
933 .reg_grp = IQS7222_REG_GRP_BTN,
934 .reg_key = IQS7222_REG_KEY_DEBOUNCE,
935 .reg_offset = 0,
936 .reg_shift = 12,
937 .reg_width = 4,
938 .label = "debounce exit factor",
939 },
940 {
941 .name = "azoteq,debounce-enter",
942 .reg_grp = IQS7222_REG_GRP_BTN,
943 .reg_key = IQS7222_REG_KEY_DEBOUNCE,
944 .reg_offset = 0,
945 .reg_shift = 8,
946 .reg_width = 4,
947 .label = "debounce entrance factor",
948 },
949 {
950 .name = "azoteq,thresh",
951 .reg_grp = IQS7222_REG_GRP_BTN,
952 .reg_key = IQS7222_REG_KEY_PROX,
953 .reg_offset = 0,
954 .reg_shift = 0,
955 .reg_width = 8,
956 .val_max = 127,
957 .label = "threshold",
958 },
959 {
960 .name = "azoteq,thresh",
961 .reg_grp = IQS7222_REG_GRP_BTN,
962 .reg_key = IQS7222_REG_KEY_TOUCH,
963 .reg_offset = 1,
964 .reg_shift = 0,
965 .reg_width = 8,
966 .label = "threshold",
967 },
968 {
969 .name = "azoteq,hyst",
970 .reg_grp = IQS7222_REG_GRP_BTN,
971 .reg_key = IQS7222_REG_KEY_TOUCH,
972 .reg_offset = 1,
973 .reg_shift = 8,
974 .reg_width = 8,
975 .label = "hysteresis",
976 },
977 {
978 .name = "azoteq,lta-beta-lp",
979 .reg_grp = IQS7222_REG_GRP_FILT,
980 .reg_offset = 0,
981 .reg_shift = 12,
982 .reg_width = 4,
983 .label = "low-power mode long-term average beta",
984 },
985 {
986 .name = "azoteq,lta-beta-np",
987 .reg_grp = IQS7222_REG_GRP_FILT,
988 .reg_offset = 0,
989 .reg_shift = 8,
990 .reg_width = 4,
991 .label = "normal-power mode long-term average beta",
992 },
993 {
994 .name = "azoteq,counts-beta-lp",
995 .reg_grp = IQS7222_REG_GRP_FILT,
996 .reg_offset = 0,
997 .reg_shift = 4,
998 .reg_width = 4,
999 .label = "low-power mode counts beta",
1000 },
1001 {
1002 .name = "azoteq,counts-beta-np",
1003 .reg_grp = IQS7222_REG_GRP_FILT,
1004 .reg_offset = 0,
1005 .reg_shift = 0,
1006 .reg_width = 4,
1007 .label = "normal-power mode counts beta",
1008 },
1009 {
1010 .name = "azoteq,lta-fast-beta-lp",
1011 .reg_grp = IQS7222_REG_GRP_FILT,
1012 .reg_offset = 1,
1013 .reg_shift = 4,
1014 .reg_width = 4,
1015 .label = "low-power mode long-term average fast beta",
1016 },
1017 {
1018 .name = "azoteq,lta-fast-beta-np",
1019 .reg_grp = IQS7222_REG_GRP_FILT,
1020 .reg_offset = 1,
1021 .reg_shift = 0,
1022 .reg_width = 4,
1023 .label = "normal-power mode long-term average fast beta",
1024 },
1025 {
1026 .name = "azoteq,lower-cal",
1027 .reg_grp = IQS7222_REG_GRP_SLDR,
1028 .reg_offset = 0,
1029 .reg_shift = 8,
1030 .reg_width = 8,
1031 .label = "lower calibration",
1032 },
1033 {
1034 .name = "azoteq,static-beta",
1035 .reg_grp = IQS7222_REG_GRP_SLDR,
1036 .reg_key = IQS7222_REG_KEY_NO_WHEEL,
1037 .reg_offset = 0,
1038 .reg_shift = 6,
1039 .reg_width = 1,
1040 },
1041 {
1042 .name = "azoteq,bottom-beta",
1043 .reg_grp = IQS7222_REG_GRP_SLDR,
1044 .reg_key = IQS7222_REG_KEY_NO_WHEEL,
1045 .reg_offset = 0,
1046 .reg_shift = 3,
1047 .reg_width = 3,
1048 .label = "bottom beta",
1049 },
1050 {
1051 .name = "azoteq,static-beta",
1052 .reg_grp = IQS7222_REG_GRP_SLDR,
1053 .reg_key = IQS7222_REG_KEY_WHEEL,
1054 .reg_offset = 0,
1055 .reg_shift = 7,
1056 .reg_width = 1,
1057 },
1058 {
1059 .name = "azoteq,bottom-beta",
1060 .reg_grp = IQS7222_REG_GRP_SLDR,
1061 .reg_key = IQS7222_REG_KEY_WHEEL,
1062 .reg_offset = 0,
1063 .reg_shift = 4,
1064 .reg_width = 3,
1065 .label = "bottom beta",
1066 },
1067 {
1068 .name = "azoteq,bottom-speed",
1069 .reg_grp = IQS7222_REG_GRP_SLDR,
1070 .reg_offset = 1,
1071 .reg_shift = 8,
1072 .reg_width = 8,
1073 .label = "bottom speed",
1074 },
1075 {
1076 .name = "azoteq,upper-cal",
1077 .reg_grp = IQS7222_REG_GRP_SLDR,
1078 .reg_offset = 1,
1079 .reg_shift = 0,
1080 .reg_width = 8,
1081 .label = "upper calibration",
1082 },
1083 {
1084 .name = "azoteq,gesture-max-ms",
1085 .reg_grp = IQS7222_REG_GRP_SLDR,
1086 .reg_key = IQS7222_REG_KEY_TAP,
1087 .reg_offset = 9,
1088 .reg_shift = 8,
1089 .reg_width = 8,
1090 .val_pitch = 16,
1091 .label = "maximum gesture time",
1092 },
1093 {
1094 .name = "azoteq,gesture-max-ms",
1095 .reg_grp = IQS7222_REG_GRP_SLDR,
1096 .reg_key = IQS7222_REG_KEY_TAP_LEGACY,
1097 .reg_offset = 9,
1098 .reg_shift = 8,
1099 .reg_width = 8,
1100 .val_pitch = 4,
1101 .label = "maximum gesture time",
1102 },
1103 {
1104 .name = "azoteq,gesture-min-ms",
1105 .reg_grp = IQS7222_REG_GRP_SLDR,
1106 .reg_key = IQS7222_REG_KEY_TAP,
1107 .reg_offset = 9,
1108 .reg_shift = 3,
1109 .reg_width = 5,
1110 .val_pitch = 16,
1111 .label = "minimum gesture time",
1112 },
1113 {
1114 .name = "azoteq,gesture-min-ms",
1115 .reg_grp = IQS7222_REG_GRP_SLDR,
1116 .reg_key = IQS7222_REG_KEY_TAP_LEGACY,
1117 .reg_offset = 9,
1118 .reg_shift = 3,
1119 .reg_width = 5,
1120 .val_pitch = 4,
1121 .label = "minimum gesture time",
1122 },
1123 {
1124 .name = "azoteq,gesture-dist",
1125 .reg_grp = IQS7222_REG_GRP_SLDR,
1126 .reg_key = IQS7222_REG_KEY_AXIAL,
1127 .reg_offset = 10,
1128 .reg_shift = 8,
1129 .reg_width = 8,
1130 .val_pitch = 16,
1131 .label = "gesture distance",
1132 },
1133 {
1134 .name = "azoteq,gesture-dist",
1135 .reg_grp = IQS7222_REG_GRP_SLDR,
1136 .reg_key = IQS7222_REG_KEY_AXIAL_LEGACY,
1137 .reg_offset = 10,
1138 .reg_shift = 8,
1139 .reg_width = 8,
1140 .val_pitch = 16,
1141 .label = "gesture distance",
1142 },
1143 {
1144 .name = "azoteq,gesture-max-ms",
1145 .reg_grp = IQS7222_REG_GRP_SLDR,
1146 .reg_key = IQS7222_REG_KEY_AXIAL,
1147 .reg_offset = 10,
1148 .reg_shift = 0,
1149 .reg_width = 8,
1150 .val_pitch = 16,
1151 .label = "maximum gesture time",
1152 },
1153 {
1154 .name = "azoteq,gesture-max-ms",
1155 .reg_grp = IQS7222_REG_GRP_SLDR,
1156 .reg_key = IQS7222_REG_KEY_AXIAL_LEGACY,
1157 .reg_offset = 10,
1158 .reg_shift = 0,
1159 .reg_width = 8,
1160 .val_pitch = 4,
1161 .label = "maximum gesture time",
1162 },
1163 {
1164 .name = "azoteq,num-rows",
1165 .reg_grp = IQS7222_REG_GRP_TPAD,
1166 .reg_offset = 0,
1167 .reg_shift = 4,
1168 .reg_width = 4,
1169 .val_min = 1,
1170 .val_max = 12,
1171 .label = "number of rows",
1172 },
1173 {
1174 .name = "azoteq,num-cols",
1175 .reg_grp = IQS7222_REG_GRP_TPAD,
1176 .reg_offset = 0,
1177 .reg_shift = 0,
1178 .reg_width = 4,
1179 .val_min = 1,
1180 .val_max = 12,
1181 .label = "number of columns",
1182 },
1183 {
1184 .name = "azoteq,lower-cal-y",
1185 .reg_grp = IQS7222_REG_GRP_TPAD,
1186 .reg_offset = 1,
1187 .reg_shift = 8,
1188 .reg_width = 8,
1189 .label = "lower vertical calibration",
1190 },
1191 {
1192 .name = "azoteq,lower-cal-x",
1193 .reg_grp = IQS7222_REG_GRP_TPAD,
1194 .reg_offset = 1,
1195 .reg_shift = 0,
1196 .reg_width = 8,
1197 .label = "lower horizontal calibration",
1198 },
1199 {
1200 .name = "azoteq,upper-cal-y",
1201 .reg_grp = IQS7222_REG_GRP_TPAD,
1202 .reg_offset = 2,
1203 .reg_shift = 8,
1204 .reg_width = 8,
1205 .label = "upper vertical calibration",
1206 },
1207 {
1208 .name = "azoteq,upper-cal-x",
1209 .reg_grp = IQS7222_REG_GRP_TPAD,
1210 .reg_offset = 2,
1211 .reg_shift = 0,
1212 .reg_width = 8,
1213 .label = "upper horizontal calibration",
1214 },
1215 {
1216 .name = "azoteq,top-speed",
1217 .reg_grp = IQS7222_REG_GRP_TPAD,
1218 .reg_offset = 3,
1219 .reg_shift = 8,
1220 .reg_width = 8,
1221 .val_pitch = 4,
1222 .label = "top speed",
1223 },
1224 {
1225 .name = "azoteq,bottom-speed",
1226 .reg_grp = IQS7222_REG_GRP_TPAD,
1227 .reg_offset = 3,
1228 .reg_shift = 0,
1229 .reg_width = 8,
1230 .label = "bottom speed",
1231 },
1232 {
1233 .name = "azoteq,gesture-min-ms",
1234 .reg_grp = IQS7222_REG_GRP_TPAD,
1235 .reg_key = IQS7222_REG_KEY_TAP,
1236 .reg_offset = 20,
1237 .reg_shift = 8,
1238 .reg_width = 8,
1239 .val_pitch = 16,
1240 .label = "minimum gesture time",
1241 },
1242 {
1243 .name = "azoteq,gesture-max-ms",
1244 .reg_grp = IQS7222_REG_GRP_TPAD,
1245 .reg_key = IQS7222_REG_KEY_AXIAL,
1246 .reg_offset = 21,
1247 .reg_shift = 8,
1248 .reg_width = 8,
1249 .val_pitch = 16,
1250 .label = "maximum gesture time",
1251 },
1252 {
1253 .name = "azoteq,gesture-max-ms",
1254 .reg_grp = IQS7222_REG_GRP_TPAD,
1255 .reg_key = IQS7222_REG_KEY_TAP,
1256 .reg_offset = 21,
1257 .reg_shift = 0,
1258 .reg_width = 8,
1259 .val_pitch = 16,
1260 .label = "maximum gesture time",
1261 },
1262 {
1263 .name = "azoteq,gesture-dist",
1264 .reg_grp = IQS7222_REG_GRP_TPAD,
1265 .reg_key = IQS7222_REG_KEY_TAP,
1266 .reg_offset = 22,
1267 .reg_shift = 0,
1268 .reg_width = 16,
1269 .label = "gesture distance",
1270 },
1271 {
1272 .name = "azoteq,gesture-dist",
1273 .reg_grp = IQS7222_REG_GRP_TPAD,
1274 .reg_key = IQS7222_REG_KEY_AXIAL,
1275 .reg_offset = 23,
1276 .reg_shift = 0,
1277 .reg_width = 16,
1278 .label = "gesture distance",
1279 },
1280 {
1281 .name = "drive-open-drain",
1282 .reg_grp = IQS7222_REG_GRP_GPIO,
1283 .reg_offset = 0,
1284 .reg_shift = 1,
1285 .reg_width = 1,
1286 },
1287 {
1288 .name = "azoteq,timeout-ati-ms",
1289 .reg_grp = IQS7222_REG_GRP_SYS,
1290 .reg_offset = 1,
1291 .reg_shift = 0,
1292 .reg_width = 16,
1293 .val_pitch = 500,
1294 .label = "ATI error timeout",
1295 },
1296 {
1297 .name = "azoteq,rate-ati-ms",
1298 .reg_grp = IQS7222_REG_GRP_SYS,
1299 .reg_offset = 2,
1300 .reg_shift = 0,
1301 .reg_width = 16,
1302 .label = "ATI report rate",
1303 },
1304 {
1305 .name = "azoteq,timeout-np-ms",
1306 .reg_grp = IQS7222_REG_GRP_SYS,
1307 .reg_offset = 3,
1308 .reg_shift = 0,
1309 .reg_width = 16,
1310 .label = "normal-power mode timeout",
1311 },
1312 {
1313 .name = "azoteq,rate-np-ms",
1314 .reg_grp = IQS7222_REG_GRP_SYS,
1315 .reg_offset = 4,
1316 .reg_shift = 0,
1317 .reg_width = 16,
1318 .val_max = 3000,
1319 .label = "normal-power mode report rate",
1320 },
1321 {
1322 .name = "azoteq,timeout-lp-ms",
1323 .reg_grp = IQS7222_REG_GRP_SYS,
1324 .reg_offset = 5,
1325 .reg_shift = 0,
1326 .reg_width = 16,
1327 .label = "low-power mode timeout",
1328 },
1329 {
1330 .name = "azoteq,rate-lp-ms",
1331 .reg_grp = IQS7222_REG_GRP_SYS,
1332 .reg_offset = 6,
1333 .reg_shift = 0,
1334 .reg_width = 16,
1335 .val_max = 3000,
1336 .label = "low-power mode report rate",
1337 },
1338 {
1339 .name = "azoteq,timeout-ulp-ms",
1340 .reg_grp = IQS7222_REG_GRP_SYS,
1341 .reg_offset = 7,
1342 .reg_shift = 0,
1343 .reg_width = 16,
1344 .label = "ultra-low-power mode timeout",
1345 },
1346 {
1347 .name = "azoteq,rate-ulp-ms",
1348 .reg_grp = IQS7222_REG_GRP_SYS,
1349 .reg_offset = 8,
1350 .reg_shift = 0,
1351 .reg_width = 16,
1352 .val_max = 3000,
1353 .label = "ultra-low-power mode report rate",
1354 },
1355};
1356
1357struct iqs7222_private {
1358 const struct iqs7222_dev_desc *dev_desc;
1359 struct gpio_desc *reset_gpio;
1360 struct gpio_desc *irq_gpio;
1361 struct i2c_client *client;
1362 struct input_dev *keypad;
1363 struct touchscreen_properties prop;
1364 unsigned int kp_type[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)];
1365 unsigned int kp_code[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)];
1366 unsigned int sl_code[IQS7222_MAX_SLDR][ARRAY_SIZE(iqs7222_sl_events)];
1367 unsigned int sl_axis[IQS7222_MAX_SLDR];
1368 unsigned int tp_code[ARRAY_SIZE(iqs7222_tp_events)];
1369 u16 cycle_setup[IQS7222_MAX_CHAN / 2][IQS7222_MAX_COLS_CYCLE];
1370 u16 glbl_setup[IQS7222_MAX_COLS_GLBL];
1371 u16 btn_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_BTN];
1372 u16 chan_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_CHAN];
1373 u16 filt_setup[IQS7222_MAX_COLS_FILT];
1374 u16 sldr_setup[IQS7222_MAX_SLDR][IQS7222_MAX_COLS_SLDR];
1375 u16 tpad_setup[IQS7222_MAX_COLS_TPAD];
1376 u16 gpio_setup[ARRAY_SIZE(iqs7222_gpio_links)][IQS7222_MAX_COLS_GPIO];
1377 u16 sys_setup[IQS7222_MAX_COLS_SYS];
1378};
1379
1380static u16 *iqs7222_setup(struct iqs7222_private *iqs7222,
1381 enum iqs7222_reg_grp_id reg_grp, int row)
1382{
1383 switch (reg_grp) {
1384 case IQS7222_REG_GRP_CYCLE:
1385 return iqs7222->cycle_setup[row];
1386
1387 case IQS7222_REG_GRP_GLBL:
1388 return iqs7222->glbl_setup;
1389
1390 case IQS7222_REG_GRP_BTN:
1391 return iqs7222->btn_setup[row];
1392
1393 case IQS7222_REG_GRP_CHAN:
1394 return iqs7222->chan_setup[row];
1395
1396 case IQS7222_REG_GRP_FILT:
1397 return iqs7222->filt_setup;
1398
1399 case IQS7222_REG_GRP_SLDR:
1400 return iqs7222->sldr_setup[row];
1401
1402 case IQS7222_REG_GRP_TPAD:
1403 return iqs7222->tpad_setup;
1404
1405 case IQS7222_REG_GRP_GPIO:
1406 return iqs7222->gpio_setup[row];
1407
1408 case IQS7222_REG_GRP_SYS:
1409 return iqs7222->sys_setup;
1410
1411 default:
1412 return NULL;
1413 }
1414}
1415
1416static int iqs7222_irq_poll(struct iqs7222_private *iqs7222, u16 timeout_ms)
1417{
1418 ktime_t irq_timeout = ktime_add_ms(ktime_get(), timeout_ms);
1419 int ret;
1420
1421 do {
1422 usleep_range(1000, 1100);
1423
1424 ret = gpiod_get_value_cansleep(iqs7222->irq_gpio);
1425 if (ret < 0)
1426 return ret;
1427 else if (ret > 0)
1428 return 0;
1429 } while (ktime_compare(ktime_get(), irq_timeout) < 0);
1430
1431 return -EBUSY;
1432}
1433
1434static int iqs7222_hard_reset(struct iqs7222_private *iqs7222)
1435{
1436 struct i2c_client *client = iqs7222->client;
1437 int error;
1438
1439 if (!iqs7222->reset_gpio)
1440 return 0;
1441
1442 gpiod_set_value_cansleep(iqs7222->reset_gpio, 1);
1443 usleep_range(1000, 1100);
1444
1445 gpiod_set_value_cansleep(iqs7222->reset_gpio, 0);
1446
1447 error = iqs7222_irq_poll(iqs7222, IQS7222_RESET_TIMEOUT_MS);
1448 if (error)
1449 dev_err(&client->dev, "Failed to reset device: %d\n", error);
1450
1451 return error;
1452}
1453
1454static int iqs7222_force_comms(struct iqs7222_private *iqs7222)
1455{
1456 u8 msg_buf[] = { 0xFF, };
1457 int ret;
1458
1459 /*
1460 * The device cannot communicate until it asserts its interrupt (RDY)
1461 * pin. Attempts to do so while RDY is deasserted return an ACK; how-
1462 * ever all write data is ignored, and all read data returns 0xEE.
1463 *
1464 * Unsolicited communication must be preceded by a special force com-
1465 * munication command, after which the device eventually asserts its
1466 * RDY pin and agrees to communicate.
1467 *
1468 * Regardless of whether communication is forced or the result of an
1469 * interrupt, the device automatically deasserts its RDY pin once it
1470 * detects an I2C stop condition, or a timeout expires.
1471 */
1472 ret = gpiod_get_value_cansleep(iqs7222->irq_gpio);
1473 if (ret < 0)
1474 return ret;
1475 else if (ret > 0)
1476 return 0;
1477
1478 ret = i2c_master_send(iqs7222->client, msg_buf, sizeof(msg_buf));
1479 if (ret < (int)sizeof(msg_buf)) {
1480 if (ret >= 0)
1481 ret = -EIO;
1482
1483 /*
1484 * The datasheet states that the host must wait to retry any
1485 * failed attempt to communicate over I2C.
1486 */
1487 msleep(IQS7222_COMMS_RETRY_MS);
1488 return ret;
1489 }
1490
1491 return iqs7222_irq_poll(iqs7222, IQS7222_COMMS_TIMEOUT_MS);
1492}
1493
1494static int iqs7222_read_burst(struct iqs7222_private *iqs7222,
1495 u16 reg, void *val, u16 num_val)
1496{
1497 u8 reg_buf[sizeof(__be16)];
1498 int ret, i;
1499 struct i2c_client *client = iqs7222->client;
1500 struct i2c_msg msg[] = {
1501 {
1502 .addr = client->addr,
1503 .flags = 0,
1504 .len = reg > U8_MAX ? sizeof(reg) : sizeof(u8),
1505 .buf = reg_buf,
1506 },
1507 {
1508 .addr = client->addr,
1509 .flags = I2C_M_RD,
1510 .len = num_val * sizeof(__le16),
1511 .buf = (u8 *)val,
1512 },
1513 };
1514
1515 if (reg > U8_MAX)
1516 put_unaligned_be16(reg, reg_buf);
1517 else
1518 *reg_buf = (u8)reg;
1519
1520 /*
1521 * The following loop protects against an edge case in which the RDY
1522 * pin is automatically deasserted just as the read is initiated. In
1523 * that case, the read must be retried using forced communication.
1524 */
1525 for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1526 ret = iqs7222_force_comms(iqs7222);
1527 if (ret < 0)
1528 continue;
1529
1530 ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
1531 if (ret < (int)ARRAY_SIZE(msg)) {
1532 if (ret >= 0)
1533 ret = -EIO;
1534
1535 msleep(IQS7222_COMMS_RETRY_MS);
1536 continue;
1537 }
1538
1539 if (get_unaligned_le16(msg[1].buf) == IQS7222_COMMS_ERROR) {
1540 ret = -ENODATA;
1541 continue;
1542 }
1543
1544 ret = 0;
1545 break;
1546 }
1547
1548 /*
1549 * The following delay ensures the device has deasserted the RDY pin
1550 * following the I2C stop condition.
1551 */
1552 usleep_range(50, 100);
1553
1554 if (ret < 0)
1555 dev_err(&client->dev,
1556 "Failed to read from address 0x%04X: %d\n", reg, ret);
1557
1558 return ret;
1559}
1560
1561static int iqs7222_read_word(struct iqs7222_private *iqs7222, u16 reg, u16 *val)
1562{
1563 __le16 val_buf;
1564 int error;
1565
1566 error = iqs7222_read_burst(iqs7222, reg, &val_buf, 1);
1567 if (error)
1568 return error;
1569
1570 *val = le16_to_cpu(val_buf);
1571
1572 return 0;
1573}
1574
1575static int iqs7222_write_burst(struct iqs7222_private *iqs7222,
1576 u16 reg, const void *val, u16 num_val)
1577{
1578 int reg_len = reg > U8_MAX ? sizeof(reg) : sizeof(u8);
1579 int val_len = num_val * sizeof(__le16);
1580 int msg_len = reg_len + val_len;
1581 int ret, i;
1582 struct i2c_client *client = iqs7222->client;
1583 u8 *msg_buf;
1584
1585 msg_buf = kzalloc(msg_len, GFP_KERNEL);
1586 if (!msg_buf)
1587 return -ENOMEM;
1588
1589 if (reg > U8_MAX)
1590 put_unaligned_be16(reg, msg_buf);
1591 else
1592 *msg_buf = (u8)reg;
1593
1594 memcpy(msg_buf + reg_len, val, val_len);
1595
1596 /*
1597 * The following loop protects against an edge case in which the RDY
1598 * pin is automatically asserted just before the force communication
1599 * command is sent.
1600 *
1601 * In that case, the subsequent I2C stop condition tricks the device
1602 * into preemptively deasserting the RDY pin and the command must be
1603 * sent again.
1604 */
1605 for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1606 ret = iqs7222_force_comms(iqs7222);
1607 if (ret < 0)
1608 continue;
1609
1610 ret = i2c_master_send(client, msg_buf, msg_len);
1611 if (ret < msg_len) {
1612 if (ret >= 0)
1613 ret = -EIO;
1614
1615 msleep(IQS7222_COMMS_RETRY_MS);
1616 continue;
1617 }
1618
1619 ret = 0;
1620 break;
1621 }
1622
1623 kfree(msg_buf);
1624
1625 usleep_range(50, 100);
1626
1627 if (ret < 0)
1628 dev_err(&client->dev,
1629 "Failed to write to address 0x%04X: %d\n", reg, ret);
1630
1631 return ret;
1632}
1633
1634static int iqs7222_write_word(struct iqs7222_private *iqs7222, u16 reg, u16 val)
1635{
1636 __le16 val_buf = cpu_to_le16(val);
1637
1638 return iqs7222_write_burst(iqs7222, reg, &val_buf, 1);
1639}
1640
1641static int iqs7222_ati_trigger(struct iqs7222_private *iqs7222)
1642{
1643 struct i2c_client *client = iqs7222->client;
1644 ktime_t ati_timeout;
1645 u16 sys_status = 0;
1646 u16 sys_setup;
1647 int error, i;
1648
1649 /*
1650 * The reserved fields of the system setup register may have changed
1651 * as a result of other registers having been written. As such, read
1652 * the register's latest value to avoid unexpected behavior when the
1653 * register is written in the loop that follows.
1654 */
1655 error = iqs7222_read_word(iqs7222, IQS7222_SYS_SETUP, &sys_setup);
1656 if (error)
1657 return error;
1658
1659 for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1660 /*
1661 * Trigger ATI from streaming and normal-power modes so that
1662 * the RDY pin continues to be asserted during ATI.
1663 */
1664 error = iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP,
1665 sys_setup |
1666 IQS7222_SYS_SETUP_REDO_ATI);
1667 if (error)
1668 return error;
1669
1670 ati_timeout = ktime_add_ms(ktime_get(), IQS7222_ATI_TIMEOUT_MS);
1671
1672 do {
1673 error = iqs7222_irq_poll(iqs7222,
1674 IQS7222_COMMS_TIMEOUT_MS);
1675 if (error)
1676 continue;
1677
1678 error = iqs7222_read_word(iqs7222, IQS7222_SYS_STATUS,
1679 &sys_status);
1680 if (error)
1681 return error;
1682
1683 if (sys_status & IQS7222_SYS_STATUS_RESET)
1684 return 0;
1685
1686 if (sys_status & IQS7222_SYS_STATUS_ATI_ERROR)
1687 break;
1688
1689 if (sys_status & IQS7222_SYS_STATUS_ATI_ACTIVE)
1690 continue;
1691
1692 /*
1693 * Use stream-in-touch mode if either slider reports
1694 * absolute position.
1695 */
1696 sys_setup |= test_bit(EV_ABS, iqs7222->keypad->evbit)
1697 ? IQS7222_SYS_SETUP_INTF_MODE_TOUCH
1698 : IQS7222_SYS_SETUP_INTF_MODE_EVENT;
1699 sys_setup |= IQS7222_SYS_SETUP_PWR_MODE_AUTO;
1700
1701 return iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP,
1702 sys_setup);
1703 } while (ktime_compare(ktime_get(), ati_timeout) < 0);
1704
1705 dev_err(&client->dev,
1706 "ATI attempt %d of %d failed with status 0x%02X, %s\n",
1707 i + 1, IQS7222_NUM_RETRIES, (u8)sys_status,
1708 i + 1 < IQS7222_NUM_RETRIES ? "retrying" : "stopping");
1709 }
1710
1711 return -ETIMEDOUT;
1712}
1713
1714static int iqs7222_dev_init(struct iqs7222_private *iqs7222, int dir)
1715{
1716 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
1717 int comms_offset = dev_desc->comms_offset;
1718 int error, i, j, k;
1719
1720 /*
1721 * Acknowledge reset before writing any registers in case the device
1722 * suffers a spurious reset during initialization. Because this step
1723 * may change the reserved fields of the second filter beta register,
1724 * its cache must be updated.
1725 *
1726 * Writing the second filter beta register, in turn, may clobber the
1727 * system status register. As such, the filter beta register pair is
1728 * written first to protect against this hazard.
1729 */
1730 if (dir == WRITE) {
1731 u16 reg = dev_desc->reg_grps[IQS7222_REG_GRP_FILT].base + 1;
1732 u16 filt_setup;
1733
1734 error = iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP,
1735 iqs7222->sys_setup[0] |
1736 IQS7222_SYS_SETUP_ACK_RESET);
1737 if (error)
1738 return error;
1739
1740 error = iqs7222_read_word(iqs7222, reg, &filt_setup);
1741 if (error)
1742 return error;
1743
1744 iqs7222->filt_setup[1] &= GENMASK(7, 0);
1745 iqs7222->filt_setup[1] |= (filt_setup & ~GENMASK(7, 0));
1746 }
1747
1748 /*
1749 * Take advantage of the stop-bit disable function, if available, to
1750 * save the trouble of having to reopen a communication window after
1751 * each burst read or write.
1752 */
1753 if (comms_offset) {
1754 u16 comms_setup;
1755
1756 error = iqs7222_read_word(iqs7222,
1757 IQS7222_SYS_SETUP + comms_offset,
1758 &comms_setup);
1759 if (error)
1760 return error;
1761
1762 error = iqs7222_write_word(iqs7222,
1763 IQS7222_SYS_SETUP + comms_offset,
1764 comms_setup | IQS7222_COMMS_HOLD);
1765 if (error)
1766 return error;
1767 }
1768
1769 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) {
1770 int num_row = dev_desc->reg_grps[i].num_row;
1771 int num_col = dev_desc->reg_grps[i].num_col;
1772 u16 reg = dev_desc->reg_grps[i].base;
1773 __le16 *val_buf;
1774 u16 *val;
1775
1776 if (!num_col)
1777 continue;
1778
1779 val = iqs7222_setup(iqs7222, i, 0);
1780 if (!val)
1781 continue;
1782
1783 val_buf = kcalloc(num_col, sizeof(__le16), GFP_KERNEL);
1784 if (!val_buf)
1785 return -ENOMEM;
1786
1787 for (j = 0; j < num_row; j++) {
1788 switch (dir) {
1789 case READ:
1790 error = iqs7222_read_burst(iqs7222, reg,
1791 val_buf, num_col);
1792 for (k = 0; k < num_col; k++)
1793 val[k] = le16_to_cpu(val_buf[k]);
1794 break;
1795
1796 case WRITE:
1797 for (k = 0; k < num_col; k++)
1798 val_buf[k] = cpu_to_le16(val[k]);
1799 error = iqs7222_write_burst(iqs7222, reg,
1800 val_buf, num_col);
1801 break;
1802
1803 default:
1804 error = -EINVAL;
1805 }
1806
1807 if (error)
1808 break;
1809
1810 reg += IQS7222_REG_OFFSET;
1811 val += iqs7222_max_cols[i];
1812 }
1813
1814 kfree(val_buf);
1815
1816 if (error)
1817 return error;
1818 }
1819
1820 if (comms_offset) {
1821 u16 comms_setup;
1822
1823 error = iqs7222_read_word(iqs7222,
1824 IQS7222_SYS_SETUP + comms_offset,
1825 &comms_setup);
1826 if (error)
1827 return error;
1828
1829 error = iqs7222_write_word(iqs7222,
1830 IQS7222_SYS_SETUP + comms_offset,
1831 comms_setup & ~IQS7222_COMMS_HOLD);
1832 if (error)
1833 return error;
1834 }
1835
1836 if (dir == READ) {
1837 iqs7222->sys_setup[0] &= ~IQS7222_SYS_SETUP_INTF_MODE_MASK;
1838 iqs7222->sys_setup[0] &= ~IQS7222_SYS_SETUP_PWR_MODE_MASK;
1839 return 0;
1840 }
1841
1842 return iqs7222_ati_trigger(iqs7222);
1843}
1844
1845static int iqs7222_dev_info(struct iqs7222_private *iqs7222)
1846{
1847 struct i2c_client *client = iqs7222->client;
1848 bool prod_num_valid = false;
1849 __le16 dev_id[3];
1850 int error, i;
1851
1852 error = iqs7222_read_burst(iqs7222, IQS7222_PROD_NUM, dev_id,
1853 ARRAY_SIZE(dev_id));
1854 if (error)
1855 return error;
1856
1857 for (i = 0; i < ARRAY_SIZE(iqs7222_devs); i++) {
1858 if (le16_to_cpu(dev_id[0]) != iqs7222_devs[i].prod_num)
1859 continue;
1860
1861 prod_num_valid = true;
1862
1863 if (le16_to_cpu(dev_id[1]) < iqs7222_devs[i].fw_major)
1864 continue;
1865
1866 if (le16_to_cpu(dev_id[2]) < iqs7222_devs[i].fw_minor)
1867 continue;
1868
1869 iqs7222->dev_desc = &iqs7222_devs[i];
1870 return 0;
1871 }
1872
1873 if (prod_num_valid)
1874 dev_err(&client->dev, "Unsupported firmware revision: %u.%u\n",
1875 le16_to_cpu(dev_id[1]), le16_to_cpu(dev_id[2]));
1876 else
1877 dev_err(&client->dev, "Unrecognized product number: %u\n",
1878 le16_to_cpu(dev_id[0]));
1879
1880 return -EINVAL;
1881}
1882
1883static int iqs7222_gpio_select(struct iqs7222_private *iqs7222,
1884 struct fwnode_handle *child_node,
1885 int child_enable, u16 child_link)
1886{
1887 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
1888 struct i2c_client *client = iqs7222->client;
1889 int num_gpio = dev_desc->reg_grps[IQS7222_REG_GRP_GPIO].num_row;
1890 int error, count, i;
1891 unsigned int gpio_sel[ARRAY_SIZE(iqs7222_gpio_links)];
1892
1893 if (!num_gpio)
1894 return 0;
1895
1896 if (!fwnode_property_present(child_node, "azoteq,gpio-select"))
1897 return 0;
1898
1899 count = fwnode_property_count_u32(child_node, "azoteq,gpio-select");
1900 if (count > num_gpio) {
1901 dev_err(&client->dev, "Invalid number of %s GPIOs\n",
1902 fwnode_get_name(child_node));
1903 return -EINVAL;
1904 } else if (count < 0) {
1905 dev_err(&client->dev, "Failed to count %s GPIOs: %d\n",
1906 fwnode_get_name(child_node), count);
1907 return count;
1908 }
1909
1910 error = fwnode_property_read_u32_array(child_node,
1911 "azoteq,gpio-select",
1912 gpio_sel, count);
1913 if (error) {
1914 dev_err(&client->dev, "Failed to read %s GPIOs: %d\n",
1915 fwnode_get_name(child_node), error);
1916 return error;
1917 }
1918
1919 for (i = 0; i < count; i++) {
1920 u16 *gpio_setup;
1921
1922 if (gpio_sel[i] >= num_gpio) {
1923 dev_err(&client->dev, "Invalid %s GPIO: %u\n",
1924 fwnode_get_name(child_node), gpio_sel[i]);
1925 return -EINVAL;
1926 }
1927
1928 gpio_setup = iqs7222->gpio_setup[gpio_sel[i]];
1929
1930 if (gpio_setup[2] && child_link != gpio_setup[2]) {
1931 dev_err(&client->dev,
1932 "Conflicting GPIO %u event types\n",
1933 gpio_sel[i]);
1934 return -EINVAL;
1935 }
1936
1937 gpio_setup[0] |= IQS7222_GPIO_SETUP_0_GPIO_EN;
1938 gpio_setup[1] |= child_enable;
1939 gpio_setup[2] = child_link;
1940 }
1941
1942 return 0;
1943}
1944
1945static int iqs7222_parse_props(struct iqs7222_private *iqs7222,
1946 struct fwnode_handle *reg_grp_node,
1947 int reg_grp_index,
1948 enum iqs7222_reg_grp_id reg_grp,
1949 enum iqs7222_reg_key_id reg_key)
1950{
1951 u16 *setup = iqs7222_setup(iqs7222, reg_grp, reg_grp_index);
1952 struct i2c_client *client = iqs7222->client;
1953 int i;
1954
1955 if (!setup)
1956 return 0;
1957
1958 for (i = 0; i < ARRAY_SIZE(iqs7222_props); i++) {
1959 const char *name = iqs7222_props[i].name;
1960 int reg_offset = iqs7222_props[i].reg_offset;
1961 int reg_shift = iqs7222_props[i].reg_shift;
1962 int reg_width = iqs7222_props[i].reg_width;
1963 int val_pitch = iqs7222_props[i].val_pitch ? : 1;
1964 int val_min = iqs7222_props[i].val_min;
1965 int val_max = iqs7222_props[i].val_max;
1966 bool invert = iqs7222_props[i].invert;
1967 const char *label = iqs7222_props[i].label ? : name;
1968 unsigned int val;
1969 int error;
1970
1971 if (iqs7222_props[i].reg_grp != reg_grp ||
1972 iqs7222_props[i].reg_key != reg_key)
1973 continue;
1974
1975 /*
1976 * Boolean register fields are one bit wide; they are forcibly
1977 * reset to provide a means to undo changes by a bootloader if
1978 * necessary.
1979 *
1980 * Scalar fields, on the other hand, are left untouched unless
1981 * their corresponding properties are present.
1982 */
1983 if (reg_width == 1) {
1984 if (invert)
1985 setup[reg_offset] |= BIT(reg_shift);
1986 else
1987 setup[reg_offset] &= ~BIT(reg_shift);
1988 }
1989
1990 if (!fwnode_property_present(reg_grp_node, name))
1991 continue;
1992
1993 if (reg_width == 1) {
1994 if (invert)
1995 setup[reg_offset] &= ~BIT(reg_shift);
1996 else
1997 setup[reg_offset] |= BIT(reg_shift);
1998
1999 continue;
2000 }
2001
2002 error = fwnode_property_read_u32(reg_grp_node, name, &val);
2003 if (error) {
2004 dev_err(&client->dev, "Failed to read %s %s: %d\n",
2005 fwnode_get_name(reg_grp_node), label, error);
2006 return error;
2007 }
2008
2009 if (!val_max)
2010 val_max = GENMASK(reg_width - 1, 0) * val_pitch;
2011
2012 if (val < val_min || val > val_max) {
2013 dev_err(&client->dev, "Invalid %s %s: %u\n",
2014 fwnode_get_name(reg_grp_node), label, val);
2015 return -EINVAL;
2016 }
2017
2018 setup[reg_offset] &= ~GENMASK(reg_shift + reg_width - 1,
2019 reg_shift);
2020 setup[reg_offset] |= (val / val_pitch << reg_shift);
2021 }
2022
2023 return 0;
2024}
2025
2026static int iqs7222_parse_event(struct iqs7222_private *iqs7222,
2027 struct fwnode_handle *event_node,
2028 int reg_grp_index,
2029 enum iqs7222_reg_grp_id reg_grp,
2030 enum iqs7222_reg_key_id reg_key,
2031 u16 event_enable, u16 event_link,
2032 unsigned int *event_type,
2033 unsigned int *event_code)
2034{
2035 struct i2c_client *client = iqs7222->client;
2036 int error;
2037
2038 error = iqs7222_parse_props(iqs7222, event_node, reg_grp_index,
2039 reg_grp, reg_key);
2040 if (error)
2041 return error;
2042
2043 error = iqs7222_gpio_select(iqs7222, event_node, event_enable,
2044 event_link);
2045 if (error)
2046 return error;
2047
2048 error = fwnode_property_read_u32(event_node, "linux,code", event_code);
2049 if (error == -EINVAL) {
2050 return 0;
2051 } else if (error) {
2052 dev_err(&client->dev, "Failed to read %s code: %d\n",
2053 fwnode_get_name(event_node), error);
2054 return error;
2055 }
2056
2057 if (!event_type) {
2058 input_set_capability(iqs7222->keypad, EV_KEY, *event_code);
2059 return 0;
2060 }
2061
2062 error = fwnode_property_read_u32(event_node, "linux,input-type",
2063 event_type);
2064 if (error == -EINVAL) {
2065 *event_type = EV_KEY;
2066 } else if (error) {
2067 dev_err(&client->dev, "Failed to read %s input type: %d\n",
2068 fwnode_get_name(event_node), error);
2069 return error;
2070 } else if (*event_type != EV_KEY && *event_type != EV_SW) {
2071 dev_err(&client->dev, "Invalid %s input type: %d\n",
2072 fwnode_get_name(event_node), *event_type);
2073 return -EINVAL;
2074 }
2075
2076 input_set_capability(iqs7222->keypad, *event_type, *event_code);
2077
2078 return 0;
2079}
2080
2081static int iqs7222_parse_cycle(struct iqs7222_private *iqs7222,
2082 struct fwnode_handle *cycle_node, int cycle_index)
2083{
2084 u16 *cycle_setup = iqs7222->cycle_setup[cycle_index];
2085 struct i2c_client *client = iqs7222->client;
2086 unsigned int pins[9];
2087 int error, count, i;
2088
2089 /*
2090 * Each channel shares a cycle with one other channel; the mapping of
2091 * channels to cycles is fixed. Properties defined for a cycle impact
2092 * both channels tied to the cycle.
2093 *
2094 * Unlike channels which are restricted to a select range of CRx pins
2095 * based on channel number, any cycle can claim any of the device's 9
2096 * CTx pins (CTx0-8).
2097 */
2098 if (!fwnode_property_present(cycle_node, "azoteq,tx-enable"))
2099 return 0;
2100
2101 count = fwnode_property_count_u32(cycle_node, "azoteq,tx-enable");
2102 if (count < 0) {
2103 dev_err(&client->dev, "Failed to count %s CTx pins: %d\n",
2104 fwnode_get_name(cycle_node), count);
2105 return count;
2106 } else if (count > ARRAY_SIZE(pins)) {
2107 dev_err(&client->dev, "Invalid number of %s CTx pins\n",
2108 fwnode_get_name(cycle_node));
2109 return -EINVAL;
2110 }
2111
2112 error = fwnode_property_read_u32_array(cycle_node, "azoteq,tx-enable",
2113 pins, count);
2114 if (error) {
2115 dev_err(&client->dev, "Failed to read %s CTx pins: %d\n",
2116 fwnode_get_name(cycle_node), error);
2117 return error;
2118 }
2119
2120 cycle_setup[1] &= ~GENMASK(7 + ARRAY_SIZE(pins) - 1, 7);
2121
2122 for (i = 0; i < count; i++) {
2123 if (pins[i] > 8) {
2124 dev_err(&client->dev, "Invalid %s CTx pin: %u\n",
2125 fwnode_get_name(cycle_node), pins[i]);
2126 return -EINVAL;
2127 }
2128
2129 cycle_setup[1] |= BIT(pins[i] + 7);
2130 }
2131
2132 return 0;
2133}
2134
2135static int iqs7222_parse_chan(struct iqs7222_private *iqs7222,
2136 struct fwnode_handle *chan_node, int chan_index)
2137{
2138 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2139 struct i2c_client *client = iqs7222->client;
2140 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2141 int ext_chan = rounddown(num_chan, 10);
2142 int error, i;
2143 u16 *chan_setup = iqs7222->chan_setup[chan_index];
2144 u16 *sys_setup = iqs7222->sys_setup;
2145 unsigned int val;
2146
2147 if (dev_desc->allow_offset &&
2148 fwnode_property_present(chan_node, "azoteq,ulp-allow"))
2149 sys_setup[dev_desc->allow_offset] &= ~BIT(chan_index);
2150
2151 chan_setup[0] |= IQS7222_CHAN_SETUP_0_CHAN_EN;
2152
2153 /*
2154 * The reference channel function allows for differential measurements
2155 * and is only available in the case of IQS7222A or IQS7222C.
2156 */
2157 if (dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_col > 4 &&
2158 fwnode_property_present(chan_node, "azoteq,ref-select")) {
2159 u16 *ref_setup;
2160
2161 error = fwnode_property_read_u32(chan_node, "azoteq,ref-select",
2162 &val);
2163 if (error) {
2164 dev_err(&client->dev,
2165 "Failed to read %s reference channel: %d\n",
2166 fwnode_get_name(chan_node), error);
2167 return error;
2168 }
2169
2170 if (val >= ext_chan) {
2171 dev_err(&client->dev,
2172 "Invalid %s reference channel: %u\n",
2173 fwnode_get_name(chan_node), val);
2174 return -EINVAL;
2175 }
2176
2177 ref_setup = iqs7222->chan_setup[val];
2178
2179 /*
2180 * Configure the current channel as a follower of the selected
2181 * reference channel.
2182 */
2183 chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW;
2184 chan_setup[4] = val * 42 + 1048;
2185
2186 error = fwnode_property_read_u32(chan_node, "azoteq,ref-weight",
2187 &val);
2188 if (!error) {
2189 if (val > U16_MAX) {
2190 dev_err(&client->dev,
2191 "Invalid %s reference weight: %u\n",
2192 fwnode_get_name(chan_node), val);
2193 return -EINVAL;
2194 }
2195
2196 chan_setup[5] = val;
2197 } else if (error != -EINVAL) {
2198 dev_err(&client->dev,
2199 "Failed to read %s reference weight: %d\n",
2200 fwnode_get_name(chan_node), error);
2201 return error;
2202 }
2203
2204 /*
2205 * Configure the selected channel as a reference channel which
2206 * serves the current channel.
2207 */
2208 ref_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF;
2209 ref_setup[5] |= BIT(chan_index);
2210
2211 ref_setup[4] = dev_desc->touch_link;
2212 if (fwnode_property_present(chan_node, "azoteq,use-prox"))
2213 ref_setup[4] -= 2;
2214 } else if (dev_desc->reg_grps[IQS7222_REG_GRP_TPAD].num_row &&
2215 fwnode_property_present(chan_node,
2216 "azoteq,counts-filt-enable")) {
2217 /*
2218 * In the case of IQS7222D, however, the reference mode field
2219 * is partially repurposed as a counts filter enable control.
2220 */
2221 chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF;
2222 }
2223
2224 if (fwnode_property_present(chan_node, "azoteq,rx-enable")) {
2225 /*
2226 * Each channel can claim up to 4 CRx pins. The first half of
2227 * the channels can use CRx0-3, while the second half can use
2228 * CRx4-7.
2229 */
2230 unsigned int pins[4];
2231 int count;
2232
2233 count = fwnode_property_count_u32(chan_node,
2234 "azoteq,rx-enable");
2235 if (count < 0) {
2236 dev_err(&client->dev,
2237 "Failed to count %s CRx pins: %d\n",
2238 fwnode_get_name(chan_node), count);
2239 return count;
2240 } else if (count > ARRAY_SIZE(pins)) {
2241 dev_err(&client->dev,
2242 "Invalid number of %s CRx pins\n",
2243 fwnode_get_name(chan_node));
2244 return -EINVAL;
2245 }
2246
2247 error = fwnode_property_read_u32_array(chan_node,
2248 "azoteq,rx-enable",
2249 pins, count);
2250 if (error) {
2251 dev_err(&client->dev,
2252 "Failed to read %s CRx pins: %d\n",
2253 fwnode_get_name(chan_node), error);
2254 return error;
2255 }
2256
2257 chan_setup[0] &= ~GENMASK(4 + ARRAY_SIZE(pins) - 1, 4);
2258
2259 for (i = 0; i < count; i++) {
2260 int min_crx = chan_index < ext_chan / 2 ? 0 : 4;
2261
2262 if (pins[i] < min_crx || pins[i] > min_crx + 3) {
2263 dev_err(&client->dev,
2264 "Invalid %s CRx pin: %u\n",
2265 fwnode_get_name(chan_node), pins[i]);
2266 return -EINVAL;
2267 }
2268
2269 chan_setup[0] |= BIT(pins[i] + 4 - min_crx);
2270 }
2271 }
2272
2273 for (i = 0; i < ARRAY_SIZE(iqs7222_kp_events); i++) {
2274 const char *event_name = iqs7222_kp_events[i].name;
2275 u16 event_enable = iqs7222_kp_events[i].enable;
2276 struct fwnode_handle *event_node;
2277
2278 event_node = fwnode_get_named_child_node(chan_node, event_name);
2279 if (!event_node)
2280 continue;
2281
2282 error = fwnode_property_read_u32(event_node,
2283 "azoteq,timeout-press-ms",
2284 &val);
2285 if (!error) {
2286 /*
2287 * The IQS7222B employs a global pair of press timeout
2288 * registers as opposed to channel-specific registers.
2289 */
2290 u16 *setup = dev_desc->reg_grps
2291 [IQS7222_REG_GRP_BTN].num_col > 2 ?
2292 &iqs7222->btn_setup[chan_index][2] :
2293 &sys_setup[9];
2294
2295 if (val > U8_MAX * 500) {
2296 dev_err(&client->dev,
2297 "Invalid %s press timeout: %u\n",
2298 fwnode_get_name(event_node), val);
2299 fwnode_handle_put(event_node);
2300 return -EINVAL;
2301 }
2302
2303 *setup &= ~(U8_MAX << i * 8);
2304 *setup |= (val / 500 << i * 8);
2305 } else if (error != -EINVAL) {
2306 dev_err(&client->dev,
2307 "Failed to read %s press timeout: %d\n",
2308 fwnode_get_name(event_node), error);
2309 fwnode_handle_put(event_node);
2310 return error;
2311 }
2312
2313 error = iqs7222_parse_event(iqs7222, event_node, chan_index,
2314 IQS7222_REG_GRP_BTN,
2315 iqs7222_kp_events[i].reg_key,
2316 BIT(chan_index),
2317 dev_desc->touch_link - (i ? 0 : 2),
2318 &iqs7222->kp_type[chan_index][i],
2319 &iqs7222->kp_code[chan_index][i]);
2320 fwnode_handle_put(event_node);
2321 if (error)
2322 return error;
2323
2324 if (!dev_desc->event_offset)
2325 continue;
2326
2327 sys_setup[dev_desc->event_offset] |= event_enable;
2328 }
2329
2330 /*
2331 * The following call handles a special pair of properties that apply
2332 * to a channel node, but reside within the button (event) group.
2333 */
2334 return iqs7222_parse_props(iqs7222, chan_node, chan_index,
2335 IQS7222_REG_GRP_BTN,
2336 IQS7222_REG_KEY_DEBOUNCE);
2337}
2338
2339static int iqs7222_parse_sldr(struct iqs7222_private *iqs7222,
2340 struct fwnode_handle *sldr_node, int sldr_index)
2341{
2342 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2343 struct i2c_client *client = iqs7222->client;
2344 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2345 int ext_chan = rounddown(num_chan, 10);
2346 int count, error, reg_offset, i;
2347 u16 *event_mask = &iqs7222->sys_setup[dev_desc->event_offset];
2348 u16 *sldr_setup = iqs7222->sldr_setup[sldr_index];
2349 unsigned int chan_sel[4], val;
2350
2351 /*
2352 * Each slider can be spread across 3 to 4 channels. It is possible to
2353 * select only 2 channels, but doing so prevents the slider from using
2354 * the specified resolution.
2355 */
2356 count = fwnode_property_count_u32(sldr_node, "azoteq,channel-select");
2357 if (count < 0) {
2358 dev_err(&client->dev, "Failed to count %s channels: %d\n",
2359 fwnode_get_name(sldr_node), count);
2360 return count;
2361 } else if (count < 3 || count > ARRAY_SIZE(chan_sel)) {
2362 dev_err(&client->dev, "Invalid number of %s channels\n",
2363 fwnode_get_name(sldr_node));
2364 return -EINVAL;
2365 }
2366
2367 error = fwnode_property_read_u32_array(sldr_node,
2368 "azoteq,channel-select",
2369 chan_sel, count);
2370 if (error) {
2371 dev_err(&client->dev, "Failed to read %s channels: %d\n",
2372 fwnode_get_name(sldr_node), error);
2373 return error;
2374 }
2375
2376 /*
2377 * Resolution and top speed, if small enough, are packed into a single
2378 * register. Otherwise, each occupies its own register and the rest of
2379 * the slider-related register addresses are offset by one.
2380 */
2381 reg_offset = dev_desc->sldr_res < U16_MAX ? 0 : 1;
2382
2383 sldr_setup[0] |= count;
2384 sldr_setup[3 + reg_offset] &= ~GENMASK(ext_chan - 1, 0);
2385
2386 for (i = 0; i < ARRAY_SIZE(chan_sel); i++) {
2387 sldr_setup[5 + reg_offset + i] = 0;
2388 if (i >= count)
2389 continue;
2390
2391 if (chan_sel[i] >= ext_chan) {
2392 dev_err(&client->dev, "Invalid %s channel: %u\n",
2393 fwnode_get_name(sldr_node), chan_sel[i]);
2394 return -EINVAL;
2395 }
2396
2397 /*
2398 * The following fields indicate which channels participate in
2399 * the slider, as well as each channel's relative placement.
2400 */
2401 sldr_setup[3 + reg_offset] |= BIT(chan_sel[i]);
2402 sldr_setup[5 + reg_offset + i] = chan_sel[i] * 42 + 1080;
2403 }
2404
2405 sldr_setup[4 + reg_offset] = dev_desc->touch_link;
2406 if (fwnode_property_present(sldr_node, "azoteq,use-prox"))
2407 sldr_setup[4 + reg_offset] -= 2;
2408
2409 error = fwnode_property_read_u32(sldr_node, "azoteq,slider-size", &val);
2410 if (!error) {
2411 if (val > dev_desc->sldr_res) {
2412 dev_err(&client->dev, "Invalid %s size: %u\n",
2413 fwnode_get_name(sldr_node), val);
2414 return -EINVAL;
2415 }
2416
2417 if (reg_offset) {
2418 sldr_setup[3] = val;
2419 } else {
2420 sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_RES_MASK;
2421 sldr_setup[2] |= (val / 16 <<
2422 IQS7222_SLDR_SETUP_2_RES_SHIFT);
2423 }
2424 } else if (error != -EINVAL) {
2425 dev_err(&client->dev, "Failed to read %s size: %d\n",
2426 fwnode_get_name(sldr_node), error);
2427 return error;
2428 }
2429
2430 if (!(reg_offset ? sldr_setup[3]
2431 : sldr_setup[2] & IQS7222_SLDR_SETUP_2_RES_MASK)) {
2432 dev_err(&client->dev, "Undefined %s size\n",
2433 fwnode_get_name(sldr_node));
2434 return -EINVAL;
2435 }
2436
2437 error = fwnode_property_read_u32(sldr_node, "azoteq,top-speed", &val);
2438 if (!error) {
2439 if (val > (reg_offset ? U16_MAX : U8_MAX * 4)) {
2440 dev_err(&client->dev, "Invalid %s top speed: %u\n",
2441 fwnode_get_name(sldr_node), val);
2442 return -EINVAL;
2443 }
2444
2445 if (reg_offset) {
2446 sldr_setup[2] = val;
2447 } else {
2448 sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK;
2449 sldr_setup[2] |= (val / 4);
2450 }
2451 } else if (error != -EINVAL) {
2452 dev_err(&client->dev, "Failed to read %s top speed: %d\n",
2453 fwnode_get_name(sldr_node), error);
2454 return error;
2455 }
2456
2457 error = fwnode_property_read_u32(sldr_node, "linux,axis", &val);
2458 if (!error) {
2459 u16 sldr_max = sldr_setup[3] - 1;
2460
2461 if (!reg_offset) {
2462 sldr_max = sldr_setup[2];
2463
2464 sldr_max &= IQS7222_SLDR_SETUP_2_RES_MASK;
2465 sldr_max >>= IQS7222_SLDR_SETUP_2_RES_SHIFT;
2466
2467 sldr_max = sldr_max * 16 - 1;
2468 }
2469
2470 input_set_abs_params(iqs7222->keypad, val, 0, sldr_max, 0, 0);
2471 iqs7222->sl_axis[sldr_index] = val;
2472 } else if (error != -EINVAL) {
2473 dev_err(&client->dev, "Failed to read %s axis: %d\n",
2474 fwnode_get_name(sldr_node), error);
2475 return error;
2476 }
2477
2478 if (dev_desc->wheel_enable) {
2479 sldr_setup[0] &= ~dev_desc->wheel_enable;
2480 if (iqs7222->sl_axis[sldr_index] == ABS_WHEEL)
2481 sldr_setup[0] |= dev_desc->wheel_enable;
2482 }
2483
2484 /*
2485 * The absence of a register offset makes it safe to assume the device
2486 * supports gestures, each of which is first disabled until explicitly
2487 * enabled.
2488 */
2489 if (!reg_offset)
2490 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++)
2491 sldr_setup[9] &= ~iqs7222_sl_events[i].enable;
2492
2493 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) {
2494 const char *event_name = iqs7222_sl_events[i].name;
2495 struct fwnode_handle *event_node;
2496 enum iqs7222_reg_key_id reg_key;
2497
2498 event_node = fwnode_get_named_child_node(sldr_node, event_name);
2499 if (!event_node)
2500 continue;
2501
2502 /*
2503 * Depending on the device, gestures are either offered using
2504 * one of two timing resolutions, or are not supported at all.
2505 */
2506 if (reg_offset)
2507 reg_key = IQS7222_REG_KEY_RESERVED;
2508 else if (dev_desc->legacy_gesture &&
2509 iqs7222_sl_events[i].reg_key == IQS7222_REG_KEY_TAP)
2510 reg_key = IQS7222_REG_KEY_TAP_LEGACY;
2511 else if (dev_desc->legacy_gesture &&
2512 iqs7222_sl_events[i].reg_key == IQS7222_REG_KEY_AXIAL)
2513 reg_key = IQS7222_REG_KEY_AXIAL_LEGACY;
2514 else
2515 reg_key = iqs7222_sl_events[i].reg_key;
2516
2517 /*
2518 * The press/release event does not expose a direct GPIO link,
2519 * but one can be emulated by tying each of the participating
2520 * channels to the same GPIO.
2521 */
2522 error = iqs7222_parse_event(iqs7222, event_node, sldr_index,
2523 IQS7222_REG_GRP_SLDR, reg_key,
2524 i ? iqs7222_sl_events[i].enable
2525 : sldr_setup[3 + reg_offset],
2526 i ? 1568 + sldr_index * 30
2527 : sldr_setup[4 + reg_offset],
2528 NULL,
2529 &iqs7222->sl_code[sldr_index][i]);
2530 fwnode_handle_put(event_node);
2531 if (error)
2532 return error;
2533
2534 if (!reg_offset)
2535 sldr_setup[9] |= iqs7222_sl_events[i].enable;
2536
2537 if (!dev_desc->event_offset)
2538 continue;
2539
2540 /*
2541 * The press/release event is determined based on whether the
2542 * coordinate field reports 0xFFFF and solely relies on touch
2543 * or proximity interrupts to be unmasked.
2544 */
2545 if (i && !reg_offset)
2546 *event_mask |= (IQS7222_EVENT_MASK_SLDR << sldr_index);
2547 else if (sldr_setup[4 + reg_offset] == dev_desc->touch_link)
2548 *event_mask |= IQS7222_EVENT_MASK_TOUCH;
2549 else
2550 *event_mask |= IQS7222_EVENT_MASK_PROX;
2551 }
2552
2553 /*
2554 * The following call handles a special pair of properties that shift
2555 * to make room for a wheel enable control in the case of IQS7222C.
2556 */
2557 return iqs7222_parse_props(iqs7222, sldr_node, sldr_index,
2558 IQS7222_REG_GRP_SLDR,
2559 dev_desc->wheel_enable ?
2560 IQS7222_REG_KEY_WHEEL :
2561 IQS7222_REG_KEY_NO_WHEEL);
2562}
2563
2564static int iqs7222_parse_tpad(struct iqs7222_private *iqs7222,
2565 struct fwnode_handle *tpad_node, int tpad_index)
2566{
2567 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2568 struct touchscreen_properties *prop = &iqs7222->prop;
2569 struct i2c_client *client = iqs7222->client;
2570 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2571 int count, error, i;
2572 u16 *event_mask = &iqs7222->sys_setup[dev_desc->event_offset];
2573 u16 *tpad_setup = iqs7222->tpad_setup;
2574 unsigned int chan_sel[12];
2575
2576 error = iqs7222_parse_props(iqs7222, tpad_node, tpad_index,
2577 IQS7222_REG_GRP_TPAD,
2578 IQS7222_REG_KEY_NONE);
2579 if (error)
2580 return error;
2581
2582 count = fwnode_property_count_u32(tpad_node, "azoteq,channel-select");
2583 if (count < 0) {
2584 dev_err(&client->dev, "Failed to count %s channels: %d\n",
2585 fwnode_get_name(tpad_node), count);
2586 return count;
2587 } else if (!count || count > ARRAY_SIZE(chan_sel)) {
2588 dev_err(&client->dev, "Invalid number of %s channels\n",
2589 fwnode_get_name(tpad_node));
2590 return -EINVAL;
2591 }
2592
2593 error = fwnode_property_read_u32_array(tpad_node,
2594 "azoteq,channel-select",
2595 chan_sel, count);
2596 if (error) {
2597 dev_err(&client->dev, "Failed to read %s channels: %d\n",
2598 fwnode_get_name(tpad_node), error);
2599 return error;
2600 }
2601
2602 tpad_setup[6] &= ~GENMASK(num_chan - 1, 0);
2603
2604 for (i = 0; i < ARRAY_SIZE(chan_sel); i++) {
2605 tpad_setup[8 + i] = 0;
2606 if (i >= count || chan_sel[i] == U8_MAX)
2607 continue;
2608
2609 if (chan_sel[i] >= num_chan) {
2610 dev_err(&client->dev, "Invalid %s channel: %u\n",
2611 fwnode_get_name(tpad_node), chan_sel[i]);
2612 return -EINVAL;
2613 }
2614
2615 /*
2616 * The following fields indicate which channels participate in
2617 * the trackpad, as well as each channel's relative placement.
2618 */
2619 tpad_setup[6] |= BIT(chan_sel[i]);
2620 tpad_setup[8 + i] = chan_sel[i] * 34 + 1072;
2621 }
2622
2623 tpad_setup[7] = dev_desc->touch_link;
2624 if (fwnode_property_present(tpad_node, "azoteq,use-prox"))
2625 tpad_setup[7] -= 2;
2626
2627 for (i = 0; i < ARRAY_SIZE(iqs7222_tp_events); i++)
2628 tpad_setup[20] &= ~(iqs7222_tp_events[i].strict |
2629 iqs7222_tp_events[i].enable);
2630
2631 for (i = 0; i < ARRAY_SIZE(iqs7222_tp_events); i++) {
2632 const char *event_name = iqs7222_tp_events[i].name;
2633 struct fwnode_handle *event_node;
2634
2635 event_node = fwnode_get_named_child_node(tpad_node, event_name);
2636 if (!event_node)
2637 continue;
2638
2639 if (fwnode_property_present(event_node,
2640 "azoteq,gesture-angle-tighten"))
2641 tpad_setup[20] |= iqs7222_tp_events[i].strict;
2642
2643 tpad_setup[20] |= iqs7222_tp_events[i].enable;
2644
2645 error = iqs7222_parse_event(iqs7222, event_node, tpad_index,
2646 IQS7222_REG_GRP_TPAD,
2647 iqs7222_tp_events[i].reg_key,
2648 iqs7222_tp_events[i].link, 1566,
2649 NULL,
2650 &iqs7222->tp_code[i]);
2651 fwnode_handle_put(event_node);
2652 if (error)
2653 return error;
2654
2655 if (!dev_desc->event_offset)
2656 continue;
2657
2658 /*
2659 * The press/release event is determined based on whether the
2660 * coordinate fields report 0xFFFF and solely relies on touch
2661 * or proximity interrupts to be unmasked.
2662 */
2663 if (i)
2664 *event_mask |= IQS7222_EVENT_MASK_TPAD;
2665 else if (tpad_setup[7] == dev_desc->touch_link)
2666 *event_mask |= IQS7222_EVENT_MASK_TOUCH;
2667 else
2668 *event_mask |= IQS7222_EVENT_MASK_PROX;
2669 }
2670
2671 if (!iqs7222->tp_code[0])
2672 return 0;
2673
2674 input_set_abs_params(iqs7222->keypad, ABS_X,
2675 0, (tpad_setup[4] ? : 1) - 1, 0, 0);
2676
2677 input_set_abs_params(iqs7222->keypad, ABS_Y,
2678 0, (tpad_setup[5] ? : 1) - 1, 0, 0);
2679
2680 touchscreen_parse_properties(iqs7222->keypad, false, prop);
2681
2682 if (prop->max_x >= U16_MAX || prop->max_y >= U16_MAX) {
2683 dev_err(&client->dev, "Invalid trackpad size: %u*%u\n",
2684 prop->max_x, prop->max_y);
2685 return -EINVAL;
2686 }
2687
2688 tpad_setup[4] = prop->max_x + 1;
2689 tpad_setup[5] = prop->max_y + 1;
2690
2691 return 0;
2692}
2693
2694static int (*iqs7222_parse_extra[IQS7222_NUM_REG_GRPS])
2695 (struct iqs7222_private *iqs7222,
2696 struct fwnode_handle *reg_grp_node,
2697 int reg_grp_index) = {
2698 [IQS7222_REG_GRP_CYCLE] = iqs7222_parse_cycle,
2699 [IQS7222_REG_GRP_CHAN] = iqs7222_parse_chan,
2700 [IQS7222_REG_GRP_SLDR] = iqs7222_parse_sldr,
2701 [IQS7222_REG_GRP_TPAD] = iqs7222_parse_tpad,
2702};
2703
2704static int iqs7222_parse_reg_grp(struct iqs7222_private *iqs7222,
2705 enum iqs7222_reg_grp_id reg_grp,
2706 int reg_grp_index)
2707{
2708 struct i2c_client *client = iqs7222->client;
2709 struct fwnode_handle *reg_grp_node;
2710 int error;
2711
2712 if (iqs7222_reg_grp_names[reg_grp]) {
2713 char reg_grp_name[16];
2714
2715 snprintf(reg_grp_name, sizeof(reg_grp_name),
2716 iqs7222_reg_grp_names[reg_grp], reg_grp_index);
2717
2718 reg_grp_node = device_get_named_child_node(&client->dev,
2719 reg_grp_name);
2720 } else {
2721 reg_grp_node = fwnode_handle_get(dev_fwnode(&client->dev));
2722 }
2723
2724 if (!reg_grp_node)
2725 return 0;
2726
2727 error = iqs7222_parse_props(iqs7222, reg_grp_node, reg_grp_index,
2728 reg_grp, IQS7222_REG_KEY_NONE);
2729
2730 if (!error && iqs7222_parse_extra[reg_grp])
2731 error = iqs7222_parse_extra[reg_grp](iqs7222, reg_grp_node,
2732 reg_grp_index);
2733
2734 fwnode_handle_put(reg_grp_node);
2735
2736 return error;
2737}
2738
2739static int iqs7222_parse_all(struct iqs7222_private *iqs7222)
2740{
2741 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2742 const struct iqs7222_reg_grp_desc *reg_grps = dev_desc->reg_grps;
2743 u16 *sys_setup = iqs7222->sys_setup;
2744 int error, i, j;
2745
2746 if (dev_desc->allow_offset)
2747 sys_setup[dev_desc->allow_offset] = U16_MAX;
2748
2749 if (dev_desc->event_offset)
2750 sys_setup[dev_desc->event_offset] = IQS7222_EVENT_MASK_ATI;
2751
2752 for (i = 0; i < reg_grps[IQS7222_REG_GRP_GPIO].num_row; i++) {
2753 u16 *gpio_setup = iqs7222->gpio_setup[i];
2754
2755 gpio_setup[0] &= ~IQS7222_GPIO_SETUP_0_GPIO_EN;
2756 gpio_setup[1] = 0;
2757 gpio_setup[2] = 0;
2758
2759 if (reg_grps[IQS7222_REG_GRP_GPIO].num_row == 1)
2760 continue;
2761
2762 /*
2763 * The IQS7222C and IQS7222D expose multiple GPIO and must be
2764 * informed as to which GPIO this group represents.
2765 */
2766 for (j = 0; j < ARRAY_SIZE(iqs7222_gpio_links); j++)
2767 gpio_setup[0] &= ~BIT(iqs7222_gpio_links[j]);
2768
2769 gpio_setup[0] |= BIT(iqs7222_gpio_links[i]);
2770 }
2771
2772 for (i = 0; i < reg_grps[IQS7222_REG_GRP_CHAN].num_row; i++) {
2773 u16 *chan_setup = iqs7222->chan_setup[i];
2774
2775 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_REF_MODE_MASK;
2776 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_CHAN_EN;
2777
2778 chan_setup[5] = 0;
2779 }
2780
2781 for (i = 0; i < reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) {
2782 u16 *sldr_setup = iqs7222->sldr_setup[i];
2783
2784 sldr_setup[0] &= ~IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK;
2785 }
2786
2787 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) {
2788 for (j = 0; j < reg_grps[i].num_row; j++) {
2789 error = iqs7222_parse_reg_grp(iqs7222, i, j);
2790 if (error)
2791 return error;
2792 }
2793 }
2794
2795 return 0;
2796}
2797
2798static int iqs7222_report(struct iqs7222_private *iqs7222)
2799{
2800 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2801 struct i2c_client *client = iqs7222->client;
2802 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2803 int num_stat = dev_desc->reg_grps[IQS7222_REG_GRP_STAT].num_col;
2804 int error, i, j;
2805 __le16 status[IQS7222_MAX_COLS_STAT];
2806
2807 error = iqs7222_read_burst(iqs7222, IQS7222_SYS_STATUS, status,
2808 num_stat);
2809 if (error)
2810 return error;
2811
2812 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_RESET) {
2813 dev_err(&client->dev, "Unexpected device reset\n");
2814 return iqs7222_dev_init(iqs7222, WRITE);
2815 }
2816
2817 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ERROR) {
2818 dev_err(&client->dev, "Unexpected ATI error\n");
2819 return iqs7222_ati_trigger(iqs7222);
2820 }
2821
2822 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ACTIVE)
2823 return 0;
2824
2825 for (i = 0; i < num_chan; i++) {
2826 u16 *chan_setup = iqs7222->chan_setup[i];
2827
2828 if (!(chan_setup[0] & IQS7222_CHAN_SETUP_0_CHAN_EN))
2829 continue;
2830
2831 for (j = 0; j < ARRAY_SIZE(iqs7222_kp_events); j++) {
2832 /*
2833 * Proximity state begins at offset 2 and spills into
2834 * offset 3 for devices with more than 16 channels.
2835 *
2836 * Touch state begins at the first offset immediately
2837 * following proximity state.
2838 */
2839 int k = 2 + j * (num_chan > 16 ? 2 : 1);
2840 u16 state = le16_to_cpu(status[k + i / 16]);
2841
2842 if (!iqs7222->kp_type[i][j])
2843 continue;
2844
2845 input_event(iqs7222->keypad,
2846 iqs7222->kp_type[i][j],
2847 iqs7222->kp_code[i][j],
2848 !!(state & BIT(i % 16)));
2849 }
2850 }
2851
2852 for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) {
2853 u16 *sldr_setup = iqs7222->sldr_setup[i];
2854 u16 sldr_pos = le16_to_cpu(status[4 + i]);
2855 u16 state = le16_to_cpu(status[6 + i]);
2856
2857 if (!(sldr_setup[0] & IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK))
2858 continue;
2859
2860 if (sldr_pos < dev_desc->sldr_res)
2861 input_report_abs(iqs7222->keypad, iqs7222->sl_axis[i],
2862 sldr_pos);
2863
2864 input_report_key(iqs7222->keypad, iqs7222->sl_code[i][0],
2865 sldr_pos < dev_desc->sldr_res);
2866
2867 /*
2868 * A maximum resolution indicates the device does not support
2869 * gestures, in which case the remaining fields are ignored.
2870 */
2871 if (dev_desc->sldr_res == U16_MAX)
2872 continue;
2873
2874 if (!(le16_to_cpu(status[1]) & IQS7222_EVENT_MASK_SLDR << i))
2875 continue;
2876
2877 /*
2878 * Skip the press/release event, as it does not have separate
2879 * status fields and is handled separately.
2880 */
2881 for (j = 1; j < ARRAY_SIZE(iqs7222_sl_events); j++) {
2882 u16 mask = iqs7222_sl_events[j].mask;
2883 u16 val = iqs7222_sl_events[j].val;
2884
2885 input_report_key(iqs7222->keypad,
2886 iqs7222->sl_code[i][j],
2887 (state & mask) == val);
2888 }
2889
2890 input_sync(iqs7222->keypad);
2891
2892 for (j = 1; j < ARRAY_SIZE(iqs7222_sl_events); j++)
2893 input_report_key(iqs7222->keypad,
2894 iqs7222->sl_code[i][j], 0);
2895 }
2896
2897 for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_TPAD].num_row; i++) {
2898 u16 tpad_pos_x = le16_to_cpu(status[4]);
2899 u16 tpad_pos_y = le16_to_cpu(status[5]);
2900 u16 state = le16_to_cpu(status[6]);
2901
2902 input_report_key(iqs7222->keypad, iqs7222->tp_code[0],
2903 tpad_pos_x < U16_MAX);
2904
2905 if (tpad_pos_x < U16_MAX)
2906 touchscreen_report_pos(iqs7222->keypad, &iqs7222->prop,
2907 tpad_pos_x, tpad_pos_y, false);
2908
2909 if (!(le16_to_cpu(status[1]) & IQS7222_EVENT_MASK_TPAD))
2910 continue;
2911
2912 /*
2913 * Skip the press/release event, as it does not have separate
2914 * status fields and is handled separately.
2915 */
2916 for (j = 1; j < ARRAY_SIZE(iqs7222_tp_events); j++) {
2917 u16 mask = iqs7222_tp_events[j].mask;
2918 u16 val = iqs7222_tp_events[j].val;
2919
2920 input_report_key(iqs7222->keypad,
2921 iqs7222->tp_code[j],
2922 (state & mask) == val);
2923 }
2924
2925 input_sync(iqs7222->keypad);
2926
2927 for (j = 1; j < ARRAY_SIZE(iqs7222_tp_events); j++)
2928 input_report_key(iqs7222->keypad,
2929 iqs7222->tp_code[j], 0);
2930 }
2931
2932 input_sync(iqs7222->keypad);
2933
2934 return 0;
2935}
2936
2937static irqreturn_t iqs7222_irq(int irq, void *context)
2938{
2939 struct iqs7222_private *iqs7222 = context;
2940
2941 return iqs7222_report(iqs7222) ? IRQ_NONE : IRQ_HANDLED;
2942}
2943
2944static int iqs7222_probe(struct i2c_client *client)
2945{
2946 struct iqs7222_private *iqs7222;
2947 unsigned long irq_flags;
2948 int error, irq;
2949
2950 iqs7222 = devm_kzalloc(&client->dev, sizeof(*iqs7222), GFP_KERNEL);
2951 if (!iqs7222)
2952 return -ENOMEM;
2953
2954 i2c_set_clientdata(client, iqs7222);
2955 iqs7222->client = client;
2956
2957 iqs7222->keypad = devm_input_allocate_device(&client->dev);
2958 if (!iqs7222->keypad)
2959 return -ENOMEM;
2960
2961 iqs7222->keypad->name = client->name;
2962 iqs7222->keypad->id.bustype = BUS_I2C;
2963
2964 /*
2965 * The RDY pin behaves as an interrupt, but must also be polled ahead
2966 * of unsolicited I2C communication. As such, it is first opened as a
2967 * GPIO and then passed to gpiod_to_irq() to register the interrupt.
2968 */
2969 iqs7222->irq_gpio = devm_gpiod_get(&client->dev, "irq", GPIOD_IN);
2970 if (IS_ERR(iqs7222->irq_gpio)) {
2971 error = PTR_ERR(iqs7222->irq_gpio);
2972 dev_err(&client->dev, "Failed to request IRQ GPIO: %d\n",
2973 error);
2974 return error;
2975 }
2976
2977 iqs7222->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
2978 GPIOD_OUT_HIGH);
2979 if (IS_ERR(iqs7222->reset_gpio)) {
2980 error = PTR_ERR(iqs7222->reset_gpio);
2981 dev_err(&client->dev, "Failed to request reset GPIO: %d\n",
2982 error);
2983 return error;
2984 }
2985
2986 error = iqs7222_hard_reset(iqs7222);
2987 if (error)
2988 return error;
2989
2990 error = iqs7222_dev_info(iqs7222);
2991 if (error)
2992 return error;
2993
2994 error = iqs7222_dev_init(iqs7222, READ);
2995 if (error)
2996 return error;
2997
2998 error = iqs7222_parse_all(iqs7222);
2999 if (error)
3000 return error;
3001
3002 error = iqs7222_dev_init(iqs7222, WRITE);
3003 if (error)
3004 return error;
3005
3006 error = iqs7222_report(iqs7222);
3007 if (error)
3008 return error;
3009
3010 error = input_register_device(iqs7222->keypad);
3011 if (error) {
3012 dev_err(&client->dev, "Failed to register device: %d\n", error);
3013 return error;
3014 }
3015
3016 irq = gpiod_to_irq(iqs7222->irq_gpio);
3017 if (irq < 0)
3018 return irq;
3019
3020 irq_flags = gpiod_is_active_low(iqs7222->irq_gpio) ? IRQF_TRIGGER_LOW
3021 : IRQF_TRIGGER_HIGH;
3022 irq_flags |= IRQF_ONESHOT;
3023
3024 error = devm_request_threaded_irq(&client->dev, irq, NULL, iqs7222_irq,
3025 irq_flags, client->name, iqs7222);
3026 if (error)
3027 dev_err(&client->dev, "Failed to request IRQ: %d\n", error);
3028
3029 return error;
3030}
3031
3032static const struct of_device_id iqs7222_of_match[] = {
3033 { .compatible = "azoteq,iqs7222a" },
3034 { .compatible = "azoteq,iqs7222b" },
3035 { .compatible = "azoteq,iqs7222c" },
3036 { .compatible = "azoteq,iqs7222d" },
3037 { }
3038};
3039MODULE_DEVICE_TABLE(of, iqs7222_of_match);
3040
3041static struct i2c_driver iqs7222_i2c_driver = {
3042 .driver = {
3043 .name = "iqs7222",
3044 .of_match_table = iqs7222_of_match,
3045 },
3046 .probe = iqs7222_probe,
3047};
3048module_i2c_driver(iqs7222_i2c_driver);
3049
3050MODULE_AUTHOR("Jeff LaBundy <jeff@labundy.com>");
3051MODULE_DESCRIPTION("Azoteq IQS7222A/B/C/D Capacitive Touch Controller");
3052MODULE_LICENSE("GPL");