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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 1998-2000 Michel Aubry
4 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
6 * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
7 * Portions copyright (c) 2001 Sun Microsystems
8 *
9 *
10 * RCC/ServerWorks IDE driver for Linux
11 *
12 * OSB4: `Open South Bridge' IDE Interface (fn 1)
13 * supports UDMA mode 2 (33 MB/s)
14 *
15 * CSB5: `Champion South Bridge' IDE Interface (fn 1)
16 * all revisions support UDMA mode 4 (66 MB/s)
17 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
18 *
19 * *** The CSB5 does not provide ANY register ***
20 * *** to detect 80-conductor cable presence. ***
21 *
22 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
23 *
24 * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
25 * controller same as the CSB6. Single channel ATA100 only.
26 *
27 * Documentation:
28 * Available under NDA only. Errata info very hard to get.
29 *
30 */
31
32#include <linux/types.h>
33#include <linux/module.h>
34#include <linux/kernel.h>
35#include <linux/pci.h>
36#include <linux/ide.h>
37#include <linux/init.h>
38
39#include <asm/io.h>
40
41#define DRV_NAME "serverworks"
42
43#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
44#define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
45
46/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
47 * can overrun their FIFOs when used with the CSB5 */
48static const char *svwks_bad_ata100[] = {
49 "ST320011A",
50 "ST340016A",
51 "ST360021A",
52 "ST380021A",
53 NULL
54};
55
56static int check_in_drive_lists (ide_drive_t *drive, const char **list)
57{
58 char *m = (char *)&drive->id[ATA_ID_PROD];
59
60 while (*list)
61 if (!strcmp(*list++, m))
62 return 1;
63 return 0;
64}
65
66static u8 svwks_udma_filter(ide_drive_t *drive)
67{
68 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
69
70 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
71 return 0x1f;
72 } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
73 return 0x07;
74 } else {
75 u8 btr = 0, mode, mask;
76
77 pci_read_config_byte(dev, 0x5A, &btr);
78 mode = btr & 0x3;
79
80 /* If someone decides to do UDMA133 on CSB5 the same
81 issue will bite so be inclusive */
82 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
83 mode = 2;
84
85 switch(mode) {
86 case 3: mask = 0x3f; break;
87 case 2: mask = 0x1f; break;
88 case 1: mask = 0x07; break;
89 default: mask = 0x00; break;
90 }
91
92 return mask;
93 }
94}
95
96static u8 svwks_csb_check (struct pci_dev *dev)
97{
98 switch (dev->device) {
99 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
100 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
101 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
102 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
103 return 1;
104 default:
105 break;
106 }
107 return 0;
108}
109
110static void svwks_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
111{
112 static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
113 static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
114
115 struct pci_dev *dev = to_pci_dev(hwif->dev);
116 const u8 pio = drive->pio_mode - XFER_PIO_0;
117
118 pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
119
120 if (svwks_csb_check(dev)) {
121 u16 csb_pio = 0;
122
123 pci_read_config_word(dev, 0x4a, &csb_pio);
124
125 csb_pio &= ~(0x0f << (4 * drive->dn));
126 csb_pio |= (pio << (4 * drive->dn));
127
128 pci_write_config_word(dev, 0x4a, csb_pio);
129 }
130}
131
132static void svwks_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
133{
134 static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
135 static const u8 dma_modes[] = { 0x77, 0x21, 0x20 };
136 static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
137
138 struct pci_dev *dev = to_pci_dev(hwif->dev);
139 const u8 speed = drive->dma_mode;
140 u8 unit = drive->dn & 1;
141
142 u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0;
143
144 pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
145 pci_read_config_byte(dev, 0x54, &ultra_enable);
146
147 ultra_timing &= ~(0x0F << (4*unit));
148 ultra_enable &= ~(0x01 << drive->dn);
149
150 if (speed >= XFER_UDMA_0) {
151 dma_timing |= dma_modes[2];
152 ultra_timing |= (udma_modes[speed - XFER_UDMA_0] << (4 * unit));
153 ultra_enable |= (0x01 << drive->dn);
154 } else if (speed >= XFER_MW_DMA_0)
155 dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
156
157 pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
158 pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
159 pci_write_config_byte(dev, 0x54, ultra_enable);
160}
161
162static int init_chipset_svwks(struct pci_dev *dev)
163{
164 unsigned int reg;
165 u8 btr;
166
167 /* force Master Latency Timer value to 64 PCICLKs */
168 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
169
170 /* OSB4 : South Bridge and IDE */
171 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
172 struct pci_dev *isa_dev =
173 pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
174 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
175 if (isa_dev) {
176 pci_read_config_dword(isa_dev, 0x64, ®);
177 reg &= ~0x00002000; /* disable 600ns interrupt mask */
178 if(!(reg & 0x00004000))
179 printk(KERN_DEBUG DRV_NAME " %s: UDMA not BIOS "
180 "enabled.\n", pci_name(dev));
181 reg |= 0x00004000; /* enable UDMA/33 support */
182 pci_write_config_dword(isa_dev, 0x64, reg);
183 pci_dev_put(isa_dev);
184 }
185 }
186
187 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
188 else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
189 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
190 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
191
192 /* Third Channel Test */
193 if (!(PCI_FUNC(dev->devfn) & 1)) {
194 struct pci_dev * findev = NULL;
195 u32 reg4c = 0;
196 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
197 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
198 if (findev) {
199 pci_read_config_dword(findev, 0x4C, ®4c);
200 reg4c &= ~0x000007FF;
201 reg4c |= 0x00000040;
202 reg4c |= 0x00000020;
203 pci_write_config_dword(findev, 0x4C, reg4c);
204 pci_dev_put(findev);
205 }
206 outb_p(0x06, 0x0c00);
207 dev->irq = inb_p(0x0c01);
208 } else {
209 struct pci_dev * findev = NULL;
210 u8 reg41 = 0;
211
212 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
213 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
214 if (findev) {
215 pci_read_config_byte(findev, 0x41, ®41);
216 reg41 &= ~0x40;
217 pci_write_config_byte(findev, 0x41, reg41);
218 pci_dev_put(findev);
219 }
220 /*
221 * This is a device pin issue on CSB6.
222 * Since there will be a future raid mode,
223 * early versions of the chipset require the
224 * interrupt pin to be set, and it is a compatibility
225 * mode issue.
226 */
227 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
228 dev->irq = 0;
229 }
230// pci_read_config_dword(dev, 0x40, &pioreg)
231// pci_write_config_dword(dev, 0x40, 0x99999999);
232// pci_read_config_dword(dev, 0x44, &dmareg);
233// pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
234 /* setup the UDMA Control register
235 *
236 * 1. clear bit 6 to enable DMA
237 * 2. enable DMA modes with bits 0-1
238 * 00 : legacy
239 * 01 : udma2
240 * 10 : udma2/udma4
241 * 11 : udma2/udma4/udma5
242 */
243 pci_read_config_byte(dev, 0x5A, &btr);
244 btr &= ~0x40;
245 if (!(PCI_FUNC(dev->devfn) & 1))
246 btr |= 0x2;
247 else
248 btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
249 pci_write_config_byte(dev, 0x5A, btr);
250 }
251 /* Setup HT1000 SouthBridge Controller - Single Channel Only */
252 else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
253 pci_read_config_byte(dev, 0x5A, &btr);
254 btr &= ~0x40;
255 btr |= 0x3;
256 pci_write_config_byte(dev, 0x5A, btr);
257 }
258
259 return 0;
260}
261
262static u8 ata66_svwks_svwks(ide_hwif_t *hwif)
263{
264 return ATA_CBL_PATA80;
265}
266
267/* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
268 * of the subsystem device ID indicate presence of an 80-pin cable.
269 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
270 * Bit 15 set = secondary IDE channel has 80-pin cable.
271 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
272 * Bit 14 set = primary IDE channel has 80-pin cable.
273 */
274static u8 ata66_svwks_dell(ide_hwif_t *hwif)
275{
276 struct pci_dev *dev = to_pci_dev(hwif->dev);
277
278 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
279 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
280 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
281 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
282 return ((1 << (hwif->channel + 14)) &
283 dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
284 return ATA_CBL_PATA40;
285}
286
287/* Sun Cobalt Alpine hardware avoids the 80-pin cable
288 * detect issue by attaching the drives directly to the board.
289 * This check follows the Dell precedent (how scary is that?!)
290 *
291 * WARNING: this only works on Alpine hardware!
292 */
293static u8 ata66_svwks_cobalt(ide_hwif_t *hwif)
294{
295 struct pci_dev *dev = to_pci_dev(hwif->dev);
296
297 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
298 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
299 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
300 return ((1 << (hwif->channel + 14)) &
301 dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
302 return ATA_CBL_PATA40;
303}
304
305static u8 svwks_cable_detect(ide_hwif_t *hwif)
306{
307 struct pci_dev *dev = to_pci_dev(hwif->dev);
308
309 /* Server Works */
310 if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
311 return ata66_svwks_svwks (hwif);
312
313 /* Dell PowerEdge */
314 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
315 return ata66_svwks_dell (hwif);
316
317 /* Cobalt Alpine */
318 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
319 return ata66_svwks_cobalt (hwif);
320
321 /* Per Specified Design by OEM, and ASIC Architect */
322 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
323 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
324 return ATA_CBL_PATA80;
325
326 return ATA_CBL_PATA40;
327}
328
329static const struct ide_port_ops osb4_port_ops = {
330 .set_pio_mode = svwks_set_pio_mode,
331 .set_dma_mode = svwks_set_dma_mode,
332};
333
334static const struct ide_port_ops svwks_port_ops = {
335 .set_pio_mode = svwks_set_pio_mode,
336 .set_dma_mode = svwks_set_dma_mode,
337 .udma_filter = svwks_udma_filter,
338 .cable_detect = svwks_cable_detect,
339};
340
341static const struct ide_port_info serverworks_chipsets[] = {
342 { /* 0: OSB4 */
343 .name = DRV_NAME,
344 .init_chipset = init_chipset_svwks,
345 .port_ops = &osb4_port_ops,
346 .pio_mask = ATA_PIO4,
347 .mwdma_mask = ATA_MWDMA2,
348 .udma_mask = 0x00, /* UDMA is problematic on OSB4 */
349 },
350 { /* 1: CSB5 */
351 .name = DRV_NAME,
352 .init_chipset = init_chipset_svwks,
353 .port_ops = &svwks_port_ops,
354 .pio_mask = ATA_PIO4,
355 .mwdma_mask = ATA_MWDMA2,
356 .udma_mask = ATA_UDMA5,
357 },
358 { /* 2: CSB6 */
359 .name = DRV_NAME,
360 .init_chipset = init_chipset_svwks,
361 .port_ops = &svwks_port_ops,
362 .pio_mask = ATA_PIO4,
363 .mwdma_mask = ATA_MWDMA2,
364 .udma_mask = ATA_UDMA5,
365 },
366 { /* 3: CSB6-2 */
367 .name = DRV_NAME,
368 .init_chipset = init_chipset_svwks,
369 .port_ops = &svwks_port_ops,
370 .host_flags = IDE_HFLAG_SINGLE,
371 .pio_mask = ATA_PIO4,
372 .mwdma_mask = ATA_MWDMA2,
373 .udma_mask = ATA_UDMA5,
374 },
375 { /* 4: HT1000 */
376 .name = DRV_NAME,
377 .init_chipset = init_chipset_svwks,
378 .port_ops = &svwks_port_ops,
379 .host_flags = IDE_HFLAG_SINGLE,
380 .pio_mask = ATA_PIO4,
381 .mwdma_mask = ATA_MWDMA2,
382 .udma_mask = ATA_UDMA5,
383 }
384};
385
386/**
387 * svwks_init_one - called when a OSB/CSB is found
388 * @dev: the svwks device
389 * @id: the matching pci id
390 *
391 * Called when the PCI registration layer (or the IDE initialization)
392 * finds a device matching our IDE device tables.
393 */
394
395static int svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
396{
397 struct ide_port_info d;
398 u8 idx = id->driver_data;
399
400 d = serverworks_chipsets[idx];
401
402 if (idx == 1)
403 d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
404 else if (idx == 2 || idx == 3) {
405 if ((PCI_FUNC(dev->devfn) & 1) == 0) {
406 if (pci_resource_start(dev, 0) != 0x01f1)
407 d.host_flags |= IDE_HFLAG_NON_BOOTABLE;
408 d.host_flags |= IDE_HFLAG_SINGLE;
409 } else
410 d.host_flags &= ~IDE_HFLAG_SINGLE;
411 }
412
413 return ide_pci_init_one(dev, &d, NULL);
414}
415
416static const struct pci_device_id svwks_pci_tbl[] = {
417 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0 },
418 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 1 },
419 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2 },
420 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 3 },
421 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 },
422 { 0, },
423};
424MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
425
426static struct pci_driver svwks_pci_driver = {
427 .name = "Serverworks_IDE",
428 .id_table = svwks_pci_tbl,
429 .probe = svwks_init_one,
430 .remove = ide_pci_remove,
431 .suspend = ide_pci_suspend,
432 .resume = ide_pci_resume,
433};
434
435static int __init svwks_ide_init(void)
436{
437 return ide_pci_register_driver(&svwks_pci_driver);
438}
439
440static void __exit svwks_ide_exit(void)
441{
442 pci_unregister_driver(&svwks_pci_driver);
443}
444
445module_init(svwks_ide_init);
446module_exit(svwks_ide_exit);
447
448MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick, Bartlomiej Zolnierkiewicz");
449MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
450MODULE_LICENSE("GPL");