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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Broadcom Kona GPIO Driver
4 *
5 * Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>
6 * Copyright (C) 2012-2014 Broadcom Corporation
7 */
8
9#include <linux/bitops.h>
10#include <linux/err.h>
11#include <linux/gpio/driver.h>
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/irqdomain.h>
15#include <linux/irqchip/chained_irq.h>
16#include <linux/mod_devicetable.h>
17#include <linux/platform_device.h>
18#include <linux/property.h>
19
20#define BCM_GPIO_PASSWD 0x00a5a501
21#define GPIO_PER_BANK 32
22#define GPIO_MAX_BANK_NUM 8
23
24#define GPIO_BANK(gpio) ((gpio) >> 5)
25#define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
26
27/* There is a GPIO control register for each GPIO */
28#define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2))
29
30/* The remaining registers are per GPIO bank */
31#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
32#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
33#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
34#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
35#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
36#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
37#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
38#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
39
40#define GPIO_GPPWR_OFFSET 0x00000520
41
42#define GPIO_GPCTR0_DBR_SHIFT 5
43#define GPIO_GPCTR0_DBR_MASK 0x000001e0
44
45#define GPIO_GPCTR0_ITR_SHIFT 3
46#define GPIO_GPCTR0_ITR_MASK 0x00000018
47#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
48#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
49#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
50
51#define GPIO_GPCTR0_IOTR_MASK 0x00000001
52#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
53#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
54
55#define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
56
57#define LOCK_CODE 0xffffffff
58#define UNLOCK_CODE 0x00000000
59
60struct bcm_kona_gpio {
61 void __iomem *reg_base;
62 int num_bank;
63 raw_spinlock_t lock;
64 struct gpio_chip gpio_chip;
65 struct irq_domain *irq_domain;
66 struct bcm_kona_gpio_bank *banks;
67};
68
69struct bcm_kona_gpio_bank {
70 int id;
71 int irq;
72 /* Used in the interrupt handler */
73 struct bcm_kona_gpio *kona_gpio;
74};
75
76static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
77 int bank_id, u32 lockcode)
78{
79 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
80 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
81}
82
83static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
84 unsigned gpio)
85{
86 u32 val;
87 unsigned long flags;
88 int bank_id = GPIO_BANK(gpio);
89
90 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
91
92 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
93 val |= BIT(gpio);
94 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
95
96 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
97}
98
99static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
100 unsigned gpio)
101{
102 u32 val;
103 unsigned long flags;
104 int bank_id = GPIO_BANK(gpio);
105
106 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
107
108 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
109 val &= ~BIT(gpio);
110 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
111
112 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
113}
114
115static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
116{
117 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
118 void __iomem *reg_base = kona_gpio->reg_base;
119 u32 val;
120
121 val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
122 return val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
123}
124
125static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
126{
127 struct bcm_kona_gpio *kona_gpio;
128 void __iomem *reg_base;
129 int bank_id = GPIO_BANK(gpio);
130 int bit = GPIO_BIT(gpio);
131 u32 val, reg_offset;
132 unsigned long flags;
133
134 kona_gpio = gpiochip_get_data(chip);
135 reg_base = kona_gpio->reg_base;
136 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
137
138 /* this function only applies to output pin */
139 if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
140 goto out;
141
142 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
143
144 val = readl(reg_base + reg_offset);
145 val |= BIT(bit);
146 writel(val, reg_base + reg_offset);
147
148out:
149 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
150}
151
152static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
153{
154 struct bcm_kona_gpio *kona_gpio;
155 void __iomem *reg_base;
156 int bank_id = GPIO_BANK(gpio);
157 int bit = GPIO_BIT(gpio);
158 u32 val, reg_offset;
159 unsigned long flags;
160
161 kona_gpio = gpiochip_get_data(chip);
162 reg_base = kona_gpio->reg_base;
163 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
164
165 if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
166 reg_offset = GPIO_IN_STATUS(bank_id);
167 else
168 reg_offset = GPIO_OUT_STATUS(bank_id);
169
170 /* read the GPIO bank status */
171 val = readl(reg_base + reg_offset);
172
173 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
174
175 /* return the specified bit status */
176 return !!(val & BIT(bit));
177}
178
179static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
180{
181 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
182
183 bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
184 return 0;
185}
186
187static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
188{
189 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
190
191 bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
192}
193
194static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
195{
196 struct bcm_kona_gpio *kona_gpio;
197 void __iomem *reg_base;
198 u32 val;
199 unsigned long flags;
200
201 kona_gpio = gpiochip_get_data(chip);
202 reg_base = kona_gpio->reg_base;
203 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
204
205 val = readl(reg_base + GPIO_CONTROL(gpio));
206 val &= ~GPIO_GPCTR0_IOTR_MASK;
207 val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
208 writel(val, reg_base + GPIO_CONTROL(gpio));
209
210 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
211
212 return 0;
213}
214
215static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
216 unsigned gpio, int value)
217{
218 struct bcm_kona_gpio *kona_gpio;
219 void __iomem *reg_base;
220 int bank_id = GPIO_BANK(gpio);
221 int bit = GPIO_BIT(gpio);
222 u32 val, reg_offset;
223 unsigned long flags;
224
225 kona_gpio = gpiochip_get_data(chip);
226 reg_base = kona_gpio->reg_base;
227 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
228
229 val = readl(reg_base + GPIO_CONTROL(gpio));
230 val &= ~GPIO_GPCTR0_IOTR_MASK;
231 val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
232 writel(val, reg_base + GPIO_CONTROL(gpio));
233 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
234
235 val = readl(reg_base + reg_offset);
236 val |= BIT(bit);
237 writel(val, reg_base + reg_offset);
238
239 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
240
241 return 0;
242}
243
244static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
245{
246 struct bcm_kona_gpio *kona_gpio;
247
248 kona_gpio = gpiochip_get_data(chip);
249 if (gpio >= kona_gpio->gpio_chip.ngpio)
250 return -ENXIO;
251 return irq_create_mapping(kona_gpio->irq_domain, gpio);
252}
253
254static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
255 unsigned debounce)
256{
257 struct bcm_kona_gpio *kona_gpio;
258 void __iomem *reg_base;
259 u32 val, res;
260 unsigned long flags;
261
262 kona_gpio = gpiochip_get_data(chip);
263 reg_base = kona_gpio->reg_base;
264 /* debounce must be 1-128ms (or 0) */
265 if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
266 dev_err(chip->parent, "Debounce value %u not in range\n",
267 debounce);
268 return -EINVAL;
269 }
270
271 /* calculate debounce bit value */
272 if (debounce != 0) {
273 /* Convert to ms */
274 debounce /= 1000;
275 /* find the MSB */
276 res = fls(debounce) - 1;
277 /* Check if MSB-1 is set (round up or down) */
278 if (res > 0 && (debounce & BIT(res - 1)))
279 res++;
280 }
281
282 /* spin lock for read-modify-write of the GPIO register */
283 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
284
285 val = readl(reg_base + GPIO_CONTROL(gpio));
286 val &= ~GPIO_GPCTR0_DBR_MASK;
287
288 if (debounce == 0) {
289 /* disable debounce */
290 val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
291 } else {
292 val |= GPIO_GPCTR0_DB_ENABLE_MASK |
293 (res << GPIO_GPCTR0_DBR_SHIFT);
294 }
295
296 writel(val, reg_base + GPIO_CONTROL(gpio));
297
298 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
299
300 return 0;
301}
302
303static int bcm_kona_gpio_set_config(struct gpio_chip *chip, unsigned gpio,
304 unsigned long config)
305{
306 u32 debounce;
307
308 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
309 return -ENOTSUPP;
310
311 debounce = pinconf_to_config_argument(config);
312 return bcm_kona_gpio_set_debounce(chip, gpio, debounce);
313}
314
315static const struct gpio_chip template_chip = {
316 .label = "bcm-kona-gpio",
317 .owner = THIS_MODULE,
318 .request = bcm_kona_gpio_request,
319 .free = bcm_kona_gpio_free,
320 .get_direction = bcm_kona_gpio_get_dir,
321 .direction_input = bcm_kona_gpio_direction_input,
322 .get = bcm_kona_gpio_get,
323 .direction_output = bcm_kona_gpio_direction_output,
324 .set = bcm_kona_gpio_set,
325 .set_config = bcm_kona_gpio_set_config,
326 .to_irq = bcm_kona_gpio_to_irq,
327 .base = 0,
328};
329
330static void bcm_kona_gpio_irq_ack(struct irq_data *d)
331{
332 struct bcm_kona_gpio *kona_gpio;
333 void __iomem *reg_base;
334 unsigned gpio = d->hwirq;
335 int bank_id = GPIO_BANK(gpio);
336 int bit = GPIO_BIT(gpio);
337 u32 val;
338 unsigned long flags;
339
340 kona_gpio = irq_data_get_irq_chip_data(d);
341 reg_base = kona_gpio->reg_base;
342 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
343
344 val = readl(reg_base + GPIO_INT_STATUS(bank_id));
345 val |= BIT(bit);
346 writel(val, reg_base + GPIO_INT_STATUS(bank_id));
347
348 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
349}
350
351static void bcm_kona_gpio_irq_mask(struct irq_data *d)
352{
353 struct bcm_kona_gpio *kona_gpio;
354 void __iomem *reg_base;
355 unsigned gpio = d->hwirq;
356 int bank_id = GPIO_BANK(gpio);
357 int bit = GPIO_BIT(gpio);
358 u32 val;
359 unsigned long flags;
360
361 kona_gpio = irq_data_get_irq_chip_data(d);
362 reg_base = kona_gpio->reg_base;
363 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
364
365 val = readl(reg_base + GPIO_INT_MASK(bank_id));
366 val |= BIT(bit);
367 writel(val, reg_base + GPIO_INT_MASK(bank_id));
368 gpiochip_disable_irq(&kona_gpio->gpio_chip, gpio);
369
370 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
371}
372
373static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
374{
375 struct bcm_kona_gpio *kona_gpio;
376 void __iomem *reg_base;
377 unsigned gpio = d->hwirq;
378 int bank_id = GPIO_BANK(gpio);
379 int bit = GPIO_BIT(gpio);
380 u32 val;
381 unsigned long flags;
382
383 kona_gpio = irq_data_get_irq_chip_data(d);
384 reg_base = kona_gpio->reg_base;
385 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
386
387 val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
388 val |= BIT(bit);
389 writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
390 gpiochip_enable_irq(&kona_gpio->gpio_chip, gpio);
391
392 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
393}
394
395static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
396{
397 struct bcm_kona_gpio *kona_gpio;
398 void __iomem *reg_base;
399 unsigned gpio = d->hwirq;
400 u32 lvl_type;
401 u32 val;
402 unsigned long flags;
403
404 kona_gpio = irq_data_get_irq_chip_data(d);
405 reg_base = kona_gpio->reg_base;
406 switch (type & IRQ_TYPE_SENSE_MASK) {
407 case IRQ_TYPE_EDGE_RISING:
408 lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
409 break;
410
411 case IRQ_TYPE_EDGE_FALLING:
412 lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
413 break;
414
415 case IRQ_TYPE_EDGE_BOTH:
416 lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
417 break;
418
419 case IRQ_TYPE_LEVEL_HIGH:
420 case IRQ_TYPE_LEVEL_LOW:
421 /* BCM GPIO doesn't support level triggering */
422 default:
423 dev_err(kona_gpio->gpio_chip.parent,
424 "Invalid BCM GPIO irq type 0x%x\n", type);
425 return -EINVAL;
426 }
427
428 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
429
430 val = readl(reg_base + GPIO_CONTROL(gpio));
431 val &= ~GPIO_GPCTR0_ITR_MASK;
432 val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
433 writel(val, reg_base + GPIO_CONTROL(gpio));
434
435 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
436
437 return 0;
438}
439
440static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
441{
442 void __iomem *reg_base;
443 int bit, bank_id;
444 unsigned long sta;
445 struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
446 struct irq_chip *chip = irq_desc_get_chip(desc);
447
448 chained_irq_enter(chip, desc);
449
450 /*
451 * For bank interrupts, we can't use chip_data to store the kona_gpio
452 * pointer, since GIC needs it for its own purposes. Therefore, we get
453 * our pointer from the bank structure.
454 */
455 reg_base = bank->kona_gpio->reg_base;
456 bank_id = bank->id;
457
458 while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
459 (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
460 for_each_set_bit(bit, &sta, 32) {
461 int hwirq = GPIO_PER_BANK * bank_id + bit;
462 /*
463 * Clear interrupt before handler is called so we don't
464 * miss any interrupt occurred during executing them.
465 */
466 writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
467 BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
468 /* Invoke interrupt handler */
469 generic_handle_domain_irq(bank->kona_gpio->irq_domain,
470 hwirq);
471 }
472 }
473
474 chained_irq_exit(chip, desc);
475}
476
477static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
478{
479 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
480
481 return gpiochip_reqres_irq(&kona_gpio->gpio_chip, d->hwirq);
482}
483
484static void bcm_kona_gpio_irq_relres(struct irq_data *d)
485{
486 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
487
488 gpiochip_relres_irq(&kona_gpio->gpio_chip, d->hwirq);
489}
490
491static struct irq_chip bcm_gpio_irq_chip = {
492 .name = "bcm-kona-gpio",
493 .irq_ack = bcm_kona_gpio_irq_ack,
494 .irq_mask = bcm_kona_gpio_irq_mask,
495 .irq_unmask = bcm_kona_gpio_irq_unmask,
496 .irq_set_type = bcm_kona_gpio_irq_set_type,
497 .irq_request_resources = bcm_kona_gpio_irq_reqres,
498 .irq_release_resources = bcm_kona_gpio_irq_relres,
499};
500
501static struct of_device_id const bcm_kona_gpio_of_match[] = {
502 { .compatible = "brcm,kona-gpio" },
503 {}
504};
505
506/*
507 * This lock class tells lockdep that GPIO irqs are in a different
508 * category than their parents, so it won't report false recursion.
509 */
510static struct lock_class_key gpio_lock_class;
511static struct lock_class_key gpio_request_class;
512
513static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
514 irq_hw_number_t hwirq)
515{
516 int ret;
517
518 ret = irq_set_chip_data(irq, d->host_data);
519 if (ret < 0)
520 return ret;
521 irq_set_lockdep_class(irq, &gpio_lock_class, &gpio_request_class);
522 irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
523 irq_set_noprobe(irq);
524
525 return 0;
526}
527
528static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
529{
530 irq_set_chip_and_handler(irq, NULL, NULL);
531 irq_set_chip_data(irq, NULL);
532}
533
534static const struct irq_domain_ops bcm_kona_irq_ops = {
535 .map = bcm_kona_gpio_irq_map,
536 .unmap = bcm_kona_gpio_irq_unmap,
537 .xlate = irq_domain_xlate_twocell,
538};
539
540static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
541{
542 void __iomem *reg_base;
543 int i;
544
545 reg_base = kona_gpio->reg_base;
546 /* disable interrupts and clear status */
547 for (i = 0; i < kona_gpio->num_bank; i++) {
548 /* Unlock the entire bank first */
549 bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);
550 writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
551 writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
552 /* Now re-lock the bank */
553 bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);
554 }
555}
556
557static int bcm_kona_gpio_probe(struct platform_device *pdev)
558{
559 struct device *dev = &pdev->dev;
560 struct bcm_kona_gpio_bank *bank;
561 struct bcm_kona_gpio *kona_gpio;
562 struct gpio_chip *chip;
563 int ret;
564 int i;
565
566 kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
567 if (!kona_gpio)
568 return -ENOMEM;
569
570 kona_gpio->gpio_chip = template_chip;
571 chip = &kona_gpio->gpio_chip;
572 ret = platform_irq_count(pdev);
573 if (!ret) {
574 dev_err(dev, "Couldn't determine # GPIO banks\n");
575 return -ENOENT;
576 } else if (ret < 0) {
577 return dev_err_probe(dev, ret, "Couldn't determine GPIO banks\n");
578 }
579 kona_gpio->num_bank = ret;
580
581 if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
582 dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
583 GPIO_MAX_BANK_NUM);
584 return -ENXIO;
585 }
586 kona_gpio->banks = devm_kcalloc(dev,
587 kona_gpio->num_bank,
588 sizeof(*kona_gpio->banks),
589 GFP_KERNEL);
590 if (!kona_gpio->banks)
591 return -ENOMEM;
592
593 chip->parent = dev;
594 chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
595
596 kona_gpio->irq_domain = irq_domain_create_linear(dev_fwnode(dev),
597 chip->ngpio,
598 &bcm_kona_irq_ops,
599 kona_gpio);
600 if (!kona_gpio->irq_domain) {
601 dev_err(dev, "Couldn't allocate IRQ domain\n");
602 return -ENXIO;
603 }
604
605 kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
606 if (IS_ERR(kona_gpio->reg_base)) {
607 ret = PTR_ERR(kona_gpio->reg_base);
608 goto err_irq_domain;
609 }
610
611 for (i = 0; i < kona_gpio->num_bank; i++) {
612 bank = &kona_gpio->banks[i];
613 bank->id = i;
614 bank->irq = platform_get_irq(pdev, i);
615 bank->kona_gpio = kona_gpio;
616 if (bank->irq < 0) {
617 dev_err(dev, "Couldn't get IRQ for bank %d", i);
618 ret = -ENOENT;
619 goto err_irq_domain;
620 }
621 }
622
623 dev_info(&pdev->dev, "Setting up Kona GPIO\n");
624
625 bcm_kona_gpio_reset(kona_gpio);
626
627 ret = devm_gpiochip_add_data(dev, chip, kona_gpio);
628 if (ret < 0) {
629 dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
630 goto err_irq_domain;
631 }
632 for (i = 0; i < kona_gpio->num_bank; i++) {
633 bank = &kona_gpio->banks[i];
634 irq_set_chained_handler_and_data(bank->irq,
635 bcm_kona_gpio_irq_handler,
636 bank);
637 }
638
639 raw_spin_lock_init(&kona_gpio->lock);
640
641 return 0;
642
643err_irq_domain:
644 irq_domain_remove(kona_gpio->irq_domain);
645
646 return ret;
647}
648
649static struct platform_driver bcm_kona_gpio_driver = {
650 .driver = {
651 .name = "bcm-kona-gpio",
652 .of_match_table = bcm_kona_gpio_of_match,
653 },
654 .probe = bcm_kona_gpio_probe,
655};
656builtin_platform_driver(bcm_kona_gpio_driver);
1/*
2 * Broadcom Kona GPIO Driver
3 *
4 * Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>
5 * Copyright (C) 2012-2014 Broadcom Corporation
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/bitops.h>
18#include <linux/err.h>
19#include <linux/io.h>
20#include <linux/gpio/driver.h>
21#include <linux/of_device.h>
22#include <linux/of_irq.h>
23#include <linux/init.h>
24#include <linux/irqdomain.h>
25#include <linux/irqchip/chained_irq.h>
26
27#define BCM_GPIO_PASSWD 0x00a5a501
28#define GPIO_PER_BANK 32
29#define GPIO_MAX_BANK_NUM 8
30
31#define GPIO_BANK(gpio) ((gpio) >> 5)
32#define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
33
34/* There is a GPIO control register for each GPIO */
35#define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2))
36
37/* The remaining registers are per GPIO bank */
38#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
39#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
40#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
41#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
42#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
43#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
44#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
45#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
46
47#define GPIO_GPPWR_OFFSET 0x00000520
48
49#define GPIO_GPCTR0_DBR_SHIFT 5
50#define GPIO_GPCTR0_DBR_MASK 0x000001e0
51
52#define GPIO_GPCTR0_ITR_SHIFT 3
53#define GPIO_GPCTR0_ITR_MASK 0x00000018
54#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
55#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
56#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
57
58#define GPIO_GPCTR0_IOTR_MASK 0x00000001
59#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
60#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
61
62#define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
63
64#define LOCK_CODE 0xffffffff
65#define UNLOCK_CODE 0x00000000
66
67struct bcm_kona_gpio {
68 void __iomem *reg_base;
69 int num_bank;
70 raw_spinlock_t lock;
71 struct gpio_chip gpio_chip;
72 struct irq_domain *irq_domain;
73 struct bcm_kona_gpio_bank *banks;
74 struct platform_device *pdev;
75};
76
77struct bcm_kona_gpio_bank {
78 int id;
79 int irq;
80 /* Used in the interrupt handler */
81 struct bcm_kona_gpio *kona_gpio;
82};
83
84static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
85 int bank_id, u32 lockcode)
86{
87 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
88 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
89}
90
91static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
92 unsigned gpio)
93{
94 u32 val;
95 unsigned long flags;
96 int bank_id = GPIO_BANK(gpio);
97
98 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
99
100 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
101 val |= BIT(gpio);
102 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
103
104 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
105}
106
107static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
108 unsigned gpio)
109{
110 u32 val;
111 unsigned long flags;
112 int bank_id = GPIO_BANK(gpio);
113
114 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
115
116 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
117 val &= ~BIT(gpio);
118 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
119
120 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
121}
122
123static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
124{
125 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
126 void __iomem *reg_base = kona_gpio->reg_base;
127 u32 val;
128
129 val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
130 return !!val;
131}
132
133static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
134{
135 struct bcm_kona_gpio *kona_gpio;
136 void __iomem *reg_base;
137 int bank_id = GPIO_BANK(gpio);
138 int bit = GPIO_BIT(gpio);
139 u32 val, reg_offset;
140 unsigned long flags;
141
142 kona_gpio = gpiochip_get_data(chip);
143 reg_base = kona_gpio->reg_base;
144 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
145
146 /* this function only applies to output pin */
147 if (bcm_kona_gpio_get_dir(chip, gpio) == 1)
148 goto out;
149
150 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
151
152 val = readl(reg_base + reg_offset);
153 val |= BIT(bit);
154 writel(val, reg_base + reg_offset);
155
156out:
157 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
158}
159
160static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
161{
162 struct bcm_kona_gpio *kona_gpio;
163 void __iomem *reg_base;
164 int bank_id = GPIO_BANK(gpio);
165 int bit = GPIO_BIT(gpio);
166 u32 val, reg_offset;
167 unsigned long flags;
168
169 kona_gpio = gpiochip_get_data(chip);
170 reg_base = kona_gpio->reg_base;
171 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
172
173 if (bcm_kona_gpio_get_dir(chip, gpio) == 1)
174 reg_offset = GPIO_IN_STATUS(bank_id);
175 else
176 reg_offset = GPIO_OUT_STATUS(bank_id);
177
178 /* read the GPIO bank status */
179 val = readl(reg_base + reg_offset);
180
181 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
182
183 /* return the specified bit status */
184 return !!(val & BIT(bit));
185}
186
187static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
188{
189 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
190
191 bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
192 return 0;
193}
194
195static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
196{
197 struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
198
199 bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
200}
201
202static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
203{
204 struct bcm_kona_gpio *kona_gpio;
205 void __iomem *reg_base;
206 u32 val;
207 unsigned long flags;
208
209 kona_gpio = gpiochip_get_data(chip);
210 reg_base = kona_gpio->reg_base;
211 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
212
213 val = readl(reg_base + GPIO_CONTROL(gpio));
214 val &= ~GPIO_GPCTR0_IOTR_MASK;
215 val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
216 writel(val, reg_base + GPIO_CONTROL(gpio));
217
218 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
219
220 return 0;
221}
222
223static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
224 unsigned gpio, int value)
225{
226 struct bcm_kona_gpio *kona_gpio;
227 void __iomem *reg_base;
228 int bank_id = GPIO_BANK(gpio);
229 int bit = GPIO_BIT(gpio);
230 u32 val, reg_offset;
231 unsigned long flags;
232
233 kona_gpio = gpiochip_get_data(chip);
234 reg_base = kona_gpio->reg_base;
235 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
236
237 val = readl(reg_base + GPIO_CONTROL(gpio));
238 val &= ~GPIO_GPCTR0_IOTR_MASK;
239 val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
240 writel(val, reg_base + GPIO_CONTROL(gpio));
241 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
242
243 val = readl(reg_base + reg_offset);
244 val |= BIT(bit);
245 writel(val, reg_base + reg_offset);
246
247 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
248
249 return 0;
250}
251
252static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
253{
254 struct bcm_kona_gpio *kona_gpio;
255
256 kona_gpio = gpiochip_get_data(chip);
257 if (gpio >= kona_gpio->gpio_chip.ngpio)
258 return -ENXIO;
259 return irq_create_mapping(kona_gpio->irq_domain, gpio);
260}
261
262static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
263 unsigned debounce)
264{
265 struct bcm_kona_gpio *kona_gpio;
266 void __iomem *reg_base;
267 u32 val, res;
268 unsigned long flags;
269
270 kona_gpio = gpiochip_get_data(chip);
271 reg_base = kona_gpio->reg_base;
272 /* debounce must be 1-128ms (or 0) */
273 if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
274 dev_err(chip->parent, "Debounce value %u not in range\n",
275 debounce);
276 return -EINVAL;
277 }
278
279 /* calculate debounce bit value */
280 if (debounce != 0) {
281 /* Convert to ms */
282 debounce /= 1000;
283 /* find the MSB */
284 res = fls(debounce) - 1;
285 /* Check if MSB-1 is set (round up or down) */
286 if (res > 0 && (debounce & BIT(res - 1)))
287 res++;
288 }
289
290 /* spin lock for read-modify-write of the GPIO register */
291 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
292
293 val = readl(reg_base + GPIO_CONTROL(gpio));
294 val &= ~GPIO_GPCTR0_DBR_MASK;
295
296 if (debounce == 0) {
297 /* disable debounce */
298 val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
299 } else {
300 val |= GPIO_GPCTR0_DB_ENABLE_MASK |
301 (res << GPIO_GPCTR0_DBR_SHIFT);
302 }
303
304 writel(val, reg_base + GPIO_CONTROL(gpio));
305
306 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
307
308 return 0;
309}
310
311static int bcm_kona_gpio_set_config(struct gpio_chip *chip, unsigned gpio,
312 unsigned long config)
313{
314 u32 debounce;
315
316 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
317 return -ENOTSUPP;
318
319 debounce = pinconf_to_config_argument(config);
320 return bcm_kona_gpio_set_debounce(chip, gpio, debounce);
321}
322
323static const struct gpio_chip template_chip = {
324 .label = "bcm-kona-gpio",
325 .owner = THIS_MODULE,
326 .request = bcm_kona_gpio_request,
327 .free = bcm_kona_gpio_free,
328 .get_direction = bcm_kona_gpio_get_dir,
329 .direction_input = bcm_kona_gpio_direction_input,
330 .get = bcm_kona_gpio_get,
331 .direction_output = bcm_kona_gpio_direction_output,
332 .set = bcm_kona_gpio_set,
333 .set_config = bcm_kona_gpio_set_config,
334 .to_irq = bcm_kona_gpio_to_irq,
335 .base = 0,
336};
337
338static void bcm_kona_gpio_irq_ack(struct irq_data *d)
339{
340 struct bcm_kona_gpio *kona_gpio;
341 void __iomem *reg_base;
342 unsigned gpio = d->hwirq;
343 int bank_id = GPIO_BANK(gpio);
344 int bit = GPIO_BIT(gpio);
345 u32 val;
346 unsigned long flags;
347
348 kona_gpio = irq_data_get_irq_chip_data(d);
349 reg_base = kona_gpio->reg_base;
350 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
351
352 val = readl(reg_base + GPIO_INT_STATUS(bank_id));
353 val |= BIT(bit);
354 writel(val, reg_base + GPIO_INT_STATUS(bank_id));
355
356 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
357}
358
359static void bcm_kona_gpio_irq_mask(struct irq_data *d)
360{
361 struct bcm_kona_gpio *kona_gpio;
362 void __iomem *reg_base;
363 unsigned gpio = d->hwirq;
364 int bank_id = GPIO_BANK(gpio);
365 int bit = GPIO_BIT(gpio);
366 u32 val;
367 unsigned long flags;
368
369 kona_gpio = irq_data_get_irq_chip_data(d);
370 reg_base = kona_gpio->reg_base;
371 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
372
373 val = readl(reg_base + GPIO_INT_MASK(bank_id));
374 val |= BIT(bit);
375 writel(val, reg_base + GPIO_INT_MASK(bank_id));
376 gpiochip_disable_irq(&kona_gpio->gpio_chip, gpio);
377
378 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
379}
380
381static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
382{
383 struct bcm_kona_gpio *kona_gpio;
384 void __iomem *reg_base;
385 unsigned gpio = d->hwirq;
386 int bank_id = GPIO_BANK(gpio);
387 int bit = GPIO_BIT(gpio);
388 u32 val;
389 unsigned long flags;
390
391 kona_gpio = irq_data_get_irq_chip_data(d);
392 reg_base = kona_gpio->reg_base;
393 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
394
395 val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
396 val |= BIT(bit);
397 writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
398 gpiochip_enable_irq(&kona_gpio->gpio_chip, gpio);
399
400 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
401}
402
403static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
404{
405 struct bcm_kona_gpio *kona_gpio;
406 void __iomem *reg_base;
407 unsigned gpio = d->hwirq;
408 u32 lvl_type;
409 u32 val;
410 unsigned long flags;
411
412 kona_gpio = irq_data_get_irq_chip_data(d);
413 reg_base = kona_gpio->reg_base;
414 switch (type & IRQ_TYPE_SENSE_MASK) {
415 case IRQ_TYPE_EDGE_RISING:
416 lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
417 break;
418
419 case IRQ_TYPE_EDGE_FALLING:
420 lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
421 break;
422
423 case IRQ_TYPE_EDGE_BOTH:
424 lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
425 break;
426
427 case IRQ_TYPE_LEVEL_HIGH:
428 case IRQ_TYPE_LEVEL_LOW:
429 /* BCM GPIO doesn't support level triggering */
430 default:
431 dev_err(kona_gpio->gpio_chip.parent,
432 "Invalid BCM GPIO irq type 0x%x\n", type);
433 return -EINVAL;
434 }
435
436 raw_spin_lock_irqsave(&kona_gpio->lock, flags);
437
438 val = readl(reg_base + GPIO_CONTROL(gpio));
439 val &= ~GPIO_GPCTR0_ITR_MASK;
440 val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
441 writel(val, reg_base + GPIO_CONTROL(gpio));
442
443 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
444
445 return 0;
446}
447
448static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
449{
450 void __iomem *reg_base;
451 int bit, bank_id;
452 unsigned long sta;
453 struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
454 struct irq_chip *chip = irq_desc_get_chip(desc);
455
456 chained_irq_enter(chip, desc);
457
458 /*
459 * For bank interrupts, we can't use chip_data to store the kona_gpio
460 * pointer, since GIC needs it for its own purposes. Therefore, we get
461 * our pointer from the bank structure.
462 */
463 reg_base = bank->kona_gpio->reg_base;
464 bank_id = bank->id;
465
466 while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
467 (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
468 for_each_set_bit(bit, &sta, 32) {
469 int hwirq = GPIO_PER_BANK * bank_id + bit;
470 int child_irq =
471 irq_find_mapping(bank->kona_gpio->irq_domain,
472 hwirq);
473 /*
474 * Clear interrupt before handler is called so we don't
475 * miss any interrupt occurred during executing them.
476 */
477 writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
478 BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
479 /* Invoke interrupt handler */
480 generic_handle_irq(child_irq);
481 }
482 }
483
484 chained_irq_exit(chip, desc);
485}
486
487static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
488{
489 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
490
491 return gpiochip_reqres_irq(&kona_gpio->gpio_chip, d->hwirq);
492}
493
494static void bcm_kona_gpio_irq_relres(struct irq_data *d)
495{
496 struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
497
498 gpiochip_relres_irq(&kona_gpio->gpio_chip, d->hwirq);
499}
500
501static struct irq_chip bcm_gpio_irq_chip = {
502 .name = "bcm-kona-gpio",
503 .irq_ack = bcm_kona_gpio_irq_ack,
504 .irq_mask = bcm_kona_gpio_irq_mask,
505 .irq_unmask = bcm_kona_gpio_irq_unmask,
506 .irq_set_type = bcm_kona_gpio_irq_set_type,
507 .irq_request_resources = bcm_kona_gpio_irq_reqres,
508 .irq_release_resources = bcm_kona_gpio_irq_relres,
509};
510
511static struct of_device_id const bcm_kona_gpio_of_match[] = {
512 { .compatible = "brcm,kona-gpio" },
513 {}
514};
515
516/*
517 * This lock class tells lockdep that GPIO irqs are in a different
518 * category than their parents, so it won't report false recursion.
519 */
520static struct lock_class_key gpio_lock_class;
521static struct lock_class_key gpio_request_class;
522
523static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
524 irq_hw_number_t hwirq)
525{
526 int ret;
527
528 ret = irq_set_chip_data(irq, d->host_data);
529 if (ret < 0)
530 return ret;
531 irq_set_lockdep_class(irq, &gpio_lock_class, &gpio_request_class);
532 irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
533 irq_set_noprobe(irq);
534
535 return 0;
536}
537
538static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
539{
540 irq_set_chip_and_handler(irq, NULL, NULL);
541 irq_set_chip_data(irq, NULL);
542}
543
544static const struct irq_domain_ops bcm_kona_irq_ops = {
545 .map = bcm_kona_gpio_irq_map,
546 .unmap = bcm_kona_gpio_irq_unmap,
547 .xlate = irq_domain_xlate_twocell,
548};
549
550static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
551{
552 void __iomem *reg_base;
553 int i;
554
555 reg_base = kona_gpio->reg_base;
556 /* disable interrupts and clear status */
557 for (i = 0; i < kona_gpio->num_bank; i++) {
558 /* Unlock the entire bank first */
559 bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);
560 writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
561 writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
562 /* Now re-lock the bank */
563 bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);
564 }
565}
566
567static int bcm_kona_gpio_probe(struct platform_device *pdev)
568{
569 struct device *dev = &pdev->dev;
570 const struct of_device_id *match;
571 struct bcm_kona_gpio_bank *bank;
572 struct bcm_kona_gpio *kona_gpio;
573 struct gpio_chip *chip;
574 int ret;
575 int i;
576
577 match = of_match_device(bcm_kona_gpio_of_match, dev);
578 if (!match) {
579 dev_err(dev, "Failed to find gpio controller\n");
580 return -ENODEV;
581 }
582
583 kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
584 if (!kona_gpio)
585 return -ENOMEM;
586
587 kona_gpio->gpio_chip = template_chip;
588 chip = &kona_gpio->gpio_chip;
589 kona_gpio->num_bank = of_irq_count(dev->of_node);
590 if (kona_gpio->num_bank == 0) {
591 dev_err(dev, "Couldn't determine # GPIO banks\n");
592 return -ENOENT;
593 }
594 if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
595 dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
596 GPIO_MAX_BANK_NUM);
597 return -ENXIO;
598 }
599 kona_gpio->banks = devm_kcalloc(dev,
600 kona_gpio->num_bank,
601 sizeof(*kona_gpio->banks),
602 GFP_KERNEL);
603 if (!kona_gpio->banks)
604 return -ENOMEM;
605
606 kona_gpio->pdev = pdev;
607 platform_set_drvdata(pdev, kona_gpio);
608 chip->of_node = dev->of_node;
609 chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
610
611 kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
612 chip->ngpio,
613 &bcm_kona_irq_ops,
614 kona_gpio);
615 if (!kona_gpio->irq_domain) {
616 dev_err(dev, "Couldn't allocate IRQ domain\n");
617 return -ENXIO;
618 }
619
620 kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
621 if (IS_ERR(kona_gpio->reg_base)) {
622 ret = -ENXIO;
623 goto err_irq_domain;
624 }
625
626 for (i = 0; i < kona_gpio->num_bank; i++) {
627 bank = &kona_gpio->banks[i];
628 bank->id = i;
629 bank->irq = platform_get_irq(pdev, i);
630 bank->kona_gpio = kona_gpio;
631 if (bank->irq < 0) {
632 dev_err(dev, "Couldn't get IRQ for bank %d", i);
633 ret = -ENOENT;
634 goto err_irq_domain;
635 }
636 }
637
638 dev_info(&pdev->dev, "Setting up Kona GPIO\n");
639
640 bcm_kona_gpio_reset(kona_gpio);
641
642 ret = devm_gpiochip_add_data(dev, chip, kona_gpio);
643 if (ret < 0) {
644 dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
645 goto err_irq_domain;
646 }
647 for (i = 0; i < kona_gpio->num_bank; i++) {
648 bank = &kona_gpio->banks[i];
649 irq_set_chained_handler_and_data(bank->irq,
650 bcm_kona_gpio_irq_handler,
651 bank);
652 }
653
654 raw_spin_lock_init(&kona_gpio->lock);
655
656 return 0;
657
658err_irq_domain:
659 irq_domain_remove(kona_gpio->irq_domain);
660
661 return ret;
662}
663
664static struct platform_driver bcm_kona_gpio_driver = {
665 .driver = {
666 .name = "bcm-kona-gpio",
667 .of_match_table = bcm_kona_gpio_of_match,
668 },
669 .probe = bcm_kona_gpio_probe,
670};
671builtin_platform_driver(bcm_kona_gpio_driver);