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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * This file contains driver for the Cadence Triple Timer Counter Rev 06
4 *
5 * Copyright (C) 2011-2013 Xilinx
6 *
7 * based on arch/mips/kernel/time.c timer driver
8 */
9
10#include <linux/clk.h>
11#include <linux/interrupt.h>
12#include <linux/clockchips.h>
13#include <linux/clocksource.h>
14#include <linux/of_address.h>
15#include <linux/of_irq.h>
16#include <linux/platform_device.h>
17#include <linux/slab.h>
18#include <linux/sched_clock.h>
19#include <linux/module.h>
20#include <linux/of_platform.h>
21
22/*
23 * This driver configures the 2 16/32-bit count-up timers as follows:
24 *
25 * T1: Timer 1, clocksource for generic timekeeping
26 * T2: Timer 2, clockevent source for hrtimers
27 * T3: Timer 3, <unused>
28 *
29 * The input frequency to the timer module for emulation is 2.5MHz which is
30 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
31 * the timers are clocked at 78.125KHz (12.8 us resolution).
32
33 * The input frequency to the timer module in silicon is configurable and
34 * obtained from device tree. The pre-scaler of 32 is used.
35 */
36
37/*
38 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
39 * and use same offsets for Timer 2
40 */
41#define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
42#define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
43#define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
44#define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
45#define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
46#define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
47
48#define TTC_CNT_CNTRL_DISABLE_MASK 0x1
49
50#define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */
51#define TTC_CLK_CNTRL_PSV_MASK 0x1e
52#define TTC_CLK_CNTRL_PSV_SHIFT 1
53
54/*
55 * Setup the timers to use pre-scaling, using a fixed value for now that will
56 * work across most input frequency, but it may need to be more dynamic
57 */
58#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
59#define PRESCALE 2048 /* The exponent must match this */
60#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
61#define CLK_CNTRL_PRESCALE_EN 1
62#define CNT_CNTRL_RESET (1 << 4)
63
64#define MAX_F_ERR 50
65
66/**
67 * struct ttc_timer - This definition defines local timer structure
68 *
69 * @base_addr: Base address of timer
70 * @freq: Timer input clock frequency
71 * @clk: Associated clock source
72 * @clk_rate_change_nb: Notifier block for clock rate changes
73 */
74struct ttc_timer {
75 void __iomem *base_addr;
76 unsigned long freq;
77 struct clk *clk;
78 struct notifier_block clk_rate_change_nb;
79};
80
81#define to_ttc_timer(x) \
82 container_of(x, struct ttc_timer, clk_rate_change_nb)
83
84struct ttc_timer_clocksource {
85 u32 scale_clk_ctrl_reg_old;
86 u32 scale_clk_ctrl_reg_new;
87 struct ttc_timer ttc;
88 struct clocksource cs;
89};
90
91#define to_ttc_timer_clksrc(x) \
92 container_of(x, struct ttc_timer_clocksource, cs)
93
94struct ttc_timer_clockevent {
95 struct ttc_timer ttc;
96 struct clock_event_device ce;
97};
98
99#define to_ttc_timer_clkevent(x) \
100 container_of(x, struct ttc_timer_clockevent, ce)
101
102static void __iomem *ttc_sched_clock_val_reg;
103
104/**
105 * ttc_set_interval - Set the timer interval value
106 *
107 * @timer: Pointer to the timer instance
108 * @cycles: Timer interval ticks
109 **/
110static void ttc_set_interval(struct ttc_timer *timer,
111 unsigned long cycles)
112{
113 u32 ctrl_reg;
114
115 /* Disable the counter, set the counter value and re-enable counter */
116 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
117 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
118 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
119
120 writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
121
122 /*
123 * Reset the counter (0x10) so that it starts from 0, one-shot
124 * mode makes this needed for timing to be right.
125 */
126 ctrl_reg |= CNT_CNTRL_RESET;
127 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
128 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
129}
130
131/**
132 * ttc_clock_event_interrupt - Clock event timer interrupt handler
133 *
134 * @irq: IRQ number of the Timer
135 * @dev_id: void pointer to the ttc_timer instance
136 *
137 * Returns: Always IRQ_HANDLED - success
138 **/
139static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
140{
141 struct ttc_timer_clockevent *ttce = dev_id;
142 struct ttc_timer *timer = &ttce->ttc;
143
144 /* Acknowledge the interrupt and call event handler */
145 readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
146
147 ttce->ce.event_handler(&ttce->ce);
148
149 return IRQ_HANDLED;
150}
151
152/**
153 * __ttc_clocksource_read - Reads the timer counter register
154 * @cs: &clocksource to read from
155 *
156 * Returns: Current timer counter register value
157 **/
158static u64 __ttc_clocksource_read(struct clocksource *cs)
159{
160 struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
161
162 return (u64)readl_relaxed(timer->base_addr +
163 TTC_COUNT_VAL_OFFSET);
164}
165
166static u64 notrace ttc_sched_clock_read(void)
167{
168 return readl_relaxed(ttc_sched_clock_val_reg);
169}
170
171/**
172 * ttc_set_next_event - Sets the time interval for next event
173 *
174 * @cycles: Timer interval ticks
175 * @evt: Address of clock event instance
176 *
177 * Returns: Always %0 - success
178 **/
179static int ttc_set_next_event(unsigned long cycles,
180 struct clock_event_device *evt)
181{
182 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
183 struct ttc_timer *timer = &ttce->ttc;
184
185 ttc_set_interval(timer, cycles);
186 return 0;
187}
188
189/**
190 * ttc_shutdown - Sets the state of timer
191 * @evt: Address of clock event instance
192 *
193 * Used for shutdown or oneshot.
194 *
195 * Returns: Always %0 - success
196 **/
197static int ttc_shutdown(struct clock_event_device *evt)
198{
199 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
200 struct ttc_timer *timer = &ttce->ttc;
201 u32 ctrl_reg;
202
203 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
204 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
205 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
206 return 0;
207}
208
209/**
210 * ttc_set_periodic - Sets the state of timer
211 * @evt: Address of clock event instance
212 *
213 * Returns: Always %0 - success
214 */
215static int ttc_set_periodic(struct clock_event_device *evt)
216{
217 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
218 struct ttc_timer *timer = &ttce->ttc;
219
220 ttc_set_interval(timer,
221 DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ));
222 return 0;
223}
224
225static int ttc_resume(struct clock_event_device *evt)
226{
227 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
228 struct ttc_timer *timer = &ttce->ttc;
229 u32 ctrl_reg;
230
231 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
232 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
233 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
234 return 0;
235}
236
237static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
238 unsigned long event, void *data)
239{
240 struct clk_notifier_data *ndata = data;
241 struct ttc_timer *ttc = to_ttc_timer(nb);
242 struct ttc_timer_clocksource *ttccs = container_of(ttc,
243 struct ttc_timer_clocksource, ttc);
244
245 switch (event) {
246 case PRE_RATE_CHANGE:
247 {
248 u32 psv;
249 unsigned long factor, rate_low, rate_high;
250
251 if (ndata->new_rate > ndata->old_rate) {
252 factor = DIV_ROUND_CLOSEST(ndata->new_rate,
253 ndata->old_rate);
254 rate_low = ndata->old_rate;
255 rate_high = ndata->new_rate;
256 } else {
257 factor = DIV_ROUND_CLOSEST(ndata->old_rate,
258 ndata->new_rate);
259 rate_low = ndata->new_rate;
260 rate_high = ndata->old_rate;
261 }
262
263 if (!is_power_of_2(factor))
264 return NOTIFY_BAD;
265
266 if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR)
267 return NOTIFY_BAD;
268
269 factor = __ilog2_u32(factor);
270
271 /*
272 * store timer clock ctrl register so we can restore it in case
273 * of an abort.
274 */
275 ttccs->scale_clk_ctrl_reg_old =
276 readl_relaxed(ttccs->ttc.base_addr +
277 TTC_CLK_CNTRL_OFFSET);
278
279 psv = (ttccs->scale_clk_ctrl_reg_old &
280 TTC_CLK_CNTRL_PSV_MASK) >>
281 TTC_CLK_CNTRL_PSV_SHIFT;
282 if (ndata->new_rate < ndata->old_rate)
283 psv -= factor;
284 else
285 psv += factor;
286
287 /* prescaler within legal range? */
288 if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT))
289 return NOTIFY_BAD;
290
291 ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old &
292 ~TTC_CLK_CNTRL_PSV_MASK;
293 ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT;
294
295
296 /* scale down: adjust divider in post-change notification */
297 if (ndata->new_rate < ndata->old_rate)
298 return NOTIFY_DONE;
299
300 /* scale up: adjust divider now - before frequency change */
301 writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
302 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
303 break;
304 }
305 case POST_RATE_CHANGE:
306 /* scale up: pre-change notification did the adjustment */
307 if (ndata->new_rate > ndata->old_rate)
308 return NOTIFY_OK;
309
310 /* scale down: adjust divider now - after frequency change */
311 writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
312 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
313 break;
314
315 case ABORT_RATE_CHANGE:
316 /* we have to undo the adjustment in case we scale up */
317 if (ndata->new_rate < ndata->old_rate)
318 return NOTIFY_OK;
319
320 /* restore original register value */
321 writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
322 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
323 fallthrough;
324 default:
325 return NOTIFY_DONE;
326 }
327
328 return NOTIFY_DONE;
329}
330
331static int __init ttc_setup_clocksource(struct clk *clk, void __iomem *base,
332 u32 timer_width)
333{
334 struct ttc_timer_clocksource *ttccs;
335 int err;
336
337 ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
338 if (!ttccs)
339 return -ENOMEM;
340
341 ttccs->ttc.clk = clk;
342
343 err = clk_prepare_enable(ttccs->ttc.clk);
344 if (err) {
345 kfree(ttccs);
346 return err;
347 }
348
349 ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);
350
351 ttccs->ttc.clk_rate_change_nb.notifier_call =
352 ttc_rate_change_clocksource_cb;
353 ttccs->ttc.clk_rate_change_nb.next = NULL;
354
355 err = clk_notifier_register(ttccs->ttc.clk,
356 &ttccs->ttc.clk_rate_change_nb);
357 if (err)
358 pr_warn("Unable to register clock notifier.\n");
359
360 ttccs->ttc.base_addr = base;
361 ttccs->cs.name = "ttc_clocksource";
362 ttccs->cs.rating = 200;
363 ttccs->cs.read = __ttc_clocksource_read;
364 ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width);
365 ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
366
367 /*
368 * Setup the clock source counter to be an incrementing counter
369 * with no interrupt and it rolls over at 0xFFFF. Pre-scale
370 * it by 32 also. Let it start running now.
371 */
372 writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
373 writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
374 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
375 writel_relaxed(CNT_CNTRL_RESET,
376 ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
377
378 err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
379 if (err) {
380 kfree(ttccs);
381 return err;
382 }
383
384 ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
385 sched_clock_register(ttc_sched_clock_read, timer_width,
386 ttccs->ttc.freq / PRESCALE);
387
388 return 0;
389}
390
391static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
392 unsigned long event, void *data)
393{
394 struct clk_notifier_data *ndata = data;
395 struct ttc_timer *ttc = to_ttc_timer(nb);
396 struct ttc_timer_clockevent *ttcce = container_of(ttc,
397 struct ttc_timer_clockevent, ttc);
398
399 switch (event) {
400 case POST_RATE_CHANGE:
401 /* update cached frequency */
402 ttc->freq = ndata->new_rate;
403
404 clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);
405
406 fallthrough;
407 case PRE_RATE_CHANGE:
408 case ABORT_RATE_CHANGE:
409 default:
410 return NOTIFY_DONE;
411 }
412}
413
414static int __init ttc_setup_clockevent(struct clk *clk,
415 void __iomem *base, u32 irq)
416{
417 struct ttc_timer_clockevent *ttcce;
418 int err;
419
420 ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
421 if (!ttcce)
422 return -ENOMEM;
423
424 ttcce->ttc.clk = clk;
425
426 err = clk_prepare_enable(ttcce->ttc.clk);
427 if (err)
428 goto out_kfree;
429
430 ttcce->ttc.clk_rate_change_nb.notifier_call =
431 ttc_rate_change_clockevent_cb;
432 ttcce->ttc.clk_rate_change_nb.next = NULL;
433
434 err = clk_notifier_register(ttcce->ttc.clk,
435 &ttcce->ttc.clk_rate_change_nb);
436 if (err) {
437 pr_warn("Unable to register clock notifier.\n");
438 goto out_kfree;
439 }
440
441 ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
442
443 ttcce->ttc.base_addr = base;
444 ttcce->ce.name = "ttc_clockevent";
445 ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
446 ttcce->ce.set_next_event = ttc_set_next_event;
447 ttcce->ce.set_state_shutdown = ttc_shutdown;
448 ttcce->ce.set_state_periodic = ttc_set_periodic;
449 ttcce->ce.set_state_oneshot = ttc_shutdown;
450 ttcce->ce.tick_resume = ttc_resume;
451 ttcce->ce.rating = 200;
452 ttcce->ce.irq = irq;
453 ttcce->ce.cpumask = cpu_possible_mask;
454
455 /*
456 * Setup the clock event timer to be an interval timer which
457 * is prescaled by 32 using the interval interrupt. Leave it
458 * disabled for now.
459 */
460 writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
461 writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
462 ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
463 writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
464
465 err = request_irq(irq, ttc_clock_event_interrupt,
466 IRQF_TIMER, ttcce->ce.name, ttcce);
467 if (err)
468 goto out_kfree;
469
470 clockevents_config_and_register(&ttcce->ce,
471 ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
472
473 return 0;
474
475out_kfree:
476 kfree(ttcce);
477 return err;
478}
479
480static int __init ttc_timer_probe(struct platform_device *pdev)
481{
482 unsigned int irq;
483 void __iomem *timer_baseaddr;
484 struct clk *clk_cs, *clk_ce;
485 static int initialized;
486 int clksel, ret;
487 u32 timer_width = 16;
488 struct device_node *timer = pdev->dev.of_node;
489
490 if (initialized)
491 return 0;
492
493 initialized = 1;
494
495 /*
496 * Get the 1st Triple Timer Counter (TTC) block from the device tree
497 * and use it. Note that the event timer uses the interrupt and it's the
498 * 2nd TTC hence the irq_of_parse_and_map(,1)
499 */
500 timer_baseaddr = devm_of_iomap(&pdev->dev, timer, 0, NULL);
501 if (IS_ERR(timer_baseaddr)) {
502 pr_err("ERROR: invalid timer base address\n");
503 return PTR_ERR(timer_baseaddr);
504 }
505
506 irq = irq_of_parse_and_map(timer, 1);
507 if (irq <= 0) {
508 pr_err("ERROR: invalid interrupt number\n");
509 return -EINVAL;
510 }
511
512 of_property_read_u32(timer, "timer-width", &timer_width);
513
514 clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
515 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
516 clk_cs = of_clk_get(timer, clksel);
517 if (IS_ERR(clk_cs)) {
518 pr_err("ERROR: timer input clock not found\n");
519 return PTR_ERR(clk_cs);
520 }
521
522 clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
523 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
524 clk_ce = of_clk_get(timer, clksel);
525 if (IS_ERR(clk_ce)) {
526 pr_err("ERROR: timer input clock not found\n");
527 ret = PTR_ERR(clk_ce);
528 goto put_clk_cs;
529 }
530
531 ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width);
532 if (ret)
533 goto put_clk_ce;
534
535 ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
536 if (ret)
537 goto put_clk_ce;
538
539 pr_info("%pOFn #0 at %p, irq=%d\n", timer, timer_baseaddr, irq);
540
541 return 0;
542
543put_clk_ce:
544 clk_put(clk_ce);
545put_clk_cs:
546 clk_put(clk_cs);
547 return ret;
548}
549
550static const struct of_device_id ttc_timer_of_match[] = {
551 {.compatible = "cdns,ttc"},
552 {},
553};
554
555MODULE_DEVICE_TABLE(of, ttc_timer_of_match);
556
557static struct platform_driver ttc_timer_driver = {
558 .driver = {
559 .name = "cdns_ttc_timer",
560 .of_match_table = ttc_timer_of_match,
561 },
562};
563builtin_platform_driver_probe(ttc_timer_driver, ttc_timer_probe);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * This file contains driver for the Cadence Triple Timer Counter Rev 06
4 *
5 * Copyright (C) 2011-2013 Xilinx
6 *
7 * based on arch/mips/kernel/time.c timer driver
8 */
9
10#include <linux/clk.h>
11#include <linux/interrupt.h>
12#include <linux/clockchips.h>
13#include <linux/clocksource.h>
14#include <linux/of_address.h>
15#include <linux/of_irq.h>
16#include <linux/slab.h>
17#include <linux/sched_clock.h>
18
19/*
20 * This driver configures the 2 16/32-bit count-up timers as follows:
21 *
22 * T1: Timer 1, clocksource for generic timekeeping
23 * T2: Timer 2, clockevent source for hrtimers
24 * T3: Timer 3, <unused>
25 *
26 * The input frequency to the timer module for emulation is 2.5MHz which is
27 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
28 * the timers are clocked at 78.125KHz (12.8 us resolution).
29
30 * The input frequency to the timer module in silicon is configurable and
31 * obtained from device tree. The pre-scaler of 32 is used.
32 */
33
34/*
35 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
36 * and use same offsets for Timer 2
37 */
38#define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
39#define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
40#define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
41#define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
42#define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
43#define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
44
45#define TTC_CNT_CNTRL_DISABLE_MASK 0x1
46
47#define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */
48#define TTC_CLK_CNTRL_PSV_MASK 0x1e
49#define TTC_CLK_CNTRL_PSV_SHIFT 1
50
51/*
52 * Setup the timers to use pre-scaling, using a fixed value for now that will
53 * work across most input frequency, but it may need to be more dynamic
54 */
55#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
56#define PRESCALE 2048 /* The exponent must match this */
57#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
58#define CLK_CNTRL_PRESCALE_EN 1
59#define CNT_CNTRL_RESET (1 << 4)
60
61#define MAX_F_ERR 50
62
63/**
64 * struct ttc_timer - This definition defines local timer structure
65 *
66 * @base_addr: Base address of timer
67 * @freq: Timer input clock frequency
68 * @clk: Associated clock source
69 * @clk_rate_change_nb Notifier block for clock rate changes
70 */
71struct ttc_timer {
72 void __iomem *base_addr;
73 unsigned long freq;
74 struct clk *clk;
75 struct notifier_block clk_rate_change_nb;
76};
77
78#define to_ttc_timer(x) \
79 container_of(x, struct ttc_timer, clk_rate_change_nb)
80
81struct ttc_timer_clocksource {
82 u32 scale_clk_ctrl_reg_old;
83 u32 scale_clk_ctrl_reg_new;
84 struct ttc_timer ttc;
85 struct clocksource cs;
86};
87
88#define to_ttc_timer_clksrc(x) \
89 container_of(x, struct ttc_timer_clocksource, cs)
90
91struct ttc_timer_clockevent {
92 struct ttc_timer ttc;
93 struct clock_event_device ce;
94};
95
96#define to_ttc_timer_clkevent(x) \
97 container_of(x, struct ttc_timer_clockevent, ce)
98
99static void __iomem *ttc_sched_clock_val_reg;
100
101/**
102 * ttc_set_interval - Set the timer interval value
103 *
104 * @timer: Pointer to the timer instance
105 * @cycles: Timer interval ticks
106 **/
107static void ttc_set_interval(struct ttc_timer *timer,
108 unsigned long cycles)
109{
110 u32 ctrl_reg;
111
112 /* Disable the counter, set the counter value and re-enable counter */
113 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
114 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
115 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
116
117 writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
118
119 /*
120 * Reset the counter (0x10) so that it starts from 0, one-shot
121 * mode makes this needed for timing to be right.
122 */
123 ctrl_reg |= CNT_CNTRL_RESET;
124 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
125 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
126}
127
128/**
129 * ttc_clock_event_interrupt - Clock event timer interrupt handler
130 *
131 * @irq: IRQ number of the Timer
132 * @dev_id: void pointer to the ttc_timer instance
133 *
134 * returns: Always IRQ_HANDLED - success
135 **/
136static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
137{
138 struct ttc_timer_clockevent *ttce = dev_id;
139 struct ttc_timer *timer = &ttce->ttc;
140
141 /* Acknowledge the interrupt and call event handler */
142 readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
143
144 ttce->ce.event_handler(&ttce->ce);
145
146 return IRQ_HANDLED;
147}
148
149/**
150 * __ttc_clocksource_read - Reads the timer counter register
151 *
152 * returns: Current timer counter register value
153 **/
154static u64 __ttc_clocksource_read(struct clocksource *cs)
155{
156 struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
157
158 return (u64)readl_relaxed(timer->base_addr +
159 TTC_COUNT_VAL_OFFSET);
160}
161
162static u64 notrace ttc_sched_clock_read(void)
163{
164 return readl_relaxed(ttc_sched_clock_val_reg);
165}
166
167/**
168 * ttc_set_next_event - Sets the time interval for next event
169 *
170 * @cycles: Timer interval ticks
171 * @evt: Address of clock event instance
172 *
173 * returns: Always 0 - success
174 **/
175static int ttc_set_next_event(unsigned long cycles,
176 struct clock_event_device *evt)
177{
178 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
179 struct ttc_timer *timer = &ttce->ttc;
180
181 ttc_set_interval(timer, cycles);
182 return 0;
183}
184
185/**
186 * ttc_set_{shutdown|oneshot|periodic} - Sets the state of timer
187 *
188 * @evt: Address of clock event instance
189 **/
190static int ttc_shutdown(struct clock_event_device *evt)
191{
192 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
193 struct ttc_timer *timer = &ttce->ttc;
194 u32 ctrl_reg;
195
196 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
197 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
198 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
199 return 0;
200}
201
202static int ttc_set_periodic(struct clock_event_device *evt)
203{
204 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
205 struct ttc_timer *timer = &ttce->ttc;
206
207 ttc_set_interval(timer,
208 DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ));
209 return 0;
210}
211
212static int ttc_resume(struct clock_event_device *evt)
213{
214 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
215 struct ttc_timer *timer = &ttce->ttc;
216 u32 ctrl_reg;
217
218 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
219 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
220 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
221 return 0;
222}
223
224static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
225 unsigned long event, void *data)
226{
227 struct clk_notifier_data *ndata = data;
228 struct ttc_timer *ttc = to_ttc_timer(nb);
229 struct ttc_timer_clocksource *ttccs = container_of(ttc,
230 struct ttc_timer_clocksource, ttc);
231
232 switch (event) {
233 case PRE_RATE_CHANGE:
234 {
235 u32 psv;
236 unsigned long factor, rate_low, rate_high;
237
238 if (ndata->new_rate > ndata->old_rate) {
239 factor = DIV_ROUND_CLOSEST(ndata->new_rate,
240 ndata->old_rate);
241 rate_low = ndata->old_rate;
242 rate_high = ndata->new_rate;
243 } else {
244 factor = DIV_ROUND_CLOSEST(ndata->old_rate,
245 ndata->new_rate);
246 rate_low = ndata->new_rate;
247 rate_high = ndata->old_rate;
248 }
249
250 if (!is_power_of_2(factor))
251 return NOTIFY_BAD;
252
253 if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR)
254 return NOTIFY_BAD;
255
256 factor = __ilog2_u32(factor);
257
258 /*
259 * store timer clock ctrl register so we can restore it in case
260 * of an abort.
261 */
262 ttccs->scale_clk_ctrl_reg_old =
263 readl_relaxed(ttccs->ttc.base_addr +
264 TTC_CLK_CNTRL_OFFSET);
265
266 psv = (ttccs->scale_clk_ctrl_reg_old &
267 TTC_CLK_CNTRL_PSV_MASK) >>
268 TTC_CLK_CNTRL_PSV_SHIFT;
269 if (ndata->new_rate < ndata->old_rate)
270 psv -= factor;
271 else
272 psv += factor;
273
274 /* prescaler within legal range? */
275 if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT))
276 return NOTIFY_BAD;
277
278 ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old &
279 ~TTC_CLK_CNTRL_PSV_MASK;
280 ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT;
281
282
283 /* scale down: adjust divider in post-change notification */
284 if (ndata->new_rate < ndata->old_rate)
285 return NOTIFY_DONE;
286
287 /* scale up: adjust divider now - before frequency change */
288 writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
289 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
290 break;
291 }
292 case POST_RATE_CHANGE:
293 /* scale up: pre-change notification did the adjustment */
294 if (ndata->new_rate > ndata->old_rate)
295 return NOTIFY_OK;
296
297 /* scale down: adjust divider now - after frequency change */
298 writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
299 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
300 break;
301
302 case ABORT_RATE_CHANGE:
303 /* we have to undo the adjustment in case we scale up */
304 if (ndata->new_rate < ndata->old_rate)
305 return NOTIFY_OK;
306
307 /* restore original register value */
308 writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
309 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
310 /* fall through */
311 default:
312 return NOTIFY_DONE;
313 }
314
315 return NOTIFY_DONE;
316}
317
318static int __init ttc_setup_clocksource(struct clk *clk, void __iomem *base,
319 u32 timer_width)
320{
321 struct ttc_timer_clocksource *ttccs;
322 int err;
323
324 ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
325 if (!ttccs)
326 return -ENOMEM;
327
328 ttccs->ttc.clk = clk;
329
330 err = clk_prepare_enable(ttccs->ttc.clk);
331 if (err) {
332 kfree(ttccs);
333 return err;
334 }
335
336 ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);
337
338 ttccs->ttc.clk_rate_change_nb.notifier_call =
339 ttc_rate_change_clocksource_cb;
340 ttccs->ttc.clk_rate_change_nb.next = NULL;
341
342 err = clk_notifier_register(ttccs->ttc.clk,
343 &ttccs->ttc.clk_rate_change_nb);
344 if (err)
345 pr_warn("Unable to register clock notifier.\n");
346
347 ttccs->ttc.base_addr = base;
348 ttccs->cs.name = "ttc_clocksource";
349 ttccs->cs.rating = 200;
350 ttccs->cs.read = __ttc_clocksource_read;
351 ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width);
352 ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
353
354 /*
355 * Setup the clock source counter to be an incrementing counter
356 * with no interrupt and it rolls over at 0xFFFF. Pre-scale
357 * it by 32 also. Let it start running now.
358 */
359 writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
360 writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
361 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
362 writel_relaxed(CNT_CNTRL_RESET,
363 ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
364
365 err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
366 if (err) {
367 kfree(ttccs);
368 return err;
369 }
370
371 ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
372 sched_clock_register(ttc_sched_clock_read, timer_width,
373 ttccs->ttc.freq / PRESCALE);
374
375 return 0;
376}
377
378static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
379 unsigned long event, void *data)
380{
381 struct clk_notifier_data *ndata = data;
382 struct ttc_timer *ttc = to_ttc_timer(nb);
383 struct ttc_timer_clockevent *ttcce = container_of(ttc,
384 struct ttc_timer_clockevent, ttc);
385
386 switch (event) {
387 case POST_RATE_CHANGE:
388 /* update cached frequency */
389 ttc->freq = ndata->new_rate;
390
391 clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);
392
393 /* fall through */
394 case PRE_RATE_CHANGE:
395 case ABORT_RATE_CHANGE:
396 default:
397 return NOTIFY_DONE;
398 }
399}
400
401static int __init ttc_setup_clockevent(struct clk *clk,
402 void __iomem *base, u32 irq)
403{
404 struct ttc_timer_clockevent *ttcce;
405 int err;
406
407 ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
408 if (!ttcce)
409 return -ENOMEM;
410
411 ttcce->ttc.clk = clk;
412
413 err = clk_prepare_enable(ttcce->ttc.clk);
414 if (err) {
415 kfree(ttcce);
416 return err;
417 }
418
419 ttcce->ttc.clk_rate_change_nb.notifier_call =
420 ttc_rate_change_clockevent_cb;
421 ttcce->ttc.clk_rate_change_nb.next = NULL;
422
423 err = clk_notifier_register(ttcce->ttc.clk,
424 &ttcce->ttc.clk_rate_change_nb);
425 if (err) {
426 pr_warn("Unable to register clock notifier.\n");
427 return err;
428 }
429
430 ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
431
432 ttcce->ttc.base_addr = base;
433 ttcce->ce.name = "ttc_clockevent";
434 ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
435 ttcce->ce.set_next_event = ttc_set_next_event;
436 ttcce->ce.set_state_shutdown = ttc_shutdown;
437 ttcce->ce.set_state_periodic = ttc_set_periodic;
438 ttcce->ce.set_state_oneshot = ttc_shutdown;
439 ttcce->ce.tick_resume = ttc_resume;
440 ttcce->ce.rating = 200;
441 ttcce->ce.irq = irq;
442 ttcce->ce.cpumask = cpu_possible_mask;
443
444 /*
445 * Setup the clock event timer to be an interval timer which
446 * is prescaled by 32 using the interval interrupt. Leave it
447 * disabled for now.
448 */
449 writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
450 writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
451 ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
452 writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
453
454 err = request_irq(irq, ttc_clock_event_interrupt,
455 IRQF_TIMER, ttcce->ce.name, ttcce);
456 if (err) {
457 kfree(ttcce);
458 return err;
459 }
460
461 clockevents_config_and_register(&ttcce->ce,
462 ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
463
464 return 0;
465}
466
467/**
468 * ttc_timer_init - Initialize the timer
469 *
470 * Initializes the timer hardware and register the clock source and clock event
471 * timers with Linux kernal timer framework
472 */
473static int __init ttc_timer_init(struct device_node *timer)
474{
475 unsigned int irq;
476 void __iomem *timer_baseaddr;
477 struct clk *clk_cs, *clk_ce;
478 static int initialized;
479 int clksel, ret;
480 u32 timer_width = 16;
481
482 if (initialized)
483 return 0;
484
485 initialized = 1;
486
487 /*
488 * Get the 1st Triple Timer Counter (TTC) block from the device tree
489 * and use it. Note that the event timer uses the interrupt and it's the
490 * 2nd TTC hence the irq_of_parse_and_map(,1)
491 */
492 timer_baseaddr = of_iomap(timer, 0);
493 if (!timer_baseaddr) {
494 pr_err("ERROR: invalid timer base address\n");
495 return -ENXIO;
496 }
497
498 irq = irq_of_parse_and_map(timer, 1);
499 if (irq <= 0) {
500 pr_err("ERROR: invalid interrupt number\n");
501 return -EINVAL;
502 }
503
504 of_property_read_u32(timer, "timer-width", &timer_width);
505
506 clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
507 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
508 clk_cs = of_clk_get(timer, clksel);
509 if (IS_ERR(clk_cs)) {
510 pr_err("ERROR: timer input clock not found\n");
511 return PTR_ERR(clk_cs);
512 }
513
514 clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
515 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
516 clk_ce = of_clk_get(timer, clksel);
517 if (IS_ERR(clk_ce)) {
518 pr_err("ERROR: timer input clock not found\n");
519 return PTR_ERR(clk_ce);
520 }
521
522 ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width);
523 if (ret)
524 return ret;
525
526 ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
527 if (ret)
528 return ret;
529
530 pr_info("%pOFn #0 at %p, irq=%d\n", timer, timer_baseaddr, irq);
531
532 return 0;
533}
534
535TIMER_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);