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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Ingenic SoCs TCU IRQ driver
4 * Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
5 * Copyright (C) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
6 */
7
8#include <linux/bitops.h>
9#include <linux/clk.h>
10#include <linux/clockchips.h>
11#include <linux/clocksource.h>
12#include <linux/cpuhotplug.h>
13#include <linux/interrupt.h>
14#include <linux/mfd/ingenic-tcu.h>
15#include <linux/mfd/syscon.h>
16#include <linux/of.h>
17#include <linux/of_irq.h>
18#include <linux/overflow.h>
19#include <linux/platform_device.h>
20#include <linux/regmap.h>
21#include <linux/sched_clock.h>
22
23#include <dt-bindings/clock/ingenic,tcu.h>
24
25static DEFINE_PER_CPU(call_single_data_t, ingenic_cevt_csd);
26
27struct ingenic_soc_info {
28 unsigned int num_channels;
29};
30
31struct ingenic_tcu_timer {
32 unsigned int cpu;
33 unsigned int channel;
34 struct clock_event_device cevt;
35 struct clk *clk;
36 char name[8];
37};
38
39struct ingenic_tcu {
40 struct regmap *map;
41 struct device_node *np;
42 struct clk *cs_clk;
43 unsigned int cs_channel;
44 struct clocksource cs;
45 unsigned long pwm_channels_mask;
46 struct ingenic_tcu_timer timers[];
47};
48
49static struct ingenic_tcu *ingenic_tcu;
50
51static u64 notrace ingenic_tcu_timer_read(void)
52{
53 struct ingenic_tcu *tcu = ingenic_tcu;
54 unsigned int count;
55
56 regmap_read(tcu->map, TCU_REG_TCNTc(tcu->cs_channel), &count);
57
58 return count;
59}
60
61static u64 notrace ingenic_tcu_timer_cs_read(struct clocksource *cs)
62{
63 return ingenic_tcu_timer_read();
64}
65
66static inline struct ingenic_tcu *
67to_ingenic_tcu(struct ingenic_tcu_timer *timer)
68{
69 return container_of(timer, struct ingenic_tcu, timers[timer->cpu]);
70}
71
72static inline struct ingenic_tcu_timer *
73to_ingenic_tcu_timer(struct clock_event_device *evt)
74{
75 return container_of(evt, struct ingenic_tcu_timer, cevt);
76}
77
78static int ingenic_tcu_cevt_set_state_shutdown(struct clock_event_device *evt)
79{
80 struct ingenic_tcu_timer *timer = to_ingenic_tcu_timer(evt);
81 struct ingenic_tcu *tcu = to_ingenic_tcu(timer);
82
83 regmap_write(tcu->map, TCU_REG_TECR, BIT(timer->channel));
84
85 return 0;
86}
87
88static int ingenic_tcu_cevt_set_next(unsigned long next,
89 struct clock_event_device *evt)
90{
91 struct ingenic_tcu_timer *timer = to_ingenic_tcu_timer(evt);
92 struct ingenic_tcu *tcu = to_ingenic_tcu(timer);
93
94 if (next > 0xffff)
95 return -EINVAL;
96
97 regmap_write(tcu->map, TCU_REG_TDFRc(timer->channel), next);
98 regmap_write(tcu->map, TCU_REG_TCNTc(timer->channel), 0);
99 regmap_write(tcu->map, TCU_REG_TESR, BIT(timer->channel));
100
101 return 0;
102}
103
104static void ingenic_per_cpu_event_handler(void *info)
105{
106 struct clock_event_device *cevt = (struct clock_event_device *) info;
107
108 cevt->event_handler(cevt);
109}
110
111static irqreturn_t ingenic_tcu_cevt_cb(int irq, void *dev_id)
112{
113 struct ingenic_tcu_timer *timer = dev_id;
114 struct ingenic_tcu *tcu = to_ingenic_tcu(timer);
115 call_single_data_t *csd;
116
117 regmap_write(tcu->map, TCU_REG_TECR, BIT(timer->channel));
118
119 if (timer->cevt.event_handler) {
120 csd = &per_cpu(ingenic_cevt_csd, timer->cpu);
121 csd->info = (void *) &timer->cevt;
122 csd->func = ingenic_per_cpu_event_handler;
123 smp_call_function_single_async(timer->cpu, csd);
124 }
125
126 return IRQ_HANDLED;
127}
128
129static struct clk *ingenic_tcu_get_clock(struct device_node *np, int id)
130{
131 struct of_phandle_args args;
132
133 args.np = np;
134 args.args_count = 1;
135 args.args[0] = id;
136
137 return of_clk_get_from_provider(&args);
138}
139
140static int ingenic_tcu_setup_cevt(unsigned int cpu)
141{
142 struct ingenic_tcu *tcu = ingenic_tcu;
143 struct ingenic_tcu_timer *timer = &tcu->timers[cpu];
144 unsigned int timer_virq;
145 struct irq_domain *domain;
146 unsigned long rate;
147 int err;
148
149 timer->clk = ingenic_tcu_get_clock(tcu->np, timer->channel);
150 if (IS_ERR(timer->clk))
151 return PTR_ERR(timer->clk);
152
153 err = clk_prepare_enable(timer->clk);
154 if (err)
155 goto err_clk_put;
156
157 rate = clk_get_rate(timer->clk);
158 if (!rate) {
159 err = -EINVAL;
160 goto err_clk_disable;
161 }
162
163 domain = irq_find_host(tcu->np);
164 if (!domain) {
165 err = -ENODEV;
166 goto err_clk_disable;
167 }
168
169 timer_virq = irq_create_mapping(domain, timer->channel);
170 if (!timer_virq) {
171 err = -EINVAL;
172 goto err_clk_disable;
173 }
174
175 snprintf(timer->name, sizeof(timer->name), "TCU%u", timer->channel);
176
177 err = request_irq(timer_virq, ingenic_tcu_cevt_cb, IRQF_TIMER,
178 timer->name, timer);
179 if (err)
180 goto err_irq_dispose_mapping;
181
182 timer->cpu = smp_processor_id();
183 timer->cevt.cpumask = cpumask_of(smp_processor_id());
184 timer->cevt.features = CLOCK_EVT_FEAT_ONESHOT;
185 timer->cevt.name = timer->name;
186 timer->cevt.rating = 200;
187 timer->cevt.set_state_shutdown = ingenic_tcu_cevt_set_state_shutdown;
188 timer->cevt.set_next_event = ingenic_tcu_cevt_set_next;
189
190 clockevents_config_and_register(&timer->cevt, rate, 10, 0xffff);
191
192 return 0;
193
194err_irq_dispose_mapping:
195 irq_dispose_mapping(timer_virq);
196err_clk_disable:
197 clk_disable_unprepare(timer->clk);
198err_clk_put:
199 clk_put(timer->clk);
200 return err;
201}
202
203static int __init ingenic_tcu_clocksource_init(struct device_node *np,
204 struct ingenic_tcu *tcu)
205{
206 unsigned int channel = tcu->cs_channel;
207 struct clocksource *cs = &tcu->cs;
208 unsigned long rate;
209 int err;
210
211 tcu->cs_clk = ingenic_tcu_get_clock(np, channel);
212 if (IS_ERR(tcu->cs_clk))
213 return PTR_ERR(tcu->cs_clk);
214
215 err = clk_prepare_enable(tcu->cs_clk);
216 if (err)
217 goto err_clk_put;
218
219 rate = clk_get_rate(tcu->cs_clk);
220 if (!rate) {
221 err = -EINVAL;
222 goto err_clk_disable;
223 }
224
225 /* Reset channel */
226 regmap_update_bits(tcu->map, TCU_REG_TCSRc(channel),
227 0xffff & ~TCU_TCSR_RESERVED_BITS, 0);
228
229 /* Reset counter */
230 regmap_write(tcu->map, TCU_REG_TDFRc(channel), 0xffff);
231 regmap_write(tcu->map, TCU_REG_TCNTc(channel), 0);
232
233 /* Enable channel */
234 regmap_write(tcu->map, TCU_REG_TESR, BIT(channel));
235
236 cs->name = "ingenic-timer";
237 cs->rating = 200;
238 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
239 cs->mask = CLOCKSOURCE_MASK(16);
240 cs->read = ingenic_tcu_timer_cs_read;
241
242 err = clocksource_register_hz(cs, rate);
243 if (err)
244 goto err_clk_disable;
245
246 return 0;
247
248err_clk_disable:
249 clk_disable_unprepare(tcu->cs_clk);
250err_clk_put:
251 clk_put(tcu->cs_clk);
252 return err;
253}
254
255static const struct ingenic_soc_info jz4740_soc_info = {
256 .num_channels = 8,
257};
258
259static const struct ingenic_soc_info jz4725b_soc_info = {
260 .num_channels = 6,
261};
262
263static const struct of_device_id ingenic_tcu_of_match[] = {
264 { .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, },
265 { .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, },
266 { .compatible = "ingenic,jz4760-tcu", .data = &jz4740_soc_info, },
267 { .compatible = "ingenic,jz4770-tcu", .data = &jz4740_soc_info, },
268 { .compatible = "ingenic,x1000-tcu", .data = &jz4740_soc_info, },
269 { /* sentinel */ }
270};
271
272static int __init ingenic_tcu_init(struct device_node *np)
273{
274 const struct of_device_id *id = of_match_node(ingenic_tcu_of_match, np);
275 const struct ingenic_soc_info *soc_info = id->data;
276 struct ingenic_tcu_timer *timer;
277 struct ingenic_tcu *tcu;
278 struct regmap *map;
279 unsigned int cpu;
280 int ret, last_bit = -1;
281 long rate;
282
283 of_node_clear_flag(np, OF_POPULATED);
284
285 map = device_node_to_regmap(np);
286 if (IS_ERR(map))
287 return PTR_ERR(map);
288
289 tcu = kzalloc(struct_size(tcu, timers, num_possible_cpus()),
290 GFP_KERNEL);
291 if (!tcu)
292 return -ENOMEM;
293
294 /*
295 * Enable all TCU channels for PWM use by default except channels 0/1,
296 * and channel 2 if target CPU is JZ4780/X2000 and SMP is selected.
297 */
298 tcu->pwm_channels_mask = GENMASK(soc_info->num_channels - 1,
299 num_possible_cpus() + 1);
300 of_property_read_u32(np, "ingenic,pwm-channels-mask",
301 (u32 *)&tcu->pwm_channels_mask);
302
303 /* Verify that we have at least num_possible_cpus() + 1 free channels */
304 if (hweight8(tcu->pwm_channels_mask) >
305 soc_info->num_channels - num_possible_cpus() + 1) {
306 pr_crit("%s: Invalid PWM channel mask: 0x%02lx\n", __func__,
307 tcu->pwm_channels_mask);
308 ret = -EINVAL;
309 goto err_free_ingenic_tcu;
310 }
311
312 tcu->map = map;
313 tcu->np = np;
314 ingenic_tcu = tcu;
315
316 for (cpu = 0; cpu < num_possible_cpus(); cpu++) {
317 timer = &tcu->timers[cpu];
318
319 timer->cpu = cpu;
320 timer->channel = find_next_zero_bit(&tcu->pwm_channels_mask,
321 soc_info->num_channels,
322 last_bit + 1);
323 last_bit = timer->channel;
324 }
325
326 tcu->cs_channel = find_next_zero_bit(&tcu->pwm_channels_mask,
327 soc_info->num_channels,
328 last_bit + 1);
329
330 ret = ingenic_tcu_clocksource_init(np, tcu);
331 if (ret) {
332 pr_crit("%s: Unable to init clocksource: %d\n", __func__, ret);
333 goto err_free_ingenic_tcu;
334 }
335
336 /* Setup clock events on each CPU core */
337 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "Ingenic XBurst: online",
338 ingenic_tcu_setup_cevt, NULL);
339 if (ret < 0) {
340 pr_crit("%s: Unable to start CPU timers: %d\n", __func__, ret);
341 goto err_tcu_clocksource_cleanup;
342 }
343
344 /* Register the sched_clock at the end as there's no way to undo it */
345 rate = clk_get_rate(tcu->cs_clk);
346 sched_clock_register(ingenic_tcu_timer_read, 16, rate);
347
348 return 0;
349
350err_tcu_clocksource_cleanup:
351 clocksource_unregister(&tcu->cs);
352 clk_disable_unprepare(tcu->cs_clk);
353 clk_put(tcu->cs_clk);
354err_free_ingenic_tcu:
355 kfree(tcu);
356 return ret;
357}
358
359TIMER_OF_DECLARE(jz4740_tcu_intc, "ingenic,jz4740-tcu", ingenic_tcu_init);
360TIMER_OF_DECLARE(jz4725b_tcu_intc, "ingenic,jz4725b-tcu", ingenic_tcu_init);
361TIMER_OF_DECLARE(jz4760_tcu_intc, "ingenic,jz4760-tcu", ingenic_tcu_init);
362TIMER_OF_DECLARE(jz4770_tcu_intc, "ingenic,jz4770-tcu", ingenic_tcu_init);
363TIMER_OF_DECLARE(x1000_tcu_intc, "ingenic,x1000-tcu", ingenic_tcu_init);
364
365static int __init ingenic_tcu_probe(struct platform_device *pdev)
366{
367 platform_set_drvdata(pdev, ingenic_tcu);
368
369 return 0;
370}
371
372static int ingenic_tcu_suspend(struct device *dev)
373{
374 struct ingenic_tcu *tcu = dev_get_drvdata(dev);
375 unsigned int cpu;
376
377 clk_disable(tcu->cs_clk);
378
379 for (cpu = 0; cpu < num_online_cpus(); cpu++)
380 clk_disable(tcu->timers[cpu].clk);
381
382 return 0;
383}
384
385static int ingenic_tcu_resume(struct device *dev)
386{
387 struct ingenic_tcu *tcu = dev_get_drvdata(dev);
388 unsigned int cpu;
389 int ret;
390
391 for (cpu = 0; cpu < num_online_cpus(); cpu++) {
392 ret = clk_enable(tcu->timers[cpu].clk);
393 if (ret)
394 goto err_timer_clk_disable;
395 }
396
397 ret = clk_enable(tcu->cs_clk);
398 if (ret)
399 goto err_timer_clk_disable;
400
401 return 0;
402
403err_timer_clk_disable:
404 for (; cpu > 0; cpu--)
405 clk_disable(tcu->timers[cpu - 1].clk);
406 return ret;
407}
408
409static const struct dev_pm_ops ingenic_tcu_pm_ops = {
410 /* _noirq: We want the TCU clocks to be gated last / ungated first */
411 .suspend_noirq = ingenic_tcu_suspend,
412 .resume_noirq = ingenic_tcu_resume,
413};
414
415static struct platform_driver ingenic_tcu_driver = {
416 .driver = {
417 .name = "ingenic-tcu-timer",
418 .pm = pm_sleep_ptr(&ingenic_tcu_pm_ops),
419 .of_match_table = ingenic_tcu_of_match,
420 },
421};
422builtin_platform_driver_probe(ingenic_tcu_driver, ingenic_tcu_probe);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * JZ47xx SoCs TCU IRQ driver
4 * Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
5 */
6
7#include <linux/bitops.h>
8#include <linux/clk.h>
9#include <linux/clockchips.h>
10#include <linux/clocksource.h>
11#include <linux/interrupt.h>
12#include <linux/mfd/ingenic-tcu.h>
13#include <linux/mfd/syscon.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/of_platform.h>
18#include <linux/platform_device.h>
19#include <linux/regmap.h>
20#include <linux/sched_clock.h>
21
22#include <dt-bindings/clock/ingenic,tcu.h>
23
24struct ingenic_soc_info {
25 unsigned int num_channels;
26};
27
28struct ingenic_tcu {
29 struct regmap *map;
30 struct clk *timer_clk, *cs_clk;
31 unsigned int timer_channel, cs_channel;
32 struct clock_event_device cevt;
33 struct clocksource cs;
34 char name[4];
35 unsigned long pwm_channels_mask;
36};
37
38static struct ingenic_tcu *ingenic_tcu;
39
40static u64 notrace ingenic_tcu_timer_read(void)
41{
42 struct ingenic_tcu *tcu = ingenic_tcu;
43 unsigned int count;
44
45 regmap_read(tcu->map, TCU_REG_TCNTc(tcu->cs_channel), &count);
46
47 return count;
48}
49
50static u64 notrace ingenic_tcu_timer_cs_read(struct clocksource *cs)
51{
52 return ingenic_tcu_timer_read();
53}
54
55static inline struct ingenic_tcu *to_ingenic_tcu(struct clock_event_device *evt)
56{
57 return container_of(evt, struct ingenic_tcu, cevt);
58}
59
60static int ingenic_tcu_cevt_set_state_shutdown(struct clock_event_device *evt)
61{
62 struct ingenic_tcu *tcu = to_ingenic_tcu(evt);
63
64 regmap_write(tcu->map, TCU_REG_TECR, BIT(tcu->timer_channel));
65
66 return 0;
67}
68
69static int ingenic_tcu_cevt_set_next(unsigned long next,
70 struct clock_event_device *evt)
71{
72 struct ingenic_tcu *tcu = to_ingenic_tcu(evt);
73
74 if (next > 0xffff)
75 return -EINVAL;
76
77 regmap_write(tcu->map, TCU_REG_TDFRc(tcu->timer_channel), next);
78 regmap_write(tcu->map, TCU_REG_TCNTc(tcu->timer_channel), 0);
79 regmap_write(tcu->map, TCU_REG_TESR, BIT(tcu->timer_channel));
80
81 return 0;
82}
83
84static irqreturn_t ingenic_tcu_cevt_cb(int irq, void *dev_id)
85{
86 struct clock_event_device *evt = dev_id;
87 struct ingenic_tcu *tcu = to_ingenic_tcu(evt);
88
89 regmap_write(tcu->map, TCU_REG_TECR, BIT(tcu->timer_channel));
90
91 if (evt->event_handler)
92 evt->event_handler(evt);
93
94 return IRQ_HANDLED;
95}
96
97static struct clk * __init ingenic_tcu_get_clock(struct device_node *np, int id)
98{
99 struct of_phandle_args args;
100
101 args.np = np;
102 args.args_count = 1;
103 args.args[0] = id;
104
105 return of_clk_get_from_provider(&args);
106}
107
108static int __init ingenic_tcu_timer_init(struct device_node *np,
109 struct ingenic_tcu *tcu)
110{
111 unsigned int timer_virq, channel = tcu->timer_channel;
112 struct irq_domain *domain;
113 unsigned long rate;
114 int err;
115
116 tcu->timer_clk = ingenic_tcu_get_clock(np, channel);
117 if (IS_ERR(tcu->timer_clk))
118 return PTR_ERR(tcu->timer_clk);
119
120 err = clk_prepare_enable(tcu->timer_clk);
121 if (err)
122 goto err_clk_put;
123
124 rate = clk_get_rate(tcu->timer_clk);
125 if (!rate) {
126 err = -EINVAL;
127 goto err_clk_disable;
128 }
129
130 domain = irq_find_host(np);
131 if (!domain) {
132 err = -ENODEV;
133 goto err_clk_disable;
134 }
135
136 timer_virq = irq_create_mapping(domain, channel);
137 if (!timer_virq) {
138 err = -EINVAL;
139 goto err_clk_disable;
140 }
141
142 snprintf(tcu->name, sizeof(tcu->name), "TCU");
143
144 err = request_irq(timer_virq, ingenic_tcu_cevt_cb, IRQF_TIMER,
145 tcu->name, &tcu->cevt);
146 if (err)
147 goto err_irq_dispose_mapping;
148
149 tcu->cevt.cpumask = cpumask_of(smp_processor_id());
150 tcu->cevt.features = CLOCK_EVT_FEAT_ONESHOT;
151 tcu->cevt.name = tcu->name;
152 tcu->cevt.rating = 200;
153 tcu->cevt.set_state_shutdown = ingenic_tcu_cevt_set_state_shutdown;
154 tcu->cevt.set_next_event = ingenic_tcu_cevt_set_next;
155
156 clockevents_config_and_register(&tcu->cevt, rate, 10, 0xffff);
157
158 return 0;
159
160err_irq_dispose_mapping:
161 irq_dispose_mapping(timer_virq);
162err_clk_disable:
163 clk_disable_unprepare(tcu->timer_clk);
164err_clk_put:
165 clk_put(tcu->timer_clk);
166 return err;
167}
168
169static int __init ingenic_tcu_clocksource_init(struct device_node *np,
170 struct ingenic_tcu *tcu)
171{
172 unsigned int channel = tcu->cs_channel;
173 struct clocksource *cs = &tcu->cs;
174 unsigned long rate;
175 int err;
176
177 tcu->cs_clk = ingenic_tcu_get_clock(np, channel);
178 if (IS_ERR(tcu->cs_clk))
179 return PTR_ERR(tcu->cs_clk);
180
181 err = clk_prepare_enable(tcu->cs_clk);
182 if (err)
183 goto err_clk_put;
184
185 rate = clk_get_rate(tcu->cs_clk);
186 if (!rate) {
187 err = -EINVAL;
188 goto err_clk_disable;
189 }
190
191 /* Reset channel */
192 regmap_update_bits(tcu->map, TCU_REG_TCSRc(channel),
193 0xffff & ~TCU_TCSR_RESERVED_BITS, 0);
194
195 /* Reset counter */
196 regmap_write(tcu->map, TCU_REG_TDFRc(channel), 0xffff);
197 regmap_write(tcu->map, TCU_REG_TCNTc(channel), 0);
198
199 /* Enable channel */
200 regmap_write(tcu->map, TCU_REG_TESR, BIT(channel));
201
202 cs->name = "ingenic-timer";
203 cs->rating = 200;
204 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
205 cs->mask = CLOCKSOURCE_MASK(16);
206 cs->read = ingenic_tcu_timer_cs_read;
207
208 err = clocksource_register_hz(cs, rate);
209 if (err)
210 goto err_clk_disable;
211
212 return 0;
213
214err_clk_disable:
215 clk_disable_unprepare(tcu->cs_clk);
216err_clk_put:
217 clk_put(tcu->cs_clk);
218 return err;
219}
220
221static const struct ingenic_soc_info jz4740_soc_info = {
222 .num_channels = 8,
223};
224
225static const struct ingenic_soc_info jz4725b_soc_info = {
226 .num_channels = 6,
227};
228
229static const struct of_device_id ingenic_tcu_of_match[] = {
230 { .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, },
231 { .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, },
232 { .compatible = "ingenic,jz4770-tcu", .data = &jz4740_soc_info, },
233 { /* sentinel */ }
234};
235
236static int __init ingenic_tcu_init(struct device_node *np)
237{
238 const struct of_device_id *id = of_match_node(ingenic_tcu_of_match, np);
239 const struct ingenic_soc_info *soc_info = id->data;
240 struct ingenic_tcu *tcu;
241 struct regmap *map;
242 long rate;
243 int ret;
244
245 of_node_clear_flag(np, OF_POPULATED);
246
247 map = device_node_to_regmap(np);
248 if (IS_ERR(map))
249 return PTR_ERR(map);
250
251 tcu = kzalloc(sizeof(*tcu), GFP_KERNEL);
252 if (!tcu)
253 return -ENOMEM;
254
255 /* Enable all TCU channels for PWM use by default except channels 0/1 */
256 tcu->pwm_channels_mask = GENMASK(soc_info->num_channels - 1, 2);
257 of_property_read_u32(np, "ingenic,pwm-channels-mask",
258 (u32 *)&tcu->pwm_channels_mask);
259
260 /* Verify that we have at least two free channels */
261 if (hweight8(tcu->pwm_channels_mask) > soc_info->num_channels - 2) {
262 pr_crit("%s: Invalid PWM channel mask: 0x%02lx\n", __func__,
263 tcu->pwm_channels_mask);
264 ret = -EINVAL;
265 goto err_free_ingenic_tcu;
266 }
267
268 tcu->map = map;
269 ingenic_tcu = tcu;
270
271 tcu->timer_channel = find_first_zero_bit(&tcu->pwm_channels_mask,
272 soc_info->num_channels);
273 tcu->cs_channel = find_next_zero_bit(&tcu->pwm_channels_mask,
274 soc_info->num_channels,
275 tcu->timer_channel + 1);
276
277 ret = ingenic_tcu_clocksource_init(np, tcu);
278 if (ret) {
279 pr_crit("%s: Unable to init clocksource: %d\n", __func__, ret);
280 goto err_free_ingenic_tcu;
281 }
282
283 ret = ingenic_tcu_timer_init(np, tcu);
284 if (ret)
285 goto err_tcu_clocksource_cleanup;
286
287 /* Register the sched_clock at the end as there's no way to undo it */
288 rate = clk_get_rate(tcu->cs_clk);
289 sched_clock_register(ingenic_tcu_timer_read, 16, rate);
290
291 return 0;
292
293err_tcu_clocksource_cleanup:
294 clocksource_unregister(&tcu->cs);
295 clk_disable_unprepare(tcu->cs_clk);
296 clk_put(tcu->cs_clk);
297err_free_ingenic_tcu:
298 kfree(tcu);
299 return ret;
300}
301
302TIMER_OF_DECLARE(jz4740_tcu_intc, "ingenic,jz4740-tcu", ingenic_tcu_init);
303TIMER_OF_DECLARE(jz4725b_tcu_intc, "ingenic,jz4725b-tcu", ingenic_tcu_init);
304TIMER_OF_DECLARE(jz4770_tcu_intc, "ingenic,jz4770-tcu", ingenic_tcu_init);
305
306
307static int __init ingenic_tcu_probe(struct platform_device *pdev)
308{
309 platform_set_drvdata(pdev, ingenic_tcu);
310
311 return 0;
312}
313
314static int __maybe_unused ingenic_tcu_suspend(struct device *dev)
315{
316 struct ingenic_tcu *tcu = dev_get_drvdata(dev);
317
318 clk_disable(tcu->cs_clk);
319 clk_disable(tcu->timer_clk);
320 return 0;
321}
322
323static int __maybe_unused ingenic_tcu_resume(struct device *dev)
324{
325 struct ingenic_tcu *tcu = dev_get_drvdata(dev);
326 int ret;
327
328 ret = clk_enable(tcu->timer_clk);
329 if (ret)
330 return ret;
331
332 ret = clk_enable(tcu->cs_clk);
333 if (ret) {
334 clk_disable(tcu->timer_clk);
335 return ret;
336 }
337
338 return 0;
339}
340
341static const struct dev_pm_ops __maybe_unused ingenic_tcu_pm_ops = {
342 /* _noirq: We want the TCU clocks to be gated last / ungated first */
343 .suspend_noirq = ingenic_tcu_suspend,
344 .resume_noirq = ingenic_tcu_resume,
345};
346
347static struct platform_driver ingenic_tcu_driver = {
348 .driver = {
349 .name = "ingenic-tcu-timer",
350#ifdef CONFIG_PM_SLEEP
351 .pm = &ingenic_tcu_pm_ops,
352#endif
353 .of_match_table = ingenic_tcu_of_match,
354 },
355};
356builtin_platform_driver_probe(ingenic_tcu_driver, ingenic_tcu_probe);