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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * In-Memory Collection (IMC) Performance Monitor counter support.
4 *
5 * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.
6 * (C) 2017 Anju T Sudhakar, IBM Corporation.
7 * (C) 2017 Hemant K Shaw, IBM Corporation.
8 */
9#include <linux/of.h>
10#include <linux/perf_event.h>
11#include <linux/slab.h>
12#include <asm/opal.h>
13#include <asm/imc-pmu.h>
14#include <asm/cputhreads.h>
15#include <asm/smp.h>
16#include <linux/string.h>
17#include <linux/spinlock.h>
18
19/* Nest IMC data structures and variables */
20
21/*
22 * Used to avoid races in counting the nest-pmu units during hotplug
23 * register and unregister
24 */
25static DEFINE_MUTEX(nest_init_lock);
26static DEFINE_PER_CPU(struct imc_pmu_ref *, local_nest_imc_refc);
27static struct imc_pmu **per_nest_pmu_arr;
28static cpumask_t nest_imc_cpumask;
29static struct imc_pmu_ref *nest_imc_refc;
30static int nest_pmus;
31
32/* Core IMC data structures and variables */
33
34static cpumask_t core_imc_cpumask;
35static struct imc_pmu_ref *core_imc_refc;
36static struct imc_pmu *core_imc_pmu;
37
38/* Thread IMC data structures and variables */
39
40static DEFINE_PER_CPU(u64 *, thread_imc_mem);
41static struct imc_pmu *thread_imc_pmu;
42static int thread_imc_mem_size;
43
44/* Trace IMC data structures */
45static DEFINE_PER_CPU(u64 *, trace_imc_mem);
46static struct imc_pmu_ref *trace_imc_refc;
47static int trace_imc_mem_size;
48
49/*
50 * Global data structure used to avoid races between thread,
51 * core and trace-imc
52 */
53static struct imc_pmu_ref imc_global_refc = {
54 .lock = __SPIN_LOCK_UNLOCKED(imc_global_refc.lock),
55 .id = 0,
56 .refc = 0,
57};
58
59static struct imc_pmu *imc_event_to_pmu(struct perf_event *event)
60{
61 return container_of(event->pmu, struct imc_pmu, pmu);
62}
63
64PMU_FORMAT_ATTR(event, "config:0-61");
65PMU_FORMAT_ATTR(offset, "config:0-31");
66PMU_FORMAT_ATTR(rvalue, "config:32");
67PMU_FORMAT_ATTR(mode, "config:33-40");
68static struct attribute *imc_format_attrs[] = {
69 &format_attr_event.attr,
70 &format_attr_offset.attr,
71 &format_attr_rvalue.attr,
72 &format_attr_mode.attr,
73 NULL,
74};
75
76static const struct attribute_group imc_format_group = {
77 .name = "format",
78 .attrs = imc_format_attrs,
79};
80
81/* Format attribute for imc trace-mode */
82PMU_FORMAT_ATTR(cpmc_reserved, "config:0-19");
83PMU_FORMAT_ATTR(cpmc_event, "config:20-27");
84PMU_FORMAT_ATTR(cpmc_samplesel, "config:28-29");
85PMU_FORMAT_ATTR(cpmc_load, "config:30-61");
86static struct attribute *trace_imc_format_attrs[] = {
87 &format_attr_event.attr,
88 &format_attr_cpmc_reserved.attr,
89 &format_attr_cpmc_event.attr,
90 &format_attr_cpmc_samplesel.attr,
91 &format_attr_cpmc_load.attr,
92 NULL,
93};
94
95static const struct attribute_group trace_imc_format_group = {
96.name = "format",
97.attrs = trace_imc_format_attrs,
98};
99
100/* Get the cpumask printed to a buffer "buf" */
101static ssize_t imc_pmu_cpumask_get_attr(struct device *dev,
102 struct device_attribute *attr,
103 char *buf)
104{
105 struct pmu *pmu = dev_get_drvdata(dev);
106 struct imc_pmu *imc_pmu = container_of(pmu, struct imc_pmu, pmu);
107 cpumask_t *active_mask;
108
109 switch(imc_pmu->domain){
110 case IMC_DOMAIN_NEST:
111 active_mask = &nest_imc_cpumask;
112 break;
113 case IMC_DOMAIN_CORE:
114 active_mask = &core_imc_cpumask;
115 break;
116 default:
117 return 0;
118 }
119
120 return cpumap_print_to_pagebuf(true, buf, active_mask);
121}
122
123static DEVICE_ATTR(cpumask, S_IRUGO, imc_pmu_cpumask_get_attr, NULL);
124
125static struct attribute *imc_pmu_cpumask_attrs[] = {
126 &dev_attr_cpumask.attr,
127 NULL,
128};
129
130static const struct attribute_group imc_pmu_cpumask_attr_group = {
131 .attrs = imc_pmu_cpumask_attrs,
132};
133
134/* device_str_attr_create : Populate event "name" and string "str" in attribute */
135static struct attribute *device_str_attr_create(const char *name, const char *str)
136{
137 struct perf_pmu_events_attr *attr;
138
139 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
140 if (!attr)
141 return NULL;
142 sysfs_attr_init(&attr->attr.attr);
143
144 attr->event_str = str;
145 attr->attr.attr.name = name;
146 attr->attr.attr.mode = 0444;
147 attr->attr.show = perf_event_sysfs_show;
148
149 return &attr->attr.attr;
150}
151
152static int imc_parse_event(struct device_node *np, const char *scale,
153 const char *unit, const char *prefix,
154 u32 base, struct imc_events *event)
155{
156 const char *s;
157 u32 reg;
158
159 if (of_property_read_u32(np, "reg", ®))
160 goto error;
161 /* Add the base_reg value to the "reg" */
162 event->value = base + reg;
163
164 if (of_property_read_string(np, "event-name", &s))
165 goto error;
166
167 event->name = kasprintf(GFP_KERNEL, "%s%s", prefix, s);
168 if (!event->name)
169 goto error;
170
171 if (of_property_read_string(np, "scale", &s))
172 s = scale;
173
174 if (s) {
175 event->scale = kstrdup(s, GFP_KERNEL);
176 if (!event->scale)
177 goto error;
178 }
179
180 if (of_property_read_string(np, "unit", &s))
181 s = unit;
182
183 if (s) {
184 event->unit = kstrdup(s, GFP_KERNEL);
185 if (!event->unit)
186 goto error;
187 }
188
189 return 0;
190error:
191 kfree(event->unit);
192 kfree(event->scale);
193 kfree(event->name);
194 return -EINVAL;
195}
196
197/*
198 * imc_free_events: Function to cleanup the events list, having
199 * "nr_entries".
200 */
201static void imc_free_events(struct imc_events *events, int nr_entries)
202{
203 int i;
204
205 /* Nothing to clean, return */
206 if (!events)
207 return;
208 for (i = 0; i < nr_entries; i++) {
209 kfree(events[i].unit);
210 kfree(events[i].scale);
211 kfree(events[i].name);
212 }
213
214 kfree(events);
215}
216
217/*
218 * update_events_in_group: Update the "events" information in an attr_group
219 * and assign the attr_group to the pmu "pmu".
220 */
221static int update_events_in_group(struct device_node *node, struct imc_pmu *pmu)
222{
223 struct attribute_group *attr_group;
224 struct attribute **attrs, *dev_str;
225 struct device_node *np, *pmu_events;
226 u32 handle, base_reg;
227 int i = 0, j = 0, ct, ret;
228 const char *prefix, *g_scale, *g_unit;
229 const char *ev_val_str, *ev_scale_str, *ev_unit_str;
230
231 if (!of_property_read_u32(node, "events", &handle))
232 pmu_events = of_find_node_by_phandle(handle);
233 else
234 return 0;
235
236 /* Did not find any node with a given phandle */
237 if (!pmu_events)
238 return 0;
239
240 /* Get a count of number of child nodes */
241 ct = of_get_child_count(pmu_events);
242
243 /* Get the event prefix */
244 if (of_property_read_string(node, "events-prefix", &prefix)) {
245 of_node_put(pmu_events);
246 return 0;
247 }
248
249 /* Get a global unit and scale data if available */
250 if (of_property_read_string(node, "scale", &g_scale))
251 g_scale = NULL;
252
253 if (of_property_read_string(node, "unit", &g_unit))
254 g_unit = NULL;
255
256 /* "reg" property gives out the base offset of the counters data */
257 of_property_read_u32(node, "reg", &base_reg);
258
259 /* Allocate memory for the events */
260 pmu->events = kcalloc(ct, sizeof(struct imc_events), GFP_KERNEL);
261 if (!pmu->events) {
262 of_node_put(pmu_events);
263 return -ENOMEM;
264 }
265
266 ct = 0;
267 /* Parse the events and update the struct */
268 for_each_child_of_node(pmu_events, np) {
269 ret = imc_parse_event(np, g_scale, g_unit, prefix, base_reg, &pmu->events[ct]);
270 if (!ret)
271 ct++;
272 }
273
274 of_node_put(pmu_events);
275
276 /* Allocate memory for attribute group */
277 attr_group = kzalloc(sizeof(*attr_group), GFP_KERNEL);
278 if (!attr_group) {
279 imc_free_events(pmu->events, ct);
280 return -ENOMEM;
281 }
282
283 /*
284 * Allocate memory for attributes.
285 * Since we have count of events for this pmu, we also allocate
286 * memory for the scale and unit attribute for now.
287 * "ct" has the total event structs added from the events-parent node.
288 * So allocate three times the "ct" (this includes event, event_scale and
289 * event_unit).
290 */
291 attrs = kcalloc(((ct * 3) + 1), sizeof(struct attribute *), GFP_KERNEL);
292 if (!attrs) {
293 kfree(attr_group);
294 imc_free_events(pmu->events, ct);
295 return -ENOMEM;
296 }
297
298 attr_group->name = "events";
299 attr_group->attrs = attrs;
300 do {
301 ev_val_str = kasprintf(GFP_KERNEL, "event=0x%x", pmu->events[i].value);
302 if (!ev_val_str)
303 continue;
304 dev_str = device_str_attr_create(pmu->events[i].name, ev_val_str);
305 if (!dev_str)
306 continue;
307
308 attrs[j++] = dev_str;
309 if (pmu->events[i].scale) {
310 ev_scale_str = kasprintf(GFP_KERNEL, "%s.scale", pmu->events[i].name);
311 if (!ev_scale_str)
312 continue;
313 dev_str = device_str_attr_create(ev_scale_str, pmu->events[i].scale);
314 if (!dev_str)
315 continue;
316
317 attrs[j++] = dev_str;
318 }
319
320 if (pmu->events[i].unit) {
321 ev_unit_str = kasprintf(GFP_KERNEL, "%s.unit", pmu->events[i].name);
322 if (!ev_unit_str)
323 continue;
324 dev_str = device_str_attr_create(ev_unit_str, pmu->events[i].unit);
325 if (!dev_str)
326 continue;
327
328 attrs[j++] = dev_str;
329 }
330 } while (++i < ct);
331
332 /* Save the event attribute */
333 pmu->attr_groups[IMC_EVENT_ATTR] = attr_group;
334
335 return 0;
336}
337
338/* get_nest_pmu_ref: Return the imc_pmu_ref struct for the given node */
339static struct imc_pmu_ref *get_nest_pmu_ref(int cpu)
340{
341 return per_cpu(local_nest_imc_refc, cpu);
342}
343
344static void nest_change_cpu_context(int old_cpu, int new_cpu)
345{
346 struct imc_pmu **pn = per_nest_pmu_arr;
347
348 if (old_cpu < 0 || new_cpu < 0)
349 return;
350
351 while (*pn) {
352 perf_pmu_migrate_context(&(*pn)->pmu, old_cpu, new_cpu);
353 pn++;
354 }
355}
356
357static int ppc_nest_imc_cpu_offline(unsigned int cpu)
358{
359 int nid, target = -1;
360 const struct cpumask *l_cpumask;
361 struct imc_pmu_ref *ref;
362
363 /*
364 * Check in the designated list for this cpu. Dont bother
365 * if not one of them.
366 */
367 if (!cpumask_test_and_clear_cpu(cpu, &nest_imc_cpumask))
368 return 0;
369
370 /*
371 * Check whether nest_imc is registered. We could end up here if the
372 * cpuhotplug callback registration fails. i.e, callback invokes the
373 * offline path for all successfully registered nodes. At this stage,
374 * nest_imc pmu will not be registered and we should return here.
375 *
376 * We return with a zero since this is not an offline failure. And
377 * cpuhp_setup_state() returns the actual failure reason to the caller,
378 * which in turn will call the cleanup routine.
379 */
380 if (!nest_pmus)
381 return 0;
382
383 /*
384 * Now that this cpu is one of the designated,
385 * find a next cpu a) which is online and b) in same chip.
386 */
387 nid = cpu_to_node(cpu);
388 l_cpumask = cpumask_of_node(nid);
389 target = cpumask_last(l_cpumask);
390
391 /*
392 * If this(target) is the last cpu in the cpumask for this chip,
393 * check for any possible online cpu in the chip.
394 */
395 if (unlikely(target == cpu))
396 target = cpumask_any_but(l_cpumask, cpu);
397
398 /*
399 * Update the cpumask with the target cpu and
400 * migrate the context if needed
401 */
402 if (target >= 0 && target < nr_cpu_ids) {
403 cpumask_set_cpu(target, &nest_imc_cpumask);
404 nest_change_cpu_context(cpu, target);
405 } else {
406 opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
407 get_hard_smp_processor_id(cpu));
408 /*
409 * If this is the last cpu in this chip then, skip the reference
410 * count lock and make the reference count on this chip zero.
411 */
412 ref = get_nest_pmu_ref(cpu);
413 if (!ref)
414 return -EINVAL;
415
416 ref->refc = 0;
417 }
418 return 0;
419}
420
421static int ppc_nest_imc_cpu_online(unsigned int cpu)
422{
423 const struct cpumask *l_cpumask;
424 static struct cpumask tmp_mask;
425 int res;
426
427 /* Get the cpumask of this node */
428 l_cpumask = cpumask_of_node(cpu_to_node(cpu));
429
430 /*
431 * If this is not the first online CPU on this node, then
432 * just return.
433 */
434 if (cpumask_and(&tmp_mask, l_cpumask, &nest_imc_cpumask))
435 return 0;
436
437 /*
438 * If this is the first online cpu on this node
439 * disable the nest counters by making an OPAL call.
440 */
441 res = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
442 get_hard_smp_processor_id(cpu));
443 if (res)
444 return res;
445
446 /* Make this CPU the designated target for counter collection */
447 cpumask_set_cpu(cpu, &nest_imc_cpumask);
448 return 0;
449}
450
451static int nest_pmu_cpumask_init(void)
452{
453 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE,
454 "perf/powerpc/imc:online",
455 ppc_nest_imc_cpu_online,
456 ppc_nest_imc_cpu_offline);
457}
458
459static void nest_imc_counters_release(struct perf_event *event)
460{
461 int rc, node_id;
462 struct imc_pmu_ref *ref;
463
464 if (event->cpu < 0)
465 return;
466
467 node_id = cpu_to_node(event->cpu);
468
469 /*
470 * See if we need to disable the nest PMU.
471 * If no events are currently in use, then we have to take a
472 * lock to ensure that we don't race with another task doing
473 * enable or disable the nest counters.
474 */
475 ref = get_nest_pmu_ref(event->cpu);
476 if (!ref)
477 return;
478
479 /* Take the lock for this node and then decrement the reference count */
480 spin_lock(&ref->lock);
481 if (ref->refc == 0) {
482 /*
483 * The scenario where this is true is, when perf session is
484 * started, followed by offlining of all cpus in a given node.
485 *
486 * In the cpuhotplug offline path, ppc_nest_imc_cpu_offline()
487 * function set the ref->count to zero, if the cpu which is
488 * about to offline is the last cpu in a given node and make
489 * an OPAL call to disable the engine in that node.
490 *
491 */
492 spin_unlock(&ref->lock);
493 return;
494 }
495 ref->refc--;
496 if (ref->refc == 0) {
497 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
498 get_hard_smp_processor_id(event->cpu));
499 if (rc) {
500 spin_unlock(&ref->lock);
501 pr_err("nest-imc: Unable to stop the counters for core %d\n", node_id);
502 return;
503 }
504 } else if (ref->refc < 0) {
505 WARN(1, "nest-imc: Invalid event reference count\n");
506 ref->refc = 0;
507 }
508 spin_unlock(&ref->lock);
509}
510
511static int nest_imc_event_init(struct perf_event *event)
512{
513 int chip_id, rc, node_id;
514 u32 l_config, config = event->attr.config;
515 struct imc_mem_info *pcni;
516 struct imc_pmu *pmu;
517 struct imc_pmu_ref *ref;
518 bool flag = false;
519
520 if (event->attr.type != event->pmu->type)
521 return -ENOENT;
522
523 /* Sampling not supported */
524 if (event->hw.sample_period)
525 return -EINVAL;
526
527 if (event->cpu < 0)
528 return -EINVAL;
529
530 pmu = imc_event_to_pmu(event);
531
532 /* Sanity check for config (event offset) */
533 if ((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size)
534 return -EINVAL;
535
536 /*
537 * Nest HW counter memory resides in a per-chip reserve-memory (HOMER).
538 * Get the base memory address for this cpu.
539 */
540 chip_id = cpu_to_chip_id(event->cpu);
541
542 /* Return, if chip_id is not valid */
543 if (chip_id < 0)
544 return -ENODEV;
545
546 pcni = pmu->mem_info;
547 do {
548 if (pcni->id == chip_id) {
549 flag = true;
550 break;
551 }
552 pcni++;
553 } while (pcni->vbase);
554
555 if (!flag)
556 return -ENODEV;
557
558 /*
559 * Add the event offset to the base address.
560 */
561 l_config = config & IMC_EVENT_OFFSET_MASK;
562 event->hw.event_base = (u64)pcni->vbase + l_config;
563 node_id = cpu_to_node(event->cpu);
564
565 /*
566 * Get the imc_pmu_ref struct for this node.
567 * Take the lock and then increment the count of nest pmu events inited.
568 */
569 ref = get_nest_pmu_ref(event->cpu);
570 if (!ref)
571 return -EINVAL;
572
573 spin_lock(&ref->lock);
574 if (ref->refc == 0) {
575 rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_NEST,
576 get_hard_smp_processor_id(event->cpu));
577 if (rc) {
578 spin_unlock(&ref->lock);
579 pr_err("nest-imc: Unable to start the counters for node %d\n",
580 node_id);
581 return rc;
582 }
583 }
584 ++ref->refc;
585 spin_unlock(&ref->lock);
586
587 event->destroy = nest_imc_counters_release;
588 return 0;
589}
590
591/*
592 * core_imc_mem_init : Initializes memory for the current core.
593 *
594 * Uses alloc_pages_node() and uses the returned address as an argument to
595 * an opal call to configure the pdbar. The address sent as an argument is
596 * converted to physical address before the opal call is made. This is the
597 * base address at which the core imc counters are populated.
598 */
599static int core_imc_mem_init(int cpu, int size)
600{
601 int nid, rc = 0, core_id = (cpu / threads_per_core);
602 struct imc_mem_info *mem_info;
603 struct page *page;
604
605 /*
606 * alloc_pages_node() will allocate memory for core in the
607 * local node only.
608 */
609 nid = cpu_to_node(cpu);
610 mem_info = &core_imc_pmu->mem_info[core_id];
611 mem_info->id = core_id;
612
613 /* We need only vbase for core counters */
614 page = alloc_pages_node(nid,
615 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
616 __GFP_NOWARN, get_order(size));
617 if (!page)
618 return -ENOMEM;
619 mem_info->vbase = page_address(page);
620
621 core_imc_refc[core_id].id = core_id;
622 spin_lock_init(&core_imc_refc[core_id].lock);
623
624 rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_CORE,
625 __pa((void *)mem_info->vbase),
626 get_hard_smp_processor_id(cpu));
627 if (rc) {
628 free_pages((u64)mem_info->vbase, get_order(size));
629 mem_info->vbase = NULL;
630 }
631
632 return rc;
633}
634
635static bool is_core_imc_mem_inited(int cpu)
636{
637 struct imc_mem_info *mem_info;
638 int core_id = (cpu / threads_per_core);
639
640 mem_info = &core_imc_pmu->mem_info[core_id];
641 if (!mem_info->vbase)
642 return false;
643
644 return true;
645}
646
647static int ppc_core_imc_cpu_online(unsigned int cpu)
648{
649 const struct cpumask *l_cpumask;
650 static struct cpumask tmp_mask;
651 int ret = 0;
652
653 /* Get the cpumask for this core */
654 l_cpumask = cpu_sibling_mask(cpu);
655
656 /* If a cpu for this core is already set, then, don't do anything */
657 if (cpumask_and(&tmp_mask, l_cpumask, &core_imc_cpumask))
658 return 0;
659
660 if (!is_core_imc_mem_inited(cpu)) {
661 ret = core_imc_mem_init(cpu, core_imc_pmu->counter_mem_size);
662 if (ret) {
663 pr_info("core_imc memory allocation for cpu %d failed\n", cpu);
664 return ret;
665 }
666 }
667
668 /* set the cpu in the mask */
669 cpumask_set_cpu(cpu, &core_imc_cpumask);
670 return 0;
671}
672
673static int ppc_core_imc_cpu_offline(unsigned int cpu)
674{
675 unsigned int core_id;
676 int ncpu;
677 struct imc_pmu_ref *ref;
678
679 /*
680 * clear this cpu out of the mask, if not present in the mask,
681 * don't bother doing anything.
682 */
683 if (!cpumask_test_and_clear_cpu(cpu, &core_imc_cpumask))
684 return 0;
685
686 /*
687 * Check whether core_imc is registered. We could end up here
688 * if the cpuhotplug callback registration fails. i.e, callback
689 * invokes the offline path for all successfully registered cpus.
690 * At this stage, core_imc pmu will not be registered and we
691 * should return here.
692 *
693 * We return with a zero since this is not an offline failure.
694 * And cpuhp_setup_state() returns the actual failure reason
695 * to the caller, which inturn will call the cleanup routine.
696 */
697 if (!core_imc_pmu->pmu.event_init)
698 return 0;
699
700 /* Find any online cpu in that core except the current "cpu" */
701 ncpu = cpumask_last(cpu_sibling_mask(cpu));
702
703 if (unlikely(ncpu == cpu))
704 ncpu = cpumask_any_but(cpu_sibling_mask(cpu), cpu);
705
706 if (ncpu >= 0 && ncpu < nr_cpu_ids) {
707 cpumask_set_cpu(ncpu, &core_imc_cpumask);
708 perf_pmu_migrate_context(&core_imc_pmu->pmu, cpu, ncpu);
709 } else {
710 /*
711 * If this is the last cpu in this core then skip taking reference
712 * count lock for this core and directly zero "refc" for this core.
713 */
714 opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
715 get_hard_smp_processor_id(cpu));
716 core_id = cpu / threads_per_core;
717 ref = &core_imc_refc[core_id];
718 if (!ref)
719 return -EINVAL;
720
721 ref->refc = 0;
722 /*
723 * Reduce the global reference count, if this is the
724 * last cpu in this core and core-imc event running
725 * in this cpu.
726 */
727 spin_lock(&imc_global_refc.lock);
728 if (imc_global_refc.id == IMC_DOMAIN_CORE)
729 imc_global_refc.refc--;
730
731 spin_unlock(&imc_global_refc.lock);
732 }
733 return 0;
734}
735
736static int core_imc_pmu_cpumask_init(void)
737{
738 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE,
739 "perf/powerpc/imc_core:online",
740 ppc_core_imc_cpu_online,
741 ppc_core_imc_cpu_offline);
742}
743
744static void reset_global_refc(struct perf_event *event)
745{
746 spin_lock(&imc_global_refc.lock);
747 imc_global_refc.refc--;
748
749 /*
750 * If no other thread is running any
751 * event for this domain(thread/core/trace),
752 * set the global id to zero.
753 */
754 if (imc_global_refc.refc <= 0) {
755 imc_global_refc.refc = 0;
756 imc_global_refc.id = 0;
757 }
758 spin_unlock(&imc_global_refc.lock);
759}
760
761static void core_imc_counters_release(struct perf_event *event)
762{
763 int rc, core_id;
764 struct imc_pmu_ref *ref;
765
766 if (event->cpu < 0)
767 return;
768 /*
769 * See if we need to disable the IMC PMU.
770 * If no events are currently in use, then we have to take a
771 * lock to ensure that we don't race with another task doing
772 * enable or disable the core counters.
773 */
774 core_id = event->cpu / threads_per_core;
775
776 /* Take the lock and decrement the refernce count for this core */
777 ref = &core_imc_refc[core_id];
778 if (!ref)
779 return;
780
781 spin_lock(&ref->lock);
782 if (ref->refc == 0) {
783 /*
784 * The scenario where this is true is, when perf session is
785 * started, followed by offlining of all cpus in a given core.
786 *
787 * In the cpuhotplug offline path, ppc_core_imc_cpu_offline()
788 * function set the ref->count to zero, if the cpu which is
789 * about to offline is the last cpu in a given core and make
790 * an OPAL call to disable the engine in that core.
791 *
792 */
793 spin_unlock(&ref->lock);
794 return;
795 }
796 ref->refc--;
797 if (ref->refc == 0) {
798 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
799 get_hard_smp_processor_id(event->cpu));
800 if (rc) {
801 spin_unlock(&ref->lock);
802 pr_err("IMC: Unable to stop the counters for core %d\n", core_id);
803 return;
804 }
805 } else if (ref->refc < 0) {
806 WARN(1, "core-imc: Invalid event reference count\n");
807 ref->refc = 0;
808 }
809 spin_unlock(&ref->lock);
810
811 reset_global_refc(event);
812}
813
814static int core_imc_event_init(struct perf_event *event)
815{
816 int core_id, rc;
817 u64 config = event->attr.config;
818 struct imc_mem_info *pcmi;
819 struct imc_pmu *pmu;
820 struct imc_pmu_ref *ref;
821
822 if (event->attr.type != event->pmu->type)
823 return -ENOENT;
824
825 /* Sampling not supported */
826 if (event->hw.sample_period)
827 return -EINVAL;
828
829 if (event->cpu < 0)
830 return -EINVAL;
831
832 event->hw.idx = -1;
833 pmu = imc_event_to_pmu(event);
834
835 /* Sanity check for config (event offset) */
836 if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
837 return -EINVAL;
838
839 if (!is_core_imc_mem_inited(event->cpu))
840 return -ENODEV;
841
842 core_id = event->cpu / threads_per_core;
843 pcmi = &core_imc_pmu->mem_info[core_id];
844 if ((!pcmi->vbase))
845 return -ENODEV;
846
847 ref = &core_imc_refc[core_id];
848 if (!ref)
849 return -EINVAL;
850
851 /*
852 * Core pmu units are enabled only when it is used.
853 * See if this is triggered for the first time.
854 * If yes, take the lock and enable the core counters.
855 * If not, just increment the count in core_imc_refc struct.
856 */
857 spin_lock(&ref->lock);
858 if (ref->refc == 0) {
859 rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
860 get_hard_smp_processor_id(event->cpu));
861 if (rc) {
862 spin_unlock(&ref->lock);
863 pr_err("core-imc: Unable to start the counters for core %d\n",
864 core_id);
865 return rc;
866 }
867 }
868 ++ref->refc;
869 spin_unlock(&ref->lock);
870
871 /*
872 * Since the system can run either in accumulation or trace-mode
873 * of IMC at a time, core-imc events are allowed only if no other
874 * trace/thread imc events are enabled/monitored.
875 *
876 * Take the global lock, and check the refc.id
877 * to know whether any other trace/thread imc
878 * events are running.
879 */
880 spin_lock(&imc_global_refc.lock);
881 if (imc_global_refc.id == 0 || imc_global_refc.id == IMC_DOMAIN_CORE) {
882 /*
883 * No other trace/thread imc events are running in
884 * the system, so set the refc.id to core-imc.
885 */
886 imc_global_refc.id = IMC_DOMAIN_CORE;
887 imc_global_refc.refc++;
888 } else {
889 spin_unlock(&imc_global_refc.lock);
890 return -EBUSY;
891 }
892 spin_unlock(&imc_global_refc.lock);
893
894 event->hw.event_base = (u64)pcmi->vbase + (config & IMC_EVENT_OFFSET_MASK);
895 event->destroy = core_imc_counters_release;
896 return 0;
897}
898
899/*
900 * Allocates a page of memory for each of the online cpus, and load
901 * LDBAR with 0.
902 * The physical base address of the page allocated for a cpu will be
903 * written to the LDBAR for that cpu, when the thread-imc event
904 * is added.
905 *
906 * LDBAR Register Layout:
907 *
908 * 0 4 8 12 16 20 24 28
909 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
910 * | | [ ] [ Counter Address [8:50]
911 * | * Mode |
912 * | * PB Scope
913 * * Enable/Disable
914 *
915 * 32 36 40 44 48 52 56 60
916 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
917 * Counter Address [8:50] ]
918 *
919 */
920static int thread_imc_mem_alloc(int cpu_id, int size)
921{
922 u64 *local_mem = per_cpu(thread_imc_mem, cpu_id);
923 int nid = cpu_to_node(cpu_id);
924
925 if (!local_mem) {
926 struct page *page;
927 /*
928 * This case could happen only once at start, since we dont
929 * free the memory in cpu offline path.
930 */
931 page = alloc_pages_node(nid,
932 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
933 __GFP_NOWARN, get_order(size));
934 if (!page)
935 return -ENOMEM;
936 local_mem = page_address(page);
937
938 per_cpu(thread_imc_mem, cpu_id) = local_mem;
939 }
940
941 mtspr(SPRN_LDBAR, 0);
942 return 0;
943}
944
945static int ppc_thread_imc_cpu_online(unsigned int cpu)
946{
947 return thread_imc_mem_alloc(cpu, thread_imc_mem_size);
948}
949
950static int ppc_thread_imc_cpu_offline(unsigned int cpu)
951{
952 /*
953 * Set the bit 0 of LDBAR to zero.
954 *
955 * If bit 0 of LDBAR is unset, it will stop posting
956 * the counter data to memory.
957 * For thread-imc, bit 0 of LDBAR will be set to 1 in the
958 * event_add function. So reset this bit here, to stop the updates
959 * to memory in the cpu_offline path.
960 */
961 mtspr(SPRN_LDBAR, (mfspr(SPRN_LDBAR) & (~(1UL << 63))));
962
963 /* Reduce the refc if thread-imc event running on this cpu */
964 spin_lock(&imc_global_refc.lock);
965 if (imc_global_refc.id == IMC_DOMAIN_THREAD)
966 imc_global_refc.refc--;
967 spin_unlock(&imc_global_refc.lock);
968
969 return 0;
970}
971
972static int thread_imc_cpu_init(void)
973{
974 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE,
975 "perf/powerpc/imc_thread:online",
976 ppc_thread_imc_cpu_online,
977 ppc_thread_imc_cpu_offline);
978}
979
980static int thread_imc_event_init(struct perf_event *event)
981{
982 u32 config = event->attr.config;
983 struct task_struct *target;
984 struct imc_pmu *pmu;
985
986 if (event->attr.type != event->pmu->type)
987 return -ENOENT;
988
989 if (!perfmon_capable())
990 return -EACCES;
991
992 /* Sampling not supported */
993 if (event->hw.sample_period)
994 return -EINVAL;
995
996 event->hw.idx = -1;
997 pmu = imc_event_to_pmu(event);
998
999 /* Sanity check for config offset */
1000 if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
1001 return -EINVAL;
1002
1003 target = event->hw.target;
1004 if (!target)
1005 return -EINVAL;
1006
1007 spin_lock(&imc_global_refc.lock);
1008 /*
1009 * Check if any other trace/core imc events are running in the
1010 * system, if not set the global id to thread-imc.
1011 */
1012 if (imc_global_refc.id == 0 || imc_global_refc.id == IMC_DOMAIN_THREAD) {
1013 imc_global_refc.id = IMC_DOMAIN_THREAD;
1014 imc_global_refc.refc++;
1015 } else {
1016 spin_unlock(&imc_global_refc.lock);
1017 return -EBUSY;
1018 }
1019 spin_unlock(&imc_global_refc.lock);
1020
1021 event->pmu->task_ctx_nr = perf_sw_context;
1022 event->destroy = reset_global_refc;
1023 return 0;
1024}
1025
1026static bool is_thread_imc_pmu(struct perf_event *event)
1027{
1028 if (!strncmp(event->pmu->name, "thread_imc", strlen("thread_imc")))
1029 return true;
1030
1031 return false;
1032}
1033
1034static __be64 *get_event_base_addr(struct perf_event *event)
1035{
1036 u64 addr;
1037
1038 if (is_thread_imc_pmu(event)) {
1039 addr = (u64)per_cpu(thread_imc_mem, smp_processor_id());
1040 return (__be64 *)(addr + (event->attr.config & IMC_EVENT_OFFSET_MASK));
1041 }
1042
1043 return (__be64 *)event->hw.event_base;
1044}
1045
1046static void thread_imc_pmu_start_txn(struct pmu *pmu,
1047 unsigned int txn_flags)
1048{
1049 if (txn_flags & ~PERF_PMU_TXN_ADD)
1050 return;
1051 perf_pmu_disable(pmu);
1052}
1053
1054static void thread_imc_pmu_cancel_txn(struct pmu *pmu)
1055{
1056 perf_pmu_enable(pmu);
1057}
1058
1059static int thread_imc_pmu_commit_txn(struct pmu *pmu)
1060{
1061 perf_pmu_enable(pmu);
1062 return 0;
1063}
1064
1065static u64 imc_read_counter(struct perf_event *event)
1066{
1067 __be64 *addr;
1068 u64 data;
1069
1070 /*
1071 * In-Memory Collection (IMC) counters are free flowing counters.
1072 * So we take a snapshot of the counter value on enable and save it
1073 * to calculate the delta at later stage to present the event counter
1074 * value.
1075 */
1076 addr = get_event_base_addr(event);
1077 data = be64_to_cpu(READ_ONCE(*addr));
1078 local64_set(&event->hw.prev_count, data);
1079
1080 return data;
1081}
1082
1083static void imc_event_update(struct perf_event *event)
1084{
1085 u64 counter_prev, counter_new, final_count;
1086
1087 counter_prev = local64_read(&event->hw.prev_count);
1088 counter_new = imc_read_counter(event);
1089 final_count = counter_new - counter_prev;
1090
1091 /* Update the delta to the event count */
1092 local64_add(final_count, &event->count);
1093}
1094
1095static void imc_event_start(struct perf_event *event, int flags)
1096{
1097 /*
1098 * In Memory Counters are free flowing counters. HW or the microcode
1099 * keeps adding to the counter offset in memory. To get event
1100 * counter value, we snapshot the value here and we calculate
1101 * delta at later point.
1102 */
1103 imc_read_counter(event);
1104}
1105
1106static void imc_event_stop(struct perf_event *event, int flags)
1107{
1108 /*
1109 * Take a snapshot and calculate the delta and update
1110 * the event counter values.
1111 */
1112 imc_event_update(event);
1113}
1114
1115static int imc_event_add(struct perf_event *event, int flags)
1116{
1117 if (flags & PERF_EF_START)
1118 imc_event_start(event, flags);
1119
1120 return 0;
1121}
1122
1123static int thread_imc_event_add(struct perf_event *event, int flags)
1124{
1125 int core_id;
1126 struct imc_pmu_ref *ref;
1127 u64 ldbar_value, *local_mem = per_cpu(thread_imc_mem, smp_processor_id());
1128
1129 if (flags & PERF_EF_START)
1130 imc_event_start(event, flags);
1131
1132 if (!is_core_imc_mem_inited(smp_processor_id()))
1133 return -EINVAL;
1134
1135 core_id = smp_processor_id() / threads_per_core;
1136 ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | THREAD_IMC_ENABLE;
1137 mtspr(SPRN_LDBAR, ldbar_value);
1138
1139 /*
1140 * imc pmus are enabled only when it is used.
1141 * See if this is triggered for the first time.
1142 * If yes, take the lock and enable the counters.
1143 * If not, just increment the count in ref count struct.
1144 */
1145 ref = &core_imc_refc[core_id];
1146 if (!ref)
1147 return -EINVAL;
1148
1149 spin_lock(&ref->lock);
1150 if (ref->refc == 0) {
1151 if (opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
1152 get_hard_smp_processor_id(smp_processor_id()))) {
1153 spin_unlock(&ref->lock);
1154 pr_err("thread-imc: Unable to start the counter\
1155 for core %d\n", core_id);
1156 return -EINVAL;
1157 }
1158 }
1159 ++ref->refc;
1160 spin_unlock(&ref->lock);
1161 return 0;
1162}
1163
1164static void thread_imc_event_del(struct perf_event *event, int flags)
1165{
1166
1167 int core_id;
1168 struct imc_pmu_ref *ref;
1169
1170 core_id = smp_processor_id() / threads_per_core;
1171 ref = &core_imc_refc[core_id];
1172 if (!ref) {
1173 pr_debug("imc: Failed to get event reference count\n");
1174 return;
1175 }
1176
1177 spin_lock(&ref->lock);
1178 ref->refc--;
1179 if (ref->refc == 0) {
1180 if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
1181 get_hard_smp_processor_id(smp_processor_id()))) {
1182 spin_unlock(&ref->lock);
1183 pr_err("thread-imc: Unable to stop the counters\
1184 for core %d\n", core_id);
1185 return;
1186 }
1187 } else if (ref->refc < 0) {
1188 ref->refc = 0;
1189 }
1190 spin_unlock(&ref->lock);
1191
1192 /* Set bit 0 of LDBAR to zero, to stop posting updates to memory */
1193 mtspr(SPRN_LDBAR, (mfspr(SPRN_LDBAR) & (~(1UL << 63))));
1194
1195 /*
1196 * Take a snapshot and calculate the delta and update
1197 * the event counter values.
1198 */
1199 imc_event_update(event);
1200}
1201
1202/*
1203 * Allocate a page of memory for each cpu, and load LDBAR with 0.
1204 */
1205static int trace_imc_mem_alloc(int cpu_id, int size)
1206{
1207 u64 *local_mem = per_cpu(trace_imc_mem, cpu_id);
1208 int phys_id = cpu_to_node(cpu_id), rc = 0;
1209 int core_id = (cpu_id / threads_per_core);
1210
1211 if (!local_mem) {
1212 struct page *page;
1213
1214 page = alloc_pages_node(phys_id,
1215 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
1216 __GFP_NOWARN, get_order(size));
1217 if (!page)
1218 return -ENOMEM;
1219 local_mem = page_address(page);
1220 per_cpu(trace_imc_mem, cpu_id) = local_mem;
1221
1222 /* Initialise the counters for trace mode */
1223 rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_TRACE, __pa((void *)local_mem),
1224 get_hard_smp_processor_id(cpu_id));
1225 if (rc) {
1226 pr_info("IMC:opal init failed for trace imc\n");
1227 return rc;
1228 }
1229 }
1230
1231 trace_imc_refc[core_id].id = core_id;
1232 spin_lock_init(&trace_imc_refc[core_id].lock);
1233
1234 mtspr(SPRN_LDBAR, 0);
1235 return 0;
1236}
1237
1238static int ppc_trace_imc_cpu_online(unsigned int cpu)
1239{
1240 return trace_imc_mem_alloc(cpu, trace_imc_mem_size);
1241}
1242
1243static int ppc_trace_imc_cpu_offline(unsigned int cpu)
1244{
1245 /*
1246 * No need to set bit 0 of LDBAR to zero, as
1247 * it is set to zero for imc trace-mode
1248 *
1249 * Reduce the refc if any trace-imc event running
1250 * on this cpu.
1251 */
1252 spin_lock(&imc_global_refc.lock);
1253 if (imc_global_refc.id == IMC_DOMAIN_TRACE)
1254 imc_global_refc.refc--;
1255 spin_unlock(&imc_global_refc.lock);
1256
1257 return 0;
1258}
1259
1260static int trace_imc_cpu_init(void)
1261{
1262 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE,
1263 "perf/powerpc/imc_trace:online",
1264 ppc_trace_imc_cpu_online,
1265 ppc_trace_imc_cpu_offline);
1266}
1267
1268static u64 get_trace_imc_event_base_addr(void)
1269{
1270 return (u64)per_cpu(trace_imc_mem, smp_processor_id());
1271}
1272
1273/*
1274 * Function to parse trace-imc data obtained
1275 * and to prepare the perf sample.
1276 */
1277static int trace_imc_prepare_sample(struct trace_imc_data *mem,
1278 struct perf_sample_data *data,
1279 u64 *prev_tb,
1280 struct perf_event_header *header,
1281 struct perf_event *event)
1282{
1283 /* Sanity checks for a valid record */
1284 if (be64_to_cpu(READ_ONCE(mem->tb1)) > *prev_tb)
1285 *prev_tb = be64_to_cpu(READ_ONCE(mem->tb1));
1286 else
1287 return -EINVAL;
1288
1289 if ((be64_to_cpu(READ_ONCE(mem->tb1)) & IMC_TRACE_RECORD_TB1_MASK) !=
1290 be64_to_cpu(READ_ONCE(mem->tb2)))
1291 return -EINVAL;
1292
1293 /* Prepare perf sample */
1294 data->ip = be64_to_cpu(READ_ONCE(mem->ip));
1295 data->period = event->hw.last_period;
1296
1297 header->type = PERF_RECORD_SAMPLE;
1298 header->size = sizeof(*header) + event->header_size;
1299 header->misc = 0;
1300
1301 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
1302 switch (IMC_TRACE_RECORD_VAL_HVPR(be64_to_cpu(READ_ONCE(mem->val)))) {
1303 case 0:/* when MSR HV and PR not set in the trace-record */
1304 header->misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1305 break;
1306 case 1: /* MSR HV is 0 and PR is 1 */
1307 header->misc |= PERF_RECORD_MISC_GUEST_USER;
1308 break;
1309 case 2: /* MSR HV is 1 and PR is 0 */
1310 header->misc |= PERF_RECORD_MISC_KERNEL;
1311 break;
1312 case 3: /* MSR HV is 1 and PR is 1 */
1313 header->misc |= PERF_RECORD_MISC_USER;
1314 break;
1315 default:
1316 pr_info("IMC: Unable to set the flag based on MSR bits\n");
1317 break;
1318 }
1319 } else {
1320 if (is_kernel_addr(data->ip))
1321 header->misc |= PERF_RECORD_MISC_KERNEL;
1322 else
1323 header->misc |= PERF_RECORD_MISC_USER;
1324 }
1325 perf_event_header__init_id(header, data, event);
1326
1327 return 0;
1328}
1329
1330static void dump_trace_imc_data(struct perf_event *event)
1331{
1332 struct trace_imc_data *mem;
1333 int i, ret;
1334 u64 prev_tb = 0;
1335
1336 mem = (struct trace_imc_data *)get_trace_imc_event_base_addr();
1337 for (i = 0; i < (trace_imc_mem_size / sizeof(struct trace_imc_data));
1338 i++, mem++) {
1339 struct perf_sample_data data;
1340 struct perf_event_header header;
1341
1342 ret = trace_imc_prepare_sample(mem, &data, &prev_tb, &header, event);
1343 if (ret) /* Exit, if not a valid record */
1344 break;
1345 else {
1346 /* If this is a valid record, create the sample */
1347 struct perf_output_handle handle;
1348
1349 if (perf_output_begin(&handle, &data, event, header.size))
1350 return;
1351
1352 perf_output_sample(&handle, &header, &data, event);
1353 perf_output_end(&handle);
1354 }
1355 }
1356}
1357
1358static int trace_imc_event_add(struct perf_event *event, int flags)
1359{
1360 int core_id = smp_processor_id() / threads_per_core;
1361 struct imc_pmu_ref *ref = NULL;
1362 u64 local_mem, ldbar_value;
1363
1364 /* Set trace-imc bit in ldbar and load ldbar with per-thread memory address */
1365 local_mem = get_trace_imc_event_base_addr();
1366 ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | TRACE_IMC_ENABLE;
1367
1368 /* trace-imc reference count */
1369 if (trace_imc_refc)
1370 ref = &trace_imc_refc[core_id];
1371 if (!ref) {
1372 pr_debug("imc: Failed to get the event reference count\n");
1373 return -EINVAL;
1374 }
1375
1376 mtspr(SPRN_LDBAR, ldbar_value);
1377 spin_lock(&ref->lock);
1378 if (ref->refc == 0) {
1379 if (opal_imc_counters_start(OPAL_IMC_COUNTERS_TRACE,
1380 get_hard_smp_processor_id(smp_processor_id()))) {
1381 spin_unlock(&ref->lock);
1382 pr_err("trace-imc: Unable to start the counters for core %d\n", core_id);
1383 return -EINVAL;
1384 }
1385 }
1386 ++ref->refc;
1387 spin_unlock(&ref->lock);
1388 return 0;
1389}
1390
1391static void trace_imc_event_read(struct perf_event *event)
1392{
1393 return;
1394}
1395
1396static void trace_imc_event_stop(struct perf_event *event, int flags)
1397{
1398 u64 local_mem = get_trace_imc_event_base_addr();
1399 dump_trace_imc_data(event);
1400 memset((void *)local_mem, 0, sizeof(u64));
1401}
1402
1403static void trace_imc_event_start(struct perf_event *event, int flags)
1404{
1405 return;
1406}
1407
1408static void trace_imc_event_del(struct perf_event *event, int flags)
1409{
1410 int core_id = smp_processor_id() / threads_per_core;
1411 struct imc_pmu_ref *ref = NULL;
1412
1413 if (trace_imc_refc)
1414 ref = &trace_imc_refc[core_id];
1415 if (!ref) {
1416 pr_debug("imc: Failed to get event reference count\n");
1417 return;
1418 }
1419
1420 spin_lock(&ref->lock);
1421 ref->refc--;
1422 if (ref->refc == 0) {
1423 if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_TRACE,
1424 get_hard_smp_processor_id(smp_processor_id()))) {
1425 spin_unlock(&ref->lock);
1426 pr_err("trace-imc: Unable to stop the counters for core %d\n", core_id);
1427 return;
1428 }
1429 } else if (ref->refc < 0) {
1430 ref->refc = 0;
1431 }
1432 spin_unlock(&ref->lock);
1433
1434 trace_imc_event_stop(event, flags);
1435}
1436
1437static int trace_imc_event_init(struct perf_event *event)
1438{
1439 if (event->attr.type != event->pmu->type)
1440 return -ENOENT;
1441
1442 if (!perfmon_capable())
1443 return -EACCES;
1444
1445 /* Return if this is a couting event */
1446 if (event->attr.sample_period == 0)
1447 return -ENOENT;
1448
1449 /*
1450 * Take the global lock, and make sure
1451 * no other thread is running any core/thread imc
1452 * events
1453 */
1454 spin_lock(&imc_global_refc.lock);
1455 if (imc_global_refc.id == 0 || imc_global_refc.id == IMC_DOMAIN_TRACE) {
1456 /*
1457 * No core/thread imc events are running in the
1458 * system, so set the refc.id to trace-imc.
1459 */
1460 imc_global_refc.id = IMC_DOMAIN_TRACE;
1461 imc_global_refc.refc++;
1462 } else {
1463 spin_unlock(&imc_global_refc.lock);
1464 return -EBUSY;
1465 }
1466 spin_unlock(&imc_global_refc.lock);
1467
1468 event->hw.idx = -1;
1469
1470 /*
1471 * There can only be a single PMU for perf_hw_context events which is assigned to
1472 * core PMU. Hence use "perf_sw_context" for trace_imc.
1473 */
1474 event->pmu->task_ctx_nr = perf_sw_context;
1475 event->destroy = reset_global_refc;
1476 return 0;
1477}
1478
1479/* update_pmu_ops : Populate the appropriate operations for "pmu" */
1480static int update_pmu_ops(struct imc_pmu *pmu)
1481{
1482 pmu->pmu.task_ctx_nr = perf_invalid_context;
1483 pmu->pmu.add = imc_event_add;
1484 pmu->pmu.del = imc_event_stop;
1485 pmu->pmu.start = imc_event_start;
1486 pmu->pmu.stop = imc_event_stop;
1487 pmu->pmu.read = imc_event_update;
1488 pmu->pmu.attr_groups = pmu->attr_groups;
1489 pmu->pmu.capabilities = PERF_PMU_CAP_NO_EXCLUDE;
1490 pmu->attr_groups[IMC_FORMAT_ATTR] = &imc_format_group;
1491
1492 switch (pmu->domain) {
1493 case IMC_DOMAIN_NEST:
1494 pmu->pmu.event_init = nest_imc_event_init;
1495 pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1496 break;
1497 case IMC_DOMAIN_CORE:
1498 pmu->pmu.event_init = core_imc_event_init;
1499 pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1500 break;
1501 case IMC_DOMAIN_THREAD:
1502 pmu->pmu.event_init = thread_imc_event_init;
1503 pmu->pmu.add = thread_imc_event_add;
1504 pmu->pmu.del = thread_imc_event_del;
1505 pmu->pmu.start_txn = thread_imc_pmu_start_txn;
1506 pmu->pmu.cancel_txn = thread_imc_pmu_cancel_txn;
1507 pmu->pmu.commit_txn = thread_imc_pmu_commit_txn;
1508 break;
1509 case IMC_DOMAIN_TRACE:
1510 pmu->pmu.event_init = trace_imc_event_init;
1511 pmu->pmu.add = trace_imc_event_add;
1512 pmu->pmu.del = trace_imc_event_del;
1513 pmu->pmu.start = trace_imc_event_start;
1514 pmu->pmu.stop = trace_imc_event_stop;
1515 pmu->pmu.read = trace_imc_event_read;
1516 pmu->attr_groups[IMC_FORMAT_ATTR] = &trace_imc_format_group;
1517 break;
1518 default:
1519 break;
1520 }
1521
1522 return 0;
1523}
1524
1525/* init_nest_pmu_ref: Initialize the imc_pmu_ref struct for all the nodes */
1526static int init_nest_pmu_ref(void)
1527{
1528 int nid, i, cpu;
1529
1530 nest_imc_refc = kcalloc(num_possible_nodes(), sizeof(*nest_imc_refc),
1531 GFP_KERNEL);
1532
1533 if (!nest_imc_refc)
1534 return -ENOMEM;
1535
1536 i = 0;
1537 for_each_node(nid) {
1538 /*
1539 * Take the lock to avoid races while tracking the number of
1540 * sessions using the chip's nest pmu units.
1541 */
1542 spin_lock_init(&nest_imc_refc[i].lock);
1543
1544 /*
1545 * Loop to init the "id" with the node_id. Variable "i" initialized to
1546 * 0 and will be used as index to the array. "i" will not go off the
1547 * end of the array since the "for_each_node" loops for "N_POSSIBLE"
1548 * nodes only.
1549 */
1550 nest_imc_refc[i++].id = nid;
1551 }
1552
1553 /*
1554 * Loop to init the per_cpu "local_nest_imc_refc" with the proper
1555 * "nest_imc_refc" index. This makes get_nest_pmu_ref() alot simple.
1556 */
1557 for_each_possible_cpu(cpu) {
1558 nid = cpu_to_node(cpu);
1559 for (i = 0; i < num_possible_nodes(); i++) {
1560 if (nest_imc_refc[i].id == nid) {
1561 per_cpu(local_nest_imc_refc, cpu) = &nest_imc_refc[i];
1562 break;
1563 }
1564 }
1565 }
1566 return 0;
1567}
1568
1569static void cleanup_all_core_imc_memory(void)
1570{
1571 int i, nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1572 struct imc_mem_info *ptr = core_imc_pmu->mem_info;
1573 int size = core_imc_pmu->counter_mem_size;
1574
1575 /* mem_info will never be NULL */
1576 for (i = 0; i < nr_cores; i++) {
1577 if (ptr[i].vbase)
1578 free_pages((u64)ptr[i].vbase, get_order(size));
1579 }
1580
1581 kfree(ptr);
1582 kfree(core_imc_refc);
1583}
1584
1585static void thread_imc_ldbar_disable(void *dummy)
1586{
1587 /*
1588 * By setting 0th bit of LDBAR to zero, we disable thread-imc
1589 * updates to memory.
1590 */
1591 mtspr(SPRN_LDBAR, (mfspr(SPRN_LDBAR) & (~(1UL << 63))));
1592}
1593
1594void thread_imc_disable(void)
1595{
1596 on_each_cpu(thread_imc_ldbar_disable, NULL, 1);
1597}
1598
1599static void cleanup_all_thread_imc_memory(void)
1600{
1601 int i, order = get_order(thread_imc_mem_size);
1602
1603 for_each_online_cpu(i) {
1604 if (per_cpu(thread_imc_mem, i))
1605 free_pages((u64)per_cpu(thread_imc_mem, i), order);
1606
1607 }
1608}
1609
1610static void cleanup_all_trace_imc_memory(void)
1611{
1612 int i, order = get_order(trace_imc_mem_size);
1613
1614 for_each_online_cpu(i) {
1615 if (per_cpu(trace_imc_mem, i))
1616 free_pages((u64)per_cpu(trace_imc_mem, i), order);
1617
1618 }
1619 kfree(trace_imc_refc);
1620}
1621
1622/* Function to free the attr_groups which are dynamically allocated */
1623static void imc_common_mem_free(struct imc_pmu *pmu_ptr)
1624{
1625 if (pmu_ptr->attr_groups[IMC_EVENT_ATTR])
1626 kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]->attrs);
1627 kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]);
1628}
1629
1630/*
1631 * Common function to unregister cpu hotplug callback and
1632 * free the memory.
1633 * TODO: Need to handle pmu unregistering, which will be
1634 * done in followup series.
1635 */
1636static void imc_common_cpuhp_mem_free(struct imc_pmu *pmu_ptr)
1637{
1638 if (pmu_ptr->domain == IMC_DOMAIN_NEST) {
1639 mutex_lock(&nest_init_lock);
1640 if (nest_pmus == 1) {
1641 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE);
1642 kfree(nest_imc_refc);
1643 kfree(per_nest_pmu_arr);
1644 per_nest_pmu_arr = NULL;
1645 }
1646
1647 if (nest_pmus > 0)
1648 nest_pmus--;
1649 mutex_unlock(&nest_init_lock);
1650 }
1651
1652 /* Free core_imc memory */
1653 if (pmu_ptr->domain == IMC_DOMAIN_CORE) {
1654 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE);
1655 cleanup_all_core_imc_memory();
1656 }
1657
1658 /* Free thread_imc memory */
1659 if (pmu_ptr->domain == IMC_DOMAIN_THREAD) {
1660 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE);
1661 cleanup_all_thread_imc_memory();
1662 }
1663
1664 if (pmu_ptr->domain == IMC_DOMAIN_TRACE) {
1665 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE);
1666 cleanup_all_trace_imc_memory();
1667 }
1668}
1669
1670/*
1671 * Function to unregister thread-imc if core-imc
1672 * is not registered.
1673 */
1674void unregister_thread_imc(void)
1675{
1676 imc_common_cpuhp_mem_free(thread_imc_pmu);
1677 imc_common_mem_free(thread_imc_pmu);
1678 perf_pmu_unregister(&thread_imc_pmu->pmu);
1679}
1680
1681/*
1682 * imc_mem_init : Function to support memory allocation for core imc.
1683 */
1684static int imc_mem_init(struct imc_pmu *pmu_ptr, struct device_node *parent,
1685 int pmu_index)
1686{
1687 const char *s;
1688 int nr_cores, cpu, res = -ENOMEM;
1689
1690 if (of_property_read_string(parent, "name", &s))
1691 return -ENODEV;
1692
1693 switch (pmu_ptr->domain) {
1694 case IMC_DOMAIN_NEST:
1695 /* Update the pmu name */
1696 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s_imc", "nest_", s);
1697 if (!pmu_ptr->pmu.name)
1698 goto err;
1699
1700 /* Needed for hotplug/migration */
1701 if (!per_nest_pmu_arr) {
1702 per_nest_pmu_arr = kcalloc(get_max_nest_dev() + 1,
1703 sizeof(struct imc_pmu *),
1704 GFP_KERNEL);
1705 if (!per_nest_pmu_arr)
1706 goto err;
1707 }
1708 per_nest_pmu_arr[pmu_index] = pmu_ptr;
1709 break;
1710 case IMC_DOMAIN_CORE:
1711 /* Update the pmu name */
1712 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1713 if (!pmu_ptr->pmu.name)
1714 goto err;
1715
1716 nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1717 pmu_ptr->mem_info = kcalloc(nr_cores, sizeof(struct imc_mem_info),
1718 GFP_KERNEL);
1719
1720 if (!pmu_ptr->mem_info)
1721 goto err;
1722
1723 core_imc_refc = kcalloc(nr_cores, sizeof(struct imc_pmu_ref),
1724 GFP_KERNEL);
1725
1726 if (!core_imc_refc) {
1727 kfree(pmu_ptr->mem_info);
1728 goto err;
1729 }
1730
1731 core_imc_pmu = pmu_ptr;
1732 break;
1733 case IMC_DOMAIN_THREAD:
1734 /* Update the pmu name */
1735 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1736 if (!pmu_ptr->pmu.name)
1737 goto err;
1738
1739 thread_imc_mem_size = pmu_ptr->counter_mem_size;
1740 for_each_online_cpu(cpu) {
1741 res = thread_imc_mem_alloc(cpu, pmu_ptr->counter_mem_size);
1742 if (res) {
1743 cleanup_all_thread_imc_memory();
1744 goto err;
1745 }
1746 }
1747
1748 thread_imc_pmu = pmu_ptr;
1749 break;
1750 case IMC_DOMAIN_TRACE:
1751 /* Update the pmu name */
1752 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1753 if (!pmu_ptr->pmu.name)
1754 return -ENOMEM;
1755
1756 nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1757 trace_imc_refc = kcalloc(nr_cores, sizeof(struct imc_pmu_ref),
1758 GFP_KERNEL);
1759 if (!trace_imc_refc)
1760 return -ENOMEM;
1761
1762 trace_imc_mem_size = pmu_ptr->counter_mem_size;
1763 for_each_online_cpu(cpu) {
1764 res = trace_imc_mem_alloc(cpu, trace_imc_mem_size);
1765 if (res) {
1766 cleanup_all_trace_imc_memory();
1767 goto err;
1768 }
1769 }
1770 break;
1771 default:
1772 return -EINVAL;
1773 }
1774
1775 return 0;
1776err:
1777 return res;
1778}
1779
1780/*
1781 * init_imc_pmu : Setup and register the IMC pmu device.
1782 *
1783 * @parent: Device tree unit node
1784 * @pmu_ptr: memory allocated for this pmu
1785 * @pmu_idx: Count of nest pmc registered
1786 *
1787 * init_imc_pmu() setup pmu cpumask and registers for a cpu hotplug callback.
1788 * Handles failure cases and accordingly frees memory.
1789 */
1790int init_imc_pmu(struct device_node *parent, struct imc_pmu *pmu_ptr, int pmu_idx)
1791{
1792 int ret;
1793
1794 ret = imc_mem_init(pmu_ptr, parent, pmu_idx);
1795 if (ret)
1796 goto err_free_mem;
1797
1798 switch (pmu_ptr->domain) {
1799 case IMC_DOMAIN_NEST:
1800 /*
1801 * Nest imc pmu need only one cpu per chip, we initialize the
1802 * cpumask for the first nest imc pmu and use the same for the
1803 * rest. To handle the cpuhotplug callback unregister, we track
1804 * the number of nest pmus in "nest_pmus".
1805 */
1806 mutex_lock(&nest_init_lock);
1807 if (nest_pmus == 0) {
1808 ret = init_nest_pmu_ref();
1809 if (ret) {
1810 mutex_unlock(&nest_init_lock);
1811 kfree(per_nest_pmu_arr);
1812 per_nest_pmu_arr = NULL;
1813 goto err_free_mem;
1814 }
1815 /* Register for cpu hotplug notification. */
1816 ret = nest_pmu_cpumask_init();
1817 if (ret) {
1818 mutex_unlock(&nest_init_lock);
1819 kfree(nest_imc_refc);
1820 kfree(per_nest_pmu_arr);
1821 per_nest_pmu_arr = NULL;
1822 goto err_free_mem;
1823 }
1824 }
1825 nest_pmus++;
1826 mutex_unlock(&nest_init_lock);
1827 break;
1828 case IMC_DOMAIN_CORE:
1829 ret = core_imc_pmu_cpumask_init();
1830 if (ret) {
1831 cleanup_all_core_imc_memory();
1832 goto err_free_mem;
1833 }
1834
1835 break;
1836 case IMC_DOMAIN_THREAD:
1837 ret = thread_imc_cpu_init();
1838 if (ret) {
1839 cleanup_all_thread_imc_memory();
1840 goto err_free_mem;
1841 }
1842
1843 break;
1844 case IMC_DOMAIN_TRACE:
1845 ret = trace_imc_cpu_init();
1846 if (ret) {
1847 cleanup_all_trace_imc_memory();
1848 goto err_free_mem;
1849 }
1850
1851 break;
1852 default:
1853 return -EINVAL; /* Unknown domain */
1854 }
1855
1856 ret = update_events_in_group(parent, pmu_ptr);
1857 if (ret)
1858 goto err_free_cpuhp_mem;
1859
1860 ret = update_pmu_ops(pmu_ptr);
1861 if (ret)
1862 goto err_free_cpuhp_mem;
1863
1864 ret = perf_pmu_register(&pmu_ptr->pmu, pmu_ptr->pmu.name, -1);
1865 if (ret)
1866 goto err_free_cpuhp_mem;
1867
1868 pr_debug("%s performance monitor hardware support registered\n",
1869 pmu_ptr->pmu.name);
1870
1871 return 0;
1872
1873err_free_cpuhp_mem:
1874 imc_common_cpuhp_mem_free(pmu_ptr);
1875err_free_mem:
1876 imc_common_mem_free(pmu_ptr);
1877 return ret;
1878}
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * In-Memory Collection (IMC) Performance Monitor counter support.
4 *
5 * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.
6 * (C) 2017 Anju T Sudhakar, IBM Corporation.
7 * (C) 2017 Hemant K Shaw, IBM Corporation.
8 */
9#include <linux/perf_event.h>
10#include <linux/slab.h>
11#include <asm/opal.h>
12#include <asm/imc-pmu.h>
13#include <asm/cputhreads.h>
14#include <asm/smp.h>
15#include <linux/string.h>
16
17/* Nest IMC data structures and variables */
18
19/*
20 * Used to avoid races in counting the nest-pmu units during hotplug
21 * register and unregister
22 */
23static DEFINE_MUTEX(nest_init_lock);
24static DEFINE_PER_CPU(struct imc_pmu_ref *, local_nest_imc_refc);
25static struct imc_pmu **per_nest_pmu_arr;
26static cpumask_t nest_imc_cpumask;
27static struct imc_pmu_ref *nest_imc_refc;
28static int nest_pmus;
29
30/* Core IMC data structures and variables */
31
32static cpumask_t core_imc_cpumask;
33static struct imc_pmu_ref *core_imc_refc;
34static struct imc_pmu *core_imc_pmu;
35
36/* Thread IMC data structures and variables */
37
38static DEFINE_PER_CPU(u64 *, thread_imc_mem);
39static struct imc_pmu *thread_imc_pmu;
40static int thread_imc_mem_size;
41
42/* Trace IMC data structures */
43static DEFINE_PER_CPU(u64 *, trace_imc_mem);
44static struct imc_pmu_ref *trace_imc_refc;
45static int trace_imc_mem_size;
46
47static struct imc_pmu *imc_event_to_pmu(struct perf_event *event)
48{
49 return container_of(event->pmu, struct imc_pmu, pmu);
50}
51
52PMU_FORMAT_ATTR(event, "config:0-61");
53PMU_FORMAT_ATTR(offset, "config:0-31");
54PMU_FORMAT_ATTR(rvalue, "config:32");
55PMU_FORMAT_ATTR(mode, "config:33-40");
56static struct attribute *imc_format_attrs[] = {
57 &format_attr_event.attr,
58 &format_attr_offset.attr,
59 &format_attr_rvalue.attr,
60 &format_attr_mode.attr,
61 NULL,
62};
63
64static struct attribute_group imc_format_group = {
65 .name = "format",
66 .attrs = imc_format_attrs,
67};
68
69/* Format attribute for imc trace-mode */
70PMU_FORMAT_ATTR(cpmc_reserved, "config:0-19");
71PMU_FORMAT_ATTR(cpmc_event, "config:20-27");
72PMU_FORMAT_ATTR(cpmc_samplesel, "config:28-29");
73PMU_FORMAT_ATTR(cpmc_load, "config:30-61");
74static struct attribute *trace_imc_format_attrs[] = {
75 &format_attr_event.attr,
76 &format_attr_cpmc_reserved.attr,
77 &format_attr_cpmc_event.attr,
78 &format_attr_cpmc_samplesel.attr,
79 &format_attr_cpmc_load.attr,
80 NULL,
81};
82
83static struct attribute_group trace_imc_format_group = {
84.name = "format",
85.attrs = trace_imc_format_attrs,
86};
87
88/* Get the cpumask printed to a buffer "buf" */
89static ssize_t imc_pmu_cpumask_get_attr(struct device *dev,
90 struct device_attribute *attr,
91 char *buf)
92{
93 struct pmu *pmu = dev_get_drvdata(dev);
94 struct imc_pmu *imc_pmu = container_of(pmu, struct imc_pmu, pmu);
95 cpumask_t *active_mask;
96
97 switch(imc_pmu->domain){
98 case IMC_DOMAIN_NEST:
99 active_mask = &nest_imc_cpumask;
100 break;
101 case IMC_DOMAIN_CORE:
102 active_mask = &core_imc_cpumask;
103 break;
104 default:
105 return 0;
106 }
107
108 return cpumap_print_to_pagebuf(true, buf, active_mask);
109}
110
111static DEVICE_ATTR(cpumask, S_IRUGO, imc_pmu_cpumask_get_attr, NULL);
112
113static struct attribute *imc_pmu_cpumask_attrs[] = {
114 &dev_attr_cpumask.attr,
115 NULL,
116};
117
118static struct attribute_group imc_pmu_cpumask_attr_group = {
119 .attrs = imc_pmu_cpumask_attrs,
120};
121
122/* device_str_attr_create : Populate event "name" and string "str" in attribute */
123static struct attribute *device_str_attr_create(const char *name, const char *str)
124{
125 struct perf_pmu_events_attr *attr;
126
127 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
128 if (!attr)
129 return NULL;
130 sysfs_attr_init(&attr->attr.attr);
131
132 attr->event_str = str;
133 attr->attr.attr.name = name;
134 attr->attr.attr.mode = 0444;
135 attr->attr.show = perf_event_sysfs_show;
136
137 return &attr->attr.attr;
138}
139
140static int imc_parse_event(struct device_node *np, const char *scale,
141 const char *unit, const char *prefix,
142 u32 base, struct imc_events *event)
143{
144 const char *s;
145 u32 reg;
146
147 if (of_property_read_u32(np, "reg", ®))
148 goto error;
149 /* Add the base_reg value to the "reg" */
150 event->value = base + reg;
151
152 if (of_property_read_string(np, "event-name", &s))
153 goto error;
154
155 event->name = kasprintf(GFP_KERNEL, "%s%s", prefix, s);
156 if (!event->name)
157 goto error;
158
159 if (of_property_read_string(np, "scale", &s))
160 s = scale;
161
162 if (s) {
163 event->scale = kstrdup(s, GFP_KERNEL);
164 if (!event->scale)
165 goto error;
166 }
167
168 if (of_property_read_string(np, "unit", &s))
169 s = unit;
170
171 if (s) {
172 event->unit = kstrdup(s, GFP_KERNEL);
173 if (!event->unit)
174 goto error;
175 }
176
177 return 0;
178error:
179 kfree(event->unit);
180 kfree(event->scale);
181 kfree(event->name);
182 return -EINVAL;
183}
184
185/*
186 * imc_free_events: Function to cleanup the events list, having
187 * "nr_entries".
188 */
189static void imc_free_events(struct imc_events *events, int nr_entries)
190{
191 int i;
192
193 /* Nothing to clean, return */
194 if (!events)
195 return;
196 for (i = 0; i < nr_entries; i++) {
197 kfree(events[i].unit);
198 kfree(events[i].scale);
199 kfree(events[i].name);
200 }
201
202 kfree(events);
203}
204
205/*
206 * update_events_in_group: Update the "events" information in an attr_group
207 * and assign the attr_group to the pmu "pmu".
208 */
209static int update_events_in_group(struct device_node *node, struct imc_pmu *pmu)
210{
211 struct attribute_group *attr_group;
212 struct attribute **attrs, *dev_str;
213 struct device_node *np, *pmu_events;
214 u32 handle, base_reg;
215 int i = 0, j = 0, ct, ret;
216 const char *prefix, *g_scale, *g_unit;
217 const char *ev_val_str, *ev_scale_str, *ev_unit_str;
218
219 if (!of_property_read_u32(node, "events", &handle))
220 pmu_events = of_find_node_by_phandle(handle);
221 else
222 return 0;
223
224 /* Did not find any node with a given phandle */
225 if (!pmu_events)
226 return 0;
227
228 /* Get a count of number of child nodes */
229 ct = of_get_child_count(pmu_events);
230
231 /* Get the event prefix */
232 if (of_property_read_string(node, "events-prefix", &prefix))
233 return 0;
234
235 /* Get a global unit and scale data if available */
236 if (of_property_read_string(node, "scale", &g_scale))
237 g_scale = NULL;
238
239 if (of_property_read_string(node, "unit", &g_unit))
240 g_unit = NULL;
241
242 /* "reg" property gives out the base offset of the counters data */
243 of_property_read_u32(node, "reg", &base_reg);
244
245 /* Allocate memory for the events */
246 pmu->events = kcalloc(ct, sizeof(struct imc_events), GFP_KERNEL);
247 if (!pmu->events)
248 return -ENOMEM;
249
250 ct = 0;
251 /* Parse the events and update the struct */
252 for_each_child_of_node(pmu_events, np) {
253 ret = imc_parse_event(np, g_scale, g_unit, prefix, base_reg, &pmu->events[ct]);
254 if (!ret)
255 ct++;
256 }
257
258 /* Allocate memory for attribute group */
259 attr_group = kzalloc(sizeof(*attr_group), GFP_KERNEL);
260 if (!attr_group) {
261 imc_free_events(pmu->events, ct);
262 return -ENOMEM;
263 }
264
265 /*
266 * Allocate memory for attributes.
267 * Since we have count of events for this pmu, we also allocate
268 * memory for the scale and unit attribute for now.
269 * "ct" has the total event structs added from the events-parent node.
270 * So allocate three times the "ct" (this includes event, event_scale and
271 * event_unit).
272 */
273 attrs = kcalloc(((ct * 3) + 1), sizeof(struct attribute *), GFP_KERNEL);
274 if (!attrs) {
275 kfree(attr_group);
276 imc_free_events(pmu->events, ct);
277 return -ENOMEM;
278 }
279
280 attr_group->name = "events";
281 attr_group->attrs = attrs;
282 do {
283 ev_val_str = kasprintf(GFP_KERNEL, "event=0x%x", pmu->events[i].value);
284 dev_str = device_str_attr_create(pmu->events[i].name, ev_val_str);
285 if (!dev_str)
286 continue;
287
288 attrs[j++] = dev_str;
289 if (pmu->events[i].scale) {
290 ev_scale_str = kasprintf(GFP_KERNEL, "%s.scale", pmu->events[i].name);
291 dev_str = device_str_attr_create(ev_scale_str, pmu->events[i].scale);
292 if (!dev_str)
293 continue;
294
295 attrs[j++] = dev_str;
296 }
297
298 if (pmu->events[i].unit) {
299 ev_unit_str = kasprintf(GFP_KERNEL, "%s.unit", pmu->events[i].name);
300 dev_str = device_str_attr_create(ev_unit_str, pmu->events[i].unit);
301 if (!dev_str)
302 continue;
303
304 attrs[j++] = dev_str;
305 }
306 } while (++i < ct);
307
308 /* Save the event attribute */
309 pmu->attr_groups[IMC_EVENT_ATTR] = attr_group;
310
311 return 0;
312}
313
314/* get_nest_pmu_ref: Return the imc_pmu_ref struct for the given node */
315static struct imc_pmu_ref *get_nest_pmu_ref(int cpu)
316{
317 return per_cpu(local_nest_imc_refc, cpu);
318}
319
320static void nest_change_cpu_context(int old_cpu, int new_cpu)
321{
322 struct imc_pmu **pn = per_nest_pmu_arr;
323
324 if (old_cpu < 0 || new_cpu < 0)
325 return;
326
327 while (*pn) {
328 perf_pmu_migrate_context(&(*pn)->pmu, old_cpu, new_cpu);
329 pn++;
330 }
331}
332
333static int ppc_nest_imc_cpu_offline(unsigned int cpu)
334{
335 int nid, target = -1;
336 const struct cpumask *l_cpumask;
337 struct imc_pmu_ref *ref;
338
339 /*
340 * Check in the designated list for this cpu. Dont bother
341 * if not one of them.
342 */
343 if (!cpumask_test_and_clear_cpu(cpu, &nest_imc_cpumask))
344 return 0;
345
346 /*
347 * Check whether nest_imc is registered. We could end up here if the
348 * cpuhotplug callback registration fails. i.e, callback invokes the
349 * offline path for all successfully registered nodes. At this stage,
350 * nest_imc pmu will not be registered and we should return here.
351 *
352 * We return with a zero since this is not an offline failure. And
353 * cpuhp_setup_state() returns the actual failure reason to the caller,
354 * which in turn will call the cleanup routine.
355 */
356 if (!nest_pmus)
357 return 0;
358
359 /*
360 * Now that this cpu is one of the designated,
361 * find a next cpu a) which is online and b) in same chip.
362 */
363 nid = cpu_to_node(cpu);
364 l_cpumask = cpumask_of_node(nid);
365 target = cpumask_last(l_cpumask);
366
367 /*
368 * If this(target) is the last cpu in the cpumask for this chip,
369 * check for any possible online cpu in the chip.
370 */
371 if (unlikely(target == cpu))
372 target = cpumask_any_but(l_cpumask, cpu);
373
374 /*
375 * Update the cpumask with the target cpu and
376 * migrate the context if needed
377 */
378 if (target >= 0 && target < nr_cpu_ids) {
379 cpumask_set_cpu(target, &nest_imc_cpumask);
380 nest_change_cpu_context(cpu, target);
381 } else {
382 opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
383 get_hard_smp_processor_id(cpu));
384 /*
385 * If this is the last cpu in this chip then, skip the reference
386 * count mutex lock and make the reference count on this chip zero.
387 */
388 ref = get_nest_pmu_ref(cpu);
389 if (!ref)
390 return -EINVAL;
391
392 ref->refc = 0;
393 }
394 return 0;
395}
396
397static int ppc_nest_imc_cpu_online(unsigned int cpu)
398{
399 const struct cpumask *l_cpumask;
400 static struct cpumask tmp_mask;
401 int res;
402
403 /* Get the cpumask of this node */
404 l_cpumask = cpumask_of_node(cpu_to_node(cpu));
405
406 /*
407 * If this is not the first online CPU on this node, then
408 * just return.
409 */
410 if (cpumask_and(&tmp_mask, l_cpumask, &nest_imc_cpumask))
411 return 0;
412
413 /*
414 * If this is the first online cpu on this node
415 * disable the nest counters by making an OPAL call.
416 */
417 res = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
418 get_hard_smp_processor_id(cpu));
419 if (res)
420 return res;
421
422 /* Make this CPU the designated target for counter collection */
423 cpumask_set_cpu(cpu, &nest_imc_cpumask);
424 return 0;
425}
426
427static int nest_pmu_cpumask_init(void)
428{
429 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE,
430 "perf/powerpc/imc:online",
431 ppc_nest_imc_cpu_online,
432 ppc_nest_imc_cpu_offline);
433}
434
435static void nest_imc_counters_release(struct perf_event *event)
436{
437 int rc, node_id;
438 struct imc_pmu_ref *ref;
439
440 if (event->cpu < 0)
441 return;
442
443 node_id = cpu_to_node(event->cpu);
444
445 /*
446 * See if we need to disable the nest PMU.
447 * If no events are currently in use, then we have to take a
448 * mutex to ensure that we don't race with another task doing
449 * enable or disable the nest counters.
450 */
451 ref = get_nest_pmu_ref(event->cpu);
452 if (!ref)
453 return;
454
455 /* Take the mutex lock for this node and then decrement the reference count */
456 mutex_lock(&ref->lock);
457 if (ref->refc == 0) {
458 /*
459 * The scenario where this is true is, when perf session is
460 * started, followed by offlining of all cpus in a given node.
461 *
462 * In the cpuhotplug offline path, ppc_nest_imc_cpu_offline()
463 * function set the ref->count to zero, if the cpu which is
464 * about to offline is the last cpu in a given node and make
465 * an OPAL call to disable the engine in that node.
466 *
467 */
468 mutex_unlock(&ref->lock);
469 return;
470 }
471 ref->refc--;
472 if (ref->refc == 0) {
473 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
474 get_hard_smp_processor_id(event->cpu));
475 if (rc) {
476 mutex_unlock(&ref->lock);
477 pr_err("nest-imc: Unable to stop the counters for core %d\n", node_id);
478 return;
479 }
480 } else if (ref->refc < 0) {
481 WARN(1, "nest-imc: Invalid event reference count\n");
482 ref->refc = 0;
483 }
484 mutex_unlock(&ref->lock);
485}
486
487static int nest_imc_event_init(struct perf_event *event)
488{
489 int chip_id, rc, node_id;
490 u32 l_config, config = event->attr.config;
491 struct imc_mem_info *pcni;
492 struct imc_pmu *pmu;
493 struct imc_pmu_ref *ref;
494 bool flag = false;
495
496 if (event->attr.type != event->pmu->type)
497 return -ENOENT;
498
499 /* Sampling not supported */
500 if (event->hw.sample_period)
501 return -EINVAL;
502
503 if (event->cpu < 0)
504 return -EINVAL;
505
506 pmu = imc_event_to_pmu(event);
507
508 /* Sanity check for config (event offset) */
509 if ((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size)
510 return -EINVAL;
511
512 /*
513 * Nest HW counter memory resides in a per-chip reserve-memory (HOMER).
514 * Get the base memory addresss for this cpu.
515 */
516 chip_id = cpu_to_chip_id(event->cpu);
517
518 /* Return, if chip_id is not valid */
519 if (chip_id < 0)
520 return -ENODEV;
521
522 pcni = pmu->mem_info;
523 do {
524 if (pcni->id == chip_id) {
525 flag = true;
526 break;
527 }
528 pcni++;
529 } while (pcni->vbase != 0);
530
531 if (!flag)
532 return -ENODEV;
533
534 /*
535 * Add the event offset to the base address.
536 */
537 l_config = config & IMC_EVENT_OFFSET_MASK;
538 event->hw.event_base = (u64)pcni->vbase + l_config;
539 node_id = cpu_to_node(event->cpu);
540
541 /*
542 * Get the imc_pmu_ref struct for this node.
543 * Take the mutex lock and then increment the count of nest pmu events
544 * inited.
545 */
546 ref = get_nest_pmu_ref(event->cpu);
547 if (!ref)
548 return -EINVAL;
549
550 mutex_lock(&ref->lock);
551 if (ref->refc == 0) {
552 rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_NEST,
553 get_hard_smp_processor_id(event->cpu));
554 if (rc) {
555 mutex_unlock(&ref->lock);
556 pr_err("nest-imc: Unable to start the counters for node %d\n",
557 node_id);
558 return rc;
559 }
560 }
561 ++ref->refc;
562 mutex_unlock(&ref->lock);
563
564 event->destroy = nest_imc_counters_release;
565 return 0;
566}
567
568/*
569 * core_imc_mem_init : Initializes memory for the current core.
570 *
571 * Uses alloc_pages_node() and uses the returned address as an argument to
572 * an opal call to configure the pdbar. The address sent as an argument is
573 * converted to physical address before the opal call is made. This is the
574 * base address at which the core imc counters are populated.
575 */
576static int core_imc_mem_init(int cpu, int size)
577{
578 int nid, rc = 0, core_id = (cpu / threads_per_core);
579 struct imc_mem_info *mem_info;
580 struct page *page;
581
582 /*
583 * alloc_pages_node() will allocate memory for core in the
584 * local node only.
585 */
586 nid = cpu_to_node(cpu);
587 mem_info = &core_imc_pmu->mem_info[core_id];
588 mem_info->id = core_id;
589
590 /* We need only vbase for core counters */
591 page = alloc_pages_node(nid,
592 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
593 __GFP_NOWARN, get_order(size));
594 if (!page)
595 return -ENOMEM;
596 mem_info->vbase = page_address(page);
597
598 /* Init the mutex */
599 core_imc_refc[core_id].id = core_id;
600 mutex_init(&core_imc_refc[core_id].lock);
601
602 rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_CORE,
603 __pa((void *)mem_info->vbase),
604 get_hard_smp_processor_id(cpu));
605 if (rc) {
606 free_pages((u64)mem_info->vbase, get_order(size));
607 mem_info->vbase = NULL;
608 }
609
610 return rc;
611}
612
613static bool is_core_imc_mem_inited(int cpu)
614{
615 struct imc_mem_info *mem_info;
616 int core_id = (cpu / threads_per_core);
617
618 mem_info = &core_imc_pmu->mem_info[core_id];
619 if (!mem_info->vbase)
620 return false;
621
622 return true;
623}
624
625static int ppc_core_imc_cpu_online(unsigned int cpu)
626{
627 const struct cpumask *l_cpumask;
628 static struct cpumask tmp_mask;
629 int ret = 0;
630
631 /* Get the cpumask for this core */
632 l_cpumask = cpu_sibling_mask(cpu);
633
634 /* If a cpu for this core is already set, then, don't do anything */
635 if (cpumask_and(&tmp_mask, l_cpumask, &core_imc_cpumask))
636 return 0;
637
638 if (!is_core_imc_mem_inited(cpu)) {
639 ret = core_imc_mem_init(cpu, core_imc_pmu->counter_mem_size);
640 if (ret) {
641 pr_info("core_imc memory allocation for cpu %d failed\n", cpu);
642 return ret;
643 }
644 }
645
646 /* set the cpu in the mask */
647 cpumask_set_cpu(cpu, &core_imc_cpumask);
648 return 0;
649}
650
651static int ppc_core_imc_cpu_offline(unsigned int cpu)
652{
653 unsigned int core_id;
654 int ncpu;
655 struct imc_pmu_ref *ref;
656
657 /*
658 * clear this cpu out of the mask, if not present in the mask,
659 * don't bother doing anything.
660 */
661 if (!cpumask_test_and_clear_cpu(cpu, &core_imc_cpumask))
662 return 0;
663
664 /*
665 * Check whether core_imc is registered. We could end up here
666 * if the cpuhotplug callback registration fails. i.e, callback
667 * invokes the offline path for all sucessfully registered cpus.
668 * At this stage, core_imc pmu will not be registered and we
669 * should return here.
670 *
671 * We return with a zero since this is not an offline failure.
672 * And cpuhp_setup_state() returns the actual failure reason
673 * to the caller, which inturn will call the cleanup routine.
674 */
675 if (!core_imc_pmu->pmu.event_init)
676 return 0;
677
678 /* Find any online cpu in that core except the current "cpu" */
679 ncpu = cpumask_last(cpu_sibling_mask(cpu));
680
681 if (unlikely(ncpu == cpu))
682 ncpu = cpumask_any_but(cpu_sibling_mask(cpu), cpu);
683
684 if (ncpu >= 0 && ncpu < nr_cpu_ids) {
685 cpumask_set_cpu(ncpu, &core_imc_cpumask);
686 perf_pmu_migrate_context(&core_imc_pmu->pmu, cpu, ncpu);
687 } else {
688 /*
689 * If this is the last cpu in this core then, skip taking refernce
690 * count mutex lock for this core and directly zero "refc" for
691 * this core.
692 */
693 opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
694 get_hard_smp_processor_id(cpu));
695 core_id = cpu / threads_per_core;
696 ref = &core_imc_refc[core_id];
697 if (!ref)
698 return -EINVAL;
699
700 ref->refc = 0;
701 }
702 return 0;
703}
704
705static int core_imc_pmu_cpumask_init(void)
706{
707 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE,
708 "perf/powerpc/imc_core:online",
709 ppc_core_imc_cpu_online,
710 ppc_core_imc_cpu_offline);
711}
712
713static void core_imc_counters_release(struct perf_event *event)
714{
715 int rc, core_id;
716 struct imc_pmu_ref *ref;
717
718 if (event->cpu < 0)
719 return;
720 /*
721 * See if we need to disable the IMC PMU.
722 * If no events are currently in use, then we have to take a
723 * mutex to ensure that we don't race with another task doing
724 * enable or disable the core counters.
725 */
726 core_id = event->cpu / threads_per_core;
727
728 /* Take the mutex lock and decrement the refernce count for this core */
729 ref = &core_imc_refc[core_id];
730 if (!ref)
731 return;
732
733 mutex_lock(&ref->lock);
734 if (ref->refc == 0) {
735 /*
736 * The scenario where this is true is, when perf session is
737 * started, followed by offlining of all cpus in a given core.
738 *
739 * In the cpuhotplug offline path, ppc_core_imc_cpu_offline()
740 * function set the ref->count to zero, if the cpu which is
741 * about to offline is the last cpu in a given core and make
742 * an OPAL call to disable the engine in that core.
743 *
744 */
745 mutex_unlock(&ref->lock);
746 return;
747 }
748 ref->refc--;
749 if (ref->refc == 0) {
750 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
751 get_hard_smp_processor_id(event->cpu));
752 if (rc) {
753 mutex_unlock(&ref->lock);
754 pr_err("IMC: Unable to stop the counters for core %d\n", core_id);
755 return;
756 }
757 } else if (ref->refc < 0) {
758 WARN(1, "core-imc: Invalid event reference count\n");
759 ref->refc = 0;
760 }
761 mutex_unlock(&ref->lock);
762}
763
764static int core_imc_event_init(struct perf_event *event)
765{
766 int core_id, rc;
767 u64 config = event->attr.config;
768 struct imc_mem_info *pcmi;
769 struct imc_pmu *pmu;
770 struct imc_pmu_ref *ref;
771
772 if (event->attr.type != event->pmu->type)
773 return -ENOENT;
774
775 /* Sampling not supported */
776 if (event->hw.sample_period)
777 return -EINVAL;
778
779 if (event->cpu < 0)
780 return -EINVAL;
781
782 event->hw.idx = -1;
783 pmu = imc_event_to_pmu(event);
784
785 /* Sanity check for config (event offset) */
786 if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
787 return -EINVAL;
788
789 if (!is_core_imc_mem_inited(event->cpu))
790 return -ENODEV;
791
792 core_id = event->cpu / threads_per_core;
793 pcmi = &core_imc_pmu->mem_info[core_id];
794 if ((!pcmi->vbase))
795 return -ENODEV;
796
797 /* Get the core_imc mutex for this core */
798 ref = &core_imc_refc[core_id];
799 if (!ref)
800 return -EINVAL;
801
802 /*
803 * Core pmu units are enabled only when it is used.
804 * See if this is triggered for the first time.
805 * If yes, take the mutex lock and enable the core counters.
806 * If not, just increment the count in core_imc_refc struct.
807 */
808 mutex_lock(&ref->lock);
809 if (ref->refc == 0) {
810 rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
811 get_hard_smp_processor_id(event->cpu));
812 if (rc) {
813 mutex_unlock(&ref->lock);
814 pr_err("core-imc: Unable to start the counters for core %d\n",
815 core_id);
816 return rc;
817 }
818 }
819 ++ref->refc;
820 mutex_unlock(&ref->lock);
821
822 event->hw.event_base = (u64)pcmi->vbase + (config & IMC_EVENT_OFFSET_MASK);
823 event->destroy = core_imc_counters_release;
824 return 0;
825}
826
827/*
828 * Allocates a page of memory for each of the online cpus, and load
829 * LDBAR with 0.
830 * The physical base address of the page allocated for a cpu will be
831 * written to the LDBAR for that cpu, when the thread-imc event
832 * is added.
833 *
834 * LDBAR Register Layout:
835 *
836 * 0 4 8 12 16 20 24 28
837 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
838 * | | [ ] [ Counter Address [8:50]
839 * | * Mode |
840 * | * PB Scope
841 * * Enable/Disable
842 *
843 * 32 36 40 44 48 52 56 60
844 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
845 * Counter Address [8:50] ]
846 *
847 */
848static int thread_imc_mem_alloc(int cpu_id, int size)
849{
850 u64 *local_mem = per_cpu(thread_imc_mem, cpu_id);
851 int nid = cpu_to_node(cpu_id);
852
853 if (!local_mem) {
854 struct page *page;
855 /*
856 * This case could happen only once at start, since we dont
857 * free the memory in cpu offline path.
858 */
859 page = alloc_pages_node(nid,
860 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
861 __GFP_NOWARN, get_order(size));
862 if (!page)
863 return -ENOMEM;
864 local_mem = page_address(page);
865
866 per_cpu(thread_imc_mem, cpu_id) = local_mem;
867 }
868
869 mtspr(SPRN_LDBAR, 0);
870 return 0;
871}
872
873static int ppc_thread_imc_cpu_online(unsigned int cpu)
874{
875 return thread_imc_mem_alloc(cpu, thread_imc_mem_size);
876}
877
878static int ppc_thread_imc_cpu_offline(unsigned int cpu)
879{
880 mtspr(SPRN_LDBAR, 0);
881 return 0;
882}
883
884static int thread_imc_cpu_init(void)
885{
886 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE,
887 "perf/powerpc/imc_thread:online",
888 ppc_thread_imc_cpu_online,
889 ppc_thread_imc_cpu_offline);
890}
891
892static int thread_imc_event_init(struct perf_event *event)
893{
894 u32 config = event->attr.config;
895 struct task_struct *target;
896 struct imc_pmu *pmu;
897
898 if (event->attr.type != event->pmu->type)
899 return -ENOENT;
900
901 if (!capable(CAP_SYS_ADMIN))
902 return -EACCES;
903
904 /* Sampling not supported */
905 if (event->hw.sample_period)
906 return -EINVAL;
907
908 event->hw.idx = -1;
909 pmu = imc_event_to_pmu(event);
910
911 /* Sanity check for config offset */
912 if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
913 return -EINVAL;
914
915 target = event->hw.target;
916 if (!target)
917 return -EINVAL;
918
919 event->pmu->task_ctx_nr = perf_sw_context;
920 return 0;
921}
922
923static bool is_thread_imc_pmu(struct perf_event *event)
924{
925 if (!strncmp(event->pmu->name, "thread_imc", strlen("thread_imc")))
926 return true;
927
928 return false;
929}
930
931static u64 * get_event_base_addr(struct perf_event *event)
932{
933 u64 addr;
934
935 if (is_thread_imc_pmu(event)) {
936 addr = (u64)per_cpu(thread_imc_mem, smp_processor_id());
937 return (u64 *)(addr + (event->attr.config & IMC_EVENT_OFFSET_MASK));
938 }
939
940 return (u64 *)event->hw.event_base;
941}
942
943static void thread_imc_pmu_start_txn(struct pmu *pmu,
944 unsigned int txn_flags)
945{
946 if (txn_flags & ~PERF_PMU_TXN_ADD)
947 return;
948 perf_pmu_disable(pmu);
949}
950
951static void thread_imc_pmu_cancel_txn(struct pmu *pmu)
952{
953 perf_pmu_enable(pmu);
954}
955
956static int thread_imc_pmu_commit_txn(struct pmu *pmu)
957{
958 perf_pmu_enable(pmu);
959 return 0;
960}
961
962static u64 imc_read_counter(struct perf_event *event)
963{
964 u64 *addr, data;
965
966 /*
967 * In-Memory Collection (IMC) counters are free flowing counters.
968 * So we take a snapshot of the counter value on enable and save it
969 * to calculate the delta at later stage to present the event counter
970 * value.
971 */
972 addr = get_event_base_addr(event);
973 data = be64_to_cpu(READ_ONCE(*addr));
974 local64_set(&event->hw.prev_count, data);
975
976 return data;
977}
978
979static void imc_event_update(struct perf_event *event)
980{
981 u64 counter_prev, counter_new, final_count;
982
983 counter_prev = local64_read(&event->hw.prev_count);
984 counter_new = imc_read_counter(event);
985 final_count = counter_new - counter_prev;
986
987 /* Update the delta to the event count */
988 local64_add(final_count, &event->count);
989}
990
991static void imc_event_start(struct perf_event *event, int flags)
992{
993 /*
994 * In Memory Counters are free flowing counters. HW or the microcode
995 * keeps adding to the counter offset in memory. To get event
996 * counter value, we snapshot the value here and we calculate
997 * delta at later point.
998 */
999 imc_read_counter(event);
1000}
1001
1002static void imc_event_stop(struct perf_event *event, int flags)
1003{
1004 /*
1005 * Take a snapshot and calculate the delta and update
1006 * the event counter values.
1007 */
1008 imc_event_update(event);
1009}
1010
1011static int imc_event_add(struct perf_event *event, int flags)
1012{
1013 if (flags & PERF_EF_START)
1014 imc_event_start(event, flags);
1015
1016 return 0;
1017}
1018
1019static int thread_imc_event_add(struct perf_event *event, int flags)
1020{
1021 int core_id;
1022 struct imc_pmu_ref *ref;
1023 u64 ldbar_value, *local_mem = per_cpu(thread_imc_mem, smp_processor_id());
1024
1025 if (flags & PERF_EF_START)
1026 imc_event_start(event, flags);
1027
1028 if (!is_core_imc_mem_inited(smp_processor_id()))
1029 return -EINVAL;
1030
1031 core_id = smp_processor_id() / threads_per_core;
1032 ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | THREAD_IMC_ENABLE;
1033 mtspr(SPRN_LDBAR, ldbar_value);
1034
1035 /*
1036 * imc pmus are enabled only when it is used.
1037 * See if this is triggered for the first time.
1038 * If yes, take the mutex lock and enable the counters.
1039 * If not, just increment the count in ref count struct.
1040 */
1041 ref = &core_imc_refc[core_id];
1042 if (!ref)
1043 return -EINVAL;
1044
1045 mutex_lock(&ref->lock);
1046 if (ref->refc == 0) {
1047 if (opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
1048 get_hard_smp_processor_id(smp_processor_id()))) {
1049 mutex_unlock(&ref->lock);
1050 pr_err("thread-imc: Unable to start the counter\
1051 for core %d\n", core_id);
1052 return -EINVAL;
1053 }
1054 }
1055 ++ref->refc;
1056 mutex_unlock(&ref->lock);
1057 return 0;
1058}
1059
1060static void thread_imc_event_del(struct perf_event *event, int flags)
1061{
1062
1063 int core_id;
1064 struct imc_pmu_ref *ref;
1065
1066 mtspr(SPRN_LDBAR, 0);
1067
1068 core_id = smp_processor_id() / threads_per_core;
1069 ref = &core_imc_refc[core_id];
1070
1071 mutex_lock(&ref->lock);
1072 ref->refc--;
1073 if (ref->refc == 0) {
1074 if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
1075 get_hard_smp_processor_id(smp_processor_id()))) {
1076 mutex_unlock(&ref->lock);
1077 pr_err("thread-imc: Unable to stop the counters\
1078 for core %d\n", core_id);
1079 return;
1080 }
1081 } else if (ref->refc < 0) {
1082 ref->refc = 0;
1083 }
1084 mutex_unlock(&ref->lock);
1085 /*
1086 * Take a snapshot and calculate the delta and update
1087 * the event counter values.
1088 */
1089 imc_event_update(event);
1090}
1091
1092/*
1093 * Allocate a page of memory for each cpu, and load LDBAR with 0.
1094 */
1095static int trace_imc_mem_alloc(int cpu_id, int size)
1096{
1097 u64 *local_mem = per_cpu(trace_imc_mem, cpu_id);
1098 int phys_id = cpu_to_node(cpu_id), rc = 0;
1099 int core_id = (cpu_id / threads_per_core);
1100
1101 if (!local_mem) {
1102 struct page *page;
1103
1104 page = alloc_pages_node(phys_id,
1105 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
1106 __GFP_NOWARN, get_order(size));
1107 if (!page)
1108 return -ENOMEM;
1109 local_mem = page_address(page);
1110 per_cpu(trace_imc_mem, cpu_id) = local_mem;
1111
1112 /* Initialise the counters for trace mode */
1113 rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_TRACE, __pa((void *)local_mem),
1114 get_hard_smp_processor_id(cpu_id));
1115 if (rc) {
1116 pr_info("IMC:opal init failed for trace imc\n");
1117 return rc;
1118 }
1119 }
1120
1121 /* Init the mutex, if not already */
1122 trace_imc_refc[core_id].id = core_id;
1123 mutex_init(&trace_imc_refc[core_id].lock);
1124
1125 mtspr(SPRN_LDBAR, 0);
1126 return 0;
1127}
1128
1129static int ppc_trace_imc_cpu_online(unsigned int cpu)
1130{
1131 return trace_imc_mem_alloc(cpu, trace_imc_mem_size);
1132}
1133
1134static int ppc_trace_imc_cpu_offline(unsigned int cpu)
1135{
1136 mtspr(SPRN_LDBAR, 0);
1137 return 0;
1138}
1139
1140static int trace_imc_cpu_init(void)
1141{
1142 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE,
1143 "perf/powerpc/imc_trace:online",
1144 ppc_trace_imc_cpu_online,
1145 ppc_trace_imc_cpu_offline);
1146}
1147
1148static u64 get_trace_imc_event_base_addr(void)
1149{
1150 return (u64)per_cpu(trace_imc_mem, smp_processor_id());
1151}
1152
1153/*
1154 * Function to parse trace-imc data obtained
1155 * and to prepare the perf sample.
1156 */
1157static int trace_imc_prepare_sample(struct trace_imc_data *mem,
1158 struct perf_sample_data *data,
1159 u64 *prev_tb,
1160 struct perf_event_header *header,
1161 struct perf_event *event)
1162{
1163 /* Sanity checks for a valid record */
1164 if (be64_to_cpu(READ_ONCE(mem->tb1)) > *prev_tb)
1165 *prev_tb = be64_to_cpu(READ_ONCE(mem->tb1));
1166 else
1167 return -EINVAL;
1168
1169 if ((be64_to_cpu(READ_ONCE(mem->tb1)) & IMC_TRACE_RECORD_TB1_MASK) !=
1170 be64_to_cpu(READ_ONCE(mem->tb2)))
1171 return -EINVAL;
1172
1173 /* Prepare perf sample */
1174 data->ip = be64_to_cpu(READ_ONCE(mem->ip));
1175 data->period = event->hw.last_period;
1176
1177 header->type = PERF_RECORD_SAMPLE;
1178 header->size = sizeof(*header) + event->header_size;
1179 header->misc = 0;
1180
1181 if (is_kernel_addr(data->ip))
1182 header->misc |= PERF_RECORD_MISC_KERNEL;
1183 else
1184 header->misc |= PERF_RECORD_MISC_USER;
1185
1186 perf_event_header__init_id(header, data, event);
1187
1188 return 0;
1189}
1190
1191static void dump_trace_imc_data(struct perf_event *event)
1192{
1193 struct trace_imc_data *mem;
1194 int i, ret;
1195 u64 prev_tb = 0;
1196
1197 mem = (struct trace_imc_data *)get_trace_imc_event_base_addr();
1198 for (i = 0; i < (trace_imc_mem_size / sizeof(struct trace_imc_data));
1199 i++, mem++) {
1200 struct perf_sample_data data;
1201 struct perf_event_header header;
1202
1203 ret = trace_imc_prepare_sample(mem, &data, &prev_tb, &header, event);
1204 if (ret) /* Exit, if not a valid record */
1205 break;
1206 else {
1207 /* If this is a valid record, create the sample */
1208 struct perf_output_handle handle;
1209
1210 if (perf_output_begin(&handle, event, header.size))
1211 return;
1212
1213 perf_output_sample(&handle, &header, &data, event);
1214 perf_output_end(&handle);
1215 }
1216 }
1217}
1218
1219static int trace_imc_event_add(struct perf_event *event, int flags)
1220{
1221 int core_id = smp_processor_id() / threads_per_core;
1222 struct imc_pmu_ref *ref = NULL;
1223 u64 local_mem, ldbar_value;
1224
1225 /* Set trace-imc bit in ldbar and load ldbar with per-thread memory address */
1226 local_mem = get_trace_imc_event_base_addr();
1227 ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | TRACE_IMC_ENABLE;
1228
1229 if (core_imc_refc)
1230 ref = &core_imc_refc[core_id];
1231 if (!ref) {
1232 /* If core-imc is not enabled, use trace-imc reference count */
1233 if (trace_imc_refc)
1234 ref = &trace_imc_refc[core_id];
1235 if (!ref)
1236 return -EINVAL;
1237 }
1238 mtspr(SPRN_LDBAR, ldbar_value);
1239 mutex_lock(&ref->lock);
1240 if (ref->refc == 0) {
1241 if (opal_imc_counters_start(OPAL_IMC_COUNTERS_TRACE,
1242 get_hard_smp_processor_id(smp_processor_id()))) {
1243 mutex_unlock(&ref->lock);
1244 pr_err("trace-imc: Unable to start the counters for core %d\n", core_id);
1245 mtspr(SPRN_LDBAR, 0);
1246 return -EINVAL;
1247 }
1248 }
1249 ++ref->refc;
1250 mutex_unlock(&ref->lock);
1251
1252 return 0;
1253}
1254
1255static void trace_imc_event_read(struct perf_event *event)
1256{
1257 return;
1258}
1259
1260static void trace_imc_event_stop(struct perf_event *event, int flags)
1261{
1262 u64 local_mem = get_trace_imc_event_base_addr();
1263 dump_trace_imc_data(event);
1264 memset((void *)local_mem, 0, sizeof(u64));
1265}
1266
1267static void trace_imc_event_start(struct perf_event *event, int flags)
1268{
1269 return;
1270}
1271
1272static void trace_imc_event_del(struct perf_event *event, int flags)
1273{
1274 int core_id = smp_processor_id() / threads_per_core;
1275 struct imc_pmu_ref *ref = NULL;
1276
1277 if (core_imc_refc)
1278 ref = &core_imc_refc[core_id];
1279 if (!ref) {
1280 /* If core-imc is not enabled, use trace-imc reference count */
1281 if (trace_imc_refc)
1282 ref = &trace_imc_refc[core_id];
1283 if (!ref)
1284 return;
1285 }
1286 mtspr(SPRN_LDBAR, 0);
1287 mutex_lock(&ref->lock);
1288 ref->refc--;
1289 if (ref->refc == 0) {
1290 if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_TRACE,
1291 get_hard_smp_processor_id(smp_processor_id()))) {
1292 mutex_unlock(&ref->lock);
1293 pr_err("trace-imc: Unable to stop the counters for core %d\n", core_id);
1294 return;
1295 }
1296 } else if (ref->refc < 0) {
1297 ref->refc = 0;
1298 }
1299 mutex_unlock(&ref->lock);
1300 trace_imc_event_stop(event, flags);
1301}
1302
1303static int trace_imc_event_init(struct perf_event *event)
1304{
1305 struct task_struct *target;
1306
1307 if (event->attr.type != event->pmu->type)
1308 return -ENOENT;
1309
1310 if (!capable(CAP_SYS_ADMIN))
1311 return -EACCES;
1312
1313 /* Return if this is a couting event */
1314 if (event->attr.sample_period == 0)
1315 return -ENOENT;
1316
1317 event->hw.idx = -1;
1318 target = event->hw.target;
1319
1320 event->pmu->task_ctx_nr = perf_hw_context;
1321 return 0;
1322}
1323
1324/* update_pmu_ops : Populate the appropriate operations for "pmu" */
1325static int update_pmu_ops(struct imc_pmu *pmu)
1326{
1327 pmu->pmu.task_ctx_nr = perf_invalid_context;
1328 pmu->pmu.add = imc_event_add;
1329 pmu->pmu.del = imc_event_stop;
1330 pmu->pmu.start = imc_event_start;
1331 pmu->pmu.stop = imc_event_stop;
1332 pmu->pmu.read = imc_event_update;
1333 pmu->pmu.attr_groups = pmu->attr_groups;
1334 pmu->pmu.capabilities = PERF_PMU_CAP_NO_EXCLUDE;
1335 pmu->attr_groups[IMC_FORMAT_ATTR] = &imc_format_group;
1336
1337 switch (pmu->domain) {
1338 case IMC_DOMAIN_NEST:
1339 pmu->pmu.event_init = nest_imc_event_init;
1340 pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1341 break;
1342 case IMC_DOMAIN_CORE:
1343 pmu->pmu.event_init = core_imc_event_init;
1344 pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1345 break;
1346 case IMC_DOMAIN_THREAD:
1347 pmu->pmu.event_init = thread_imc_event_init;
1348 pmu->pmu.add = thread_imc_event_add;
1349 pmu->pmu.del = thread_imc_event_del;
1350 pmu->pmu.start_txn = thread_imc_pmu_start_txn;
1351 pmu->pmu.cancel_txn = thread_imc_pmu_cancel_txn;
1352 pmu->pmu.commit_txn = thread_imc_pmu_commit_txn;
1353 break;
1354 case IMC_DOMAIN_TRACE:
1355 pmu->pmu.event_init = trace_imc_event_init;
1356 pmu->pmu.add = trace_imc_event_add;
1357 pmu->pmu.del = trace_imc_event_del;
1358 pmu->pmu.start = trace_imc_event_start;
1359 pmu->pmu.stop = trace_imc_event_stop;
1360 pmu->pmu.read = trace_imc_event_read;
1361 pmu->attr_groups[IMC_FORMAT_ATTR] = &trace_imc_format_group;
1362 default:
1363 break;
1364 }
1365
1366 return 0;
1367}
1368
1369/* init_nest_pmu_ref: Initialize the imc_pmu_ref struct for all the nodes */
1370static int init_nest_pmu_ref(void)
1371{
1372 int nid, i, cpu;
1373
1374 nest_imc_refc = kcalloc(num_possible_nodes(), sizeof(*nest_imc_refc),
1375 GFP_KERNEL);
1376
1377 if (!nest_imc_refc)
1378 return -ENOMEM;
1379
1380 i = 0;
1381 for_each_node(nid) {
1382 /*
1383 * Mutex lock to avoid races while tracking the number of
1384 * sessions using the chip's nest pmu units.
1385 */
1386 mutex_init(&nest_imc_refc[i].lock);
1387
1388 /*
1389 * Loop to init the "id" with the node_id. Variable "i" initialized to
1390 * 0 and will be used as index to the array. "i" will not go off the
1391 * end of the array since the "for_each_node" loops for "N_POSSIBLE"
1392 * nodes only.
1393 */
1394 nest_imc_refc[i++].id = nid;
1395 }
1396
1397 /*
1398 * Loop to init the per_cpu "local_nest_imc_refc" with the proper
1399 * "nest_imc_refc" index. This makes get_nest_pmu_ref() alot simple.
1400 */
1401 for_each_possible_cpu(cpu) {
1402 nid = cpu_to_node(cpu);
1403 for (i = 0; i < num_possible_nodes(); i++) {
1404 if (nest_imc_refc[i].id == nid) {
1405 per_cpu(local_nest_imc_refc, cpu) = &nest_imc_refc[i];
1406 break;
1407 }
1408 }
1409 }
1410 return 0;
1411}
1412
1413static void cleanup_all_core_imc_memory(void)
1414{
1415 int i, nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1416 struct imc_mem_info *ptr = core_imc_pmu->mem_info;
1417 int size = core_imc_pmu->counter_mem_size;
1418
1419 /* mem_info will never be NULL */
1420 for (i = 0; i < nr_cores; i++) {
1421 if (ptr[i].vbase)
1422 free_pages((u64)ptr[i].vbase, get_order(size));
1423 }
1424
1425 kfree(ptr);
1426 kfree(core_imc_refc);
1427}
1428
1429static void thread_imc_ldbar_disable(void *dummy)
1430{
1431 /*
1432 * By Zeroing LDBAR, we disable thread-imc
1433 * updates.
1434 */
1435 mtspr(SPRN_LDBAR, 0);
1436}
1437
1438void thread_imc_disable(void)
1439{
1440 on_each_cpu(thread_imc_ldbar_disable, NULL, 1);
1441}
1442
1443static void cleanup_all_thread_imc_memory(void)
1444{
1445 int i, order = get_order(thread_imc_mem_size);
1446
1447 for_each_online_cpu(i) {
1448 if (per_cpu(thread_imc_mem, i))
1449 free_pages((u64)per_cpu(thread_imc_mem, i), order);
1450
1451 }
1452}
1453
1454static void cleanup_all_trace_imc_memory(void)
1455{
1456 int i, order = get_order(trace_imc_mem_size);
1457
1458 for_each_online_cpu(i) {
1459 if (per_cpu(trace_imc_mem, i))
1460 free_pages((u64)per_cpu(trace_imc_mem, i), order);
1461
1462 }
1463 kfree(trace_imc_refc);
1464}
1465
1466/* Function to free the attr_groups which are dynamically allocated */
1467static void imc_common_mem_free(struct imc_pmu *pmu_ptr)
1468{
1469 if (pmu_ptr->attr_groups[IMC_EVENT_ATTR])
1470 kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]->attrs);
1471 kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]);
1472}
1473
1474/*
1475 * Common function to unregister cpu hotplug callback and
1476 * free the memory.
1477 * TODO: Need to handle pmu unregistering, which will be
1478 * done in followup series.
1479 */
1480static void imc_common_cpuhp_mem_free(struct imc_pmu *pmu_ptr)
1481{
1482 if (pmu_ptr->domain == IMC_DOMAIN_NEST) {
1483 mutex_lock(&nest_init_lock);
1484 if (nest_pmus == 1) {
1485 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE);
1486 kfree(nest_imc_refc);
1487 kfree(per_nest_pmu_arr);
1488 per_nest_pmu_arr = NULL;
1489 }
1490
1491 if (nest_pmus > 0)
1492 nest_pmus--;
1493 mutex_unlock(&nest_init_lock);
1494 }
1495
1496 /* Free core_imc memory */
1497 if (pmu_ptr->domain == IMC_DOMAIN_CORE) {
1498 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE);
1499 cleanup_all_core_imc_memory();
1500 }
1501
1502 /* Free thread_imc memory */
1503 if (pmu_ptr->domain == IMC_DOMAIN_THREAD) {
1504 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE);
1505 cleanup_all_thread_imc_memory();
1506 }
1507
1508 if (pmu_ptr->domain == IMC_DOMAIN_TRACE) {
1509 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE);
1510 cleanup_all_trace_imc_memory();
1511 }
1512}
1513
1514/*
1515 * Function to unregister thread-imc if core-imc
1516 * is not registered.
1517 */
1518void unregister_thread_imc(void)
1519{
1520 imc_common_cpuhp_mem_free(thread_imc_pmu);
1521 imc_common_mem_free(thread_imc_pmu);
1522 perf_pmu_unregister(&thread_imc_pmu->pmu);
1523}
1524
1525/*
1526 * imc_mem_init : Function to support memory allocation for core imc.
1527 */
1528static int imc_mem_init(struct imc_pmu *pmu_ptr, struct device_node *parent,
1529 int pmu_index)
1530{
1531 const char *s;
1532 int nr_cores, cpu, res = -ENOMEM;
1533
1534 if (of_property_read_string(parent, "name", &s))
1535 return -ENODEV;
1536
1537 switch (pmu_ptr->domain) {
1538 case IMC_DOMAIN_NEST:
1539 /* Update the pmu name */
1540 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s_imc", "nest_", s);
1541 if (!pmu_ptr->pmu.name)
1542 goto err;
1543
1544 /* Needed for hotplug/migration */
1545 if (!per_nest_pmu_arr) {
1546 per_nest_pmu_arr = kcalloc(get_max_nest_dev() + 1,
1547 sizeof(struct imc_pmu *),
1548 GFP_KERNEL);
1549 if (!per_nest_pmu_arr)
1550 goto err;
1551 }
1552 per_nest_pmu_arr[pmu_index] = pmu_ptr;
1553 break;
1554 case IMC_DOMAIN_CORE:
1555 /* Update the pmu name */
1556 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1557 if (!pmu_ptr->pmu.name)
1558 goto err;
1559
1560 nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1561 pmu_ptr->mem_info = kcalloc(nr_cores, sizeof(struct imc_mem_info),
1562 GFP_KERNEL);
1563
1564 if (!pmu_ptr->mem_info)
1565 goto err;
1566
1567 core_imc_refc = kcalloc(nr_cores, sizeof(struct imc_pmu_ref),
1568 GFP_KERNEL);
1569
1570 if (!core_imc_refc) {
1571 kfree(pmu_ptr->mem_info);
1572 goto err;
1573 }
1574
1575 core_imc_pmu = pmu_ptr;
1576 break;
1577 case IMC_DOMAIN_THREAD:
1578 /* Update the pmu name */
1579 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1580 if (!pmu_ptr->pmu.name)
1581 goto err;
1582
1583 thread_imc_mem_size = pmu_ptr->counter_mem_size;
1584 for_each_online_cpu(cpu) {
1585 res = thread_imc_mem_alloc(cpu, pmu_ptr->counter_mem_size);
1586 if (res) {
1587 cleanup_all_thread_imc_memory();
1588 goto err;
1589 }
1590 }
1591
1592 thread_imc_pmu = pmu_ptr;
1593 break;
1594 case IMC_DOMAIN_TRACE:
1595 /* Update the pmu name */
1596 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1597 if (!pmu_ptr->pmu.name)
1598 return -ENOMEM;
1599
1600 nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1601 trace_imc_refc = kcalloc(nr_cores, sizeof(struct imc_pmu_ref),
1602 GFP_KERNEL);
1603 if (!trace_imc_refc)
1604 return -ENOMEM;
1605
1606 trace_imc_mem_size = pmu_ptr->counter_mem_size;
1607 for_each_online_cpu(cpu) {
1608 res = trace_imc_mem_alloc(cpu, trace_imc_mem_size);
1609 if (res) {
1610 cleanup_all_trace_imc_memory();
1611 goto err;
1612 }
1613 }
1614 break;
1615 default:
1616 return -EINVAL;
1617 }
1618
1619 return 0;
1620err:
1621 return res;
1622}
1623
1624/*
1625 * init_imc_pmu : Setup and register the IMC pmu device.
1626 *
1627 * @parent: Device tree unit node
1628 * @pmu_ptr: memory allocated for this pmu
1629 * @pmu_idx: Count of nest pmc registered
1630 *
1631 * init_imc_pmu() setup pmu cpumask and registers for a cpu hotplug callback.
1632 * Handles failure cases and accordingly frees memory.
1633 */
1634int init_imc_pmu(struct device_node *parent, struct imc_pmu *pmu_ptr, int pmu_idx)
1635{
1636 int ret;
1637
1638 ret = imc_mem_init(pmu_ptr, parent, pmu_idx);
1639 if (ret)
1640 goto err_free_mem;
1641
1642 switch (pmu_ptr->domain) {
1643 case IMC_DOMAIN_NEST:
1644 /*
1645 * Nest imc pmu need only one cpu per chip, we initialize the
1646 * cpumask for the first nest imc pmu and use the same for the
1647 * rest. To handle the cpuhotplug callback unregister, we track
1648 * the number of nest pmus in "nest_pmus".
1649 */
1650 mutex_lock(&nest_init_lock);
1651 if (nest_pmus == 0) {
1652 ret = init_nest_pmu_ref();
1653 if (ret) {
1654 mutex_unlock(&nest_init_lock);
1655 kfree(per_nest_pmu_arr);
1656 per_nest_pmu_arr = NULL;
1657 goto err_free_mem;
1658 }
1659 /* Register for cpu hotplug notification. */
1660 ret = nest_pmu_cpumask_init();
1661 if (ret) {
1662 mutex_unlock(&nest_init_lock);
1663 kfree(nest_imc_refc);
1664 kfree(per_nest_pmu_arr);
1665 per_nest_pmu_arr = NULL;
1666 goto err_free_mem;
1667 }
1668 }
1669 nest_pmus++;
1670 mutex_unlock(&nest_init_lock);
1671 break;
1672 case IMC_DOMAIN_CORE:
1673 ret = core_imc_pmu_cpumask_init();
1674 if (ret) {
1675 cleanup_all_core_imc_memory();
1676 goto err_free_mem;
1677 }
1678
1679 break;
1680 case IMC_DOMAIN_THREAD:
1681 ret = thread_imc_cpu_init();
1682 if (ret) {
1683 cleanup_all_thread_imc_memory();
1684 goto err_free_mem;
1685 }
1686
1687 break;
1688 case IMC_DOMAIN_TRACE:
1689 ret = trace_imc_cpu_init();
1690 if (ret) {
1691 cleanup_all_trace_imc_memory();
1692 goto err_free_mem;
1693 }
1694
1695 break;
1696 default:
1697 return -EINVAL; /* Unknown domain */
1698 }
1699
1700 ret = update_events_in_group(parent, pmu_ptr);
1701 if (ret)
1702 goto err_free_cpuhp_mem;
1703
1704 ret = update_pmu_ops(pmu_ptr);
1705 if (ret)
1706 goto err_free_cpuhp_mem;
1707
1708 ret = perf_pmu_register(&pmu_ptr->pmu, pmu_ptr->pmu.name, -1);
1709 if (ret)
1710 goto err_free_cpuhp_mem;
1711
1712 pr_debug("%s performance monitor hardware support registered\n",
1713 pmu_ptr->pmu.name);
1714
1715 return 0;
1716
1717err_free_cpuhp_mem:
1718 imc_common_cpuhp_mem_free(pmu_ptr);
1719err_free_mem:
1720 imc_common_mem_free(pmu_ptr);
1721 return ret;
1722}