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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *
4 * Common boot and setup code.
5 *
6 * Copyright (C) 2001 PPC64 Team, IBM Corp
7 */
8
9#include <linux/export.h>
10#include <linux/string.h>
11#include <linux/sched.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/reboot.h>
15#include <linux/delay.h>
16#include <linux/initrd.h>
17#include <linux/seq_file.h>
18#include <linux/ioport.h>
19#include <linux/console.h>
20#include <linux/utsname.h>
21#include <linux/tty.h>
22#include <linux/root_dev.h>
23#include <linux/notifier.h>
24#include <linux/cpu.h>
25#include <linux/unistd.h>
26#include <linux/serial.h>
27#include <linux/serial_8250.h>
28#include <linux/memblock.h>
29#include <linux/pci.h>
30#include <linux/lockdep.h>
31#include <linux/memory.h>
32#include <linux/nmi.h>
33#include <linux/pgtable.h>
34#include <linux/of.h>
35#include <linux/of_fdt.h>
36
37#include <asm/asm-prototypes.h>
38#include <asm/kvm_guest.h>
39#include <asm/io.h>
40#include <asm/kdump.h>
41#include <asm/processor.h>
42#include <asm/smp.h>
43#include <asm/elf.h>
44#include <asm/machdep.h>
45#include <asm/paca.h>
46#include <asm/time.h>
47#include <asm/cputable.h>
48#include <asm/dt_cpu_ftrs.h>
49#include <asm/sections.h>
50#include <asm/btext.h>
51#include <asm/nvram.h>
52#include <asm/setup.h>
53#include <asm/rtas.h>
54#include <asm/iommu.h>
55#include <asm/serial.h>
56#include <asm/cache.h>
57#include <asm/page.h>
58#include <asm/mmu.h>
59#include <asm/firmware.h>
60#include <asm/xmon.h>
61#include <asm/udbg.h>
62#include <asm/kexec.h>
63#include <asm/code-patching.h>
64#include <asm/ftrace.h>
65#include <asm/opal.h>
66#include <asm/cputhreads.h>
67#include <asm/hw_irq.h>
68#include <asm/feature-fixups.h>
69#include <asm/kup.h>
70#include <asm/early_ioremap.h>
71#include <asm/pgalloc.h>
72
73#include "setup.h"
74
75int spinning_secondaries;
76u64 ppc64_pft_size;
77
78struct ppc64_caches ppc64_caches = {
79 .l1d = {
80 .block_size = 0x40,
81 .log_block_size = 6,
82 },
83 .l1i = {
84 .block_size = 0x40,
85 .log_block_size = 6
86 },
87};
88EXPORT_SYMBOL_GPL(ppc64_caches);
89
90#if defined(CONFIG_PPC_BOOK3E_64) && defined(CONFIG_SMP)
91void __init setup_tlb_core_data(void)
92{
93 int cpu;
94
95 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
96
97 for_each_possible_cpu(cpu) {
98 int first = cpu_first_thread_sibling(cpu);
99
100 /*
101 * If we boot via kdump on a non-primary thread,
102 * make sure we point at the thread that actually
103 * set up this TLB.
104 */
105 if (cpu_first_thread_sibling(boot_cpuid) == first)
106 first = boot_cpuid;
107
108 paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd;
109
110 /*
111 * If we have threads, we need either tlbsrx.
112 * or e6500 tablewalk mode, or else TLB handlers
113 * will be racy and could produce duplicate entries.
114 * Should we panic instead?
115 */
116 WARN_ONCE(smt_enabled_at_boot >= 2 &&
117 book3e_htw_mode != PPC_HTW_E6500,
118 "%s: unsupported MMU configuration\n", __func__);
119 }
120}
121#endif
122
123#ifdef CONFIG_SMP
124
125static char *smt_enabled_cmdline;
126
127/* Look for ibm,smt-enabled OF option */
128void __init check_smt_enabled(void)
129{
130 struct device_node *dn;
131 const char *smt_option;
132
133 /* Default to enabling all threads */
134 smt_enabled_at_boot = threads_per_core;
135
136 /* Allow the command line to overrule the OF option */
137 if (smt_enabled_cmdline) {
138 if (!strcmp(smt_enabled_cmdline, "on"))
139 smt_enabled_at_boot = threads_per_core;
140 else if (!strcmp(smt_enabled_cmdline, "off"))
141 smt_enabled_at_boot = 0;
142 else {
143 int smt;
144 int rc;
145
146 rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
147 if (!rc)
148 smt_enabled_at_boot =
149 min(threads_per_core, smt);
150 }
151 } else {
152 dn = of_find_node_by_path("/options");
153 if (dn) {
154 smt_option = of_get_property(dn, "ibm,smt-enabled",
155 NULL);
156
157 if (smt_option) {
158 if (!strcmp(smt_option, "on"))
159 smt_enabled_at_boot = threads_per_core;
160 else if (!strcmp(smt_option, "off"))
161 smt_enabled_at_boot = 0;
162 }
163
164 of_node_put(dn);
165 }
166 }
167}
168
169/* Look for smt-enabled= cmdline option */
170static int __init early_smt_enabled(char *p)
171{
172 smt_enabled_cmdline = p;
173 return 0;
174}
175early_param("smt-enabled", early_smt_enabled);
176
177#endif /* CONFIG_SMP */
178
179/** Fix up paca fields required for the boot cpu */
180static void __init fixup_boot_paca(struct paca_struct *boot_paca)
181{
182 /* The boot cpu is started */
183 boot_paca->cpu_start = 1;
184#ifdef CONFIG_PPC_BOOK3S_64
185 /*
186 * Give the early boot machine check stack somewhere to use, use
187 * half of the init stack. This is a bit hacky but there should not be
188 * deep stack usage in early init so shouldn't overflow it or overwrite
189 * things.
190 */
191 boot_paca->mc_emergency_sp = (void *)&init_thread_union +
192 (THREAD_SIZE/2);
193#endif
194 /* Allow percpu accesses to work until we setup percpu data */
195 boot_paca->data_offset = 0;
196 /* Mark interrupts soft and hard disabled in PACA */
197 boot_paca->irq_soft_mask = IRQS_DISABLED;
198 boot_paca->irq_happened = PACA_IRQ_HARD_DIS;
199 WARN_ON(mfmsr() & MSR_EE);
200}
201
202static void __init configure_exceptions(void)
203{
204 /*
205 * Setup the trampolines from the lowmem exception vectors
206 * to the kdump kernel when not using a relocatable kernel.
207 */
208 setup_kdump_trampoline();
209
210 /* Under a PAPR hypervisor, we need hypercalls */
211 if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
212 /*
213 * - PR KVM does not support AIL mode interrupts in the host
214 * while a PR guest is running.
215 *
216 * - SCV system call interrupt vectors are only implemented for
217 * AIL mode interrupts.
218 *
219 * - On pseries, AIL mode can only be enabled and disabled
220 * system-wide so when a PR VM is created on a pseries host,
221 * all CPUs of the host are set to AIL=0 mode.
222 *
223 * - Therefore host CPUs must not execute scv while a PR VM
224 * exists.
225 *
226 * - SCV support can not be disabled dynamically because the
227 * feature is advertised to host userspace. Disabling the
228 * facility and emulating it would be possible but is not
229 * implemented.
230 *
231 * - So SCV support is blanket disabled if PR KVM could possibly
232 * run. That is, PR support compiled in, booting on pseries
233 * with hash MMU.
234 */
235 if (IS_ENABLED(CONFIG_KVM_BOOK3S_PR_POSSIBLE) && !radix_enabled()) {
236 init_task.thread.fscr &= ~FSCR_SCV;
237 cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_SCV;
238 }
239
240 /* Enable AIL if possible */
241 if (!pseries_enable_reloc_on_exc()) {
242 init_task.thread.fscr &= ~FSCR_SCV;
243 cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_SCV;
244 }
245
246 /*
247 * Tell the hypervisor that we want our exceptions to
248 * be taken in little endian mode.
249 *
250 * We don't call this for big endian as our calling convention
251 * makes us always enter in BE, and the call may fail under
252 * some circumstances with kdump.
253 */
254#ifdef __LITTLE_ENDIAN__
255 pseries_little_endian_exceptions();
256#endif
257 } else {
258 /* Set endian mode using OPAL */
259 if (firmware_has_feature(FW_FEATURE_OPAL))
260 opal_configure_cores();
261
262 /* AIL on native is done in cpu_ready_for_interrupts() */
263 }
264}
265
266static void cpu_ready_for_interrupts(void)
267{
268 /*
269 * Enable AIL if supported, and we are in hypervisor mode. This
270 * is called once for every processor.
271 *
272 * If we are not in hypervisor mode the job is done once for
273 * the whole partition in configure_exceptions().
274 */
275 if (cpu_has_feature(CPU_FTR_HVMODE)) {
276 unsigned long lpcr = mfspr(SPRN_LPCR);
277 unsigned long new_lpcr = lpcr;
278
279 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
280 /* P10 DD1 does not have HAIL */
281 if (pvr_version_is(PVR_POWER10) &&
282 (mfspr(SPRN_PVR) & 0xf00) == 0x100)
283 new_lpcr |= LPCR_AIL_3;
284 else
285 new_lpcr |= LPCR_HAIL;
286 } else if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
287 new_lpcr |= LPCR_AIL_3;
288 }
289
290 if (new_lpcr != lpcr)
291 mtspr(SPRN_LPCR, new_lpcr);
292 }
293
294 /*
295 * Set HFSCR:TM based on CPU features:
296 * In the special case of TM no suspend (P9N DD2.1), Linux is
297 * told TM is off via the dt-ftrs but told to (partially) use
298 * it via OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED. So HFSCR[TM]
299 * will be off from dt-ftrs but we need to turn it on for the
300 * no suspend case.
301 */
302 if (cpu_has_feature(CPU_FTR_HVMODE)) {
303 if (cpu_has_feature(CPU_FTR_TM_COMP))
304 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) | HFSCR_TM);
305 else
306 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
307 }
308
309 /* Set IR and DR in PACA MSR */
310 get_paca()->kernel_msr = MSR_KERNEL;
311}
312
313unsigned long spr_default_dscr = 0;
314
315static void __init record_spr_defaults(void)
316{
317 if (early_cpu_has_feature(CPU_FTR_DSCR))
318 spr_default_dscr = mfspr(SPRN_DSCR);
319}
320
321/*
322 * Early initialization entry point. This is called by head.S
323 * with MMU translation disabled. We rely on the "feature" of
324 * the CPU that ignores the top 2 bits of the address in real
325 * mode so we can access kernel globals normally provided we
326 * only toy with things in the RMO region. From here, we do
327 * some early parsing of the device-tree to setup out MEMBLOCK
328 * data structures, and allocate & initialize the hash table
329 * and segment tables so we can start running with translation
330 * enabled.
331 *
332 * It is this function which will call the probe() callback of
333 * the various platform types and copy the matching one to the
334 * global ppc_md structure. Your platform can eventually do
335 * some very early initializations from the probe() routine, but
336 * this is not recommended, be very careful as, for example, the
337 * device-tree is not accessible via normal means at this point.
338 */
339
340void __init early_setup(unsigned long dt_ptr)
341{
342 static __initdata struct paca_struct boot_paca;
343
344 /* -------- printk is _NOT_ safe to use here ! ------- */
345
346 /*
347 * Assume we're on cpu 0 for now.
348 *
349 * We need to load a PACA very early for a few reasons.
350 *
351 * The stack protector canary is stored in the paca, so as soon as we
352 * call any stack protected code we need r13 pointing somewhere valid.
353 *
354 * If we are using kcov it will call in_task() in its instrumentation,
355 * which relies on the current task from the PACA.
356 *
357 * dt_cpu_ftrs_init() calls into generic OF/fdt code, as well as
358 * printk(), which can trigger both stack protector and kcov.
359 *
360 * percpu variables and spin locks also use the paca.
361 *
362 * So set up a temporary paca. It will be replaced below once we know
363 * what CPU we are on.
364 */
365 initialise_paca(&boot_paca, 0);
366 fixup_boot_paca(&boot_paca);
367 WARN_ON(local_paca);
368 setup_paca(&boot_paca); /* install the paca into registers */
369
370 /* -------- printk is now safe to use ------- */
371
372 if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && (mfmsr() & MSR_HV))
373 enable_machine_check();
374
375 /* Try new device tree based feature discovery ... */
376 if (!dt_cpu_ftrs_init(__va(dt_ptr)))
377 /* Otherwise use the old style CPU table */
378 identify_cpu(0, mfspr(SPRN_PVR));
379
380 /* Enable early debugging if any specified (see udbg.h) */
381 udbg_early_init();
382
383 udbg_printf(" -> %s(), dt_ptr: 0x%lx\n", __func__, dt_ptr);
384
385 /*
386 * Do early initialization using the flattened device
387 * tree, such as retrieving the physical memory map or
388 * calculating/retrieving the hash table size, discover
389 * boot_cpuid and boot_cpu_hwid.
390 */
391 early_init_devtree(__va(dt_ptr));
392
393 allocate_paca_ptrs();
394 allocate_paca(boot_cpuid);
395 set_hard_smp_processor_id(boot_cpuid, boot_cpu_hwid);
396 fixup_boot_paca(paca_ptrs[boot_cpuid]);
397 setup_paca(paca_ptrs[boot_cpuid]); /* install the paca into registers */
398 // smp_processor_id() now reports boot_cpuid
399
400#ifdef CONFIG_SMP
401 task_thread_info(current)->cpu = boot_cpuid; // fix task_cpu(current)
402#endif
403
404 /*
405 * Configure exception handlers. This include setting up trampolines
406 * if needed, setting exception endian mode, etc...
407 */
408 configure_exceptions();
409
410 /*
411 * Configure Kernel Userspace Protection. This needs to happen before
412 * feature fixups for platforms that implement this using features.
413 */
414 setup_kup();
415
416 /* Apply all the dynamic patching */
417 apply_feature_fixups();
418 setup_feature_keys();
419
420 /* Initialize the hash table or TLB handling */
421 early_init_mmu();
422
423 early_ioremap_setup();
424
425 /*
426 * After firmware and early platform setup code has set things up,
427 * we note the SPR values for configurable control/performance
428 * registers, and use those as initial defaults.
429 */
430 record_spr_defaults();
431
432 /*
433 * At this point, we can let interrupts switch to virtual mode
434 * (the MMU has been setup), so adjust the MSR in the PACA to
435 * have IR and DR set and enable AIL if it exists
436 */
437 cpu_ready_for_interrupts();
438
439 /*
440 * We enable ftrace here, but since we only support DYNAMIC_FTRACE, it
441 * will only actually get enabled on the boot cpu much later once
442 * ftrace itself has been initialized.
443 */
444 this_cpu_enable_ftrace();
445
446 udbg_printf(" <- %s()\n", __func__);
447
448#ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
449 /*
450 * This needs to be done *last* (after the above udbg_printf() even)
451 *
452 * Right after we return from this function, we turn on the MMU
453 * which means the real-mode access trick that btext does will
454 * no longer work, it needs to switch to using a real MMU
455 * mapping. This call will ensure that it does
456 */
457 btext_map();
458#endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
459}
460
461#ifdef CONFIG_SMP
462void early_setup_secondary(void)
463{
464 /* Mark interrupts disabled in PACA */
465 irq_soft_mask_set(IRQS_DISABLED);
466
467 /* Initialize the hash table or TLB handling */
468 early_init_mmu_secondary();
469
470 /* Perform any KUP setup that is per-cpu */
471 setup_kup();
472
473 /*
474 * At this point, we can let interrupts switch to virtual mode
475 * (the MMU has been setup), so adjust the MSR in the PACA to
476 * have IR and DR set.
477 */
478 cpu_ready_for_interrupts();
479}
480
481#endif /* CONFIG_SMP */
482
483void __noreturn panic_smp_self_stop(void)
484{
485 hard_irq_disable();
486 spin_begin();
487 while (1)
488 spin_cpu_relax();
489}
490
491#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
492static bool use_spinloop(void)
493{
494 if (IS_ENABLED(CONFIG_PPC_BOOK3S)) {
495 /*
496 * See comments in head_64.S -- not all platforms insert
497 * secondaries at __secondary_hold and wait at the spin
498 * loop.
499 */
500 if (firmware_has_feature(FW_FEATURE_OPAL))
501 return false;
502 return true;
503 }
504
505 /*
506 * When book3e boots from kexec, the ePAPR spin table does
507 * not get used.
508 */
509 return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
510}
511
512void smp_release_cpus(void)
513{
514 unsigned long *ptr;
515 int i;
516
517 if (!use_spinloop())
518 return;
519
520 /* All secondary cpus are spinning on a common spinloop, release them
521 * all now so they can start to spin on their individual paca
522 * spinloops. For non SMP kernels, the secondary cpus never get out
523 * of the common spinloop.
524 */
525
526 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
527 - PHYSICAL_START);
528 *ptr = ppc_function_entry(generic_secondary_smp_init);
529
530 /* And wait a bit for them to catch up */
531 for (i = 0; i < 100000; i++) {
532 mb();
533 HMT_low();
534 if (spinning_secondaries == 0)
535 break;
536 udelay(1);
537 }
538 pr_debug("spinning_secondaries = %d\n", spinning_secondaries);
539}
540#endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */
541
542/*
543 * Initialize some remaining members of the ppc64_caches and systemcfg
544 * structures
545 * (at least until we get rid of them completely). This is mostly some
546 * cache informations about the CPU that will be used by cache flush
547 * routines and/or provided to userland
548 */
549
550static void __init init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize,
551 u32 bsize, u32 sets)
552{
553 info->size = size;
554 info->sets = sets;
555 info->line_size = lsize;
556 info->block_size = bsize;
557 info->log_block_size = __ilog2(bsize);
558 if (bsize)
559 info->blocks_per_page = PAGE_SIZE / bsize;
560 else
561 info->blocks_per_page = 0;
562
563 if (sets == 0)
564 info->assoc = 0xffff;
565 else
566 info->assoc = size / (sets * lsize);
567}
568
569static bool __init parse_cache_info(struct device_node *np,
570 bool icache,
571 struct ppc_cache_info *info)
572{
573 static const char *ipropnames[] __initdata = {
574 "i-cache-size",
575 "i-cache-sets",
576 "i-cache-block-size",
577 "i-cache-line-size",
578 };
579 static const char *dpropnames[] __initdata = {
580 "d-cache-size",
581 "d-cache-sets",
582 "d-cache-block-size",
583 "d-cache-line-size",
584 };
585 const char **propnames = icache ? ipropnames : dpropnames;
586 const __be32 *sizep, *lsizep, *bsizep, *setsp;
587 u32 size, lsize, bsize, sets;
588 bool success = true;
589
590 size = 0;
591 sets = -1u;
592 lsize = bsize = cur_cpu_spec->dcache_bsize;
593 sizep = of_get_property(np, propnames[0], NULL);
594 if (sizep != NULL)
595 size = be32_to_cpu(*sizep);
596 setsp = of_get_property(np, propnames[1], NULL);
597 if (setsp != NULL)
598 sets = be32_to_cpu(*setsp);
599 bsizep = of_get_property(np, propnames[2], NULL);
600 lsizep = of_get_property(np, propnames[3], NULL);
601 if (bsizep == NULL)
602 bsizep = lsizep;
603 if (lsizep == NULL)
604 lsizep = bsizep;
605 if (lsizep != NULL)
606 lsize = be32_to_cpu(*lsizep);
607 if (bsizep != NULL)
608 bsize = be32_to_cpu(*bsizep);
609 if (sizep == NULL || bsizep == NULL || lsizep == NULL)
610 success = false;
611
612 /*
613 * OF is weird .. it represents fully associative caches
614 * as "1 way" which doesn't make much sense and doesn't
615 * leave room for direct mapped. We'll assume that 0
616 * in OF means direct mapped for that reason.
617 */
618 if (sets == 1)
619 sets = 0;
620 else if (sets == 0)
621 sets = 1;
622
623 init_cache_info(info, size, lsize, bsize, sets);
624
625 return success;
626}
627
628void __init initialize_cache_info(void)
629{
630 struct device_node *cpu = NULL, *l2, *l3 = NULL;
631 u32 pvr;
632
633 /*
634 * All shipping POWER8 machines have a firmware bug that
635 * puts incorrect information in the device-tree. This will
636 * be (hopefully) fixed for future chips but for now hard
637 * code the values if we are running on one of these
638 */
639 pvr = PVR_VER(mfspr(SPRN_PVR));
640 if (pvr == PVR_POWER8 || pvr == PVR_POWER8E ||
641 pvr == PVR_POWER8NVL) {
642 /* size lsize blk sets */
643 init_cache_info(&ppc64_caches.l1i, 0x8000, 128, 128, 32);
644 init_cache_info(&ppc64_caches.l1d, 0x10000, 128, 128, 64);
645 init_cache_info(&ppc64_caches.l2, 0x80000, 128, 0, 512);
646 init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192);
647 } else
648 cpu = of_find_node_by_type(NULL, "cpu");
649
650 /*
651 * We're assuming *all* of the CPUs have the same
652 * d-cache and i-cache sizes... -Peter
653 */
654 if (cpu) {
655 if (!parse_cache_info(cpu, false, &ppc64_caches.l1d))
656 pr_warn("Argh, can't find dcache properties !\n");
657
658 if (!parse_cache_info(cpu, true, &ppc64_caches.l1i))
659 pr_warn("Argh, can't find icache properties !\n");
660
661 /*
662 * Try to find the L2 and L3 if any. Assume they are
663 * unified and use the D-side properties.
664 */
665 l2 = of_find_next_cache_node(cpu);
666 of_node_put(cpu);
667 if (l2) {
668 parse_cache_info(l2, false, &ppc64_caches.l2);
669 l3 = of_find_next_cache_node(l2);
670 of_node_put(l2);
671 }
672 if (l3) {
673 parse_cache_info(l3, false, &ppc64_caches.l3);
674 of_node_put(l3);
675 }
676 }
677
678 /* For use by binfmt_elf */
679 dcache_bsize = ppc64_caches.l1d.block_size;
680 icache_bsize = ppc64_caches.l1i.block_size;
681
682 cur_cpu_spec->dcache_bsize = dcache_bsize;
683 cur_cpu_spec->icache_bsize = icache_bsize;
684}
685
686/*
687 * This returns the limit below which memory accesses to the linear
688 * mapping are guarnateed not to cause an architectural exception (e.g.,
689 * TLB or SLB miss fault).
690 *
691 * This is used to allocate PACAs and various interrupt stacks that
692 * that are accessed early in interrupt handlers that must not cause
693 * re-entrant interrupts.
694 */
695__init u64 ppc64_bolted_size(void)
696{
697#ifdef CONFIG_PPC_BOOK3E_64
698 /* Freescale BookE bolts the entire linear mapping */
699 /* XXX: BookE ppc64_rma_limit setup seems to disagree? */
700 if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E))
701 return linear_map_top;
702 /* Other BookE, we assume the first GB is bolted */
703 return 1ul << 30;
704#else
705 /* BookS radix, does not take faults on linear mapping */
706 if (early_radix_enabled())
707 return ULONG_MAX;
708
709 /* BookS hash, the first segment is bolted */
710 if (early_mmu_has_feature(MMU_FTR_1T_SEGMENT))
711 return 1UL << SID_SHIFT_1T;
712 return 1UL << SID_SHIFT;
713#endif
714}
715
716static void *__init alloc_stack(unsigned long limit, int cpu)
717{
718 void *ptr;
719
720 BUILD_BUG_ON(STACK_INT_FRAME_SIZE % 16);
721
722 ptr = memblock_alloc_try_nid(THREAD_SIZE, THREAD_ALIGN,
723 MEMBLOCK_LOW_LIMIT, limit,
724 early_cpu_to_node(cpu));
725 if (!ptr)
726 panic("cannot allocate stacks");
727
728 return ptr;
729}
730
731void __init irqstack_early_init(void)
732{
733 u64 limit = ppc64_bolted_size();
734 unsigned int i;
735
736 /*
737 * Interrupt stacks must be in the first segment since we
738 * cannot afford to take SLB misses on them. They are not
739 * accessed in realmode.
740 */
741 for_each_possible_cpu(i) {
742 softirq_ctx[i] = alloc_stack(limit, i);
743 hardirq_ctx[i] = alloc_stack(limit, i);
744 }
745}
746
747#ifdef CONFIG_PPC_BOOK3E_64
748void __init exc_lvl_early_init(void)
749{
750 unsigned int i;
751
752 for_each_possible_cpu(i) {
753 void *sp;
754
755 sp = alloc_stack(ULONG_MAX, i);
756 critirq_ctx[i] = sp;
757 paca_ptrs[i]->crit_kstack = sp + THREAD_SIZE;
758
759 sp = alloc_stack(ULONG_MAX, i);
760 dbgirq_ctx[i] = sp;
761 paca_ptrs[i]->dbg_kstack = sp + THREAD_SIZE;
762
763 sp = alloc_stack(ULONG_MAX, i);
764 mcheckirq_ctx[i] = sp;
765 paca_ptrs[i]->mc_kstack = sp + THREAD_SIZE;
766 }
767
768 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
769 patch_exception(0x040, exc_debug_debug_book3e);
770}
771#endif
772
773/*
774 * Stack space used when we detect a bad kernel stack pointer, and
775 * early in SMP boots before relocation is enabled. Exclusive emergency
776 * stack for machine checks.
777 */
778void __init emergency_stack_init(void)
779{
780 u64 limit, mce_limit;
781 unsigned int i;
782
783 /*
784 * Emergency stacks must be under 256MB, we cannot afford to take
785 * SLB misses on them. The ABI also requires them to be 128-byte
786 * aligned.
787 *
788 * Since we use these as temporary stacks during secondary CPU
789 * bringup, machine check, system reset, and HMI, we need to get
790 * at them in real mode. This means they must also be within the RMO
791 * region.
792 *
793 * The IRQ stacks allocated elsewhere in this file are zeroed and
794 * initialized in kernel/irq.c. These are initialized here in order
795 * to have emergency stacks available as early as possible.
796 */
797 limit = mce_limit = min(ppc64_bolted_size(), ppc64_rma_size);
798
799 /*
800 * Machine check on pseries calls rtas, but can't use the static
801 * rtas_args due to a machine check hitting while the lock is held.
802 * rtas args have to be under 4GB, so the machine check stack is
803 * limited to 4GB so args can be put on stack.
804 */
805 if (firmware_has_feature(FW_FEATURE_LPAR) && mce_limit > SZ_4G)
806 mce_limit = SZ_4G;
807
808 for_each_possible_cpu(i) {
809 paca_ptrs[i]->emergency_sp = alloc_stack(limit, i) + THREAD_SIZE;
810
811#ifdef CONFIG_PPC_BOOK3S_64
812 /* emergency stack for NMI exception handling. */
813 paca_ptrs[i]->nmi_emergency_sp = alloc_stack(limit, i) + THREAD_SIZE;
814
815 /* emergency stack for machine check exception handling. */
816 paca_ptrs[i]->mc_emergency_sp = alloc_stack(mce_limit, i) + THREAD_SIZE;
817#endif
818 }
819}
820
821#ifdef CONFIG_SMP
822static int pcpu_cpu_distance(unsigned int from, unsigned int to)
823{
824 if (early_cpu_to_node(from) == early_cpu_to_node(to))
825 return LOCAL_DISTANCE;
826 else
827 return REMOTE_DISTANCE;
828}
829
830static __init int pcpu_cpu_to_node(int cpu)
831{
832 return early_cpu_to_node(cpu);
833}
834
835unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
836EXPORT_SYMBOL(__per_cpu_offset);
837
838void __init setup_per_cpu_areas(void)
839{
840 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
841 size_t atom_size;
842 unsigned long delta;
843 unsigned int cpu;
844 int rc = -EINVAL;
845
846 /*
847 * BookE and BookS radix are historical values and should be revisited.
848 */
849 if (IS_ENABLED(CONFIG_PPC_BOOK3E_64)) {
850 atom_size = SZ_1M;
851 } else if (radix_enabled()) {
852 atom_size = PAGE_SIZE;
853 } else if (IS_ENABLED(CONFIG_PPC_64S_HASH_MMU)) {
854 /*
855 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
856 * to group units. For larger mappings, use 1M atom which
857 * should be large enough to contain a number of units.
858 */
859 if (mmu_linear_psize == MMU_PAGE_4K)
860 atom_size = PAGE_SIZE;
861 else
862 atom_size = SZ_1M;
863 }
864
865 if (pcpu_chosen_fc != PCPU_FC_PAGE) {
866 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
867 pcpu_cpu_to_node);
868 if (rc)
869 pr_warn("PERCPU: %s allocator failed (%d), "
870 "falling back to page size\n",
871 pcpu_fc_names[pcpu_chosen_fc], rc);
872 }
873
874 if (rc < 0)
875 rc = pcpu_page_first_chunk(0, pcpu_cpu_to_node);
876 if (rc < 0)
877 panic("cannot initialize percpu area (err=%d)", rc);
878
879 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
880 for_each_possible_cpu(cpu) {
881 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
882 paca_ptrs[cpu]->data_offset = __per_cpu_offset[cpu];
883 }
884}
885#endif
886
887#ifdef CONFIG_MEMORY_HOTPLUG
888unsigned long memory_block_size_bytes(void)
889{
890 if (ppc_md.memory_block_size)
891 return ppc_md.memory_block_size();
892
893 return MIN_MEMORY_BLOCK_SIZE;
894}
895#endif
896
897#if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
898struct ppc_pci_io ppc_pci_io;
899EXPORT_SYMBOL(ppc_pci_io);
900#endif
901
902#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
903u64 hw_nmi_get_sample_period(int watchdog_thresh)
904{
905 return ppc_proc_freq * watchdog_thresh;
906}
907#endif
908
909/*
910 * The perf based hardlockup detector breaks PMU event based branches, so
911 * disable it by default. Book3S has a soft-nmi hardlockup detector based
912 * on the decrementer interrupt, so it does not suffer from this problem.
913 *
914 * It is likely to get false positives in KVM guests, so disable it there
915 * by default too. PowerVM will not stop or arbitrarily oversubscribe
916 * CPUs, but give a minimum regular allotment even with SPLPAR, so enable
917 * the detector for non-KVM guests, assume PowerVM.
918 */
919static int __init disable_hardlockup_detector(void)
920{
921#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
922 hardlockup_detector_disable();
923#else
924 if (firmware_has_feature(FW_FEATURE_LPAR)) {
925 if (is_kvm_guest())
926 hardlockup_detector_disable();
927 }
928#endif
929
930 return 0;
931}
932early_initcall(disable_hardlockup_detector);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *
4 * Common boot and setup code.
5 *
6 * Copyright (C) 2001 PPC64 Team, IBM Corp
7 */
8
9#include <linux/export.h>
10#include <linux/string.h>
11#include <linux/sched.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/reboot.h>
15#include <linux/delay.h>
16#include <linux/initrd.h>
17#include <linux/seq_file.h>
18#include <linux/ioport.h>
19#include <linux/console.h>
20#include <linux/utsname.h>
21#include <linux/tty.h>
22#include <linux/root_dev.h>
23#include <linux/notifier.h>
24#include <linux/cpu.h>
25#include <linux/unistd.h>
26#include <linux/serial.h>
27#include <linux/serial_8250.h>
28#include <linux/memblock.h>
29#include <linux/pci.h>
30#include <linux/lockdep.h>
31#include <linux/memory.h>
32#include <linux/nmi.h>
33
34#include <asm/debugfs.h>
35#include <asm/io.h>
36#include <asm/kdump.h>
37#include <asm/prom.h>
38#include <asm/processor.h>
39#include <asm/pgtable.h>
40#include <asm/smp.h>
41#include <asm/elf.h>
42#include <asm/machdep.h>
43#include <asm/paca.h>
44#include <asm/time.h>
45#include <asm/cputable.h>
46#include <asm/dt_cpu_ftrs.h>
47#include <asm/sections.h>
48#include <asm/btext.h>
49#include <asm/nvram.h>
50#include <asm/setup.h>
51#include <asm/rtas.h>
52#include <asm/iommu.h>
53#include <asm/serial.h>
54#include <asm/cache.h>
55#include <asm/page.h>
56#include <asm/mmu.h>
57#include <asm/firmware.h>
58#include <asm/xmon.h>
59#include <asm/udbg.h>
60#include <asm/kexec.h>
61#include <asm/code-patching.h>
62#include <asm/livepatch.h>
63#include <asm/opal.h>
64#include <asm/cputhreads.h>
65#include <asm/hw_irq.h>
66#include <asm/feature-fixups.h>
67#include <asm/kup.h>
68
69#include "setup.h"
70
71#ifdef DEBUG
72#define DBG(fmt...) udbg_printf(fmt)
73#else
74#define DBG(fmt...)
75#endif
76
77int spinning_secondaries;
78u64 ppc64_pft_size;
79
80struct ppc64_caches ppc64_caches = {
81 .l1d = {
82 .block_size = 0x40,
83 .log_block_size = 6,
84 },
85 .l1i = {
86 .block_size = 0x40,
87 .log_block_size = 6
88 },
89};
90EXPORT_SYMBOL_GPL(ppc64_caches);
91
92#if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
93void __init setup_tlb_core_data(void)
94{
95 int cpu;
96
97 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
98
99 for_each_possible_cpu(cpu) {
100 int first = cpu_first_thread_sibling(cpu);
101
102 /*
103 * If we boot via kdump on a non-primary thread,
104 * make sure we point at the thread that actually
105 * set up this TLB.
106 */
107 if (cpu_first_thread_sibling(boot_cpuid) == first)
108 first = boot_cpuid;
109
110 paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd;
111
112 /*
113 * If we have threads, we need either tlbsrx.
114 * or e6500 tablewalk mode, or else TLB handlers
115 * will be racy and could produce duplicate entries.
116 * Should we panic instead?
117 */
118 WARN_ONCE(smt_enabled_at_boot >= 2 &&
119 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
120 book3e_htw_mode != PPC_HTW_E6500,
121 "%s: unsupported MMU configuration\n", __func__);
122 }
123}
124#endif
125
126#ifdef CONFIG_SMP
127
128static char *smt_enabled_cmdline;
129
130/* Look for ibm,smt-enabled OF option */
131void __init check_smt_enabled(void)
132{
133 struct device_node *dn;
134 const char *smt_option;
135
136 /* Default to enabling all threads */
137 smt_enabled_at_boot = threads_per_core;
138
139 /* Allow the command line to overrule the OF option */
140 if (smt_enabled_cmdline) {
141 if (!strcmp(smt_enabled_cmdline, "on"))
142 smt_enabled_at_boot = threads_per_core;
143 else if (!strcmp(smt_enabled_cmdline, "off"))
144 smt_enabled_at_boot = 0;
145 else {
146 int smt;
147 int rc;
148
149 rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
150 if (!rc)
151 smt_enabled_at_boot =
152 min(threads_per_core, smt);
153 }
154 } else {
155 dn = of_find_node_by_path("/options");
156 if (dn) {
157 smt_option = of_get_property(dn, "ibm,smt-enabled",
158 NULL);
159
160 if (smt_option) {
161 if (!strcmp(smt_option, "on"))
162 smt_enabled_at_boot = threads_per_core;
163 else if (!strcmp(smt_option, "off"))
164 smt_enabled_at_boot = 0;
165 }
166
167 of_node_put(dn);
168 }
169 }
170}
171
172/* Look for smt-enabled= cmdline option */
173static int __init early_smt_enabled(char *p)
174{
175 smt_enabled_cmdline = p;
176 return 0;
177}
178early_param("smt-enabled", early_smt_enabled);
179
180#endif /* CONFIG_SMP */
181
182/** Fix up paca fields required for the boot cpu */
183static void __init fixup_boot_paca(void)
184{
185 /* The boot cpu is started */
186 get_paca()->cpu_start = 1;
187 /* Allow percpu accesses to work until we setup percpu data */
188 get_paca()->data_offset = 0;
189 /* Mark interrupts disabled in PACA */
190 irq_soft_mask_set(IRQS_DISABLED);
191}
192
193static void __init configure_exceptions(void)
194{
195 /*
196 * Setup the trampolines from the lowmem exception vectors
197 * to the kdump kernel when not using a relocatable kernel.
198 */
199 setup_kdump_trampoline();
200
201 /* Under a PAPR hypervisor, we need hypercalls */
202 if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
203 /* Enable AIL if possible */
204 pseries_enable_reloc_on_exc();
205
206 /*
207 * Tell the hypervisor that we want our exceptions to
208 * be taken in little endian mode.
209 *
210 * We don't call this for big endian as our calling convention
211 * makes us always enter in BE, and the call may fail under
212 * some circumstances with kdump.
213 */
214#ifdef __LITTLE_ENDIAN__
215 pseries_little_endian_exceptions();
216#endif
217 } else {
218 /* Set endian mode using OPAL */
219 if (firmware_has_feature(FW_FEATURE_OPAL))
220 opal_configure_cores();
221
222 /* AIL on native is done in cpu_ready_for_interrupts() */
223 }
224}
225
226static void cpu_ready_for_interrupts(void)
227{
228 /*
229 * Enable AIL if supported, and we are in hypervisor mode. This
230 * is called once for every processor.
231 *
232 * If we are not in hypervisor mode the job is done once for
233 * the whole partition in configure_exceptions().
234 */
235 if (cpu_has_feature(CPU_FTR_HVMODE) &&
236 cpu_has_feature(CPU_FTR_ARCH_207S)) {
237 unsigned long lpcr = mfspr(SPRN_LPCR);
238 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
239 }
240
241 /*
242 * Set HFSCR:TM based on CPU features:
243 * In the special case of TM no suspend (P9N DD2.1), Linux is
244 * told TM is off via the dt-ftrs but told to (partially) use
245 * it via OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED. So HFSCR[TM]
246 * will be off from dt-ftrs but we need to turn it on for the
247 * no suspend case.
248 */
249 if (cpu_has_feature(CPU_FTR_HVMODE)) {
250 if (cpu_has_feature(CPU_FTR_TM_COMP))
251 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) | HFSCR_TM);
252 else
253 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
254 }
255
256 /* Set IR and DR in PACA MSR */
257 get_paca()->kernel_msr = MSR_KERNEL;
258}
259
260unsigned long spr_default_dscr = 0;
261
262void __init record_spr_defaults(void)
263{
264 if (early_cpu_has_feature(CPU_FTR_DSCR))
265 spr_default_dscr = mfspr(SPRN_DSCR);
266}
267
268/*
269 * Early initialization entry point. This is called by head.S
270 * with MMU translation disabled. We rely on the "feature" of
271 * the CPU that ignores the top 2 bits of the address in real
272 * mode so we can access kernel globals normally provided we
273 * only toy with things in the RMO region. From here, we do
274 * some early parsing of the device-tree to setup out MEMBLOCK
275 * data structures, and allocate & initialize the hash table
276 * and segment tables so we can start running with translation
277 * enabled.
278 *
279 * It is this function which will call the probe() callback of
280 * the various platform types and copy the matching one to the
281 * global ppc_md structure. Your platform can eventually do
282 * some very early initializations from the probe() routine, but
283 * this is not recommended, be very careful as, for example, the
284 * device-tree is not accessible via normal means at this point.
285 */
286
287void __init early_setup(unsigned long dt_ptr)
288{
289 static __initdata struct paca_struct boot_paca;
290
291 /* -------- printk is _NOT_ safe to use here ! ------- */
292
293 /* Try new device tree based feature discovery ... */
294 if (!dt_cpu_ftrs_init(__va(dt_ptr)))
295 /* Otherwise use the old style CPU table */
296 identify_cpu(0, mfspr(SPRN_PVR));
297
298 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
299 initialise_paca(&boot_paca, 0);
300 setup_paca(&boot_paca);
301 fixup_boot_paca();
302
303 /* -------- printk is now safe to use ------- */
304
305 /* Enable early debugging if any specified (see udbg.h) */
306 udbg_early_init();
307
308 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
309
310 /*
311 * Do early initialization using the flattened device
312 * tree, such as retrieving the physical memory map or
313 * calculating/retrieving the hash table size.
314 */
315 early_init_devtree(__va(dt_ptr));
316
317 /* Now we know the logical id of our boot cpu, setup the paca. */
318 if (boot_cpuid != 0) {
319 /* Poison paca_ptrs[0] again if it's not the boot cpu */
320 memset(&paca_ptrs[0], 0x88, sizeof(paca_ptrs[0]));
321 }
322 setup_paca(paca_ptrs[boot_cpuid]);
323 fixup_boot_paca();
324
325 /*
326 * Configure exception handlers. This include setting up trampolines
327 * if needed, setting exception endian mode, etc...
328 */
329 configure_exceptions();
330
331 /*
332 * Configure Kernel Userspace Protection. This needs to happen before
333 * feature fixups for platforms that implement this using features.
334 */
335 setup_kup();
336
337 /* Apply all the dynamic patching */
338 apply_feature_fixups();
339 setup_feature_keys();
340
341 /* Initialize the hash table or TLB handling */
342 early_init_mmu();
343
344 /*
345 * After firmware and early platform setup code has set things up,
346 * we note the SPR values for configurable control/performance
347 * registers, and use those as initial defaults.
348 */
349 record_spr_defaults();
350
351 /*
352 * At this point, we can let interrupts switch to virtual mode
353 * (the MMU has been setup), so adjust the MSR in the PACA to
354 * have IR and DR set and enable AIL if it exists
355 */
356 cpu_ready_for_interrupts();
357
358 /*
359 * We enable ftrace here, but since we only support DYNAMIC_FTRACE, it
360 * will only actually get enabled on the boot cpu much later once
361 * ftrace itself has been initialized.
362 */
363 this_cpu_enable_ftrace();
364
365 DBG(" <- early_setup()\n");
366
367#ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
368 /*
369 * This needs to be done *last* (after the above DBG() even)
370 *
371 * Right after we return from this function, we turn on the MMU
372 * which means the real-mode access trick that btext does will
373 * no longer work, it needs to switch to using a real MMU
374 * mapping. This call will ensure that it does
375 */
376 btext_map();
377#endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
378}
379
380#ifdef CONFIG_SMP
381void early_setup_secondary(void)
382{
383 /* Mark interrupts disabled in PACA */
384 irq_soft_mask_set(IRQS_DISABLED);
385
386 /* Initialize the hash table or TLB handling */
387 early_init_mmu_secondary();
388
389 /* Perform any KUP setup that is per-cpu */
390 setup_kup();
391
392 /*
393 * At this point, we can let interrupts switch to virtual mode
394 * (the MMU has been setup), so adjust the MSR in the PACA to
395 * have IR and DR set.
396 */
397 cpu_ready_for_interrupts();
398}
399
400#endif /* CONFIG_SMP */
401
402void panic_smp_self_stop(void)
403{
404 hard_irq_disable();
405 spin_begin();
406 while (1)
407 spin_cpu_relax();
408}
409
410#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
411static bool use_spinloop(void)
412{
413 if (IS_ENABLED(CONFIG_PPC_BOOK3S)) {
414 /*
415 * See comments in head_64.S -- not all platforms insert
416 * secondaries at __secondary_hold and wait at the spin
417 * loop.
418 */
419 if (firmware_has_feature(FW_FEATURE_OPAL))
420 return false;
421 return true;
422 }
423
424 /*
425 * When book3e boots from kexec, the ePAPR spin table does
426 * not get used.
427 */
428 return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
429}
430
431void smp_release_cpus(void)
432{
433 unsigned long *ptr;
434 int i;
435
436 if (!use_spinloop())
437 return;
438
439 DBG(" -> smp_release_cpus()\n");
440
441 /* All secondary cpus are spinning on a common spinloop, release them
442 * all now so they can start to spin on their individual paca
443 * spinloops. For non SMP kernels, the secondary cpus never get out
444 * of the common spinloop.
445 */
446
447 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
448 - PHYSICAL_START);
449 *ptr = ppc_function_entry(generic_secondary_smp_init);
450
451 /* And wait a bit for them to catch up */
452 for (i = 0; i < 100000; i++) {
453 mb();
454 HMT_low();
455 if (spinning_secondaries == 0)
456 break;
457 udelay(1);
458 }
459 DBG("spinning_secondaries = %d\n", spinning_secondaries);
460
461 DBG(" <- smp_release_cpus()\n");
462}
463#endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */
464
465/*
466 * Initialize some remaining members of the ppc64_caches and systemcfg
467 * structures
468 * (at least until we get rid of them completely). This is mostly some
469 * cache informations about the CPU that will be used by cache flush
470 * routines and/or provided to userland
471 */
472
473static void init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize,
474 u32 bsize, u32 sets)
475{
476 info->size = size;
477 info->sets = sets;
478 info->line_size = lsize;
479 info->block_size = bsize;
480 info->log_block_size = __ilog2(bsize);
481 if (bsize)
482 info->blocks_per_page = PAGE_SIZE / bsize;
483 else
484 info->blocks_per_page = 0;
485
486 if (sets == 0)
487 info->assoc = 0xffff;
488 else
489 info->assoc = size / (sets * lsize);
490}
491
492static bool __init parse_cache_info(struct device_node *np,
493 bool icache,
494 struct ppc_cache_info *info)
495{
496 static const char *ipropnames[] __initdata = {
497 "i-cache-size",
498 "i-cache-sets",
499 "i-cache-block-size",
500 "i-cache-line-size",
501 };
502 static const char *dpropnames[] __initdata = {
503 "d-cache-size",
504 "d-cache-sets",
505 "d-cache-block-size",
506 "d-cache-line-size",
507 };
508 const char **propnames = icache ? ipropnames : dpropnames;
509 const __be32 *sizep, *lsizep, *bsizep, *setsp;
510 u32 size, lsize, bsize, sets;
511 bool success = true;
512
513 size = 0;
514 sets = -1u;
515 lsize = bsize = cur_cpu_spec->dcache_bsize;
516 sizep = of_get_property(np, propnames[0], NULL);
517 if (sizep != NULL)
518 size = be32_to_cpu(*sizep);
519 setsp = of_get_property(np, propnames[1], NULL);
520 if (setsp != NULL)
521 sets = be32_to_cpu(*setsp);
522 bsizep = of_get_property(np, propnames[2], NULL);
523 lsizep = of_get_property(np, propnames[3], NULL);
524 if (bsizep == NULL)
525 bsizep = lsizep;
526 if (lsizep != NULL)
527 lsize = be32_to_cpu(*lsizep);
528 if (bsizep != NULL)
529 bsize = be32_to_cpu(*bsizep);
530 if (sizep == NULL || bsizep == NULL || lsizep == NULL)
531 success = false;
532
533 /*
534 * OF is weird .. it represents fully associative caches
535 * as "1 way" which doesn't make much sense and doesn't
536 * leave room for direct mapped. We'll assume that 0
537 * in OF means direct mapped for that reason.
538 */
539 if (sets == 1)
540 sets = 0;
541 else if (sets == 0)
542 sets = 1;
543
544 init_cache_info(info, size, lsize, bsize, sets);
545
546 return success;
547}
548
549void __init initialize_cache_info(void)
550{
551 struct device_node *cpu = NULL, *l2, *l3 = NULL;
552 u32 pvr;
553
554 DBG(" -> initialize_cache_info()\n");
555
556 /*
557 * All shipping POWER8 machines have a firmware bug that
558 * puts incorrect information in the device-tree. This will
559 * be (hopefully) fixed for future chips but for now hard
560 * code the values if we are running on one of these
561 */
562 pvr = PVR_VER(mfspr(SPRN_PVR));
563 if (pvr == PVR_POWER8 || pvr == PVR_POWER8E ||
564 pvr == PVR_POWER8NVL) {
565 /* size lsize blk sets */
566 init_cache_info(&ppc64_caches.l1i, 0x8000, 128, 128, 32);
567 init_cache_info(&ppc64_caches.l1d, 0x10000, 128, 128, 64);
568 init_cache_info(&ppc64_caches.l2, 0x80000, 128, 0, 512);
569 init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192);
570 } else
571 cpu = of_find_node_by_type(NULL, "cpu");
572
573 /*
574 * We're assuming *all* of the CPUs have the same
575 * d-cache and i-cache sizes... -Peter
576 */
577 if (cpu) {
578 if (!parse_cache_info(cpu, false, &ppc64_caches.l1d))
579 DBG("Argh, can't find dcache properties !\n");
580
581 if (!parse_cache_info(cpu, true, &ppc64_caches.l1i))
582 DBG("Argh, can't find icache properties !\n");
583
584 /*
585 * Try to find the L2 and L3 if any. Assume they are
586 * unified and use the D-side properties.
587 */
588 l2 = of_find_next_cache_node(cpu);
589 of_node_put(cpu);
590 if (l2) {
591 parse_cache_info(l2, false, &ppc64_caches.l2);
592 l3 = of_find_next_cache_node(l2);
593 of_node_put(l2);
594 }
595 if (l3) {
596 parse_cache_info(l3, false, &ppc64_caches.l3);
597 of_node_put(l3);
598 }
599 }
600
601 /* For use by binfmt_elf */
602 dcache_bsize = ppc64_caches.l1d.block_size;
603 icache_bsize = ppc64_caches.l1i.block_size;
604
605 cur_cpu_spec->dcache_bsize = dcache_bsize;
606 cur_cpu_spec->icache_bsize = icache_bsize;
607
608 DBG(" <- initialize_cache_info()\n");
609}
610
611/*
612 * This returns the limit below which memory accesses to the linear
613 * mapping are guarnateed not to cause an architectural exception (e.g.,
614 * TLB or SLB miss fault).
615 *
616 * This is used to allocate PACAs and various interrupt stacks that
617 * that are accessed early in interrupt handlers that must not cause
618 * re-entrant interrupts.
619 */
620__init u64 ppc64_bolted_size(void)
621{
622#ifdef CONFIG_PPC_BOOK3E
623 /* Freescale BookE bolts the entire linear mapping */
624 /* XXX: BookE ppc64_rma_limit setup seems to disagree? */
625 if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E))
626 return linear_map_top;
627 /* Other BookE, we assume the first GB is bolted */
628 return 1ul << 30;
629#else
630 /* BookS radix, does not take faults on linear mapping */
631 if (early_radix_enabled())
632 return ULONG_MAX;
633
634 /* BookS hash, the first segment is bolted */
635 if (early_mmu_has_feature(MMU_FTR_1T_SEGMENT))
636 return 1UL << SID_SHIFT_1T;
637 return 1UL << SID_SHIFT;
638#endif
639}
640
641static void *__init alloc_stack(unsigned long limit, int cpu)
642{
643 void *ptr;
644
645 BUILD_BUG_ON(STACK_INT_FRAME_SIZE % 16);
646
647 ptr = memblock_alloc_try_nid(THREAD_SIZE, THREAD_SIZE,
648 MEMBLOCK_LOW_LIMIT, limit,
649 early_cpu_to_node(cpu));
650 if (!ptr)
651 panic("cannot allocate stacks");
652
653 return ptr;
654}
655
656void __init irqstack_early_init(void)
657{
658 u64 limit = ppc64_bolted_size();
659 unsigned int i;
660
661 /*
662 * Interrupt stacks must be in the first segment since we
663 * cannot afford to take SLB misses on them. They are not
664 * accessed in realmode.
665 */
666 for_each_possible_cpu(i) {
667 softirq_ctx[i] = alloc_stack(limit, i);
668 hardirq_ctx[i] = alloc_stack(limit, i);
669 }
670}
671
672#ifdef CONFIG_PPC_BOOK3E
673void __init exc_lvl_early_init(void)
674{
675 unsigned int i;
676
677 for_each_possible_cpu(i) {
678 void *sp;
679
680 sp = alloc_stack(ULONG_MAX, i);
681 critirq_ctx[i] = sp;
682 paca_ptrs[i]->crit_kstack = sp + THREAD_SIZE;
683
684 sp = alloc_stack(ULONG_MAX, i);
685 dbgirq_ctx[i] = sp;
686 paca_ptrs[i]->dbg_kstack = sp + THREAD_SIZE;
687
688 sp = alloc_stack(ULONG_MAX, i);
689 mcheckirq_ctx[i] = sp;
690 paca_ptrs[i]->mc_kstack = sp + THREAD_SIZE;
691 }
692
693 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
694 patch_exception(0x040, exc_debug_debug_book3e);
695}
696#endif
697
698/*
699 * Stack space used when we detect a bad kernel stack pointer, and
700 * early in SMP boots before relocation is enabled. Exclusive emergency
701 * stack for machine checks.
702 */
703void __init emergency_stack_init(void)
704{
705 u64 limit;
706 unsigned int i;
707
708 /*
709 * Emergency stacks must be under 256MB, we cannot afford to take
710 * SLB misses on them. The ABI also requires them to be 128-byte
711 * aligned.
712 *
713 * Since we use these as temporary stacks during secondary CPU
714 * bringup, machine check, system reset, and HMI, we need to get
715 * at them in real mode. This means they must also be within the RMO
716 * region.
717 *
718 * The IRQ stacks allocated elsewhere in this file are zeroed and
719 * initialized in kernel/irq.c. These are initialized here in order
720 * to have emergency stacks available as early as possible.
721 */
722 limit = min(ppc64_bolted_size(), ppc64_rma_size);
723
724 for_each_possible_cpu(i) {
725 paca_ptrs[i]->emergency_sp = alloc_stack(limit, i) + THREAD_SIZE;
726
727#ifdef CONFIG_PPC_BOOK3S_64
728 /* emergency stack for NMI exception handling. */
729 paca_ptrs[i]->nmi_emergency_sp = alloc_stack(limit, i) + THREAD_SIZE;
730
731 /* emergency stack for machine check exception handling. */
732 paca_ptrs[i]->mc_emergency_sp = alloc_stack(limit, i) + THREAD_SIZE;
733#endif
734 }
735}
736
737#ifdef CONFIG_SMP
738#define PCPU_DYN_SIZE ()
739
740static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
741{
742 return memblock_alloc_try_nid(size, align, __pa(MAX_DMA_ADDRESS),
743 MEMBLOCK_ALLOC_ACCESSIBLE,
744 early_cpu_to_node(cpu));
745
746}
747
748static void __init pcpu_fc_free(void *ptr, size_t size)
749{
750 memblock_free(__pa(ptr), size);
751}
752
753static int pcpu_cpu_distance(unsigned int from, unsigned int to)
754{
755 if (early_cpu_to_node(from) == early_cpu_to_node(to))
756 return LOCAL_DISTANCE;
757 else
758 return REMOTE_DISTANCE;
759}
760
761unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
762EXPORT_SYMBOL(__per_cpu_offset);
763
764void __init setup_per_cpu_areas(void)
765{
766 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
767 size_t atom_size;
768 unsigned long delta;
769 unsigned int cpu;
770 int rc;
771
772 /*
773 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
774 * to group units. For larger mappings, use 1M atom which
775 * should be large enough to contain a number of units.
776 */
777 if (mmu_linear_psize == MMU_PAGE_4K)
778 atom_size = PAGE_SIZE;
779 else
780 atom_size = 1 << 20;
781
782 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
783 pcpu_fc_alloc, pcpu_fc_free);
784 if (rc < 0)
785 panic("cannot initialize percpu area (err=%d)", rc);
786
787 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
788 for_each_possible_cpu(cpu) {
789 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
790 paca_ptrs[cpu]->data_offset = __per_cpu_offset[cpu];
791 }
792}
793#endif
794
795#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
796unsigned long memory_block_size_bytes(void)
797{
798 if (ppc_md.memory_block_size)
799 return ppc_md.memory_block_size();
800
801 return MIN_MEMORY_BLOCK_SIZE;
802}
803#endif
804
805#if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
806struct ppc_pci_io ppc_pci_io;
807EXPORT_SYMBOL(ppc_pci_io);
808#endif
809
810#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
811u64 hw_nmi_get_sample_period(int watchdog_thresh)
812{
813 return ppc_proc_freq * watchdog_thresh;
814}
815#endif
816
817/*
818 * The perf based hardlockup detector breaks PMU event based branches, so
819 * disable it by default. Book3S has a soft-nmi hardlockup detector based
820 * on the decrementer interrupt, so it does not suffer from this problem.
821 *
822 * It is likely to get false positives in VM guests, so disable it there
823 * by default too.
824 */
825static int __init disable_hardlockup_detector(void)
826{
827#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
828 hardlockup_detector_disable();
829#else
830 if (firmware_has_feature(FW_FEATURE_LPAR))
831 hardlockup_detector_disable();
832#endif
833
834 return 0;
835}
836early_initcall(disable_hardlockup_detector);
837
838#ifdef CONFIG_PPC_BOOK3S_64
839static enum l1d_flush_type enabled_flush_types;
840static void *l1d_flush_fallback_area;
841static bool no_rfi_flush;
842bool rfi_flush;
843
844static int __init handle_no_rfi_flush(char *p)
845{
846 pr_info("rfi-flush: disabled on command line.");
847 no_rfi_flush = true;
848 return 0;
849}
850early_param("no_rfi_flush", handle_no_rfi_flush);
851
852/*
853 * The RFI flush is not KPTI, but because users will see doco that says to use
854 * nopti we hijack that option here to also disable the RFI flush.
855 */
856static int __init handle_no_pti(char *p)
857{
858 pr_info("rfi-flush: disabling due to 'nopti' on command line.\n");
859 handle_no_rfi_flush(NULL);
860 return 0;
861}
862early_param("nopti", handle_no_pti);
863
864static void do_nothing(void *unused)
865{
866 /*
867 * We don't need to do the flush explicitly, just enter+exit kernel is
868 * sufficient, the RFI exit handlers will do the right thing.
869 */
870}
871
872void rfi_flush_enable(bool enable)
873{
874 if (enable) {
875 do_rfi_flush_fixups(enabled_flush_types);
876 on_each_cpu(do_nothing, NULL, 1);
877 } else
878 do_rfi_flush_fixups(L1D_FLUSH_NONE);
879
880 rfi_flush = enable;
881}
882
883static void __ref init_fallback_flush(void)
884{
885 u64 l1d_size, limit;
886 int cpu;
887
888 /* Only allocate the fallback flush area once (at boot time). */
889 if (l1d_flush_fallback_area)
890 return;
891
892 l1d_size = ppc64_caches.l1d.size;
893
894 /*
895 * If there is no d-cache-size property in the device tree, l1d_size
896 * could be zero. That leads to the loop in the asm wrapping around to
897 * 2^64-1, and then walking off the end of the fallback area and
898 * eventually causing a page fault which is fatal. Just default to
899 * something vaguely sane.
900 */
901 if (!l1d_size)
902 l1d_size = (64 * 1024);
903
904 limit = min(ppc64_bolted_size(), ppc64_rma_size);
905
906 /*
907 * Align to L1d size, and size it at 2x L1d size, to catch possible
908 * hardware prefetch runoff. We don't have a recipe for load patterns to
909 * reliably avoid the prefetcher.
910 */
911 l1d_flush_fallback_area = memblock_alloc_try_nid(l1d_size * 2,
912 l1d_size, MEMBLOCK_LOW_LIMIT,
913 limit, NUMA_NO_NODE);
914 if (!l1d_flush_fallback_area)
915 panic("%s: Failed to allocate %llu bytes align=0x%llx max_addr=%pa\n",
916 __func__, l1d_size * 2, l1d_size, &limit);
917
918
919 for_each_possible_cpu(cpu) {
920 struct paca_struct *paca = paca_ptrs[cpu];
921 paca->rfi_flush_fallback_area = l1d_flush_fallback_area;
922 paca->l1d_flush_size = l1d_size;
923 }
924}
925
926void setup_rfi_flush(enum l1d_flush_type types, bool enable)
927{
928 if (types & L1D_FLUSH_FALLBACK) {
929 pr_info("rfi-flush: fallback displacement flush available\n");
930 init_fallback_flush();
931 }
932
933 if (types & L1D_FLUSH_ORI)
934 pr_info("rfi-flush: ori type flush available\n");
935
936 if (types & L1D_FLUSH_MTTRIG)
937 pr_info("rfi-flush: mttrig type flush available\n");
938
939 enabled_flush_types = types;
940
941 if (!no_rfi_flush && !cpu_mitigations_off())
942 rfi_flush_enable(enable);
943}
944
945#ifdef CONFIG_DEBUG_FS
946static int rfi_flush_set(void *data, u64 val)
947{
948 bool enable;
949
950 if (val == 1)
951 enable = true;
952 else if (val == 0)
953 enable = false;
954 else
955 return -EINVAL;
956
957 /* Only do anything if we're changing state */
958 if (enable != rfi_flush)
959 rfi_flush_enable(enable);
960
961 return 0;
962}
963
964static int rfi_flush_get(void *data, u64 *val)
965{
966 *val = rfi_flush ? 1 : 0;
967 return 0;
968}
969
970DEFINE_SIMPLE_ATTRIBUTE(fops_rfi_flush, rfi_flush_get, rfi_flush_set, "%llu\n");
971
972static __init int rfi_flush_debugfs_init(void)
973{
974 debugfs_create_file("rfi_flush", 0600, powerpc_debugfs_root, NULL, &fops_rfi_flush);
975 return 0;
976}
977device_initcall(rfi_flush_debugfs_init);
978#endif
979#endif /* CONFIG_PPC_BOOK3S_64 */