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1// SPDX-License-Identifier: GPL-2.0
2/***************************************************************************/
3
4/*
5 * m5272.c -- platform support for ColdFire 5272 based boards
6 *
7 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
8 * Copyright (C) 2001-2002, SnapGear Inc. (www.snapgear.com)
9 */
10
11/***************************************************************************/
12
13#include <linux/clkdev.h>
14#include <linux/kernel.h>
15#include <linux/param.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/phy.h>
19#include <linux/phy_fixed.h>
20#include <asm/machdep.h>
21#include <asm/coldfire.h>
22#include <asm/mcfsim.h>
23#include <asm/mcfuart.h>
24#include <asm/mcfclk.h>
25
26/***************************************************************************/
27
28/*
29 * Some platforms need software versions of the GPIO data registers.
30 */
31unsigned short ppdata;
32unsigned char ledbank = 0xff;
33
34/***************************************************************************/
35
36DEFINE_CLK(pll, "pll.0", MCF_CLK);
37DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
38
39static struct clk_lookup m5272_clk_lookup[] = {
40 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
41 CLKDEV_INIT(NULL, "sys.0", &clk_sys),
42 CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
43 CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
44 CLKDEV_INIT("mcftmr.2", NULL, &clk_sys),
45 CLKDEV_INIT("mcftmr.3", NULL, &clk_sys),
46 CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
47 CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
48 CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
49 CLKDEV_INIT("fec.0", NULL, &clk_sys),
50};
51
52/***************************************************************************/
53
54static void __init m5272_uarts_init(void)
55{
56 u32 v;
57
58 /* Enable the output lines for the serial ports */
59 v = readl(MCFSIM_PBCNT);
60 v = (v & ~0x000000ff) | 0x00000055;
61 writel(v, MCFSIM_PBCNT);
62
63 v = readl(MCFSIM_PDCNT);
64 v = (v & ~0x000003fc) | 0x000002a8;
65 writel(v, MCFSIM_PDCNT);
66}
67
68/***************************************************************************/
69
70static void m5272_cpu_reset(void)
71{
72 local_irq_disable();
73 /* Set watchdog to reset, and enabled */
74 __raw_writew(0, MCFSIM_WIRR);
75 __raw_writew(1, MCFSIM_WRRR);
76 __raw_writew(0, MCFSIM_WCR);
77 for (;;)
78 /* wait for watchdog to timeout */;
79}
80
81/***************************************************************************/
82
83void __init config_BSP(char *commandp, int size)
84{
85#if defined (CONFIG_MOD5272)
86 /* Set base of device vectors to be 64 */
87 writeb(0x40, MCFSIM_PIVR);
88#endif
89
90#if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
91 /* Copy command line from FLASH to local buffer... */
92 memcpy(commandp, (char *) 0xf0004000, size);
93 commandp[size-1] = 0;
94#elif defined(CONFIG_CANCam)
95 /* Copy command line from FLASH to local buffer... */
96 memcpy(commandp, (char *) 0xf0010000, size);
97 commandp[size-1] = 0;
98#endif
99
100 mach_reset = m5272_cpu_reset;
101 mach_sched_init = hw_timer_init;
102}
103
104/***************************************************************************/
105
106/*
107 * Some 5272 based boards have the FEC ethernet directly connected to
108 * an ethernet switch. In this case we need to use the fixed phy type,
109 * and we need to declare it early in boot.
110 */
111static struct fixed_phy_status nettel_fixed_phy_status __initdata = {
112 .link = 1,
113 .speed = 100,
114 .duplex = 0,
115};
116
117/***************************************************************************/
118
119static int __init init_BSP(void)
120{
121 m5272_uarts_init();
122 fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status);
123 clkdev_add_table(m5272_clk_lookup, ARRAY_SIZE(m5272_clk_lookup));
124 return 0;
125}
126
127arch_initcall(init_BSP);
128
129/***************************************************************************/
1// SPDX-License-Identifier: GPL-2.0
2/***************************************************************************/
3
4/*
5 * m5272.c -- platform support for ColdFire 5272 based boards
6 *
7 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
8 * Copyright (C) 2001-2002, SnapGear Inc. (www.snapgear.com)
9 */
10
11/***************************************************************************/
12
13#include <linux/kernel.h>
14#include <linux/param.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/phy.h>
18#include <linux/phy_fixed.h>
19#include <asm/machdep.h>
20#include <asm/coldfire.h>
21#include <asm/mcfsim.h>
22#include <asm/mcfuart.h>
23#include <asm/mcfclk.h>
24
25/***************************************************************************/
26
27/*
28 * Some platforms need software versions of the GPIO data registers.
29 */
30unsigned short ppdata;
31unsigned char ledbank = 0xff;
32
33/***************************************************************************/
34
35DEFINE_CLK(pll, "pll.0", MCF_CLK);
36DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
37DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
38DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
39DEFINE_CLK(mcftmr2, "mcftmr.2", MCF_BUSCLK);
40DEFINE_CLK(mcftmr3, "mcftmr.3", MCF_BUSCLK);
41DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
42DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
43DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
44DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
45
46struct clk *mcf_clks[] = {
47 &clk_pll,
48 &clk_sys,
49 &clk_mcftmr0,
50 &clk_mcftmr1,
51 &clk_mcftmr2,
52 &clk_mcftmr3,
53 &clk_mcfuart0,
54 &clk_mcfuart1,
55 &clk_mcfqspi0,
56 &clk_fec0,
57 NULL
58};
59
60/***************************************************************************/
61
62static void __init m5272_uarts_init(void)
63{
64 u32 v;
65
66 /* Enable the output lines for the serial ports */
67 v = readl(MCFSIM_PBCNT);
68 v = (v & ~0x000000ff) | 0x00000055;
69 writel(v, MCFSIM_PBCNT);
70
71 v = readl(MCFSIM_PDCNT);
72 v = (v & ~0x000003fc) | 0x000002a8;
73 writel(v, MCFSIM_PDCNT);
74}
75
76/***************************************************************************/
77
78static void m5272_cpu_reset(void)
79{
80 local_irq_disable();
81 /* Set watchdog to reset, and enabled */
82 __raw_writew(0, MCFSIM_WIRR);
83 __raw_writew(1, MCFSIM_WRRR);
84 __raw_writew(0, MCFSIM_WCR);
85 for (;;)
86 /* wait for watchdog to timeout */;
87}
88
89/***************************************************************************/
90
91void __init config_BSP(char *commandp, int size)
92{
93#if defined (CONFIG_MOD5272)
94 /* Set base of device vectors to be 64 */
95 writeb(0x40, MCFSIM_PIVR);
96#endif
97
98#if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
99 /* Copy command line from FLASH to local buffer... */
100 memcpy(commandp, (char *) 0xf0004000, size);
101 commandp[size-1] = 0;
102#elif defined(CONFIG_CANCam)
103 /* Copy command line from FLASH to local buffer... */
104 memcpy(commandp, (char *) 0xf0010000, size);
105 commandp[size-1] = 0;
106#endif
107
108 mach_reset = m5272_cpu_reset;
109 mach_sched_init = hw_timer_init;
110}
111
112/***************************************************************************/
113
114/*
115 * Some 5272 based boards have the FEC ethernet directly connected to
116 * an ethernet switch. In this case we need to use the fixed phy type,
117 * and we need to declare it early in boot.
118 */
119static struct fixed_phy_status nettel_fixed_phy_status __initdata = {
120 .link = 1,
121 .speed = 100,
122 .duplex = 0,
123};
124
125/***************************************************************************/
126
127static int __init init_BSP(void)
128{
129 m5272_uarts_init();
130 fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status);
131 return 0;
132}
133
134arch_initcall(init_BSP);
135
136/***************************************************************************/