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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2016, NVIDIA Corporation
4 */
5
6#include <linux/clk.h>
7#include <linux/io.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/platform_device.h>
11#include <linux/pm_runtime.h>
12#include <linux/reset.h>
13
14#include <linux/usb.h>
15#include <linux/usb/chipidea.h>
16#include <linux/usb/hcd.h>
17#include <linux/usb/of.h>
18#include <linux/usb/phy.h>
19
20#include <soc/tegra/common.h>
21
22#include "../host/ehci.h"
23
24#include "ci.h"
25
26struct tegra_usb {
27 struct ci_hdrc_platform_data data;
28 struct platform_device *dev;
29
30 const struct tegra_usb_soc_info *soc;
31 struct usb_phy *phy;
32 struct clk *clk;
33
34 bool needs_double_reset;
35};
36
37struct tegra_usb_soc_info {
38 unsigned long flags;
39 unsigned int txfifothresh;
40 enum usb_dr_mode dr_mode;
41};
42
43static const struct tegra_usb_soc_info tegra20_ehci_soc_info = {
44 .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
45 CI_HDRC_OVERRIDE_PHY_CONTROL |
46 CI_HDRC_SUPPORTS_RUNTIME_PM,
47 .dr_mode = USB_DR_MODE_HOST,
48 .txfifothresh = 10,
49};
50
51static const struct tegra_usb_soc_info tegra30_ehci_soc_info = {
52 .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
53 CI_HDRC_OVERRIDE_PHY_CONTROL |
54 CI_HDRC_SUPPORTS_RUNTIME_PM,
55 .dr_mode = USB_DR_MODE_HOST,
56 .txfifothresh = 16,
57};
58
59static const struct tegra_usb_soc_info tegra20_udc_soc_info = {
60 .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
61 CI_HDRC_OVERRIDE_PHY_CONTROL |
62 CI_HDRC_SUPPORTS_RUNTIME_PM,
63 .dr_mode = USB_DR_MODE_UNKNOWN,
64 .txfifothresh = 10,
65};
66
67static const struct tegra_usb_soc_info tegra30_udc_soc_info = {
68 .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
69 CI_HDRC_OVERRIDE_PHY_CONTROL |
70 CI_HDRC_SUPPORTS_RUNTIME_PM,
71 .dr_mode = USB_DR_MODE_UNKNOWN,
72 .txfifothresh = 16,
73};
74
75static const struct of_device_id tegra_usb_of_match[] = {
76 {
77 .compatible = "nvidia,tegra20-ehci",
78 .data = &tegra20_ehci_soc_info,
79 }, {
80 .compatible = "nvidia,tegra30-ehci",
81 .data = &tegra30_ehci_soc_info,
82 }, {
83 .compatible = "nvidia,tegra20-udc",
84 .data = &tegra20_udc_soc_info,
85 }, {
86 .compatible = "nvidia,tegra30-udc",
87 .data = &tegra30_udc_soc_info,
88 }, {
89 .compatible = "nvidia,tegra114-udc",
90 .data = &tegra30_udc_soc_info,
91 }, {
92 .compatible = "nvidia,tegra124-udc",
93 .data = &tegra30_udc_soc_info,
94 }, {
95 /* sentinel */
96 }
97};
98MODULE_DEVICE_TABLE(of, tegra_usb_of_match);
99
100static int tegra_usb_reset_controller(struct device *dev)
101{
102 struct reset_control *rst, *rst_utmi;
103 struct device_node *phy_np;
104 int err;
105
106 rst = devm_reset_control_get_shared(dev, "usb");
107 if (IS_ERR(rst)) {
108 dev_err(dev, "can't get ehci reset: %pe\n", rst);
109 return PTR_ERR(rst);
110 }
111
112 phy_np = of_parse_phandle(dev->of_node, "nvidia,phy", 0);
113 if (!phy_np)
114 return -ENOENT;
115
116 /*
117 * The 1st USB controller contains some UTMI pad registers that are
118 * global for all the controllers on the chip. Those registers are
119 * also cleared when reset is asserted to the 1st controller.
120 */
121 rst_utmi = of_reset_control_get_shared(phy_np, "utmi-pads");
122 if (IS_ERR(rst_utmi)) {
123 dev_warn(dev, "can't get utmi-pads reset from the PHY\n");
124 dev_warn(dev, "continuing, but please update your DT\n");
125 } else {
126 /*
127 * PHY driver performs UTMI-pads reset in a case of a
128 * non-legacy DT.
129 */
130 reset_control_put(rst_utmi);
131 }
132
133 of_node_put(phy_np);
134
135 /* reset control is shared, hence initialize it first */
136 err = reset_control_deassert(rst);
137 if (err)
138 return err;
139
140 err = reset_control_assert(rst);
141 if (err)
142 return err;
143
144 udelay(1);
145
146 err = reset_control_deassert(rst);
147 if (err)
148 return err;
149
150 return 0;
151}
152
153static int tegra_usb_notify_event(struct ci_hdrc *ci, unsigned int event)
154{
155 struct tegra_usb *usb = dev_get_drvdata(ci->dev->parent);
156 struct ehci_hcd *ehci;
157
158 switch (event) {
159 case CI_HDRC_CONTROLLER_RESET_EVENT:
160 if (ci->hcd) {
161 ehci = hcd_to_ehci(ci->hcd);
162 ehci->has_tdi_phy_lpm = false;
163 ehci_writel(ehci, usb->soc->txfifothresh << 16,
164 &ehci->regs->txfill_tuning);
165 }
166 break;
167 }
168
169 return 0;
170}
171
172static int tegra_usb_internal_port_reset(struct ehci_hcd *ehci,
173 u32 __iomem *portsc_reg,
174 unsigned long *flags)
175{
176 u32 saved_usbintr, temp;
177 unsigned int i, tries;
178 int retval = 0;
179
180 saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
181 /* disable USB interrupt */
182 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
183 spin_unlock_irqrestore(&ehci->lock, *flags);
184
185 /*
186 * Here we have to do Port Reset at most twice for
187 * Port Enable bit to be set.
188 */
189 for (i = 0; i < 2; i++) {
190 temp = ehci_readl(ehci, portsc_reg);
191 temp |= PORT_RESET;
192 ehci_writel(ehci, temp, portsc_reg);
193 fsleep(10000);
194 temp &= ~PORT_RESET;
195 ehci_writel(ehci, temp, portsc_reg);
196 fsleep(1000);
197 tries = 100;
198 do {
199 fsleep(1000);
200 /*
201 * Up to this point, Port Enable bit is
202 * expected to be set after 2 ms waiting.
203 * USB1 usually takes extra 45 ms, for safety,
204 * we take 100 ms as timeout.
205 */
206 temp = ehci_readl(ehci, portsc_reg);
207 } while (!(temp & PORT_PE) && tries--);
208 if (temp & PORT_PE)
209 break;
210 }
211 if (i == 2)
212 retval = -ETIMEDOUT;
213
214 /*
215 * Clear Connect Status Change bit if it's set.
216 * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
217 */
218 if (temp & PORT_CSC)
219 ehci_writel(ehci, PORT_CSC, portsc_reg);
220
221 /*
222 * Write to clear any interrupt status bits that might be set
223 * during port reset.
224 */
225 temp = ehci_readl(ehci, &ehci->regs->status);
226 ehci_writel(ehci, temp, &ehci->regs->status);
227
228 /* restore original interrupt-enable bits */
229 spin_lock_irqsave(&ehci->lock, *flags);
230 ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
231
232 return retval;
233}
234
235static int tegra_ehci_hub_control(struct ci_hdrc *ci, u16 typeReq, u16 wValue,
236 u16 wIndex, char *buf, u16 wLength,
237 bool *done, unsigned long *flags)
238{
239 struct tegra_usb *usb = dev_get_drvdata(ci->dev->parent);
240 struct ehci_hcd *ehci = hcd_to_ehci(ci->hcd);
241 u32 __iomem *status_reg;
242 int retval = 0;
243
244 status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
245
246 switch (typeReq) {
247 case SetPortFeature:
248 if (wValue != USB_PORT_FEAT_RESET || !usb->needs_double_reset)
249 break;
250
251 /* for USB1 port we need to issue Port Reset twice internally */
252 retval = tegra_usb_internal_port_reset(ehci, status_reg, flags);
253 *done = true;
254 break;
255 }
256
257 return retval;
258}
259
260static void tegra_usb_enter_lpm(struct ci_hdrc *ci, bool enable)
261{
262 /*
263 * Touching any register which belongs to AHB clock domain will
264 * hang CPU if USB controller is put into low power mode because
265 * AHB USB clock is gated on Tegra in the LPM.
266 *
267 * Tegra PHY has a separate register for checking the clock status
268 * and usb_phy_set_suspend() takes care of gating/ungating the clocks
269 * and restoring the PHY state on Tegra. Hence DEVLC/PORTSC registers
270 * shouldn't be touched directly by the CI driver.
271 */
272 usb_phy_set_suspend(ci->usb_phy, enable);
273}
274
275static int tegra_usb_probe(struct platform_device *pdev)
276{
277 const struct tegra_usb_soc_info *soc;
278 struct tegra_usb *usb;
279 int err;
280
281 usb = devm_kzalloc(&pdev->dev, sizeof(*usb), GFP_KERNEL);
282 if (!usb)
283 return -ENOMEM;
284
285 platform_set_drvdata(pdev, usb);
286
287 soc = of_device_get_match_data(&pdev->dev);
288 if (!soc) {
289 dev_err(&pdev->dev, "failed to match OF data\n");
290 return -EINVAL;
291 }
292
293 usb->phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
294 if (IS_ERR(usb->phy))
295 return dev_err_probe(&pdev->dev, PTR_ERR(usb->phy),
296 "failed to get PHY");
297
298 usb->clk = devm_clk_get(&pdev->dev, NULL);
299 if (IS_ERR(usb->clk))
300 return dev_err_probe(&pdev->dev, PTR_ERR(usb->clk),
301 "failed to get clock");
302
303 err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
304 if (err)
305 return err;
306
307 pm_runtime_enable(&pdev->dev);
308 err = pm_runtime_resume_and_get(&pdev->dev);
309 if (err)
310 return err;
311
312 if (device_property_present(&pdev->dev, "nvidia,needs-double-reset"))
313 usb->needs_double_reset = true;
314
315 err = tegra_usb_reset_controller(&pdev->dev);
316 if (err) {
317 dev_err_probe(&pdev->dev, err, "failed to reset controller");
318 goto fail_power_off;
319 }
320
321 /*
322 * USB controller registers shouldn't be touched before PHY is
323 * initialized, otherwise CPU will hang because clocks are gated.
324 * PHY driver controls gating of internal USB clocks on Tegra.
325 */
326 err = usb_phy_init(usb->phy);
327 if (err)
328 goto fail_power_off;
329
330 /* setup and register ChipIdea HDRC device */
331 usb->soc = soc;
332 usb->data.name = "tegra-usb";
333 usb->data.flags = soc->flags;
334 usb->data.usb_phy = usb->phy;
335 usb->data.dr_mode = soc->dr_mode;
336 usb->data.capoffset = DEF_CAPOFFSET;
337 usb->data.enter_lpm = tegra_usb_enter_lpm;
338 usb->data.hub_control = tegra_ehci_hub_control;
339 usb->data.notify_event = tegra_usb_notify_event;
340
341 /* Tegra PHY driver currently doesn't support LPM for ULPI */
342 if (of_usb_get_phy_mode(pdev->dev.of_node) == USBPHY_INTERFACE_MODE_ULPI)
343 usb->data.flags &= ~CI_HDRC_SUPPORTS_RUNTIME_PM;
344
345 usb->dev = ci_hdrc_add_device(&pdev->dev, pdev->resource,
346 pdev->num_resources, &usb->data);
347 if (IS_ERR(usb->dev)) {
348 err = dev_err_probe(&pdev->dev, PTR_ERR(usb->dev),
349 "failed to add HDRC device");
350 goto phy_shutdown;
351 }
352
353 return 0;
354
355phy_shutdown:
356 usb_phy_shutdown(usb->phy);
357fail_power_off:
358 pm_runtime_put_sync_suspend(&pdev->dev);
359 pm_runtime_force_suspend(&pdev->dev);
360
361 return err;
362}
363
364static void tegra_usb_remove(struct platform_device *pdev)
365{
366 struct tegra_usb *usb = platform_get_drvdata(pdev);
367
368 ci_hdrc_remove_device(usb->dev);
369 usb_phy_shutdown(usb->phy);
370
371 pm_runtime_put_sync_suspend(&pdev->dev);
372 pm_runtime_force_suspend(&pdev->dev);
373}
374
375static int __maybe_unused tegra_usb_runtime_resume(struct device *dev)
376{
377 struct tegra_usb *usb = dev_get_drvdata(dev);
378 int err;
379
380 err = clk_prepare_enable(usb->clk);
381 if (err < 0) {
382 dev_err(dev, "failed to enable clock: %d\n", err);
383 return err;
384 }
385
386 return 0;
387}
388
389static int __maybe_unused tegra_usb_runtime_suspend(struct device *dev)
390{
391 struct tegra_usb *usb = dev_get_drvdata(dev);
392
393 clk_disable_unprepare(usb->clk);
394
395 return 0;
396}
397
398static const struct dev_pm_ops tegra_usb_pm = {
399 SET_RUNTIME_PM_OPS(tegra_usb_runtime_suspend, tegra_usb_runtime_resume,
400 NULL)
401};
402
403static struct platform_driver tegra_usb_driver = {
404 .driver = {
405 .name = "tegra-usb",
406 .of_match_table = tegra_usb_of_match,
407 .pm = &tegra_usb_pm,
408 },
409 .probe = tegra_usb_probe,
410 .remove_new = tegra_usb_remove,
411};
412module_platform_driver(tegra_usb_driver);
413
414MODULE_DESCRIPTION("NVIDIA Tegra USB driver");
415MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
416MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2016, NVIDIA Corporation
4 */
5
6#include <linux/clk.h>
7#include <linux/io.h>
8#include <linux/module.h>
9#include <linux/of_device.h>
10#include <linux/reset.h>
11
12#include <linux/usb.h>
13#include <linux/usb/chipidea.h>
14#include <linux/usb/hcd.h>
15#include <linux/usb/of.h>
16#include <linux/usb/phy.h>
17
18#include "../host/ehci.h"
19
20#include "ci.h"
21
22struct tegra_usb {
23 struct ci_hdrc_platform_data data;
24 struct platform_device *dev;
25
26 const struct tegra_usb_soc_info *soc;
27 struct usb_phy *phy;
28 struct clk *clk;
29
30 bool needs_double_reset;
31};
32
33struct tegra_usb_soc_info {
34 unsigned long flags;
35 unsigned int txfifothresh;
36 enum usb_dr_mode dr_mode;
37};
38
39static const struct tegra_usb_soc_info tegra20_ehci_soc_info = {
40 .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
41 CI_HDRC_OVERRIDE_PHY_CONTROL |
42 CI_HDRC_SUPPORTS_RUNTIME_PM,
43 .dr_mode = USB_DR_MODE_HOST,
44 .txfifothresh = 10,
45};
46
47static const struct tegra_usb_soc_info tegra30_ehci_soc_info = {
48 .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
49 CI_HDRC_OVERRIDE_PHY_CONTROL |
50 CI_HDRC_SUPPORTS_RUNTIME_PM,
51 .dr_mode = USB_DR_MODE_HOST,
52 .txfifothresh = 16,
53};
54
55static const struct tegra_usb_soc_info tegra20_udc_soc_info = {
56 .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
57 CI_HDRC_OVERRIDE_PHY_CONTROL |
58 CI_HDRC_SUPPORTS_RUNTIME_PM,
59 .dr_mode = USB_DR_MODE_UNKNOWN,
60 .txfifothresh = 10,
61};
62
63static const struct tegra_usb_soc_info tegra30_udc_soc_info = {
64 .flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
65 CI_HDRC_OVERRIDE_PHY_CONTROL |
66 CI_HDRC_SUPPORTS_RUNTIME_PM,
67 .dr_mode = USB_DR_MODE_UNKNOWN,
68 .txfifothresh = 16,
69};
70
71static const struct of_device_id tegra_usb_of_match[] = {
72 {
73 .compatible = "nvidia,tegra20-ehci",
74 .data = &tegra20_ehci_soc_info,
75 }, {
76 .compatible = "nvidia,tegra30-ehci",
77 .data = &tegra30_ehci_soc_info,
78 }, {
79 .compatible = "nvidia,tegra20-udc",
80 .data = &tegra20_udc_soc_info,
81 }, {
82 .compatible = "nvidia,tegra30-udc",
83 .data = &tegra30_udc_soc_info,
84 }, {
85 .compatible = "nvidia,tegra114-udc",
86 .data = &tegra30_udc_soc_info,
87 }, {
88 .compatible = "nvidia,tegra124-udc",
89 .data = &tegra30_udc_soc_info,
90 }, {
91 /* sentinel */
92 }
93};
94MODULE_DEVICE_TABLE(of, tegra_usb_of_match);
95
96static int tegra_usb_reset_controller(struct device *dev)
97{
98 struct reset_control *rst, *rst_utmi;
99 struct device_node *phy_np;
100 int err;
101
102 rst = devm_reset_control_get_shared(dev, "usb");
103 if (IS_ERR(rst)) {
104 dev_err(dev, "can't get ehci reset: %pe\n", rst);
105 return PTR_ERR(rst);
106 }
107
108 phy_np = of_parse_phandle(dev->of_node, "nvidia,phy", 0);
109 if (!phy_np)
110 return -ENOENT;
111
112 /*
113 * The 1st USB controller contains some UTMI pad registers that are
114 * global for all the controllers on the chip. Those registers are
115 * also cleared when reset is asserted to the 1st controller.
116 */
117 rst_utmi = of_reset_control_get_shared(phy_np, "utmi-pads");
118 if (IS_ERR(rst_utmi)) {
119 dev_warn(dev, "can't get utmi-pads reset from the PHY\n");
120 dev_warn(dev, "continuing, but please update your DT\n");
121 } else {
122 /*
123 * PHY driver performs UTMI-pads reset in a case of a
124 * non-legacy DT.
125 */
126 reset_control_put(rst_utmi);
127 }
128
129 of_node_put(phy_np);
130
131 /* reset control is shared, hence initialize it first */
132 err = reset_control_deassert(rst);
133 if (err)
134 return err;
135
136 err = reset_control_assert(rst);
137 if (err)
138 return err;
139
140 udelay(1);
141
142 err = reset_control_deassert(rst);
143 if (err)
144 return err;
145
146 return 0;
147}
148
149static int tegra_usb_notify_event(struct ci_hdrc *ci, unsigned int event)
150{
151 struct tegra_usb *usb = dev_get_drvdata(ci->dev->parent);
152 struct ehci_hcd *ehci;
153
154 switch (event) {
155 case CI_HDRC_CONTROLLER_RESET_EVENT:
156 if (ci->hcd) {
157 ehci = hcd_to_ehci(ci->hcd);
158 ehci->has_tdi_phy_lpm = false;
159 ehci_writel(ehci, usb->soc->txfifothresh << 16,
160 &ehci->regs->txfill_tuning);
161 }
162 break;
163 }
164
165 return 0;
166}
167
168static int tegra_usb_internal_port_reset(struct ehci_hcd *ehci,
169 u32 __iomem *portsc_reg,
170 unsigned long *flags)
171{
172 u32 saved_usbintr, temp;
173 unsigned int i, tries;
174 int retval = 0;
175
176 saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
177 /* disable USB interrupt */
178 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
179 spin_unlock_irqrestore(&ehci->lock, *flags);
180
181 /*
182 * Here we have to do Port Reset at most twice for
183 * Port Enable bit to be set.
184 */
185 for (i = 0; i < 2; i++) {
186 temp = ehci_readl(ehci, portsc_reg);
187 temp |= PORT_RESET;
188 ehci_writel(ehci, temp, portsc_reg);
189 fsleep(10000);
190 temp &= ~PORT_RESET;
191 ehci_writel(ehci, temp, portsc_reg);
192 fsleep(1000);
193 tries = 100;
194 do {
195 fsleep(1000);
196 /*
197 * Up to this point, Port Enable bit is
198 * expected to be set after 2 ms waiting.
199 * USB1 usually takes extra 45 ms, for safety,
200 * we take 100 ms as timeout.
201 */
202 temp = ehci_readl(ehci, portsc_reg);
203 } while (!(temp & PORT_PE) && tries--);
204 if (temp & PORT_PE)
205 break;
206 }
207 if (i == 2)
208 retval = -ETIMEDOUT;
209
210 /*
211 * Clear Connect Status Change bit if it's set.
212 * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
213 */
214 if (temp & PORT_CSC)
215 ehci_writel(ehci, PORT_CSC, portsc_reg);
216
217 /*
218 * Write to clear any interrupt status bits that might be set
219 * during port reset.
220 */
221 temp = ehci_readl(ehci, &ehci->regs->status);
222 ehci_writel(ehci, temp, &ehci->regs->status);
223
224 /* restore original interrupt-enable bits */
225 spin_lock_irqsave(&ehci->lock, *flags);
226 ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
227
228 return retval;
229}
230
231static int tegra_ehci_hub_control(struct ci_hdrc *ci, u16 typeReq, u16 wValue,
232 u16 wIndex, char *buf, u16 wLength,
233 bool *done, unsigned long *flags)
234{
235 struct tegra_usb *usb = dev_get_drvdata(ci->dev->parent);
236 struct ehci_hcd *ehci = hcd_to_ehci(ci->hcd);
237 u32 __iomem *status_reg;
238 int retval = 0;
239
240 status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
241
242 switch (typeReq) {
243 case SetPortFeature:
244 if (wValue != USB_PORT_FEAT_RESET || !usb->needs_double_reset)
245 break;
246
247 /* for USB1 port we need to issue Port Reset twice internally */
248 retval = tegra_usb_internal_port_reset(ehci, status_reg, flags);
249 *done = true;
250 break;
251 }
252
253 return retval;
254}
255
256static void tegra_usb_enter_lpm(struct ci_hdrc *ci, bool enable)
257{
258 /*
259 * Touching any register which belongs to AHB clock domain will
260 * hang CPU if USB controller is put into low power mode because
261 * AHB USB clock is gated on Tegra in the LPM.
262 *
263 * Tegra PHY has a separate register for checking the clock status
264 * and usb_phy_set_suspend() takes care of gating/ungating the clocks
265 * and restoring the PHY state on Tegra. Hence DEVLC/PORTSC registers
266 * shouldn't be touched directly by the CI driver.
267 */
268 usb_phy_set_suspend(ci->usb_phy, enable);
269}
270
271static int tegra_usb_probe(struct platform_device *pdev)
272{
273 const struct tegra_usb_soc_info *soc;
274 struct tegra_usb *usb;
275 int err;
276
277 usb = devm_kzalloc(&pdev->dev, sizeof(*usb), GFP_KERNEL);
278 if (!usb)
279 return -ENOMEM;
280
281 soc = of_device_get_match_data(&pdev->dev);
282 if (!soc) {
283 dev_err(&pdev->dev, "failed to match OF data\n");
284 return -EINVAL;
285 }
286
287 usb->phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
288 if (IS_ERR(usb->phy))
289 return dev_err_probe(&pdev->dev, PTR_ERR(usb->phy),
290 "failed to get PHY\n");
291
292 usb->clk = devm_clk_get(&pdev->dev, NULL);
293 if (IS_ERR(usb->clk)) {
294 err = PTR_ERR(usb->clk);
295 dev_err(&pdev->dev, "failed to get clock: %d\n", err);
296 return err;
297 }
298
299 err = clk_prepare_enable(usb->clk);
300 if (err < 0) {
301 dev_err(&pdev->dev, "failed to enable clock: %d\n", err);
302 return err;
303 }
304
305 if (device_property_present(&pdev->dev, "nvidia,needs-double-reset"))
306 usb->needs_double_reset = true;
307
308 err = tegra_usb_reset_controller(&pdev->dev);
309 if (err) {
310 dev_err(&pdev->dev, "failed to reset controller: %d\n", err);
311 goto fail_power_off;
312 }
313
314 /*
315 * USB controller registers shouldn't be touched before PHY is
316 * initialized, otherwise CPU will hang because clocks are gated.
317 * PHY driver controls gating of internal USB clocks on Tegra.
318 */
319 err = usb_phy_init(usb->phy);
320 if (err)
321 goto fail_power_off;
322
323 platform_set_drvdata(pdev, usb);
324
325 /* setup and register ChipIdea HDRC device */
326 usb->soc = soc;
327 usb->data.name = "tegra-usb";
328 usb->data.flags = soc->flags;
329 usb->data.usb_phy = usb->phy;
330 usb->data.dr_mode = soc->dr_mode;
331 usb->data.capoffset = DEF_CAPOFFSET;
332 usb->data.enter_lpm = tegra_usb_enter_lpm;
333 usb->data.hub_control = tegra_ehci_hub_control;
334 usb->data.notify_event = tegra_usb_notify_event;
335
336 /* Tegra PHY driver currently doesn't support LPM for ULPI */
337 if (of_usb_get_phy_mode(pdev->dev.of_node) == USBPHY_INTERFACE_MODE_ULPI)
338 usb->data.flags &= ~CI_HDRC_SUPPORTS_RUNTIME_PM;
339
340 usb->dev = ci_hdrc_add_device(&pdev->dev, pdev->resource,
341 pdev->num_resources, &usb->data);
342 if (IS_ERR(usb->dev)) {
343 err = PTR_ERR(usb->dev);
344 dev_err(&pdev->dev, "failed to add HDRC device: %d\n", err);
345 goto phy_shutdown;
346 }
347
348 return 0;
349
350phy_shutdown:
351 usb_phy_shutdown(usb->phy);
352fail_power_off:
353 clk_disable_unprepare(usb->clk);
354 return err;
355}
356
357static int tegra_usb_remove(struct platform_device *pdev)
358{
359 struct tegra_usb *usb = platform_get_drvdata(pdev);
360
361 ci_hdrc_remove_device(usb->dev);
362 usb_phy_shutdown(usb->phy);
363 clk_disable_unprepare(usb->clk);
364
365 return 0;
366}
367
368static struct platform_driver tegra_usb_driver = {
369 .driver = {
370 .name = "tegra-usb",
371 .of_match_table = tegra_usb_of_match,
372 },
373 .probe = tegra_usb_probe,
374 .remove = tegra_usb_remove,
375};
376module_platform_driver(tegra_usb_driver);
377
378MODULE_DESCRIPTION("NVIDIA Tegra USB driver");
379MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
380MODULE_LICENSE("GPL v2");