1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Application UART driver for:
   4 *	Freescale STMP37XX/STMP378X
   5 *	Alphascale ASM9260
   6 *
   7 * Author: dmitry pervushin <dimka@embeddedalley.com>
   8 *
   9 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
  10 *	Provide Alphascale ASM9260 support.
  11 * Copyright 2008-2010 Freescale Semiconductor, Inc.
  12 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
  13 */
  14
  15#include <linux/kernel.h>
  16#include <linux/errno.h>
  17#include <linux/init.h>
  18#include <linux/console.h>
  19#include <linux/interrupt.h>
  20#include <linux/module.h>
  21#include <linux/slab.h>
  22#include <linux/wait.h>
  23#include <linux/tty.h>
  24#include <linux/tty_driver.h>
  25#include <linux/tty_flip.h>
  26#include <linux/serial.h>
  27#include <linux/serial_core.h>
  28#include <linux/platform_device.h>
  29#include <linux/device.h>
  30#include <linux/clk.h>
  31#include <linux/delay.h>
  32#include <linux/io.h>
  33#include <linux/of.h>
  34#include <linux/dma-mapping.h>
  35#include <linux/dmaengine.h>
  36
  37#include <linux/gpio/consumer.h>
  38#include <linux/err.h>
  39#include <linux/irq.h>
  40#include "serial_mctrl_gpio.h"
  41
  42#define MXS_AUART_PORTS 5
  43#define MXS_AUART_FIFO_SIZE		16
  44
  45#define SET_REG				0x4
  46#define CLR_REG				0x8
  47#define TOG_REG				0xc
  48
  49#define AUART_CTRL0			0x00000000
  50#define AUART_CTRL1			0x00000010
  51#define AUART_CTRL2			0x00000020
  52#define AUART_LINECTRL			0x00000030
  53#define AUART_LINECTRL2			0x00000040
  54#define AUART_INTR			0x00000050
  55#define AUART_DATA			0x00000060
  56#define AUART_STAT			0x00000070
  57#define AUART_DEBUG			0x00000080
  58#define AUART_VERSION			0x00000090
  59#define AUART_AUTOBAUD			0x000000a0
  60
  61#define AUART_CTRL0_SFTRST			(1 << 31)
  62#define AUART_CTRL0_CLKGATE			(1 << 30)
  63#define AUART_CTRL0_RXTO_ENABLE			(1 << 27)
  64#define AUART_CTRL0_RXTIMEOUT(v)		(((v) & 0x7ff) << 16)
  65#define AUART_CTRL0_XFER_COUNT(v)		((v) & 0xffff)
  66
  67#define AUART_CTRL1_XFER_COUNT(v)		((v) & 0xffff)
  68
  69#define AUART_CTRL2_DMAONERR			(1 << 26)
  70#define AUART_CTRL2_TXDMAE			(1 << 25)
  71#define AUART_CTRL2_RXDMAE			(1 << 24)
  72
  73#define AUART_CTRL2_CTSEN			(1 << 15)
  74#define AUART_CTRL2_RTSEN			(1 << 14)
  75#define AUART_CTRL2_RTS				(1 << 11)
  76#define AUART_CTRL2_RXE				(1 << 9)
  77#define AUART_CTRL2_TXE				(1 << 8)
  78#define AUART_CTRL2_UARTEN			(1 << 0)
  79
  80#define AUART_LINECTRL_BAUD_DIV_MAX		0x003fffc0
  81#define AUART_LINECTRL_BAUD_DIV_MIN		0x000000ec
  82#define AUART_LINECTRL_BAUD_DIVINT_SHIFT	16
  83#define AUART_LINECTRL_BAUD_DIVINT_MASK		0xffff0000
  84#define AUART_LINECTRL_BAUD_DIVINT(v)		(((v) & 0xffff) << 16)
  85#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT	8
  86#define AUART_LINECTRL_BAUD_DIVFRAC_MASK	0x00003f00
  87#define AUART_LINECTRL_BAUD_DIVFRAC(v)		(((v) & 0x3f) << 8)
  88#define AUART_LINECTRL_SPS			(1 << 7)
  89#define AUART_LINECTRL_WLEN_MASK		0x00000060
  90#define AUART_LINECTRL_WLEN(v)			((((v) - 5) & 0x3) << 5)
  91#define AUART_LINECTRL_FEN			(1 << 4)
  92#define AUART_LINECTRL_STP2			(1 << 3)
  93#define AUART_LINECTRL_EPS			(1 << 2)
  94#define AUART_LINECTRL_PEN			(1 << 1)
  95#define AUART_LINECTRL_BRK			(1 << 0)
  96
  97#define AUART_INTR_RTIEN			(1 << 22)
  98#define AUART_INTR_TXIEN			(1 << 21)
  99#define AUART_INTR_RXIEN			(1 << 20)
 100#define AUART_INTR_CTSMIEN			(1 << 17)
 101#define AUART_INTR_RTIS				(1 << 6)
 102#define AUART_INTR_TXIS				(1 << 5)
 103#define AUART_INTR_RXIS				(1 << 4)
 104#define AUART_INTR_CTSMIS			(1 << 1)
 105
 106#define AUART_STAT_BUSY				(1 << 29)
 107#define AUART_STAT_CTS				(1 << 28)
 108#define AUART_STAT_TXFE				(1 << 27)
 109#define AUART_STAT_TXFF				(1 << 25)
 110#define AUART_STAT_RXFE				(1 << 24)
 111#define AUART_STAT_OERR				(1 << 19)
 112#define AUART_STAT_BERR				(1 << 18)
 113#define AUART_STAT_PERR				(1 << 17)
 114#define AUART_STAT_FERR				(1 << 16)
 115#define AUART_STAT_RXCOUNT_MASK			0xffff
 116
 117/*
 118 * Start of Alphascale asm9260 defines
 119 * This list contains only differences of existing bits
 120 * between imx2x and asm9260
 121 */
 122#define ASM9260_HW_CTRL0			0x0000
 123/*
 124 * RW. Tell the UART to execute the RX DMA Command. The
 125 * UART will clear this bit at the end of receive execution.
 126 */
 127#define ASM9260_BM_CTRL0_RXDMA_RUN		BIT(28)
 128/* RW. 0 use FIFO for status register; 1 use DMA */
 129#define ASM9260_BM_CTRL0_RXTO_SOURCE_STATUS	BIT(25)
 130/*
 131 * RW. RX TIMEOUT Enable. Valid for FIFO and DMA.
 132 * Warning: If this bit is set to 0, the RX timeout will not affect receive DMA
 133 * operation. If this bit is set to 1, a receive timeout will cause the receive
 134 * DMA logic to terminate by filling the remaining DMA bytes with garbage data.
 135 */
 136#define ASM9260_BM_CTRL0_RXTO_ENABLE		BIT(24)
 137/*
 138 * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before
 139 * asserting timeout on the RX input. If the RXFIFO is not empty and the RX
 140 * input is idle, then the watchdog counter will decrement each bit-time. Note
 141 * 7-bit-time is added to the programmed value, so a value of zero will set
 142 * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also
 143 * note that the counter is reloaded at the end of each frame, so if the frame
 144 * is 10 bits long and the timeout counter value is zero, then timeout will
 145 * occur (when FIFO is not empty) even if the RX input is not idle. The default
 146 * value is 0x3 (31 bit-time).
 147 */
 148#define ASM9260_BM_CTRL0_RXTO_MASK		(0xff << 16)
 149/* TIMEOUT = (100*7+1)*(1/BAUD) */
 150#define ASM9260_BM_CTRL0_DEFAULT_RXTIMEOUT	(20 << 16)
 151
 152/* TX ctrl register */
 153#define ASM9260_HW_CTRL1			0x0010
 154/*
 155 * RW. Tell the UART to execute the TX DMA Command. The
 156 * UART will clear this bit at the end of transmit execution.
 157 */
 158#define ASM9260_BM_CTRL1_TXDMA_RUN		BIT(28)
 159
 160#define ASM9260_HW_CTRL2			0x0020
 161/*
 162 * RW. Receive Interrupt FIFO Level Select.
 163 * The trigger points for the receive interrupt are as follows:
 164 * ONE_EIGHTHS = 0x0 Trigger on FIFO full to at least 2 of 16 entries.
 165 * ONE_QUARTER = 0x1 Trigger on FIFO full to at least 4 of 16 entries.
 166 * ONE_HALF = 0x2 Trigger on FIFO full to at least 8 of 16 entries.
 167 * THREE_QUARTERS = 0x3 Trigger on FIFO full to at least 12 of 16 entries.
 168 * SEVEN_EIGHTHS = 0x4 Trigger on FIFO full to at least 14 of 16 entries.
 169 */
 170#define ASM9260_BM_CTRL2_RXIFLSEL		(7 << 20)
 171#define ASM9260_BM_CTRL2_DEFAULT_RXIFLSEL	(3 << 20)
 172/* RW. Same as RXIFLSEL */
 173#define ASM9260_BM_CTRL2_TXIFLSEL		(7 << 16)
 174#define ASM9260_BM_CTRL2_DEFAULT_TXIFLSEL	(2 << 16)
 175/* RW. Set DTR. When this bit is 1, the output is 0. */
 176#define ASM9260_BM_CTRL2_DTR			BIT(10)
 177/* RW. Loop Back Enable */
 178#define ASM9260_BM_CTRL2_LBE			BIT(7)
 179#define ASM9260_BM_CTRL2_PORT_ENABLE		BIT(0)
 180
 181#define ASM9260_HW_LINECTRL			0x0030
 182/*
 183 * RW. Stick Parity Select. When bits 1, 2, and 7 of this register are set, the
 184 * parity bit is transmitted and checked as a 0. When bits 1 and 7 are set,
 185 * and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this
 186 * bit is cleared stick parity is disabled.
 187 */
 188#define ASM9260_BM_LCTRL_SPS			BIT(7)
 189/* RW. Word length */
 190#define ASM9260_BM_LCTRL_WLEN			(3 << 5)
 191#define ASM9260_BM_LCTRL_CHRL_5			(0 << 5)
 192#define ASM9260_BM_LCTRL_CHRL_6			(1 << 5)
 193#define ASM9260_BM_LCTRL_CHRL_7			(2 << 5)
 194#define ASM9260_BM_LCTRL_CHRL_8			(3 << 5)
 195
 196/*
 197 * Interrupt register.
 198 * contains the interrupt enables and the interrupt status bits
 199 */
 200#define ASM9260_HW_INTR				0x0040
 201/* Tx FIFO EMPTY Raw Interrupt enable */
 202#define ASM9260_BM_INTR_TFEIEN			BIT(27)
 203/* Overrun Error Interrupt Enable. */
 204#define ASM9260_BM_INTR_OEIEN			BIT(26)
 205/* Break Error Interrupt Enable. */
 206#define ASM9260_BM_INTR_BEIEN			BIT(25)
 207/* Parity Error Interrupt Enable. */
 208#define ASM9260_BM_INTR_PEIEN			BIT(24)
 209/* Framing Error Interrupt Enable. */
 210#define ASM9260_BM_INTR_FEIEN			BIT(23)
 211
 212/* nUARTDSR Modem Interrupt Enable. */
 213#define ASM9260_BM_INTR_DSRMIEN			BIT(19)
 214/* nUARTDCD Modem Interrupt Enable. */
 215#define ASM9260_BM_INTR_DCDMIEN			BIT(18)
 216/* nUARTRI Modem Interrupt Enable. */
 217#define ASM9260_BM_INTR_RIMIEN			BIT(16)
 218/* Auto-Boud Timeout */
 219#define ASM9260_BM_INTR_ABTO			BIT(13)
 220#define ASM9260_BM_INTR_ABEO			BIT(12)
 221/* Tx FIFO EMPTY Raw Interrupt state */
 222#define ASM9260_BM_INTR_TFEIS			BIT(11)
 223/* Overrun Error */
 224#define ASM9260_BM_INTR_OEIS			BIT(10)
 225/* Break Error */
 226#define ASM9260_BM_INTR_BEIS			BIT(9)
 227/* Parity Error */
 228#define ASM9260_BM_INTR_PEIS			BIT(8)
 229/* Framing Error */
 230#define ASM9260_BM_INTR_FEIS			BIT(7)
 231#define ASM9260_BM_INTR_DSRMIS			BIT(3)
 232#define ASM9260_BM_INTR_DCDMIS			BIT(2)
 233#define ASM9260_BM_INTR_RIMIS			BIT(0)
 234
 235/*
 236 * RW. In DMA mode, up to 4 Received/Transmit characters can be accessed at a
 237 * time. In PIO mode, only one character can be accessed at a time. The status
 238 * register contains the receive data flags and valid bits.
 239 */
 240#define ASM9260_HW_DATA				0x0050
 241
 242#define ASM9260_HW_STAT				0x0060
 243/* RO. If 1, UARTAPP is present in this product. */
 244#define ASM9260_BM_STAT_PRESENT			BIT(31)
 245/* RO. If 1, HISPEED is present in this product. */
 246#define ASM9260_BM_STAT_HISPEED			BIT(30)
 247/* RO. Receive FIFO Full. */
 248#define ASM9260_BM_STAT_RXFULL			BIT(26)
 249
 250/* RO. The UART Debug Register contains the state of the DMA signals. */
 251#define ASM9260_HW_DEBUG			0x0070
 252/* DMA Command Run Status */
 253#define ASM9260_BM_DEBUG_TXDMARUN		BIT(5)
 254#define ASM9260_BM_DEBUG_RXDMARUN		BIT(4)
 255/* DMA Command End Status */
 256#define ASM9260_BM_DEBUG_TXCMDEND		BIT(3)
 257#define ASM9260_BM_DEBUG_RXCMDEND		BIT(2)
 258/* DMA Request Status */
 259#define ASM9260_BM_DEBUG_TXDMARQ		BIT(1)
 260#define ASM9260_BM_DEBUG_RXDMARQ		BIT(0)
 261
 262#define ASM9260_HW_ILPR				0x0080
 263
 264#define ASM9260_HW_RS485CTRL			0x0090
 265/*
 266 * RW. This bit reverses the polarity of the direction control signal on the RTS
 267 * (or DTR) pin.
 268 * If 0, The direction control pin will be driven to logic ‘0’ when the
 269 * transmitter has data to be sent. It will be driven to logic ‘1’ after the
 270 * last bit of data has been transmitted.
 271 */
 272#define ASM9260_BM_RS485CTRL_ONIV		BIT(5)
 273/* RW. Enable Auto Direction Control. */
 274#define ASM9260_BM_RS485CTRL_DIR_CTRL		BIT(4)
 275/*
 276 * RW. If 0 and DIR_CTRL = 1, pin RTS is used for direction control.
 277 * If 1 and DIR_CTRL = 1, pin DTR is used for direction control.
 278 */
 279#define ASM9260_BM_RS485CTRL_PINSEL		BIT(3)
 280/* RW. Enable Auto Address Detect (AAD). */
 281#define ASM9260_BM_RS485CTRL_AADEN		BIT(2)
 282/* RW. Disable receiver. */
 283#define ASM9260_BM_RS485CTRL_RXDIS		BIT(1)
 284/* RW. Enable RS-485/EIA-485 Normal Multidrop Mode (NMM) */
 285#define ASM9260_BM_RS485CTRL_RS485EN		BIT(0)
 286
 287#define ASM9260_HW_RS485ADRMATCH		0x00a0
 288/* Contains the address match value. */
 289#define ASM9260_BM_RS485ADRMATCH_MASK		(0xff << 0)
 290
 291#define ASM9260_HW_RS485DLY			0x00b0
 292/*
 293 * RW. Contains the direction control (RTS or DTR) delay value. This delay time
 294 * is in periods of the baud clock.
 295 */
 296#define ASM9260_BM_RS485DLY_MASK		(0xff << 0)
 297
 298#define ASM9260_HW_AUTOBAUD			0x00c0
 299/* WO. Auto-baud time-out interrupt clear bit. */
 300#define ASM9260_BM_AUTOBAUD_TO_INT_CLR		BIT(9)
 301/* WO. End of auto-baud interrupt clear bit. */
 302#define ASM9260_BM_AUTOBAUD_EO_INT_CLR		BIT(8)
 303/* Restart in case of timeout (counter restarts at next UART Rx falling edge) */
 304#define ASM9260_BM_AUTOBAUD_AUTORESTART		BIT(2)
 305/* Auto-baud mode select bit. 0 - Mode 0, 1 - Mode 1. */
 306#define ASM9260_BM_AUTOBAUD_MODE		BIT(1)
 307/*
 308 * Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is
 309 * automatically cleared after auto-baud completion.
 310 */
 311#define ASM9260_BM_AUTOBAUD_START		BIT(0)
 312
 313#define ASM9260_HW_CTRL3			0x00d0
 314#define ASM9260_BM_CTRL3_OUTCLK_DIV_MASK	(0xffff << 16)
 315/*
 316 * RW. Provide clk over OUTCLK pin. In case of asm9260 it can be configured on
 317 * pins 137 and 144.
 318 */
 319#define ASM9260_BM_CTRL3_MASTERMODE		BIT(6)
 320/* RW. Baud Rate Mode: 1 - Enable sync mode. 0 - async mode. */
 321#define ASM9260_BM_CTRL3_SYNCMODE		BIT(4)
 322/* RW. 1 - MSB bit send frist; 0 - LSB bit frist. */
 323#define ASM9260_BM_CTRL3_MSBF			BIT(2)
 324/* RW. 1 - sample rate = 8 x Baudrate; 0 - sample rate = 16 x Baudrate. */
 325#define ASM9260_BM_CTRL3_BAUD8			BIT(1)
 326/* RW. 1 - Set word length to 9bit. 0 - use ASM9260_BM_LCTRL_WLEN */
 327#define ASM9260_BM_CTRL3_9BIT			BIT(0)
 328
 329#define ASM9260_HW_ISO7816_CTRL			0x00e0
 330/* RW. Enable High Speed mode. */
 331#define ASM9260_BM_ISO7816CTRL_HS		BIT(12)
 332/* Disable Successive Receive NACK */
 333#define ASM9260_BM_ISO7816CTRL_DS_NACK		BIT(8)
 334#define ASM9260_BM_ISO7816CTRL_MAX_ITER_MASK	(0xff << 4)
 335/* Receive NACK Inhibit */
 336#define ASM9260_BM_ISO7816CTRL_INACK		BIT(3)
 337#define ASM9260_BM_ISO7816CTRL_NEG_DATA		BIT(2)
 338/* RW. 1 - ISO7816 mode; 0 - USART mode */
 339#define ASM9260_BM_ISO7816CTRL_ENABLE		BIT(0)
 340
 341#define ASM9260_HW_ISO7816_ERRCNT		0x00f0
 342/* Parity error counter. Will be cleared after reading */
 343#define ASM9260_BM_ISO7816_NB_ERRORS_MASK	(0xff << 0)
 344
 345#define ASM9260_HW_ISO7816_STATUS		0x0100
 346/* Max number of Repetitions Reached */
 347#define ASM9260_BM_ISO7816_STAT_ITERATION	BIT(0)
 348
 349/* End of Alphascale asm9260 defines */
 350
 351static struct uart_driver auart_driver;
 352
 353enum mxs_auart_type {
 354	IMX23_AUART,
 355	IMX28_AUART,
 356	ASM9260_AUART,
 357};
 358
 359struct vendor_data {
 360	const u16	*reg_offset;
 361};
 362
 363enum {
 364	REG_CTRL0,
 365	REG_CTRL1,
 366	REG_CTRL2,
 367	REG_LINECTRL,
 368	REG_LINECTRL2,
 369	REG_INTR,
 370	REG_DATA,
 371	REG_STAT,
 372	REG_DEBUG,
 373	REG_VERSION,
 374	REG_AUTOBAUD,
 375
 376	/* The size of the array - must be last */
 377	REG_ARRAY_SIZE,
 378};
 379
 380static const u16 mxs_asm9260_offsets[REG_ARRAY_SIZE] = {
 381	[REG_CTRL0] = ASM9260_HW_CTRL0,
 382	[REG_CTRL1] = ASM9260_HW_CTRL1,
 383	[REG_CTRL2] = ASM9260_HW_CTRL2,
 384	[REG_LINECTRL] = ASM9260_HW_LINECTRL,
 385	[REG_INTR] = ASM9260_HW_INTR,
 386	[REG_DATA] = ASM9260_HW_DATA,
 387	[REG_STAT] = ASM9260_HW_STAT,
 388	[REG_DEBUG] = ASM9260_HW_DEBUG,
 389	[REG_AUTOBAUD] = ASM9260_HW_AUTOBAUD,
 390};
 391
 392static const u16 mxs_stmp37xx_offsets[REG_ARRAY_SIZE] = {
 393	[REG_CTRL0] = AUART_CTRL0,
 394	[REG_CTRL1] = AUART_CTRL1,
 395	[REG_CTRL2] = AUART_CTRL2,
 396	[REG_LINECTRL] = AUART_LINECTRL,
 397	[REG_LINECTRL2] = AUART_LINECTRL2,
 398	[REG_INTR] = AUART_INTR,
 399	[REG_DATA] = AUART_DATA,
 400	[REG_STAT] = AUART_STAT,
 401	[REG_DEBUG] = AUART_DEBUG,
 402	[REG_VERSION] = AUART_VERSION,
 403	[REG_AUTOBAUD] = AUART_AUTOBAUD,
 404};
 405
 406static const struct vendor_data vendor_alphascale_asm9260 = {
 407	.reg_offset = mxs_asm9260_offsets,
 408};
 409
 410static const struct vendor_data vendor_freescale_stmp37xx = {
 411	.reg_offset = mxs_stmp37xx_offsets,
 412};
 413
 414struct mxs_auart_port {
 415	struct uart_port port;
 416
 417#define MXS_AUART_DMA_ENABLED	0x2
 418#define MXS_AUART_DMA_TX_SYNC	2  /* bit 2 */
 419#define MXS_AUART_DMA_RX_READY	3  /* bit 3 */
 420#define MXS_AUART_RTSCTS	4  /* bit 4 */
 421	unsigned long flags;
 422	unsigned int mctrl_prev;
 423	enum mxs_auart_type devtype;
 424	const struct vendor_data *vendor;
 425
 426	struct clk *clk;
 427	struct clk *clk_ahb;
 428	struct device *dev;
 429
 430	/* for DMA */
 431	struct scatterlist tx_sgl;
 432	struct dma_chan	*tx_dma_chan;
 433	void *tx_dma_buf;
 434
 435	struct scatterlist rx_sgl;
 436	struct dma_chan	*rx_dma_chan;
 437	void *rx_dma_buf;
 438
 439	struct mctrl_gpios	*gpios;
 440	int			gpio_irq[UART_GPIO_MAX];
 441	bool			ms_irq_enabled;
 442};
 443
 444static const struct of_device_id mxs_auart_dt_ids[] = {
 445	{
 446		.compatible = "fsl,imx28-auart",
 447		.data = (const void *)IMX28_AUART
 448	}, {
 449		.compatible = "fsl,imx23-auart",
 450		.data = (const void *)IMX23_AUART
 451	}, {
 452		.compatible = "alphascale,asm9260-auart",
 453		.data = (const void *)ASM9260_AUART
 454	}, { /* sentinel */ }
 455};
 456MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
 457
 458static inline int is_imx28_auart(struct mxs_auart_port *s)
 459{
 460	return s->devtype == IMX28_AUART;
 461}
 462
 463static inline int is_asm9260_auart(struct mxs_auart_port *s)
 464{
 465	return s->devtype == ASM9260_AUART;
 466}
 467
 468static inline bool auart_dma_enabled(struct mxs_auart_port *s)
 469{
 470	return s->flags & MXS_AUART_DMA_ENABLED;
 471}
 472
 473static unsigned int mxs_reg_to_offset(const struct mxs_auart_port *uap,
 474				      unsigned int reg)
 475{
 476	return uap->vendor->reg_offset[reg];
 477}
 478
 479static unsigned int mxs_read(const struct mxs_auart_port *uap,
 480			     unsigned int reg)
 481{
 482	void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
 483
 484	return readl_relaxed(addr);
 485}
 486
 487static void mxs_write(unsigned int val, struct mxs_auart_port *uap,
 488		      unsigned int reg)
 489{
 490	void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
 491
 492	writel_relaxed(val, addr);
 493}
 494
 495static void mxs_set(unsigned int val, struct mxs_auart_port *uap,
 496		    unsigned int reg)
 497{
 498	void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
 499
 500	writel_relaxed(val, addr + SET_REG);
 501}
 502
 503static void mxs_clr(unsigned int val, struct mxs_auart_port *uap,
 504		    unsigned int reg)
 505{
 506	void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg);
 507
 508	writel_relaxed(val, addr + CLR_REG);
 509}
 510
 511static void mxs_auart_stop_tx(struct uart_port *u);
 512
 513#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
 514
 515static void mxs_auart_tx_chars(struct mxs_auart_port *s);
 516
 517static void dma_tx_callback(void *param)
 518{
 519	struct mxs_auart_port *s = param;
 520	struct circ_buf *xmit = &s->port.state->xmit;
 521
 522	dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
 523
 524	/* clear the bit used to serialize the DMA tx. */
 525	clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
 526	smp_mb__after_atomic();
 527
 528	/* wake up the possible processes. */
 529	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 530		uart_write_wakeup(&s->port);
 531
 532	mxs_auart_tx_chars(s);
 533}
 534
 535static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
 536{
 537	struct dma_async_tx_descriptor *desc;
 538	struct scatterlist *sgl = &s->tx_sgl;
 539	struct dma_chan *channel = s->tx_dma_chan;
 540	u32 pio;
 541
 542	/* [1] : send PIO. Note, the first pio word is CTRL1. */
 543	pio = AUART_CTRL1_XFER_COUNT(size);
 544	desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
 545					1, DMA_TRANS_NONE, 0);
 546	if (!desc) {
 547		dev_err(s->dev, "step 1 error\n");
 548		return -EINVAL;
 549	}
 550
 551	/* [2] : set DMA buffer. */
 552	sg_init_one(sgl, s->tx_dma_buf, size);
 553	dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
 554	desc = dmaengine_prep_slave_sg(channel, sgl,
 555			1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 556	if (!desc) {
 557		dev_err(s->dev, "step 2 error\n");
 558		return -EINVAL;
 559	}
 560
 561	/* [3] : submit the DMA */
 562	desc->callback = dma_tx_callback;
 563	desc->callback_param = s;
 564	dmaengine_submit(desc);
 565	dma_async_issue_pending(channel);
 566	return 0;
 567}
 568
 569static void mxs_auart_tx_chars(struct mxs_auart_port *s)
 570{
 571	struct circ_buf *xmit = &s->port.state->xmit;
 572	bool pending;
 573	u8 ch;
 574
 575	if (auart_dma_enabled(s)) {
 576		u32 i = 0;
 577		int size;
 578		void *buffer = s->tx_dma_buf;
 579
 580		if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
 581			return;
 582
 583		while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
 584			size = min_t(u32, UART_XMIT_SIZE - i,
 585				     CIRC_CNT_TO_END(xmit->head,
 586						     xmit->tail,
 587						     UART_XMIT_SIZE));
 588			memcpy(buffer + i, xmit->buf + xmit->tail, size);
 589			xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
 590
 591			i += size;
 592			if (i >= UART_XMIT_SIZE)
 593				break;
 594		}
 595
 596		if (uart_tx_stopped(&s->port))
 597			mxs_auart_stop_tx(&s->port);
 598
 599		if (i) {
 600			mxs_auart_dma_tx(s, i);
 601		} else {
 602			clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
 603			smp_mb__after_atomic();
 604		}
 605		return;
 606	}
 607
 608	pending = uart_port_tx_flags(&s->port, ch, UART_TX_NOSTOP,
 609		!(mxs_read(s, REG_STAT) & AUART_STAT_TXFF),
 610		mxs_write(ch, s, REG_DATA));
 611	if (pending)
 612		mxs_set(AUART_INTR_TXIEN, s, REG_INTR);
 613	else
 
 
 
 
 
 
 
 
 
 
 
 
 
 614		mxs_clr(AUART_INTR_TXIEN, s, REG_INTR);
 
 
 615
 616	if (uart_tx_stopped(&s->port))
 617               mxs_auart_stop_tx(&s->port);
 618}
 619
 620static void mxs_auart_rx_char(struct mxs_auart_port *s)
 621{
 
 622	u32 stat;
 623	u8 c, flag;
 624
 625	c = mxs_read(s, REG_DATA);
 626	stat = mxs_read(s, REG_STAT);
 627
 628	flag = TTY_NORMAL;
 629	s->port.icount.rx++;
 630
 631	if (stat & AUART_STAT_BERR) {
 632		s->port.icount.brk++;
 633		if (uart_handle_break(&s->port))
 634			goto out;
 635	} else if (stat & AUART_STAT_PERR) {
 636		s->port.icount.parity++;
 637	} else if (stat & AUART_STAT_FERR) {
 638		s->port.icount.frame++;
 639	}
 640
 641	/*
 642	 * Mask off conditions which should be ingored.
 643	 */
 644	stat &= s->port.read_status_mask;
 645
 646	if (stat & AUART_STAT_BERR) {
 647		flag = TTY_BREAK;
 648	} else if (stat & AUART_STAT_PERR)
 649		flag = TTY_PARITY;
 650	else if (stat & AUART_STAT_FERR)
 651		flag = TTY_FRAME;
 652
 653	if (stat & AUART_STAT_OERR)
 654		s->port.icount.overrun++;
 655
 656	if (uart_handle_sysrq_char(&s->port, c))
 657		goto out;
 658
 659	uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
 660out:
 661	mxs_write(stat, s, REG_STAT);
 662}
 663
 664static void mxs_auart_rx_chars(struct mxs_auart_port *s)
 665{
 666	u32 stat = 0;
 667
 668	for (;;) {
 669		stat = mxs_read(s, REG_STAT);
 670		if (stat & AUART_STAT_RXFE)
 671			break;
 672		mxs_auart_rx_char(s);
 673	}
 674
 675	mxs_write(stat, s, REG_STAT);
 676	tty_flip_buffer_push(&s->port.state->port);
 677}
 678
 679static int mxs_auart_request_port(struct uart_port *u)
 680{
 681	return 0;
 682}
 683
 684static int mxs_auart_verify_port(struct uart_port *u,
 685				    struct serial_struct *ser)
 686{
 687	if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
 688		return -EINVAL;
 689	return 0;
 690}
 691
 692static void mxs_auart_config_port(struct uart_port *u, int flags)
 693{
 694}
 695
 696static const char *mxs_auart_type(struct uart_port *u)
 697{
 698	struct mxs_auart_port *s = to_auart_port(u);
 699
 700	return dev_name(s->dev);
 701}
 702
 703static void mxs_auart_release_port(struct uart_port *u)
 704{
 705}
 706
 707static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
 708{
 709	struct mxs_auart_port *s = to_auart_port(u);
 710
 711	u32 ctrl = mxs_read(s, REG_CTRL2);
 712
 713	ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);
 714	if (mctrl & TIOCM_RTS) {
 715		if (uart_cts_enabled(u))
 716			ctrl |= AUART_CTRL2_RTSEN;
 717		else
 718			ctrl |= AUART_CTRL2_RTS;
 719	}
 720
 721	mxs_write(ctrl, s, REG_CTRL2);
 722
 723	mctrl_gpio_set(s->gpios, mctrl);
 724}
 725
 726#define MCTRL_ANY_DELTA        (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS)
 727static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl)
 728{
 729	u32 mctrl_diff;
 730
 731	mctrl_diff = mctrl ^ s->mctrl_prev;
 732	s->mctrl_prev = mctrl;
 733	if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled &&
 734						s->port.state != NULL) {
 735		if (mctrl_diff & TIOCM_RI)
 736			s->port.icount.rng++;
 737		if (mctrl_diff & TIOCM_DSR)
 738			s->port.icount.dsr++;
 739		if (mctrl_diff & TIOCM_CD)
 740			uart_handle_dcd_change(&s->port, mctrl & TIOCM_CD);
 741		if (mctrl_diff & TIOCM_CTS)
 742			uart_handle_cts_change(&s->port, mctrl & TIOCM_CTS);
 743
 744		wake_up_interruptible(&s->port.state->port.delta_msr_wait);
 745	}
 746	return mctrl;
 747}
 748
 749static u32 mxs_auart_get_mctrl(struct uart_port *u)
 750{
 751	struct mxs_auart_port *s = to_auart_port(u);
 752	u32 stat = mxs_read(s, REG_STAT);
 753	u32 mctrl = 0;
 754
 755	if (stat & AUART_STAT_CTS)
 756		mctrl |= TIOCM_CTS;
 757
 758	return mctrl_gpio_get(s->gpios, &mctrl);
 759}
 760
 761/*
 762 * Enable modem status interrupts
 763 */
 764static void mxs_auart_enable_ms(struct uart_port *port)
 765{
 766	struct mxs_auart_port *s = to_auart_port(port);
 767
 768	/*
 769	 * Interrupt should not be enabled twice
 770	 */
 771	if (s->ms_irq_enabled)
 772		return;
 773
 774	s->ms_irq_enabled = true;
 775
 776	if (s->gpio_irq[UART_GPIO_CTS] >= 0)
 777		enable_irq(s->gpio_irq[UART_GPIO_CTS]);
 778	/* TODO: enable AUART_INTR_CTSMIEN otherwise */
 779
 780	if (s->gpio_irq[UART_GPIO_DSR] >= 0)
 781		enable_irq(s->gpio_irq[UART_GPIO_DSR]);
 782
 783	if (s->gpio_irq[UART_GPIO_RI] >= 0)
 784		enable_irq(s->gpio_irq[UART_GPIO_RI]);
 785
 786	if (s->gpio_irq[UART_GPIO_DCD] >= 0)
 787		enable_irq(s->gpio_irq[UART_GPIO_DCD]);
 788}
 789
 790/*
 791 * Disable modem status interrupts
 792 */
 793static void mxs_auart_disable_ms(struct uart_port *port)
 794{
 795	struct mxs_auart_port *s = to_auart_port(port);
 796
 797	/*
 798	 * Interrupt should not be disabled twice
 799	 */
 800	if (!s->ms_irq_enabled)
 801		return;
 802
 803	s->ms_irq_enabled = false;
 804
 805	if (s->gpio_irq[UART_GPIO_CTS] >= 0)
 806		disable_irq(s->gpio_irq[UART_GPIO_CTS]);
 807	/* TODO: disable AUART_INTR_CTSMIEN otherwise */
 808
 809	if (s->gpio_irq[UART_GPIO_DSR] >= 0)
 810		disable_irq(s->gpio_irq[UART_GPIO_DSR]);
 811
 812	if (s->gpio_irq[UART_GPIO_RI] >= 0)
 813		disable_irq(s->gpio_irq[UART_GPIO_RI]);
 814
 815	if (s->gpio_irq[UART_GPIO_DCD] >= 0)
 816		disable_irq(s->gpio_irq[UART_GPIO_DCD]);
 817}
 818
 819static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
 820static void dma_rx_callback(void *arg)
 821{
 822	struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
 823	struct tty_port *port = &s->port.state->port;
 824	int count;
 825	u32 stat;
 826
 827	dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);
 828
 829	stat = mxs_read(s, REG_STAT);
 830	stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
 831			AUART_STAT_PERR | AUART_STAT_FERR);
 832
 833	count = stat & AUART_STAT_RXCOUNT_MASK;
 834	tty_insert_flip_string(port, s->rx_dma_buf, count);
 835
 836	mxs_write(stat, s, REG_STAT);
 837	tty_flip_buffer_push(port);
 838
 839	/* start the next DMA for RX. */
 840	mxs_auart_dma_prep_rx(s);
 841}
 842
 843static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
 844{
 845	struct dma_async_tx_descriptor *desc;
 846	struct scatterlist *sgl = &s->rx_sgl;
 847	struct dma_chan *channel = s->rx_dma_chan;
 848	u32 pio[1];
 849
 850	/* [1] : send PIO */
 851	pio[0] = AUART_CTRL0_RXTO_ENABLE
 852		| AUART_CTRL0_RXTIMEOUT(0x80)
 853		| AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
 854	desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
 855					1, DMA_TRANS_NONE, 0);
 856	if (!desc) {
 857		dev_err(s->dev, "step 1 error\n");
 858		return -EINVAL;
 859	}
 860
 861	/* [2] : send DMA request */
 862	sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
 863	dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
 864	desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
 865					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 866	if (!desc) {
 867		dev_err(s->dev, "step 2 error\n");
 868		return -1;
 869	}
 870
 871	/* [3] : submit the DMA, but do not issue it. */
 872	desc->callback = dma_rx_callback;
 873	desc->callback_param = s;
 874	dmaengine_submit(desc);
 875	dma_async_issue_pending(channel);
 876	return 0;
 877}
 878
 879static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
 880{
 881	if (s->tx_dma_chan) {
 882		dma_release_channel(s->tx_dma_chan);
 883		s->tx_dma_chan = NULL;
 884	}
 885	if (s->rx_dma_chan) {
 886		dma_release_channel(s->rx_dma_chan);
 887		s->rx_dma_chan = NULL;
 888	}
 889
 890	kfree(s->tx_dma_buf);
 891	kfree(s->rx_dma_buf);
 892	s->tx_dma_buf = NULL;
 893	s->rx_dma_buf = NULL;
 894}
 895
 896static void mxs_auart_dma_exit(struct mxs_auart_port *s)
 897{
 898
 899	mxs_clr(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
 900		s, REG_CTRL2);
 901
 902	mxs_auart_dma_exit_channel(s);
 903	s->flags &= ~MXS_AUART_DMA_ENABLED;
 904	clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
 905	clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
 906}
 907
 908static int mxs_auart_dma_init(struct mxs_auart_port *s)
 909{
 910	struct dma_chan *chan;
 911
 912	if (auart_dma_enabled(s))
 913		return 0;
 914
 915	/* init for RX */
 916	chan = dma_request_chan(s->dev, "rx");
 917	if (IS_ERR(chan))
 918		goto err_out;
 919	s->rx_dma_chan = chan;
 920
 921	s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
 922	if (!s->rx_dma_buf)
 923		goto err_out;
 924
 925	/* init for TX */
 926	chan = dma_request_chan(s->dev, "tx");
 927	if (IS_ERR(chan))
 928		goto err_out;
 929	s->tx_dma_chan = chan;
 930
 931	s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
 932	if (!s->tx_dma_buf)
 933		goto err_out;
 934
 935	/* set the flags */
 936	s->flags |= MXS_AUART_DMA_ENABLED;
 937	dev_dbg(s->dev, "enabled the DMA support.");
 938
 939	/* The DMA buffer is now the FIFO the TTY subsystem can use */
 940	s->port.fifosize = UART_XMIT_SIZE;
 941
 942	return 0;
 943
 944err_out:
 945	mxs_auart_dma_exit_channel(s);
 946	return -EINVAL;
 947
 948}
 949
 950#define RTS_AT_AUART()	!mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_RTS)
 951#define CTS_AT_AUART()	!mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_CTS)
 952static void mxs_auart_settermios(struct uart_port *u,
 953				 struct ktermios *termios,
 954				 const struct ktermios *old)
 955{
 956	struct mxs_auart_port *s = to_auart_port(u);
 957	u32 ctrl, ctrl2, div;
 958	unsigned int cflag, baud, baud_min, baud_max;
 959
 960	cflag = termios->c_cflag;
 961
 962	ctrl = AUART_LINECTRL_FEN;
 963	ctrl2 = mxs_read(s, REG_CTRL2);
 964
 965	ctrl |= AUART_LINECTRL_WLEN(tty_get_char_size(cflag));
 966
 967	/* parity */
 968	if (cflag & PARENB) {
 969		ctrl |= AUART_LINECTRL_PEN;
 970		if ((cflag & PARODD) == 0)
 971			ctrl |= AUART_LINECTRL_EPS;
 972		if (cflag & CMSPAR)
 973			ctrl |= AUART_LINECTRL_SPS;
 974	}
 975
 976	u->read_status_mask = AUART_STAT_OERR;
 977
 978	if (termios->c_iflag & INPCK)
 979		u->read_status_mask |= AUART_STAT_PERR;
 980	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
 981		u->read_status_mask |= AUART_STAT_BERR;
 982
 983	/*
 984	 * Characters to ignore
 985	 */
 986	u->ignore_status_mask = 0;
 987	if (termios->c_iflag & IGNPAR)
 988		u->ignore_status_mask |= AUART_STAT_PERR;
 989	if (termios->c_iflag & IGNBRK) {
 990		u->ignore_status_mask |= AUART_STAT_BERR;
 991		/*
 992		 * If we're ignoring parity and break indicators,
 993		 * ignore overruns too (for real raw support).
 994		 */
 995		if (termios->c_iflag & IGNPAR)
 996			u->ignore_status_mask |= AUART_STAT_OERR;
 997	}
 998
 999	/*
1000	 * ignore all characters if CREAD is not set
1001	 */
1002	if (cflag & CREAD)
1003		ctrl2 |= AUART_CTRL2_RXE;
1004	else
1005		ctrl2 &= ~AUART_CTRL2_RXE;
1006
1007	/* figure out the stop bits requested */
1008	if (cflag & CSTOPB)
1009		ctrl |= AUART_LINECTRL_STP2;
1010
1011	/* figure out the hardware flow control settings */
1012	ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
1013	if (cflag & CRTSCTS) {
1014		/*
1015		 * The DMA has a bug(see errata:2836) in mx23.
1016		 * So we can not implement the DMA for auart in mx23,
1017		 * we can only implement the DMA support for auart
1018		 * in mx28.
1019		 */
1020		if (is_imx28_auart(s)
1021				&& test_bit(MXS_AUART_RTSCTS, &s->flags)) {
1022			if (!mxs_auart_dma_init(s))
1023				/* enable DMA tranfer */
1024				ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
1025				       | AUART_CTRL2_DMAONERR;
1026		}
1027		/* Even if RTS is GPIO line RTSEN can be enabled because
1028		 * the pinctrl configuration decides about RTS pin function */
1029		ctrl2 |= AUART_CTRL2_RTSEN;
1030		if (CTS_AT_AUART())
1031			ctrl2 |= AUART_CTRL2_CTSEN;
1032	}
1033
1034	/* set baud rate */
1035	if (is_asm9260_auart(s)) {
1036		baud = uart_get_baud_rate(u, termios, old,
1037					  u->uartclk * 4 / 0x3FFFFF,
1038					  u->uartclk / 16);
1039		div = u->uartclk * 4 / baud;
1040	} else {
1041		baud_min = DIV_ROUND_UP(u->uartclk * 32,
1042					AUART_LINECTRL_BAUD_DIV_MAX);
1043		baud_max = u->uartclk * 32 / AUART_LINECTRL_BAUD_DIV_MIN;
1044		baud = uart_get_baud_rate(u, termios, old, baud_min, baud_max);
1045		div = DIV_ROUND_CLOSEST(u->uartclk * 32, baud);
1046	}
1047
1048	ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
1049	ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
1050	mxs_write(ctrl, s, REG_LINECTRL);
1051
1052	mxs_write(ctrl2, s, REG_CTRL2);
1053
1054	uart_update_timeout(u, termios->c_cflag, baud);
1055
1056	/* prepare for the DMA RX. */
1057	if (auart_dma_enabled(s) &&
1058		!test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
1059		if (!mxs_auart_dma_prep_rx(s)) {
1060			/* Disable the normal RX interrupt. */
1061			mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN,
1062				s, REG_INTR);
1063		} else {
1064			mxs_auart_dma_exit(s);
1065			dev_err(s->dev, "We can not start up the DMA.\n");
1066		}
1067	}
1068
1069	/* CTS flow-control and modem-status interrupts */
1070	if (UART_ENABLE_MS(u, termios->c_cflag))
1071		mxs_auart_enable_ms(u);
1072	else
1073		mxs_auart_disable_ms(u);
1074}
1075
1076static void mxs_auart_set_ldisc(struct uart_port *port,
1077				struct ktermios *termios)
1078{
1079	if (termios->c_line == N_PPS) {
1080		port->flags |= UPF_HARDPPS_CD;
1081		mxs_auart_enable_ms(port);
1082	} else {
1083		port->flags &= ~UPF_HARDPPS_CD;
1084	}
1085}
1086
1087static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
1088{
1089	u32 istat;
1090	struct mxs_auart_port *s = context;
1091	u32 mctrl_temp = s->mctrl_prev;
1092	u32 stat = mxs_read(s, REG_STAT);
1093
1094	istat = mxs_read(s, REG_INTR);
1095
1096	/* ack irq */
1097	mxs_clr(istat & (AUART_INTR_RTIS | AUART_INTR_TXIS | AUART_INTR_RXIS
1098		| AUART_INTR_CTSMIS), s, REG_INTR);
1099
1100	/*
1101	 * Dealing with GPIO interrupt
1102	 */
1103	if (irq == s->gpio_irq[UART_GPIO_CTS] ||
1104	    irq == s->gpio_irq[UART_GPIO_DCD] ||
1105	    irq == s->gpio_irq[UART_GPIO_DSR] ||
1106	    irq == s->gpio_irq[UART_GPIO_RI])
1107		mxs_auart_modem_status(s,
1108				mctrl_gpio_get(s->gpios, &mctrl_temp));
1109
1110	if (istat & AUART_INTR_CTSMIS) {
1111		if (CTS_AT_AUART() && s->ms_irq_enabled)
1112			uart_handle_cts_change(&s->port,
1113					stat & AUART_STAT_CTS);
1114		mxs_clr(AUART_INTR_CTSMIS, s, REG_INTR);
1115		istat &= ~AUART_INTR_CTSMIS;
1116	}
1117
1118	if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
1119		if (!auart_dma_enabled(s))
1120			mxs_auart_rx_chars(s);
1121		istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
1122	}
1123
1124	if (istat & AUART_INTR_TXIS) {
1125		mxs_auart_tx_chars(s);
1126		istat &= ~AUART_INTR_TXIS;
1127	}
1128
1129	return IRQ_HANDLED;
1130}
1131
1132static void mxs_auart_reset_deassert(struct mxs_auart_port *s)
1133{
1134	int i;
1135	unsigned int reg;
1136
1137	mxs_clr(AUART_CTRL0_SFTRST, s, REG_CTRL0);
1138
1139	for (i = 0; i < 10000; i++) {
1140		reg = mxs_read(s, REG_CTRL0);
1141		if (!(reg & AUART_CTRL0_SFTRST))
1142			break;
1143		udelay(3);
1144	}
1145	mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1146}
1147
1148static void mxs_auart_reset_assert(struct mxs_auart_port *s)
1149{
1150	int i;
1151	u32 reg;
1152
1153	reg = mxs_read(s, REG_CTRL0);
1154	/* if already in reset state, keep it untouched */
1155	if (reg & AUART_CTRL0_SFTRST)
1156		return;
1157
1158	mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1159	mxs_set(AUART_CTRL0_SFTRST, s, REG_CTRL0);
1160
1161	for (i = 0; i < 1000; i++) {
1162		reg = mxs_read(s, REG_CTRL0);
1163		/* reset is finished when the clock is gated */
1164		if (reg & AUART_CTRL0_CLKGATE)
1165			return;
1166		udelay(10);
1167	}
1168
1169	dev_err(s->dev, "Failed to reset the unit.");
1170}
1171
1172static int mxs_auart_startup(struct uart_port *u)
1173{
1174	int ret;
1175	struct mxs_auart_port *s = to_auart_port(u);
1176
1177	ret = clk_prepare_enable(s->clk);
1178	if (ret)
1179		return ret;
1180
1181	if (uart_console(u)) {
1182		mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1183	} else {
1184		/* reset the unit to a well known state */
1185		mxs_auart_reset_assert(s);
1186		mxs_auart_reset_deassert(s);
1187	}
1188
1189	mxs_set(AUART_CTRL2_UARTEN, s, REG_CTRL2);
1190
1191	mxs_write(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
1192		  s, REG_INTR);
1193
1194	/* Reset FIFO size (it could have changed if DMA was enabled) */
1195	u->fifosize = MXS_AUART_FIFO_SIZE;
1196
1197	/*
1198	 * Enable fifo so all four bytes of a DMA word are written to
1199	 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
1200	 */
1201	mxs_set(AUART_LINECTRL_FEN, s, REG_LINECTRL);
1202
1203	/* get initial status of modem lines */
1204	mctrl_gpio_get(s->gpios, &s->mctrl_prev);
1205
1206	s->ms_irq_enabled = false;
1207	return 0;
1208}
1209
1210static void mxs_auart_shutdown(struct uart_port *u)
1211{
1212	struct mxs_auart_port *s = to_auart_port(u);
1213
1214	mxs_auart_disable_ms(u);
1215
1216	if (auart_dma_enabled(s))
1217		mxs_auart_dma_exit(s);
1218
1219	if (uart_console(u)) {
1220		mxs_clr(AUART_CTRL2_UARTEN, s, REG_CTRL2);
1221
1222		mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN |
1223			AUART_INTR_CTSMIEN, s, REG_INTR);
1224		mxs_set(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1225	} else {
1226		mxs_auart_reset_assert(s);
1227	}
1228
1229	clk_disable_unprepare(s->clk);
1230}
1231
1232static unsigned int mxs_auart_tx_empty(struct uart_port *u)
1233{
1234	struct mxs_auart_port *s = to_auart_port(u);
1235
1236	if ((mxs_read(s, REG_STAT) &
1237		 (AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE)
1238		return TIOCSER_TEMT;
1239
1240	return 0;
1241}
1242
1243static void mxs_auart_start_tx(struct uart_port *u)
1244{
1245	struct mxs_auart_port *s = to_auart_port(u);
1246
1247	/* enable transmitter */
1248	mxs_set(AUART_CTRL2_TXE, s, REG_CTRL2);
1249
1250	mxs_auart_tx_chars(s);
1251}
1252
1253static void mxs_auart_stop_tx(struct uart_port *u)
1254{
1255	struct mxs_auart_port *s = to_auart_port(u);
1256
1257	mxs_clr(AUART_CTRL2_TXE, s, REG_CTRL2);
1258}
1259
1260static void mxs_auart_stop_rx(struct uart_port *u)
1261{
1262	struct mxs_auart_port *s = to_auart_port(u);
1263
1264	mxs_clr(AUART_CTRL2_RXE, s, REG_CTRL2);
1265}
1266
1267static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
1268{
1269	struct mxs_auart_port *s = to_auart_port(u);
1270
1271	if (ctl)
1272		mxs_set(AUART_LINECTRL_BRK, s, REG_LINECTRL);
1273	else
1274		mxs_clr(AUART_LINECTRL_BRK, s, REG_LINECTRL);
1275}
1276
1277static const struct uart_ops mxs_auart_ops = {
1278	.tx_empty       = mxs_auart_tx_empty,
1279	.start_tx       = mxs_auart_start_tx,
1280	.stop_tx	= mxs_auart_stop_tx,
1281	.stop_rx	= mxs_auart_stop_rx,
1282	.enable_ms      = mxs_auart_enable_ms,
1283	.break_ctl      = mxs_auart_break_ctl,
1284	.set_mctrl	= mxs_auart_set_mctrl,
1285	.get_mctrl      = mxs_auart_get_mctrl,
1286	.startup	= mxs_auart_startup,
1287	.shutdown       = mxs_auart_shutdown,
1288	.set_termios    = mxs_auart_settermios,
1289	.set_ldisc      = mxs_auart_set_ldisc,
1290	.type	   	= mxs_auart_type,
1291	.release_port   = mxs_auart_release_port,
1292	.request_port   = mxs_auart_request_port,
1293	.config_port    = mxs_auart_config_port,
1294	.verify_port    = mxs_auart_verify_port,
1295};
1296
1297static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
1298
1299#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1300static void mxs_auart_console_putchar(struct uart_port *port, unsigned char ch)
1301{
1302	struct mxs_auart_port *s = to_auart_port(port);
1303	unsigned int to = 1000;
1304
1305	while (mxs_read(s, REG_STAT) & AUART_STAT_TXFF) {
1306		if (!to--)
1307			break;
1308		udelay(1);
1309	}
1310
1311	mxs_write(ch, s, REG_DATA);
1312}
1313
1314static void
1315auart_console_write(struct console *co, const char *str, unsigned int count)
1316{
1317	struct mxs_auart_port *s;
1318	struct uart_port *port;
1319	unsigned int old_ctrl0, old_ctrl2;
1320	unsigned int to = 20000;
1321
1322	if (co->index >= MXS_AUART_PORTS || co->index < 0)
1323		return;
1324
1325	s = auart_port[co->index];
1326	port = &s->port;
1327
1328	clk_enable(s->clk);
1329
1330	/* First save the CR then disable the interrupts */
1331	old_ctrl2 = mxs_read(s, REG_CTRL2);
1332	old_ctrl0 = mxs_read(s, REG_CTRL0);
1333
1334	mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0);
1335	mxs_set(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, s, REG_CTRL2);
1336
1337	uart_console_write(port, str, count, mxs_auart_console_putchar);
1338
1339	/* Finally, wait for transmitter to become empty ... */
1340	while (mxs_read(s, REG_STAT) & AUART_STAT_BUSY) {
1341		udelay(1);
1342		if (!to--)
1343			break;
1344	}
1345
1346	/*
1347	 * ... and restore the TCR if we waited long enough for the transmitter
1348	 * to be idle. This might keep the transmitter enabled although it is
1349	 * unused, but that is better than to disable it while it is still
1350	 * transmitting.
1351	 */
1352	if (!(mxs_read(s, REG_STAT) & AUART_STAT_BUSY)) {
1353		mxs_write(old_ctrl0, s, REG_CTRL0);
1354		mxs_write(old_ctrl2, s, REG_CTRL2);
1355	}
1356
1357	clk_disable(s->clk);
1358}
1359
1360static void __init
1361auart_console_get_options(struct mxs_auart_port *s, int *baud,
1362			  int *parity, int *bits)
1363{
1364	struct uart_port *port = &s->port;
1365	unsigned int lcr_h, quot;
1366
1367	if (!(mxs_read(s, REG_CTRL2) & AUART_CTRL2_UARTEN))
1368		return;
1369
1370	lcr_h = mxs_read(s, REG_LINECTRL);
1371
1372	*parity = 'n';
1373	if (lcr_h & AUART_LINECTRL_PEN) {
1374		if (lcr_h & AUART_LINECTRL_EPS)
1375			*parity = 'e';
1376		else
1377			*parity = 'o';
1378	}
1379
1380	if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(7))
1381		*bits = 7;
1382	else
1383		*bits = 8;
1384
1385	quot = ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVINT_MASK))
1386		>> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
1387	quot |= ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
1388		>> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
1389	if (quot == 0)
1390		quot = 1;
1391
1392	*baud = (port->uartclk << 2) / quot;
1393}
1394
1395static int __init
1396auart_console_setup(struct console *co, char *options)
1397{
1398	struct mxs_auart_port *s;
1399	int baud = 9600;
1400	int bits = 8;
1401	int parity = 'n';
1402	int flow = 'n';
1403	int ret;
1404
1405	/*
1406	 * Check whether an invalid uart number has been specified, and
1407	 * if so, search for the first available port that does have
1408	 * console support.
1409	 */
1410	if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
1411		co->index = 0;
1412	s = auart_port[co->index];
1413	if (!s)
1414		return -ENODEV;
1415
1416	ret = clk_prepare_enable(s->clk);
1417	if (ret)
1418		return ret;
1419
1420	if (options)
1421		uart_parse_options(options, &baud, &parity, &bits, &flow);
1422	else
1423		auart_console_get_options(s, &baud, &parity, &bits);
1424
1425	ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
1426
1427	clk_disable_unprepare(s->clk);
1428
1429	return ret;
1430}
1431
1432static struct console auart_console = {
1433	.name		= "ttyAPP",
1434	.write		= auart_console_write,
1435	.device		= uart_console_device,
1436	.setup		= auart_console_setup,
1437	.flags		= CON_PRINTBUFFER,
1438	.index		= -1,
1439	.data		= &auart_driver,
1440};
1441#endif
1442
1443static struct uart_driver auart_driver = {
1444	.owner		= THIS_MODULE,
1445	.driver_name	= "ttyAPP",
1446	.dev_name	= "ttyAPP",
1447	.major		= 0,
1448	.minor		= 0,
1449	.nr		= MXS_AUART_PORTS,
1450#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1451	.cons =		&auart_console,
1452#endif
1453};
1454
1455static void mxs_init_regs(struct mxs_auart_port *s)
1456{
1457	if (is_asm9260_auart(s))
1458		s->vendor = &vendor_alphascale_asm9260;
1459	else
1460		s->vendor = &vendor_freescale_stmp37xx;
1461}
1462
1463static int mxs_get_clks(struct mxs_auart_port *s,
1464			struct platform_device *pdev)
1465{
1466	int err;
1467
1468	if (!is_asm9260_auart(s)) {
1469		s->clk = devm_clk_get(&pdev->dev, NULL);
1470		return PTR_ERR_OR_ZERO(s->clk);
1471	}
1472
1473	s->clk = devm_clk_get(s->dev, "mod");
1474	if (IS_ERR(s->clk)) {
1475		dev_err(s->dev, "Failed to get \"mod\" clk\n");
1476		return PTR_ERR(s->clk);
1477	}
1478
1479	s->clk_ahb = devm_clk_get(s->dev, "ahb");
1480	if (IS_ERR(s->clk_ahb)) {
1481		dev_err(s->dev, "Failed to get \"ahb\" clk\n");
1482		return PTR_ERR(s->clk_ahb);
1483	}
1484
1485	err = clk_prepare_enable(s->clk_ahb);
1486	if (err) {
1487		dev_err(s->dev, "Failed to enable ahb_clk!\n");
1488		return err;
1489	}
1490
1491	err = clk_set_rate(s->clk, clk_get_rate(s->clk_ahb));
1492	if (err) {
1493		dev_err(s->dev, "Failed to set rate!\n");
1494		goto disable_clk_ahb;
1495	}
1496
1497	err = clk_prepare_enable(s->clk);
1498	if (err) {
1499		dev_err(s->dev, "Failed to enable clk!\n");
1500		goto disable_clk_ahb;
1501	}
1502
1503	return 0;
1504
1505disable_clk_ahb:
1506	clk_disable_unprepare(s->clk_ahb);
1507	return err;
1508}
1509
1510static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev)
1511{
1512	enum mctrl_gpio_idx i;
1513	struct gpio_desc *gpiod;
1514
1515	s->gpios = mctrl_gpio_init_noauto(dev, 0);
1516	if (IS_ERR(s->gpios))
1517		return PTR_ERR(s->gpios);
1518
1519	/* Block (enabled before) DMA option if RTS or CTS is GPIO line */
1520	if (!RTS_AT_AUART() || !CTS_AT_AUART()) {
1521		if (test_bit(MXS_AUART_RTSCTS, &s->flags))
1522			dev_warn(dev,
1523				 "DMA and flow control via gpio may cause some problems. DMA disabled!\n");
1524		clear_bit(MXS_AUART_RTSCTS, &s->flags);
1525	}
1526
1527	for (i = 0; i < UART_GPIO_MAX; i++) {
1528		gpiod = mctrl_gpio_to_gpiod(s->gpios, i);
1529		if (gpiod && (gpiod_get_direction(gpiod) == 1))
1530			s->gpio_irq[i] = gpiod_to_irq(gpiod);
1531		else
1532			s->gpio_irq[i] = -EINVAL;
1533	}
1534
1535	return 0;
1536}
1537
1538static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s)
1539{
1540	enum mctrl_gpio_idx i;
1541
1542	for (i = 0; i < UART_GPIO_MAX; i++)
1543		if (s->gpio_irq[i] >= 0)
1544			free_irq(s->gpio_irq[i], s);
1545}
1546
1547static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s)
1548{
1549	int *irq = s->gpio_irq;
1550	enum mctrl_gpio_idx i;
1551	int err = 0;
1552
1553	for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1554		if (irq[i] < 0)
1555			continue;
1556
1557		irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1558		err = request_irq(irq[i], mxs_auart_irq_handle,
1559				IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s);
1560		if (err)
1561			dev_err(s->dev, "%s - Can't get %d irq\n",
1562				__func__, irq[i]);
1563	}
1564
1565	/*
1566	 * If something went wrong, rollback.
1567	 * Be careful: i may be unsigned.
1568	 */
1569	while (err && (i-- > 0))
1570		if (irq[i] >= 0)
1571			free_irq(irq[i], s);
1572
1573	return err;
1574}
1575
1576static int mxs_auart_probe(struct platform_device *pdev)
1577{
1578	struct device_node *np = pdev->dev.of_node;
1579	struct mxs_auart_port *s;
1580	u32 version;
1581	int ret, irq;
1582	struct resource *r;
1583
1584	s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
1585	if (!s)
1586		return -ENOMEM;
1587
1588	s->port.dev = &pdev->dev;
1589	s->dev = &pdev->dev;
1590
1591	ret = of_alias_get_id(np, "serial");
1592	if (ret < 0) {
1593		dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
1594		return ret;
1595	}
1596	s->port.line = ret;
1597
1598	if (of_property_read_bool(np, "uart-has-rtscts") ||
1599	    of_property_read_bool(np, "fsl,uart-has-rtscts") /* deprecated */)
1600		set_bit(MXS_AUART_RTSCTS, &s->flags);
1601
1602	if (s->port.line >= ARRAY_SIZE(auart_port)) {
1603		dev_err(&pdev->dev, "serial%d out of range\n", s->port.line);
1604		return -EINVAL;
1605	}
1606
1607	s->devtype = (enum mxs_auart_type)of_device_get_match_data(&pdev->dev);
1608
1609	ret = mxs_get_clks(s, pdev);
1610	if (ret)
1611		return ret;
1612
1613	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1614	if (!r) {
1615		ret = -ENXIO;
1616		goto out_disable_clks;
1617	}
1618
1619	s->port.mapbase = r->start;
1620	s->port.membase = ioremap(r->start, resource_size(r));
1621	if (!s->port.membase) {
1622		ret = -ENOMEM;
1623		goto out_disable_clks;
1624	}
1625	s->port.ops = &mxs_auart_ops;
1626	s->port.iotype = UPIO_MEM;
1627	s->port.fifosize = MXS_AUART_FIFO_SIZE;
1628	s->port.uartclk = clk_get_rate(s->clk);
1629	s->port.type = PORT_IMX;
1630	s->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_MXS_AUART_CONSOLE);
1631
1632	mxs_init_regs(s);
1633
1634	s->mctrl_prev = 0;
1635
1636	irq = platform_get_irq(pdev, 0);
1637	if (irq < 0) {
1638		ret = irq;
1639		goto out_iounmap;
1640	}
1641
1642	s->port.irq = irq;
1643	ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0,
1644			       dev_name(&pdev->dev), s);
1645	if (ret)
1646		goto out_iounmap;
1647
1648	platform_set_drvdata(pdev, s);
1649
1650	ret = mxs_auart_init_gpios(s, &pdev->dev);
1651	if (ret) {
1652		dev_err(&pdev->dev, "Failed to initialize GPIOs.\n");
1653		goto out_iounmap;
1654	}
1655
1656	/*
1657	 * Get the GPIO lines IRQ
1658	 */
1659	ret = mxs_auart_request_gpio_irq(s);
1660	if (ret)
1661		goto out_iounmap;
1662
1663	auart_port[s->port.line] = s;
1664
1665	mxs_auart_reset_deassert(s);
1666
1667	ret = uart_add_one_port(&auart_driver, &s->port);
1668	if (ret)
1669		goto out_free_qpio_irq;
1670
1671	/* ASM9260 don't have version reg */
1672	if (is_asm9260_auart(s)) {
1673		dev_info(&pdev->dev, "Found APPUART ASM9260\n");
1674	} else {
1675		version = mxs_read(s, REG_VERSION);
1676		dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
1677			 (version >> 24) & 0xff,
1678			 (version >> 16) & 0xff, version & 0xffff);
1679	}
1680
1681	return 0;
1682
1683out_free_qpio_irq:
1684	mxs_auart_free_gpio_irq(s);
1685	auart_port[pdev->id] = NULL;
1686
1687out_iounmap:
1688	iounmap(s->port.membase);
1689
1690out_disable_clks:
1691	if (is_asm9260_auart(s)) {
1692		clk_disable_unprepare(s->clk);
1693		clk_disable_unprepare(s->clk_ahb);
1694	}
1695	return ret;
1696}
1697
1698static void mxs_auart_remove(struct platform_device *pdev)
1699{
1700	struct mxs_auart_port *s = platform_get_drvdata(pdev);
1701
1702	uart_remove_one_port(&auart_driver, &s->port);
1703	auart_port[pdev->id] = NULL;
1704	mxs_auart_free_gpio_irq(s);
1705	iounmap(s->port.membase);
1706	if (is_asm9260_auart(s)) {
1707		clk_disable_unprepare(s->clk);
1708		clk_disable_unprepare(s->clk_ahb);
1709	}
 
 
1710}
1711
1712static struct platform_driver mxs_auart_driver = {
1713	.probe = mxs_auart_probe,
1714	.remove_new = mxs_auart_remove,
1715	.driver = {
1716		.name = "mxs-auart",
1717		.of_match_table = mxs_auart_dt_ids,
1718	},
1719};
1720
1721static int __init mxs_auart_init(void)
1722{
1723	int r;
1724
1725	r = uart_register_driver(&auart_driver);
1726	if (r)
1727		goto out;
1728
1729	r = platform_driver_register(&mxs_auart_driver);
1730	if (r)
1731		goto out_err;
1732
1733	return 0;
1734out_err:
1735	uart_unregister_driver(&auart_driver);
1736out:
1737	return r;
1738}
1739
1740static void __exit mxs_auart_exit(void)
1741{
1742	platform_driver_unregister(&mxs_auart_driver);
1743	uart_unregister_driver(&auart_driver);
1744}
1745
1746module_init(mxs_auart_init);
1747module_exit(mxs_auart_exit);
1748MODULE_LICENSE("GPL");
1749MODULE_DESCRIPTION("Freescale MXS application uart driver");
1750MODULE_ALIAS("platform:mxs-auart");