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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI VPD support
4 *
5 * Copyright (C) 2010 Broadcom Corporation.
6 */
7
8#include <linux/pci.h>
9#include <linux/delay.h>
10#include <linux/export.h>
11#include <linux/sched/signal.h>
12#include <asm/unaligned.h>
13#include "pci.h"
14
15#define PCI_VPD_LRDT_TAG_SIZE 3
16#define PCI_VPD_SRDT_LEN_MASK 0x07
17#define PCI_VPD_SRDT_TAG_SIZE 1
18#define PCI_VPD_STIN_END 0x0f
19#define PCI_VPD_INFO_FLD_HDR_SIZE 3
20
21static u16 pci_vpd_lrdt_size(const u8 *lrdt)
22{
23 return get_unaligned_le16(lrdt + 1);
24}
25
26static u8 pci_vpd_srdt_tag(const u8 *srdt)
27{
28 return *srdt >> 3;
29}
30
31static u8 pci_vpd_srdt_size(const u8 *srdt)
32{
33 return *srdt & PCI_VPD_SRDT_LEN_MASK;
34}
35
36static u8 pci_vpd_info_field_size(const u8 *info_field)
37{
38 return info_field[2];
39}
40
41/* VPD access through PCI 2.2+ VPD capability */
42
43static struct pci_dev *pci_get_func0_dev(struct pci_dev *dev)
44{
45 return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
46}
47
48#define PCI_VPD_MAX_SIZE (PCI_VPD_ADDR_MASK + 1)
49#define PCI_VPD_SZ_INVALID UINT_MAX
50
51/**
52 * pci_vpd_size - determine actual size of Vital Product Data
53 * @dev: pci device struct
54 */
55static size_t pci_vpd_size(struct pci_dev *dev)
56{
57 size_t off = 0, size;
58 unsigned char tag, header[1+2]; /* 1 byte tag, 2 bytes length */
59
60 while (pci_read_vpd_any(dev, off, 1, header) == 1) {
61 size = 0;
62
63 if (off == 0 && (header[0] == 0x00 || header[0] == 0xff))
64 goto error;
65
66 if (header[0] & PCI_VPD_LRDT) {
67 /* Large Resource Data Type Tag */
68 if (pci_read_vpd_any(dev, off + 1, 2, &header[1]) != 2) {
69 pci_warn(dev, "failed VPD read at offset %zu\n",
70 off + 1);
71 return off ?: PCI_VPD_SZ_INVALID;
72 }
73 size = pci_vpd_lrdt_size(header);
74 if (off + size > PCI_VPD_MAX_SIZE)
75 goto error;
76
77 off += PCI_VPD_LRDT_TAG_SIZE + size;
78 } else {
79 /* Short Resource Data Type Tag */
80 tag = pci_vpd_srdt_tag(header);
81 size = pci_vpd_srdt_size(header);
82 if (off + size > PCI_VPD_MAX_SIZE)
83 goto error;
84
85 off += PCI_VPD_SRDT_TAG_SIZE + size;
86 if (tag == PCI_VPD_STIN_END) /* End tag descriptor */
87 return off;
88 }
89 }
90 return off;
91
92error:
93 pci_info(dev, "invalid VPD tag %#04x (size %zu) at offset %zu%s\n",
94 header[0], size, off, off == 0 ?
95 "; assume missing optional EEPROM" : "");
96 return off ?: PCI_VPD_SZ_INVALID;
97}
98
99static bool pci_vpd_available(struct pci_dev *dev, bool check_size)
100{
101 struct pci_vpd *vpd = &dev->vpd;
102
103 if (!vpd->cap)
104 return false;
105
106 if (vpd->len == 0 && check_size) {
107 vpd->len = pci_vpd_size(dev);
108 if (vpd->len == PCI_VPD_SZ_INVALID) {
109 vpd->cap = 0;
110 return false;
111 }
112 }
113
114 return true;
115}
116
117/*
118 * Wait for last operation to complete.
119 * This code has to spin since there is no other notification from the PCI
120 * hardware. Since the VPD is often implemented by serial attachment to an
121 * EEPROM, it may take many milliseconds to complete.
122 * @set: if true wait for flag to be set, else wait for it to be cleared
123 *
124 * Returns 0 on success, negative values indicate error.
125 */
126static int pci_vpd_wait(struct pci_dev *dev, bool set)
127{
128 struct pci_vpd *vpd = &dev->vpd;
129 unsigned long timeout = jiffies + msecs_to_jiffies(125);
130 unsigned long max_sleep = 16;
131 u16 status;
132 int ret;
133
134 do {
135 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
136 &status);
137 if (ret < 0)
138 return ret;
139
140 if (!!(status & PCI_VPD_ADDR_F) == set)
141 return 0;
142
143 if (time_after(jiffies, timeout))
144 break;
145
146 usleep_range(10, max_sleep);
147 if (max_sleep < 1024)
148 max_sleep *= 2;
149 } while (true);
150
151 pci_warn(dev, "VPD access failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n");
152 return -ETIMEDOUT;
153}
154
155static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count,
156 void *arg, bool check_size)
157{
158 struct pci_vpd *vpd = &dev->vpd;
159 unsigned int max_len;
160 int ret = 0;
161 loff_t end = pos + count;
162 u8 *buf = arg;
163
164 if (!pci_vpd_available(dev, check_size))
165 return -ENODEV;
166
167 if (pos < 0)
168 return -EINVAL;
169
170 max_len = check_size ? vpd->len : PCI_VPD_MAX_SIZE;
171
172 if (pos >= max_len)
173 return 0;
174
175 if (end > max_len) {
176 end = max_len;
177 count = end - pos;
178 }
179
180 if (mutex_lock_killable(&vpd->lock))
181 return -EINTR;
182
183 while (pos < end) {
184 u32 val;
185 unsigned int i, skip;
186
187 if (fatal_signal_pending(current)) {
188 ret = -EINTR;
189 break;
190 }
191
192 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
193 pos & ~3);
194 if (ret < 0)
195 break;
196 ret = pci_vpd_wait(dev, true);
197 if (ret < 0)
198 break;
199
200 ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
201 if (ret < 0)
202 break;
203
204 skip = pos & 3;
205 for (i = 0; i < sizeof(u32); i++) {
206 if (i >= skip) {
207 *buf++ = val;
208 if (++pos == end)
209 break;
210 }
211 val >>= 8;
212 }
213 }
214
215 mutex_unlock(&vpd->lock);
216 return ret ? ret : count;
217}
218
219static ssize_t pci_vpd_write(struct pci_dev *dev, loff_t pos, size_t count,
220 const void *arg, bool check_size)
221{
222 struct pci_vpd *vpd = &dev->vpd;
223 unsigned int max_len;
224 const u8 *buf = arg;
225 loff_t end = pos + count;
226 int ret = 0;
227
228 if (!pci_vpd_available(dev, check_size))
229 return -ENODEV;
230
231 if (pos < 0 || (pos & 3) || (count & 3))
232 return -EINVAL;
233
234 max_len = check_size ? vpd->len : PCI_VPD_MAX_SIZE;
235
236 if (end > max_len)
237 return -EINVAL;
238
239 if (mutex_lock_killable(&vpd->lock))
240 return -EINTR;
241
242 while (pos < end) {
243 ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA,
244 get_unaligned_le32(buf));
245 if (ret < 0)
246 break;
247 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
248 pos | PCI_VPD_ADDR_F);
249 if (ret < 0)
250 break;
251
252 ret = pci_vpd_wait(dev, false);
253 if (ret < 0)
254 break;
255
256 buf += sizeof(u32);
257 pos += sizeof(u32);
258 }
259
260 mutex_unlock(&vpd->lock);
261 return ret ? ret : count;
262}
263
264void pci_vpd_init(struct pci_dev *dev)
265{
266 if (dev->vpd.len == PCI_VPD_SZ_INVALID)
267 return;
268
269 dev->vpd.cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
270 mutex_init(&dev->vpd.lock);
271}
272
273static ssize_t vpd_read(struct file *filp, struct kobject *kobj,
274 struct bin_attribute *bin_attr, char *buf, loff_t off,
275 size_t count)
276{
277 struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
278 struct pci_dev *vpd_dev = dev;
279 ssize_t ret;
280
281 if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
282 vpd_dev = pci_get_func0_dev(dev);
283 if (!vpd_dev)
284 return -ENODEV;
285 }
286
287 pci_config_pm_runtime_get(vpd_dev);
288 ret = pci_read_vpd(vpd_dev, off, count, buf);
289 pci_config_pm_runtime_put(vpd_dev);
290
291 if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0)
292 pci_dev_put(vpd_dev);
293
294 return ret;
295}
296
297static ssize_t vpd_write(struct file *filp, struct kobject *kobj,
298 struct bin_attribute *bin_attr, char *buf, loff_t off,
299 size_t count)
300{
301 struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
302 struct pci_dev *vpd_dev = dev;
303 ssize_t ret;
304
305 if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
306 vpd_dev = pci_get_func0_dev(dev);
307 if (!vpd_dev)
308 return -ENODEV;
309 }
310
311 pci_config_pm_runtime_get(vpd_dev);
312 ret = pci_write_vpd(vpd_dev, off, count, buf);
313 pci_config_pm_runtime_put(vpd_dev);
314
315 if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0)
316 pci_dev_put(vpd_dev);
317
318 return ret;
319}
320static BIN_ATTR(vpd, 0600, vpd_read, vpd_write, 0);
321
322static struct bin_attribute *vpd_attrs[] = {
323 &bin_attr_vpd,
324 NULL,
325};
326
327static umode_t vpd_attr_is_visible(struct kobject *kobj,
328 struct bin_attribute *a, int n)
329{
330 struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
331
332 if (!pdev->vpd.cap)
333 return 0;
334
335 return a->attr.mode;
336}
337
338const struct attribute_group pci_dev_vpd_attr_group = {
339 .bin_attrs = vpd_attrs,
340 .is_bin_visible = vpd_attr_is_visible,
341};
342
343void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size)
344{
345 unsigned int len;
346 void *buf;
347 int cnt;
348
349 if (!pci_vpd_available(dev, true))
350 return ERR_PTR(-ENODEV);
351
352 len = dev->vpd.len;
353 buf = kmalloc(len, GFP_KERNEL);
354 if (!buf)
355 return ERR_PTR(-ENOMEM);
356
357 cnt = pci_read_vpd(dev, 0, len, buf);
358 if (cnt != len) {
359 kfree(buf);
360 return ERR_PTR(-EIO);
361 }
362
363 if (size)
364 *size = len;
365
366 return buf;
367}
368EXPORT_SYMBOL_GPL(pci_vpd_alloc);
369
370static int pci_vpd_find_tag(const u8 *buf, unsigned int len, u8 rdt, unsigned int *size)
371{
372 int i = 0;
373
374 /* look for LRDT tags only, end tag is the only SRDT tag */
375 while (i + PCI_VPD_LRDT_TAG_SIZE <= len && buf[i] & PCI_VPD_LRDT) {
376 unsigned int lrdt_len = pci_vpd_lrdt_size(buf + i);
377 u8 tag = buf[i];
378
379 i += PCI_VPD_LRDT_TAG_SIZE;
380 if (tag == rdt) {
381 if (i + lrdt_len > len)
382 lrdt_len = len - i;
383 if (size)
384 *size = lrdt_len;
385 return i;
386 }
387
388 i += lrdt_len;
389 }
390
391 return -ENOENT;
392}
393
394int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size)
395{
396 return pci_vpd_find_tag(buf, len, PCI_VPD_LRDT_ID_STRING, size);
397}
398EXPORT_SYMBOL_GPL(pci_vpd_find_id_string);
399
400static int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
401 unsigned int len, const char *kw)
402{
403 int i;
404
405 for (i = off; i + PCI_VPD_INFO_FLD_HDR_SIZE <= off + len;) {
406 if (buf[i + 0] == kw[0] &&
407 buf[i + 1] == kw[1])
408 return i;
409
410 i += PCI_VPD_INFO_FLD_HDR_SIZE +
411 pci_vpd_info_field_size(&buf[i]);
412 }
413
414 return -ENOENT;
415}
416
417static ssize_t __pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf,
418 bool check_size)
419{
420 ssize_t ret;
421
422 if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
423 dev = pci_get_func0_dev(dev);
424 if (!dev)
425 return -ENODEV;
426
427 ret = pci_vpd_read(dev, pos, count, buf, check_size);
428 pci_dev_put(dev);
429 return ret;
430 }
431
432 return pci_vpd_read(dev, pos, count, buf, check_size);
433}
434
435/**
436 * pci_read_vpd - Read one entry from Vital Product Data
437 * @dev: PCI device struct
438 * @pos: offset in VPD space
439 * @count: number of bytes to read
440 * @buf: pointer to where to store result
441 */
442ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
443{
444 return __pci_read_vpd(dev, pos, count, buf, true);
445}
446EXPORT_SYMBOL(pci_read_vpd);
447
448/* Same, but allow to access any address */
449ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
450{
451 return __pci_read_vpd(dev, pos, count, buf, false);
452}
453EXPORT_SYMBOL(pci_read_vpd_any);
454
455static ssize_t __pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count,
456 const void *buf, bool check_size)
457{
458 ssize_t ret;
459
460 if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
461 dev = pci_get_func0_dev(dev);
462 if (!dev)
463 return -ENODEV;
464
465 ret = pci_vpd_write(dev, pos, count, buf, check_size);
466 pci_dev_put(dev);
467 return ret;
468 }
469
470 return pci_vpd_write(dev, pos, count, buf, check_size);
471}
472
473/**
474 * pci_write_vpd - Write entry to Vital Product Data
475 * @dev: PCI device struct
476 * @pos: offset in VPD space
477 * @count: number of bytes to write
478 * @buf: buffer containing write data
479 */
480ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
481{
482 return __pci_write_vpd(dev, pos, count, buf, true);
483}
484EXPORT_SYMBOL(pci_write_vpd);
485
486/* Same, but allow to access any address */
487ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
488{
489 return __pci_write_vpd(dev, pos, count, buf, false);
490}
491EXPORT_SYMBOL(pci_write_vpd_any);
492
493int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
494 const char *kw, unsigned int *size)
495{
496 int ro_start, infokw_start;
497 unsigned int ro_len, infokw_size;
498
499 ro_start = pci_vpd_find_tag(buf, len, PCI_VPD_LRDT_RO_DATA, &ro_len);
500 if (ro_start < 0)
501 return ro_start;
502
503 infokw_start = pci_vpd_find_info_keyword(buf, ro_start, ro_len, kw);
504 if (infokw_start < 0)
505 return infokw_start;
506
507 infokw_size = pci_vpd_info_field_size(buf + infokw_start);
508 infokw_start += PCI_VPD_INFO_FLD_HDR_SIZE;
509
510 if (infokw_start + infokw_size > len)
511 return -EINVAL;
512
513 if (size)
514 *size = infokw_size;
515
516 return infokw_start;
517}
518EXPORT_SYMBOL_GPL(pci_vpd_find_ro_info_keyword);
519
520int pci_vpd_check_csum(const void *buf, unsigned int len)
521{
522 const u8 *vpd = buf;
523 unsigned int size;
524 u8 csum = 0;
525 int rv_start;
526
527 rv_start = pci_vpd_find_ro_info_keyword(buf, len, PCI_VPD_RO_KEYWORD_CHKSUM, &size);
528 if (rv_start == -ENOENT) /* no checksum in VPD */
529 return 1;
530 else if (rv_start < 0)
531 return rv_start;
532
533 if (!size)
534 return -EINVAL;
535
536 while (rv_start >= 0)
537 csum += vpd[rv_start--];
538
539 return csum ? -EILSEQ : 0;
540}
541EXPORT_SYMBOL_GPL(pci_vpd_check_csum);
542
543#ifdef CONFIG_PCI_QUIRKS
544/*
545 * Quirk non-zero PCI functions to route VPD access through function 0 for
546 * devices that share VPD resources between functions. The functions are
547 * expected to be identical devices.
548 */
549static void quirk_f0_vpd_link(struct pci_dev *dev)
550{
551 struct pci_dev *f0;
552
553 if (!PCI_FUNC(dev->devfn))
554 return;
555
556 f0 = pci_get_func0_dev(dev);
557 if (!f0)
558 return;
559
560 if (f0->vpd.cap && dev->class == f0->class &&
561 dev->vendor == f0->vendor && dev->device == f0->device)
562 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
563
564 pci_dev_put(f0);
565}
566DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
567 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
568
569/*
570 * If a device follows the VPD format spec, the PCI core will not read or
571 * write past the VPD End Tag. But some vendors do not follow the VPD
572 * format spec, so we can't tell how much data is safe to access. Devices
573 * may behave unpredictably if we access too much. Blacklist these devices
574 * so we don't touch VPD at all.
575 */
576static void quirk_blacklist_vpd(struct pci_dev *dev)
577{
578 dev->vpd.len = PCI_VPD_SZ_INVALID;
579 pci_warn(dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
580}
581DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
582DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
583DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
584DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
585DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
586DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
587DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
588DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
589DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
590DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
591DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
592DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID, quirk_blacklist_vpd);
593/*
594 * The Amazon Annapurna Labs 0x0031 device id is reused for other non Root Port
595 * device types, so the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
596 */
597DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
598 PCI_CLASS_BRIDGE_PCI, 8, quirk_blacklist_vpd);
599
600static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
601{
602 int chip = (dev->device & 0xf000) >> 12;
603 int func = (dev->device & 0x0f00) >> 8;
604 int prod = (dev->device & 0x00ff) >> 0;
605
606 /*
607 * If this is a T3-based adapter, there's a 1KB VPD area at offset
608 * 0xc00 which contains the preferred VPD values. If this is a T4 or
609 * later based adapter, the special VPD is at offset 0x400 for the
610 * Physical Functions (the SR-IOV Virtual Functions have no VPD
611 * Capabilities). The PCI VPD Access core routines will normally
612 * compute the size of the VPD by parsing the VPD Data Structure at
613 * offset 0x000. This will result in silent failures when attempting
614 * to accesses these other VPD areas which are beyond those computed
615 * limits.
616 */
617 if (chip == 0x0 && prod >= 0x20)
618 dev->vpd.len = 8192;
619 else if (chip >= 0x4 && func < 0x8)
620 dev->vpd.len = 2048;
621}
622
623DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
624 quirk_chelsio_extend_vpd);
625
626#endif
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI VPD support
4 *
5 * Copyright (C) 2010 Broadcom Corporation.
6 */
7
8#include <linux/pci.h>
9#include <linux/delay.h>
10#include <linux/export.h>
11#include <linux/sched/signal.h>
12#include "pci.h"
13
14/* VPD access through PCI 2.2+ VPD capability */
15
16struct pci_vpd_ops {
17 ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
18 ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
19};
20
21struct pci_vpd {
22 const struct pci_vpd_ops *ops;
23 struct mutex lock;
24 unsigned int len;
25 u16 flag;
26 u8 cap;
27 unsigned int busy:1;
28 unsigned int valid:1;
29};
30
31static struct pci_dev *pci_get_func0_dev(struct pci_dev *dev)
32{
33 return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
34}
35
36/**
37 * pci_read_vpd - Read one entry from Vital Product Data
38 * @dev: pci device struct
39 * @pos: offset in vpd space
40 * @count: number of bytes to read
41 * @buf: pointer to where to store result
42 */
43ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
44{
45 if (!dev->vpd || !dev->vpd->ops)
46 return -ENODEV;
47 return dev->vpd->ops->read(dev, pos, count, buf);
48}
49EXPORT_SYMBOL(pci_read_vpd);
50
51/**
52 * pci_write_vpd - Write entry to Vital Product Data
53 * @dev: pci device struct
54 * @pos: offset in vpd space
55 * @count: number of bytes to write
56 * @buf: buffer containing write data
57 */
58ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
59{
60 if (!dev->vpd || !dev->vpd->ops)
61 return -ENODEV;
62 return dev->vpd->ops->write(dev, pos, count, buf);
63}
64EXPORT_SYMBOL(pci_write_vpd);
65
66#define PCI_VPD_MAX_SIZE (PCI_VPD_ADDR_MASK + 1)
67
68/**
69 * pci_vpd_size - determine actual size of Vital Product Data
70 * @dev: pci device struct
71 * @old_size: current assumed size, also maximum allowed size
72 */
73static size_t pci_vpd_size(struct pci_dev *dev, size_t old_size)
74{
75 size_t off = 0;
76 unsigned char header[1+2]; /* 1 byte tag, 2 bytes length */
77
78 while (off < old_size && pci_read_vpd(dev, off, 1, header) == 1) {
79 unsigned char tag;
80
81 if (!header[0] && !off) {
82 pci_info(dev, "Invalid VPD tag 00, assume missing optional VPD EPROM\n");
83 return 0;
84 }
85
86 if (header[0] & PCI_VPD_LRDT) {
87 /* Large Resource Data Type Tag */
88 tag = pci_vpd_lrdt_tag(header);
89 /* Only read length from known tag items */
90 if ((tag == PCI_VPD_LTIN_ID_STRING) ||
91 (tag == PCI_VPD_LTIN_RO_DATA) ||
92 (tag == PCI_VPD_LTIN_RW_DATA)) {
93 if (pci_read_vpd(dev, off+1, 2,
94 &header[1]) != 2) {
95 pci_warn(dev, "invalid large VPD tag %02x size at offset %zu",
96 tag, off + 1);
97 return 0;
98 }
99 off += PCI_VPD_LRDT_TAG_SIZE +
100 pci_vpd_lrdt_size(header);
101 }
102 } else {
103 /* Short Resource Data Type Tag */
104 off += PCI_VPD_SRDT_TAG_SIZE +
105 pci_vpd_srdt_size(header);
106 tag = pci_vpd_srdt_tag(header);
107 }
108
109 if (tag == PCI_VPD_STIN_END) /* End tag descriptor */
110 return off;
111
112 if ((tag != PCI_VPD_LTIN_ID_STRING) &&
113 (tag != PCI_VPD_LTIN_RO_DATA) &&
114 (tag != PCI_VPD_LTIN_RW_DATA)) {
115 pci_warn(dev, "invalid %s VPD tag %02x at offset %zu",
116 (header[0] & PCI_VPD_LRDT) ? "large" : "short",
117 tag, off);
118 return 0;
119 }
120 }
121 return 0;
122}
123
124/*
125 * Wait for last operation to complete.
126 * This code has to spin since there is no other notification from the PCI
127 * hardware. Since the VPD is often implemented by serial attachment to an
128 * EEPROM, it may take many milliseconds to complete.
129 *
130 * Returns 0 on success, negative values indicate error.
131 */
132static int pci_vpd_wait(struct pci_dev *dev)
133{
134 struct pci_vpd *vpd = dev->vpd;
135 unsigned long timeout = jiffies + msecs_to_jiffies(125);
136 unsigned long max_sleep = 16;
137 u16 status;
138 int ret;
139
140 if (!vpd->busy)
141 return 0;
142
143 do {
144 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
145 &status);
146 if (ret < 0)
147 return ret;
148
149 if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
150 vpd->busy = 0;
151 return 0;
152 }
153
154 if (fatal_signal_pending(current))
155 return -EINTR;
156
157 if (time_after(jiffies, timeout))
158 break;
159
160 usleep_range(10, max_sleep);
161 if (max_sleep < 1024)
162 max_sleep *= 2;
163 } while (true);
164
165 pci_warn(dev, "VPD access failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n");
166 return -ETIMEDOUT;
167}
168
169static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count,
170 void *arg)
171{
172 struct pci_vpd *vpd = dev->vpd;
173 int ret;
174 loff_t end = pos + count;
175 u8 *buf = arg;
176
177 if (pos < 0)
178 return -EINVAL;
179
180 if (!vpd->valid) {
181 vpd->valid = 1;
182 vpd->len = pci_vpd_size(dev, vpd->len);
183 }
184
185 if (vpd->len == 0)
186 return -EIO;
187
188 if (pos > vpd->len)
189 return 0;
190
191 if (end > vpd->len) {
192 end = vpd->len;
193 count = end - pos;
194 }
195
196 if (mutex_lock_killable(&vpd->lock))
197 return -EINTR;
198
199 ret = pci_vpd_wait(dev);
200 if (ret < 0)
201 goto out;
202
203 while (pos < end) {
204 u32 val;
205 unsigned int i, skip;
206
207 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
208 pos & ~3);
209 if (ret < 0)
210 break;
211 vpd->busy = 1;
212 vpd->flag = PCI_VPD_ADDR_F;
213 ret = pci_vpd_wait(dev);
214 if (ret < 0)
215 break;
216
217 ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
218 if (ret < 0)
219 break;
220
221 skip = pos & 3;
222 for (i = 0; i < sizeof(u32); i++) {
223 if (i >= skip) {
224 *buf++ = val;
225 if (++pos == end)
226 break;
227 }
228 val >>= 8;
229 }
230 }
231out:
232 mutex_unlock(&vpd->lock);
233 return ret ? ret : count;
234}
235
236static ssize_t pci_vpd_write(struct pci_dev *dev, loff_t pos, size_t count,
237 const void *arg)
238{
239 struct pci_vpd *vpd = dev->vpd;
240 const u8 *buf = arg;
241 loff_t end = pos + count;
242 int ret = 0;
243
244 if (pos < 0 || (pos & 3) || (count & 3))
245 return -EINVAL;
246
247 if (!vpd->valid) {
248 vpd->valid = 1;
249 vpd->len = pci_vpd_size(dev, vpd->len);
250 }
251
252 if (vpd->len == 0)
253 return -EIO;
254
255 if (end > vpd->len)
256 return -EINVAL;
257
258 if (mutex_lock_killable(&vpd->lock))
259 return -EINTR;
260
261 ret = pci_vpd_wait(dev);
262 if (ret < 0)
263 goto out;
264
265 while (pos < end) {
266 u32 val;
267
268 val = *buf++;
269 val |= *buf++ << 8;
270 val |= *buf++ << 16;
271 val |= *buf++ << 24;
272
273 ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
274 if (ret < 0)
275 break;
276 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
277 pos | PCI_VPD_ADDR_F);
278 if (ret < 0)
279 break;
280
281 vpd->busy = 1;
282 vpd->flag = 0;
283 ret = pci_vpd_wait(dev);
284 if (ret < 0)
285 break;
286
287 pos += sizeof(u32);
288 }
289out:
290 mutex_unlock(&vpd->lock);
291 return ret ? ret : count;
292}
293
294static const struct pci_vpd_ops pci_vpd_ops = {
295 .read = pci_vpd_read,
296 .write = pci_vpd_write,
297};
298
299static ssize_t pci_vpd_f0_read(struct pci_dev *dev, loff_t pos, size_t count,
300 void *arg)
301{
302 struct pci_dev *tdev = pci_get_func0_dev(dev);
303 ssize_t ret;
304
305 if (!tdev)
306 return -ENODEV;
307
308 ret = pci_read_vpd(tdev, pos, count, arg);
309 pci_dev_put(tdev);
310 return ret;
311}
312
313static ssize_t pci_vpd_f0_write(struct pci_dev *dev, loff_t pos, size_t count,
314 const void *arg)
315{
316 struct pci_dev *tdev = pci_get_func0_dev(dev);
317 ssize_t ret;
318
319 if (!tdev)
320 return -ENODEV;
321
322 ret = pci_write_vpd(tdev, pos, count, arg);
323 pci_dev_put(tdev);
324 return ret;
325}
326
327static const struct pci_vpd_ops pci_vpd_f0_ops = {
328 .read = pci_vpd_f0_read,
329 .write = pci_vpd_f0_write,
330};
331
332void pci_vpd_init(struct pci_dev *dev)
333{
334 struct pci_vpd *vpd;
335 u8 cap;
336
337 cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
338 if (!cap)
339 return;
340
341 vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
342 if (!vpd)
343 return;
344
345 vpd->len = PCI_VPD_MAX_SIZE;
346 if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0)
347 vpd->ops = &pci_vpd_f0_ops;
348 else
349 vpd->ops = &pci_vpd_ops;
350 mutex_init(&vpd->lock);
351 vpd->cap = cap;
352 vpd->busy = 0;
353 vpd->valid = 0;
354 dev->vpd = vpd;
355}
356
357void pci_vpd_release(struct pci_dev *dev)
358{
359 kfree(dev->vpd);
360}
361
362static ssize_t vpd_read(struct file *filp, struct kobject *kobj,
363 struct bin_attribute *bin_attr, char *buf, loff_t off,
364 size_t count)
365{
366 struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
367
368 return pci_read_vpd(dev, off, count, buf);
369}
370
371static ssize_t vpd_write(struct file *filp, struct kobject *kobj,
372 struct bin_attribute *bin_attr, char *buf, loff_t off,
373 size_t count)
374{
375 struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
376
377 return pci_write_vpd(dev, off, count, buf);
378}
379static BIN_ATTR(vpd, 0600, vpd_read, vpd_write, 0);
380
381static struct bin_attribute *vpd_attrs[] = {
382 &bin_attr_vpd,
383 NULL,
384};
385
386static umode_t vpd_attr_is_visible(struct kobject *kobj,
387 struct bin_attribute *a, int n)
388{
389 struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
390
391 if (!pdev->vpd)
392 return 0;
393
394 return a->attr.mode;
395}
396
397const struct attribute_group pci_dev_vpd_attr_group = {
398 .bin_attrs = vpd_attrs,
399 .is_bin_visible = vpd_attr_is_visible,
400};
401
402int pci_vpd_find_tag(const u8 *buf, unsigned int len, u8 rdt)
403{
404 int i = 0;
405
406 /* look for LRDT tags only, end tag is the only SRDT tag */
407 while (i + PCI_VPD_LRDT_TAG_SIZE <= len && buf[i] & PCI_VPD_LRDT) {
408 if (buf[i] == rdt)
409 return i;
410
411 i += PCI_VPD_LRDT_TAG_SIZE + pci_vpd_lrdt_size(buf + i);
412 }
413
414 return -ENOENT;
415}
416EXPORT_SYMBOL_GPL(pci_vpd_find_tag);
417
418int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
419 unsigned int len, const char *kw)
420{
421 int i;
422
423 for (i = off; i + PCI_VPD_INFO_FLD_HDR_SIZE <= off + len;) {
424 if (buf[i + 0] == kw[0] &&
425 buf[i + 1] == kw[1])
426 return i;
427
428 i += PCI_VPD_INFO_FLD_HDR_SIZE +
429 pci_vpd_info_field_size(&buf[i]);
430 }
431
432 return -ENOENT;
433}
434EXPORT_SYMBOL_GPL(pci_vpd_find_info_keyword);
435
436#ifdef CONFIG_PCI_QUIRKS
437/*
438 * Quirk non-zero PCI functions to route VPD access through function 0 for
439 * devices that share VPD resources between functions. The functions are
440 * expected to be identical devices.
441 */
442static void quirk_f0_vpd_link(struct pci_dev *dev)
443{
444 struct pci_dev *f0;
445
446 if (!PCI_FUNC(dev->devfn))
447 return;
448
449 f0 = pci_get_func0_dev(dev);
450 if (!f0)
451 return;
452
453 if (f0->vpd && dev->class == f0->class &&
454 dev->vendor == f0->vendor && dev->device == f0->device)
455 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
456
457 pci_dev_put(f0);
458}
459DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
460 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
461
462/*
463 * If a device follows the VPD format spec, the PCI core will not read or
464 * write past the VPD End Tag. But some vendors do not follow the VPD
465 * format spec, so we can't tell how much data is safe to access. Devices
466 * may behave unpredictably if we access too much. Blacklist these devices
467 * so we don't touch VPD at all.
468 */
469static void quirk_blacklist_vpd(struct pci_dev *dev)
470{
471 if (dev->vpd) {
472 dev->vpd->len = 0;
473 pci_warn(dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
474 }
475}
476DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
477DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
478DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
479DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
480DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
481DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
482DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
483DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
484DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
485DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
486DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
487DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID,
488 quirk_blacklist_vpd);
489/*
490 * The Amazon Annapurna Labs 0x0031 device id is reused for other non Root Port
491 * device types, so the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
492 */
493DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
494 PCI_CLASS_BRIDGE_PCI, 8, quirk_blacklist_vpd);
495
496static void pci_vpd_set_size(struct pci_dev *dev, size_t len)
497{
498 struct pci_vpd *vpd = dev->vpd;
499
500 if (!vpd || len == 0 || len > PCI_VPD_MAX_SIZE)
501 return;
502
503 vpd->valid = 1;
504 vpd->len = len;
505}
506
507static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
508{
509 int chip = (dev->device & 0xf000) >> 12;
510 int func = (dev->device & 0x0f00) >> 8;
511 int prod = (dev->device & 0x00ff) >> 0;
512
513 /*
514 * If this is a T3-based adapter, there's a 1KB VPD area at offset
515 * 0xc00 which contains the preferred VPD values. If this is a T4 or
516 * later based adapter, the special VPD is at offset 0x400 for the
517 * Physical Functions (the SR-IOV Virtual Functions have no VPD
518 * Capabilities). The PCI VPD Access core routines will normally
519 * compute the size of the VPD by parsing the VPD Data Structure at
520 * offset 0x000. This will result in silent failures when attempting
521 * to accesses these other VPD areas which are beyond those computed
522 * limits.
523 */
524 if (chip == 0x0 && prod >= 0x20)
525 pci_vpd_set_size(dev, 8192);
526 else if (chip >= 0x4 && func < 0x8)
527 pci_vpd_set_size(dev, 2048);
528}
529
530DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
531 quirk_chelsio_extend_vpd);
532
533#endif