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1# SPDX-License-Identifier: GPL-2.0
2#
3# PCI Express Port Bus Configuration
4#
5config PCIEPORTBUS
6 bool "PCI Express Port Bus support"
7 default y if USB4
8 help
9 This enables PCI Express Port Bus support. Users can then enable
10 support for Native Hot-Plug, Advanced Error Reporting, Power
11 Management Events, and Downstream Port Containment.
12
13#
14# Include service Kconfig here
15#
16config HOTPLUG_PCI_PCIE
17 bool "PCI Express Hotplug driver"
18 depends on HOTPLUG_PCI && PCIEPORTBUS
19 default y if USB4
20 help
21 Say Y here if you have a motherboard that supports PCIe native
22 hotplug.
23
24 Thunderbolt/USB4 PCIe tunneling depends on native PCIe hotplug.
25
26 When in doubt, say N.
27
28config PCIEAER
29 bool "PCI Express Advanced Error Reporting support"
30 depends on PCIEPORTBUS
31 select RAS
32 help
33 This enables PCI Express Root Port Advanced Error Reporting
34 (AER) driver support. Error reporting messages sent to Root
35 Port will be handled by PCI Express AER driver.
36
37config PCIEAER_INJECT
38 tristate "PCI Express error injection support"
39 depends on PCIEAER
40 select GENERIC_IRQ_INJECTION
41 help
42 This enables PCI Express Root Port Advanced Error Reporting
43 (AER) software error injector.
44
45 Debugging AER code is quite difficult because it is hard
46 to trigger various real hardware errors. Software-based
47 error injection can fake almost all kinds of errors with the
48 help of a user space helper tool aer-inject, which can be
49 gotten from:
50 https://git.kernel.org/cgit/linux/kernel/git/gong.chen/aer-inject.git/
51
52config PCIEAER_CXL
53 bool "PCI Express CXL RAS support"
54 default y
55 depends on PCIEAER && CXL_PCI
56 help
57 Enables CXL error handling.
58
59 If unsure, say Y.
60
61#
62# PCI Express ECRC
63#
64config PCIE_ECRC
65 bool "PCI Express ECRC settings control"
66 depends on PCIEAER
67 help
68 Used to override firmware/bios settings for PCI Express ECRC
69 (transaction layer end-to-end CRC checking).
70
71 When in doubt, say N.
72
73#
74# PCI Express ASPM
75#
76config PCIEASPM
77 bool "PCI Express ASPM control" if EXPERT
78 default y
79 help
80 This enables OS control over PCI Express ASPM (Active State
81 Power Management) and Clock Power Management. ASPM supports
82 state L0/L0s/L1.
83
84 ASPM is initially set up by the firmware. With this option enabled,
85 Linux can modify this state in order to disable ASPM on known-bad
86 hardware or configurations and enable it when known-safe.
87
88 ASPM can be disabled or enabled at runtime via
89 /sys/module/pcie_aspm/parameters/policy
90
91 When in doubt, say Y.
92
93choice
94 prompt "Default ASPM policy"
95 default PCIEASPM_DEFAULT
96 depends on PCIEASPM
97
98config PCIEASPM_DEFAULT
99 bool "BIOS default"
100 depends on PCIEASPM
101 help
102 Use the BIOS defaults for PCI Express ASPM.
103
104config PCIEASPM_POWERSAVE
105 bool "Powersave"
106 depends on PCIEASPM
107 help
108 Enable PCI Express ASPM L0s and L1 where possible, even if the
109 BIOS did not.
110
111config PCIEASPM_POWER_SUPERSAVE
112 bool "Power Supersave"
113 depends on PCIEASPM
114 help
115 Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where
116 possible. This would result in higher power savings while staying in L1
117 where the components support it.
118
119config PCIEASPM_PERFORMANCE
120 bool "Performance"
121 depends on PCIEASPM
122 help
123 Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.
124endchoice
125
126config PCIE_PME
127 def_bool y
128 depends on PCIEPORTBUS && PM
129
130config PCIE_DPC
131 bool "PCI Express Downstream Port Containment support"
132 depends on PCIEPORTBUS && PCIEAER
133 help
134 This enables PCI Express Downstream Port Containment (DPC)
135 driver support. DPC events from Root and Downstream ports
136 will be handled by the DPC driver. If your system doesn't
137 have this capability or you do not want to use this feature,
138 it is safe to answer N.
139
140config PCIE_PTM
141 bool "PCI Express Precision Time Measurement support"
142 help
143 This enables PCI Express Precision Time Measurement (PTM)
144 support.
145
146 This is only useful if you have devices that support PTM, but it
147 is safe to enable even if you don't.
148
149config PCIE_EDR
150 bool "PCI Express Error Disconnect Recover support"
151 depends on PCIE_DPC && ACPI
152 help
153 This option adds Error Disconnect Recover support as specified
154 in the Downstream Port Containment Related Enhancements ECN to
155 the PCI Firmware Specification r3.2. Enable this if you want to
156 support hybrid DPC model which uses both firmware and OS to
157 implement DPC.
1# SPDX-License-Identifier: GPL-2.0
2#
3# PCI Express Port Bus Configuration
4#
5config PCIEPORTBUS
6 bool "PCI Express Port Bus support"
7 help
8 This enables PCI Express Port Bus support. Users can then enable
9 support for Native Hot-Plug, Advanced Error Reporting, Power
10 Management Events, and Downstream Port Containment.
11
12#
13# Include service Kconfig here
14#
15config HOTPLUG_PCI_PCIE
16 bool "PCI Express Hotplug driver"
17 depends on HOTPLUG_PCI && PCIEPORTBUS
18 help
19 Say Y here if you have a motherboard that supports PCI Express Native
20 Hotplug
21
22 When in doubt, say N.
23
24config PCIEAER
25 bool "PCI Express Advanced Error Reporting support"
26 depends on PCIEPORTBUS
27 select RAS
28 help
29 This enables PCI Express Root Port Advanced Error Reporting
30 (AER) driver support. Error reporting messages sent to Root
31 Port will be handled by PCI Express AER driver.
32
33config PCIEAER_INJECT
34 tristate "PCI Express error injection support"
35 depends on PCIEAER
36 select GENERIC_IRQ_INJECTION
37 help
38 This enables PCI Express Root Port Advanced Error Reporting
39 (AER) software error injector.
40
41 Debugging AER code is quite difficult because it is hard
42 to trigger various real hardware errors. Software-based
43 error injection can fake almost all kinds of errors with the
44 help of a user space helper tool aer-inject, which can be
45 gotten from:
46 https://www.kernel.org/pub/linux/utils/pci/aer-inject/
47
48#
49# PCI Express ECRC
50#
51config PCIE_ECRC
52 bool "PCI Express ECRC settings control"
53 depends on PCIEAER
54 help
55 Used to override firmware/bios settings for PCI Express ECRC
56 (transaction layer end-to-end CRC checking).
57
58 When in doubt, say N.
59
60#
61# PCI Express ASPM
62#
63config PCIEASPM
64 bool "PCI Express ASPM control" if EXPERT
65 default y
66 help
67 This enables OS control over PCI Express ASPM (Active State
68 Power Management) and Clock Power Management. ASPM supports
69 state L0/L0s/L1.
70
71 ASPM is initially set up by the firmware. With this option enabled,
72 Linux can modify this state in order to disable ASPM on known-bad
73 hardware or configurations and enable it when known-safe.
74
75 ASPM can be disabled or enabled at runtime via
76 /sys/module/pcie_aspm/parameters/policy
77
78 When in doubt, say Y.
79
80choice
81 prompt "Default ASPM policy"
82 default PCIEASPM_DEFAULT
83 depends on PCIEASPM
84
85config PCIEASPM_DEFAULT
86 bool "BIOS default"
87 depends on PCIEASPM
88 help
89 Use the BIOS defaults for PCI Express ASPM.
90
91config PCIEASPM_POWERSAVE
92 bool "Powersave"
93 depends on PCIEASPM
94 help
95 Enable PCI Express ASPM L0s and L1 where possible, even if the
96 BIOS did not.
97
98config PCIEASPM_POWER_SUPERSAVE
99 bool "Power Supersave"
100 depends on PCIEASPM
101 help
102 Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where
103 possible. This would result in higher power savings while staying in L1
104 where the components support it.
105
106config PCIEASPM_PERFORMANCE
107 bool "Performance"
108 depends on PCIEASPM
109 help
110 Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.
111endchoice
112
113config PCIE_PME
114 def_bool y
115 depends on PCIEPORTBUS && PM
116
117config PCIE_DPC
118 bool "PCI Express Downstream Port Containment support"
119 depends on PCIEPORTBUS && PCIEAER
120 help
121 This enables PCI Express Downstream Port Containment (DPC)
122 driver support. DPC events from Root and Downstream ports
123 will be handled by the DPC driver. If your system doesn't
124 have this capability or you do not want to use this feature,
125 it is safe to answer N.
126
127config PCIE_PTM
128 bool "PCI Express Precision Time Measurement support"
129 help
130 This enables PCI Express Precision Time Measurement (PTM)
131 support.
132
133 This is only useful if you have devices that support PTM, but it
134 is safe to enable even if you don't.
135
136config PCIE_EDR
137 bool "PCI Express Error Disconnect Recover support"
138 depends on PCIE_DPC && ACPI
139 help
140 This option adds Error Disconnect Recover support as specified
141 in the Downstream Port Containment Related Enhancements ECN to
142 the PCI Firmware Specification r3.2. Enable this if you want to
143 support hybrid DPC model which uses both firmware and OS to
144 implement DPC.