1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
  2/*
  3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
  4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5 */
  6
  7#ifndef ATH12K_QMI_H
  8#define ATH12K_QMI_H
  9
 10#include <linux/mutex.h>
 11#include <linux/soc/qcom/qmi.h>
 12
 13#define ATH12K_HOST_VERSION_STRING		"WIN"
 14#define ATH12K_QMI_WLANFW_TIMEOUT_MS		10000
 15#define ATH12K_QMI_MAX_BDF_FILE_NAME_SIZE	64
 16#define ATH12K_QMI_CALDB_ADDRESS		0x4BA00000
 17#define ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01	128
 18#define ATH12K_QMI_WLFW_NODE_ID_BASE		0x07
 19#define ATH12K_QMI_WLFW_SERVICE_ID_V01		0x45
 20#define ATH12K_QMI_WLFW_SERVICE_VERS_V01	0x01
 21#define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01	0x02
 22#define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850 0x1
 23
 24#define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274	0x07
 25#define ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01	32
 26#define ATH12K_QMI_RESP_LEN_MAX			8192
 27#define ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01	52
 28#define ATH12K_QMI_CALDB_SIZE			0x480000
 29#define ATH12K_QMI_BDF_EXT_STR_LENGTH		0x20
 30#define ATH12K_QMI_FW_MEM_REQ_SEGMENT_CNT	3
 31#define ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01 4
 32#define ATH12K_QMI_DEVMEM_CMEM_INDEX	0
 33
 34#define QMI_WLFW_REQUEST_MEM_IND_V01		0x0035
 35#define QMI_WLFW_FW_MEM_READY_IND_V01		0x0037
 36#define QMI_WLFW_FW_READY_IND_V01		0x0038
 37
 38#define QMI_WLANFW_MAX_DATA_SIZE_V01		6144
 39#define ATH12K_FIRMWARE_MODE_OFF		4
 40#define ATH12K_QMI_TARGET_MEM_MODE_DEFAULT	0
 41
 42#define ATH12K_BOARD_ID_DEFAULT	0xFF
 43
 44struct ath12k_base;
 45
 46enum ath12k_qmi_file_type {
 47	ATH12K_QMI_FILE_TYPE_BDF_GOLDEN	= 0,
 48	ATH12K_QMI_FILE_TYPE_CALDATA	= 2,
 49	ATH12K_QMI_FILE_TYPE_EEPROM	= 3,
 50	ATH12K_QMI_MAX_FILE_TYPE	= 4,
 51};
 52
 53enum ath12k_qmi_bdf_type {
 54	ATH12K_QMI_BDF_TYPE_BIN			= 0,
 55	ATH12K_QMI_BDF_TYPE_ELF			= 1,
 56	ATH12K_QMI_BDF_TYPE_REGDB		= 4,
 57	ATH12K_QMI_BDF_TYPE_CALIBRATION		= 5,
 58};
 59
 60enum ath12k_qmi_event_type {
 61	ATH12K_QMI_EVENT_SERVER_ARRIVE,
 62	ATH12K_QMI_EVENT_SERVER_EXIT,
 63	ATH12K_QMI_EVENT_REQUEST_MEM,
 64	ATH12K_QMI_EVENT_FW_MEM_READY,
 65	ATH12K_QMI_EVENT_FW_READY,
 66	ATH12K_QMI_EVENT_REGISTER_DRIVER,
 67	ATH12K_QMI_EVENT_UNREGISTER_DRIVER,
 68	ATH12K_QMI_EVENT_RECOVERY,
 69	ATH12K_QMI_EVENT_FORCE_FW_ASSERT,
 70	ATH12K_QMI_EVENT_POWER_UP,
 71	ATH12K_QMI_EVENT_POWER_DOWN,
 72	ATH12K_QMI_EVENT_MAX,
 73};
 74
 75struct ath12k_qmi_driver_event {
 76	struct list_head list;
 77	enum ath12k_qmi_event_type type;
 78	void *data;
 79};
 80
 81struct ath12k_qmi_ce_cfg {
 82	const struct ce_pipe_config *tgt_ce;
 83	int tgt_ce_len;
 84	const struct service_to_pipe *svc_to_ce_map;
 85	int svc_to_ce_map_len;
 86	const u8 *shadow_reg;
 87	int shadow_reg_len;
 88	u32 *shadow_reg_v3;
 89	int shadow_reg_v3_len;
 90};
 91
 92struct ath12k_qmi_event_msg {
 93	struct list_head list;
 94	enum ath12k_qmi_event_type type;
 95};
 96
 97struct target_mem_chunk {
 98	u32 size;
 99	u32 type;
100	dma_addr_t paddr;
101	union {
102		void __iomem *ioaddr;
103		void *addr;
104	} v;
105};
106
107struct target_info {
108	u32 chip_id;
109	u32 chip_family;
110	u32 board_id;
111	u32 soc_id;
112	u32 fw_version;
113	u32 eeprom_caldata;
114	char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1];
115	char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1];
116	char bdf_ext[ATH12K_QMI_BDF_EXT_STR_LENGTH];
117};
118
119struct m3_mem_region {
120	u32 size;
121	dma_addr_t paddr;
122	void *vaddr;
123};
124
125struct dev_mem_info {
126	u64 start;
127	u64 size;
128};
129
130struct ath12k_qmi {
131	struct ath12k_base *ab;
132	struct qmi_handle handle;
133	struct sockaddr_qrtr sq;
134	struct work_struct event_work;
135	struct workqueue_struct *event_wq;
136	struct list_head event_list;
137	spinlock_t event_lock; /* spinlock for qmi event list */
138	struct ath12k_qmi_ce_cfg ce_cfg;
139	struct target_mem_chunk target_mem[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
140	u32 mem_seg_count;
141	u32 target_mem_mode;
142	bool target_mem_delayed;
143	u8 cal_done;
144	struct target_info target;
145	struct m3_mem_region m3_mem;
146	unsigned int service_ins_id;
147	struct dev_mem_info dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01];
148};
149
150#define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN		261
151#define QMI_WLANFW_HOST_CAP_REQ_V01			0x0034
152#define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN	7
153#define QMI_WLFW_HOST_CAP_RESP_V01			0x0034
154#define QMI_WLFW_MAX_NUM_GPIO_V01			32
155#define QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01		64
156#define QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01		3
157
158struct qmi_wlanfw_host_ddr_range {
159	u64 start;
160	u64 size;
161};
162
163enum ath12k_qmi_target_mem {
164	HOST_DDR_REGION_TYPE = 0x1,
165	BDF_MEM_REGION_TYPE = 0x2,
166	M3_DUMP_REGION_TYPE = 0x3,
167	CALDB_MEM_REGION_TYPE = 0x4,
168	PAGEABLE_MEM_REGION_TYPE = 0x9,
169};
170
171enum qmi_wlanfw_host_build_type {
172	WLANFW_HOST_BUILD_TYPE_ENUM_MIN_VAL_V01 = INT_MIN,
173	QMI_WLANFW_HOST_BUILD_TYPE_UNSPECIFIED_V01 = 0,
174	QMI_WLANFW_HOST_BUILD_TYPE_PRIMARY_V01 = 1,
175	QMI_WLANFW_HOST_BUILD_TYPE_SECONDARY_V01 = 2,
176	WLANFW_HOST_BUILD_TYPE_ENUM_MAX_VAL_V01 = INT_MAX,
177};
178
179#define QMI_WLFW_MAX_NUM_MLO_CHIPS_V01 3
180#define QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01 2
181
182struct wlfw_host_mlo_chip_info_s_v01 {
183	u8 chip_id;
184	u8 num_local_links;
185	u8 hw_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01];
186	u8 valid_mlo_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01];
187};
188
189enum ath12k_qmi_cnss_feature {
190	CNSS_FEATURE_MIN_ENUM_VAL_V01 = INT_MIN,
191	CNSS_QDSS_CFG_MISS_V01 = 3,
192	CNSS_PCIE_PERST_NO_PULL_V01 = 4,
193	CNSS_MAX_FEATURE_V01 = 64,
194	CNSS_FEATURE_MAX_ENUM_VAL_V01 = INT_MAX,
195};
196
197struct qmi_wlanfw_host_cap_req_msg_v01 {
198	u8 num_clients_valid;
199	u32 num_clients;
200	u8 wake_msi_valid;
201	u32 wake_msi;
202	u8 gpios_valid;
203	u32 gpios_len;
204	u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01];
205	u8 nm_modem_valid;
206	u8 nm_modem;
207	u8 bdf_support_valid;
208	u8 bdf_support;
209	u8 bdf_cache_support_valid;
210	u8 bdf_cache_support;
211	u8 m3_support_valid;
212	u8 m3_support;
213	u8 m3_cache_support_valid;
214	u8 m3_cache_support;
215	u8 cal_filesys_support_valid;
216	u8 cal_filesys_support;
217	u8 cal_cache_support_valid;
218	u8 cal_cache_support;
219	u8 cal_done_valid;
220	u8 cal_done;
221	u8 mem_bucket_valid;
222	u32 mem_bucket;
223	u8 mem_cfg_mode_valid;
224	u8 mem_cfg_mode;
225	u8 cal_duration_valid;
226	u16 cal_duraiton;
227	u8 platform_name_valid;
228	char platform_name[QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 + 1];
229	u8 ddr_range_valid;
230	struct qmi_wlanfw_host_ddr_range ddr_range[QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01];
231	u8 host_build_type_valid;
232	enum qmi_wlanfw_host_build_type host_build_type;
233	u8 mlo_capable_valid;
234	u8 mlo_capable;
235	u8 mlo_chip_id_valid;
236	u16 mlo_chip_id;
237	u8 mlo_group_id_valid;
238	u8 mlo_group_id;
239	u8 max_mlo_peer_valid;
240	u16 max_mlo_peer;
241	u8 mlo_num_chips_valid;
242	u8 mlo_num_chips;
243	u8 mlo_chip_info_valid;
244	struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_NUM_MLO_CHIPS_V01];
245	u8 feature_list_valid;
246	u64 feature_list;
247
248};
249
250struct qmi_wlanfw_host_cap_resp_msg_v01 {
251	struct qmi_response_type_v01 resp;
252};
253
254#define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN		54
255#define QMI_WLANFW_IND_REGISTER_REQ_V01				0x0020
256#define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN		18
257#define QMI_WLANFW_IND_REGISTER_RESP_V01			0x0020
258#define QMI_WLANFW_CLIENT_ID					0x4b4e454c
259
260struct qmi_wlanfw_ind_register_req_msg_v01 {
261	u8 fw_ready_enable_valid;
262	u8 fw_ready_enable;
263	u8 initiate_cal_download_enable_valid;
264	u8 initiate_cal_download_enable;
265	u8 initiate_cal_update_enable_valid;
266	u8 initiate_cal_update_enable;
267	u8 msa_ready_enable_valid;
268	u8 msa_ready_enable;
269	u8 pin_connect_result_enable_valid;
270	u8 pin_connect_result_enable;
271	u8 client_id_valid;
272	u32 client_id;
273	u8 request_mem_enable_valid;
274	u8 request_mem_enable;
275	u8 fw_mem_ready_enable_valid;
276	u8 fw_mem_ready_enable;
277	u8 fw_init_done_enable_valid;
278	u8 fw_init_done_enable;
279	u8 rejuvenate_enable_valid;
280	u32 rejuvenate_enable;
281	u8 xo_cal_enable_valid;
282	u8 xo_cal_enable;
283	u8 cal_done_enable_valid;
284	u8 cal_done_enable;
285};
286
287struct qmi_wlanfw_ind_register_resp_msg_v01 {
288	struct qmi_response_type_v01 resp;
289	u8 fw_status_valid;
290	u64 fw_status;
291};
292
293#define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN	1824
294#define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN	888
295#define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN	7
296#define QMI_WLANFW_REQUEST_MEM_IND_V01			0x0035
297#define QMI_WLANFW_RESPOND_MEM_REQ_V01			0x0036
298#define QMI_WLANFW_RESPOND_MEM_RESP_V01			0x0036
299#define QMI_WLANFW_MAX_NUM_MEM_CFG_V01			2
300#define QMI_WLANFW_MAX_STR_LEN_V01                      16
301
302struct qmi_wlanfw_mem_cfg_s_v01 {
303	u64 offset;
304	u32 size;
305	u8 secure_flag;
306};
307
308enum qmi_wlanfw_mem_type_enum_v01 {
309	WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN,
310	QMI_WLANFW_MEM_TYPE_MSA_V01 = 0,
311	QMI_WLANFW_MEM_TYPE_DDR_V01 = 1,
312	QMI_WLANFW_MEM_BDF_V01 = 2,
313	QMI_WLANFW_MEM_M3_V01 = 3,
314	QMI_WLANFW_MEM_CAL_V01 = 4,
315	QMI_WLANFW_MEM_DPD_V01 = 5,
316	WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX,
317};
318
319struct qmi_wlanfw_mem_seg_s_v01 {
320	u32 size;
321	enum qmi_wlanfw_mem_type_enum_v01 type;
322	u32 mem_cfg_len;
323	struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01];
324};
325
326struct qmi_wlanfw_request_mem_ind_msg_v01 {
327	u32 mem_seg_len;
328	struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
329};
330
331struct qmi_wlanfw_mem_seg_resp_s_v01 {
332	u64 addr;
333	u32 size;
334	enum qmi_wlanfw_mem_type_enum_v01 type;
335	u8 restore;
336};
337
338struct qmi_wlanfw_respond_mem_req_msg_v01 {
339	u32 mem_seg_len;
340	struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
341};
342
343struct qmi_wlanfw_respond_mem_resp_msg_v01 {
344	struct qmi_response_type_v01 resp;
345};
346
347struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 {
348	char placeholder;
349};
350
351struct qmi_wlanfw_fw_ready_ind_msg_v01 {
352	char placeholder;
353};
354
355#define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN	0
356#define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN	207
357#define QMI_WLANFW_CAP_REQ_V01			0x0024
358#define QMI_WLANFW_CAP_RESP_V01			0x0024
359
360enum qmi_wlanfw_pipedir_enum_v01 {
361	QMI_WLFW_PIPEDIR_NONE_V01 = 0,
362	QMI_WLFW_PIPEDIR_IN_V01 = 1,
363	QMI_WLFW_PIPEDIR_OUT_V01 = 2,
364	QMI_WLFW_PIPEDIR_INOUT_V01 = 3,
365};
366
367struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 {
368	__le32 pipe_num;
369	__le32 pipe_dir;
370	__le32 nentries;
371	__le32 nbytes_max;
372	__le32 flags;
373};
374
375struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 {
376	__le32 service_id;
377	__le32 pipe_dir;
378	__le32 pipe_num;
379};
380
381struct qmi_wlanfw_shadow_reg_cfg_s_v01 {
382	u16 id;
383	u16 offset;
384};
385
386struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 {
387	u32 addr;
388};
389
390struct qmi_wlanfw_memory_region_info_s_v01 {
391	u64 region_addr;
392	u32 size;
393	u8 secure_flag;
394};
395
396struct qmi_wlanfw_rf_chip_info_s_v01 {
397	u32 chip_id;
398	u32 chip_family;
399};
400
401struct qmi_wlanfw_rf_board_info_s_v01 {
402	u32 board_id;
403};
404
405struct qmi_wlanfw_soc_info_s_v01 {
406	u32 soc_id;
407};
408
409struct qmi_wlanfw_fw_version_info_s_v01 {
410	u32 fw_version;
411	char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1];
412};
413
414struct qmi_wlanfw_dev_mem_info_s_v01 {
415	u64 start;
416	u64 size;
417};
418
419enum qmi_wlanfw_cal_temp_id_enum_v01 {
420	QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0,
421	QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1,
422	QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2,
423	QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3,
424	QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4,
425	QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF,
426};
427
428enum qmi_wlanfw_rd_card_chain_cap_v01 {
429	WLFW_RD_CARD_CHAIN_CAP_MIN_VAL_V01 = INT_MIN,
430	WLFW_RD_CARD_CHAIN_CAP_UNSPECIFIED_V01 = 0,
431	WLFW_RD_CARD_CHAIN_CAP_1x1_V01 = 1,
432	WLFW_RD_CARD_CHAIN_CAP_2x2_V01 = 2,
433	WLFW_RD_CARD_CHAIN_CAP_MAX_VAL_V01 = INT_MAX,
434};
435
436struct qmi_wlanfw_cap_resp_msg_v01 {
437	struct qmi_response_type_v01 resp;
438	u8 chip_info_valid;
439	struct qmi_wlanfw_rf_chip_info_s_v01 chip_info;
440	u8 board_info_valid;
441	struct qmi_wlanfw_rf_board_info_s_v01 board_info;
442	u8 soc_info_valid;
443	struct qmi_wlanfw_soc_info_s_v01 soc_info;
444	u8 fw_version_info_valid;
445	struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info;
446	u8 fw_build_id_valid;
447	char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1];
448	u8 num_macs_valid;
449	u8 num_macs;
450	u8 voltage_mv_valid;
451	u32 voltage_mv;
452	u8 time_freq_hz_valid;
453	u32 time_freq_hz;
454	u8 otp_version_valid;
455	u32 otp_version;
456	u8 eeprom_caldata_read_timeout_valid;
457	u32 eeprom_caldata_read_timeout;
458	u8 fw_caps_valid;
459	u64 fw_caps;
460	u8 rd_card_chain_cap_valid;
461	enum qmi_wlanfw_rd_card_chain_cap_v01 rd_card_chain_cap;
462	u8 dev_mem_info_valid;
463	struct qmi_wlanfw_dev_mem_info_s_v01 dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01];
464};
465
466struct qmi_wlanfw_cap_req_msg_v01 {
467	char placeholder;
468};
469
470#define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN	6182
471#define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN	7
472#define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01		0x0025
473#define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01			0x0025
474/* TODO: Need to check with MCL and FW team that data can be pointer and
475 * can be last element in structure
476 */
477struct qmi_wlanfw_bdf_download_req_msg_v01 {
478	u8 valid;
479	u8 file_id_valid;
480	enum qmi_wlanfw_cal_temp_id_enum_v01 file_id;
481	u8 total_size_valid;
482	u32 total_size;
483	u8 seg_id_valid;
484	u32 seg_id;
485	u8 data_valid;
486	u32 data_len;
487	u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01];
488	u8 end_valid;
489	u8 end;
490	u8 bdf_type_valid;
491	u8 bdf_type;
492
493};
494
495struct qmi_wlanfw_bdf_download_resp_msg_v01 {
496	struct qmi_response_type_v01 resp;
497};
498
499#define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN	18
500#define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN	7
501#define QMI_WLANFW_M3_INFO_RESP_V01		0x003C
502#define QMI_WLANFW_M3_INFO_REQ_V01		0x003C
503
504struct qmi_wlanfw_m3_info_req_msg_v01 {
505	u64 addr;
506	u32 size;
507};
508
509struct qmi_wlanfw_m3_info_resp_msg_v01 {
510	struct qmi_response_type_v01 resp;
511};
512
513#define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN	11
514#define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN	7
515#define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN		803
516#define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN	7
517#define QMI_WLANFW_WLAN_MODE_REQ_V01			0x0022
518#define QMI_WLANFW_WLAN_MODE_RESP_V01			0x0022
519#define QMI_WLANFW_WLAN_CFG_REQ_V01			0x0023
520#define QMI_WLANFW_WLAN_CFG_RESP_V01			0x0023
521#define QMI_WLANFW_MAX_STR_LEN_V01			16
522#define QMI_WLANFW_MAX_NUM_CE_V01			12
523#define QMI_WLANFW_MAX_NUM_SVC_V01			24
524#define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01		24
525#define QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01		60
526
527struct qmi_wlanfw_wlan_mode_req_msg_v01 {
528	u32 mode;
529	u8 hw_debug_valid;
530	u8 hw_debug;
531};
532
533struct qmi_wlanfw_wlan_mode_resp_msg_v01 {
534	struct qmi_response_type_v01 resp;
535};
536
537struct qmi_wlanfw_wlan_cfg_req_msg_v01 {
538	u8 host_version_valid;
539	char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1];
540	u8  tgt_cfg_valid;
541	u32  tgt_cfg_len;
542	struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01
543			tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01];
544	u8  svc_cfg_valid;
545	u32 svc_cfg_len;
546	struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01
547			svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01];
548	u8 shadow_reg_valid;
549	u32 shadow_reg_len;
550	struct qmi_wlanfw_shadow_reg_cfg_s_v01
551		shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01];
552	u8 shadow_reg_v3_valid;
553	u32 shadow_reg_v3_len;
554	struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01
555		shadow_reg_v3[QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01];
556};
557
558struct qmi_wlanfw_wlan_cfg_resp_msg_v01 {
559	struct qmi_response_type_v01 resp;
560};
561
562int ath12k_qmi_firmware_start(struct ath12k_base *ab,
563			      u32 mode);
564void ath12k_qmi_firmware_stop(struct ath12k_base *ab);
565void ath12k_qmi_deinit_service(struct ath12k_base *ab);
566int ath12k_qmi_init_service(struct ath12k_base *ab);
567void ath12k_qmi_free_resource(struct ath12k_base *ab);
568
569#endif