Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare XPCS helpers
5 *
6 * Author: Jose Abreu <Jose.Abreu@synopsys.com>
7 */
8
9#include <linux/delay.h>
10#include <linux/pcs/pcs-xpcs.h>
11#include <linux/mdio.h>
12#include <linux/phylink.h>
13#include <linux/workqueue.h>
14#include "pcs-xpcs.h"
15
16#define phylink_pcs_to_xpcs(pl_pcs) \
17 container_of((pl_pcs), struct dw_xpcs, pcs)
18
19static const int xpcs_usxgmii_features[] = {
20 ETHTOOL_LINK_MODE_Pause_BIT,
21 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
22 ETHTOOL_LINK_MODE_Autoneg_BIT,
23 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
24 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
25 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
26 ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
27 __ETHTOOL_LINK_MODE_MASK_NBITS,
28};
29
30static const int xpcs_10gkr_features[] = {
31 ETHTOOL_LINK_MODE_Pause_BIT,
32 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
33 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
34 __ETHTOOL_LINK_MODE_MASK_NBITS,
35};
36
37static const int xpcs_xlgmii_features[] = {
38 ETHTOOL_LINK_MODE_Pause_BIT,
39 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
40 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
41 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
42 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
43 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
44 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
45 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
46 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
47 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
48 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
49 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
50 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
51 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
52 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
53 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
54 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
55 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
56 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
57 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
58 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
59 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
60 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
61 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
62 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
63 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
64 __ETHTOOL_LINK_MODE_MASK_NBITS,
65};
66
67static const int xpcs_10gbaser_features[] = {
68 ETHTOOL_LINK_MODE_Pause_BIT,
69 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
70 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
71 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
72 ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
73 ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
74 __ETHTOOL_LINK_MODE_MASK_NBITS,
75};
76
77static const int xpcs_sgmii_features[] = {
78 ETHTOOL_LINK_MODE_Pause_BIT,
79 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
80 ETHTOOL_LINK_MODE_Autoneg_BIT,
81 ETHTOOL_LINK_MODE_10baseT_Half_BIT,
82 ETHTOOL_LINK_MODE_10baseT_Full_BIT,
83 ETHTOOL_LINK_MODE_100baseT_Half_BIT,
84 ETHTOOL_LINK_MODE_100baseT_Full_BIT,
85 ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
86 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
87 __ETHTOOL_LINK_MODE_MASK_NBITS,
88};
89
90static const int xpcs_1000basex_features[] = {
91 ETHTOOL_LINK_MODE_Pause_BIT,
92 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
93 ETHTOOL_LINK_MODE_Autoneg_BIT,
94 ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
95 __ETHTOOL_LINK_MODE_MASK_NBITS,
96};
97
98static const int xpcs_2500basex_features[] = {
99 ETHTOOL_LINK_MODE_Pause_BIT,
100 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
101 ETHTOOL_LINK_MODE_Autoneg_BIT,
102 ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
103 ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
104 __ETHTOOL_LINK_MODE_MASK_NBITS,
105};
106
107static const phy_interface_t xpcs_usxgmii_interfaces[] = {
108 PHY_INTERFACE_MODE_USXGMII,
109};
110
111static const phy_interface_t xpcs_10gkr_interfaces[] = {
112 PHY_INTERFACE_MODE_10GKR,
113};
114
115static const phy_interface_t xpcs_xlgmii_interfaces[] = {
116 PHY_INTERFACE_MODE_XLGMII,
117};
118
119static const phy_interface_t xpcs_10gbaser_interfaces[] = {
120 PHY_INTERFACE_MODE_10GBASER,
121};
122
123static const phy_interface_t xpcs_sgmii_interfaces[] = {
124 PHY_INTERFACE_MODE_SGMII,
125};
126
127static const phy_interface_t xpcs_1000basex_interfaces[] = {
128 PHY_INTERFACE_MODE_1000BASEX,
129};
130
131static const phy_interface_t xpcs_2500basex_interfaces[] = {
132 PHY_INTERFACE_MODE_2500BASEX,
133 PHY_INTERFACE_MODE_MAX,
134};
135
136enum {
137 DW_XPCS_USXGMII,
138 DW_XPCS_10GKR,
139 DW_XPCS_XLGMII,
140 DW_XPCS_10GBASER,
141 DW_XPCS_SGMII,
142 DW_XPCS_1000BASEX,
143 DW_XPCS_2500BASEX,
144 DW_XPCS_INTERFACE_MAX,
145};
146
147struct xpcs_compat {
148 const int *supported;
149 const phy_interface_t *interface;
150 int num_interfaces;
151 int an_mode;
152 int (*pma_config)(struct dw_xpcs *xpcs);
153};
154
155struct xpcs_id {
156 u32 id;
157 u32 mask;
158 const struct xpcs_compat *compat;
159};
160
161static const struct xpcs_compat *xpcs_find_compat(const struct xpcs_id *id,
162 phy_interface_t interface)
163{
164 int i, j;
165
166 for (i = 0; i < DW_XPCS_INTERFACE_MAX; i++) {
167 const struct xpcs_compat *compat = &id->compat[i];
168
169 for (j = 0; j < compat->num_interfaces; j++)
170 if (compat->interface[j] == interface)
171 return compat;
172 }
173
174 return NULL;
175}
176
177int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface)
178{
179 const struct xpcs_compat *compat;
180
181 compat = xpcs_find_compat(xpcs->id, interface);
182 if (!compat)
183 return -ENODEV;
184
185 return compat->an_mode;
186}
187EXPORT_SYMBOL_GPL(xpcs_get_an_mode);
188
189static bool __xpcs_linkmode_supported(const struct xpcs_compat *compat,
190 enum ethtool_link_mode_bit_indices linkmode)
191{
192 int i;
193
194 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++)
195 if (compat->supported[i] == linkmode)
196 return true;
197
198 return false;
199}
200
201#define xpcs_linkmode_supported(compat, mode) \
202 __xpcs_linkmode_supported(compat, ETHTOOL_LINK_MODE_ ## mode ## _BIT)
203
204int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg)
205{
206 return mdiodev_c45_read(xpcs->mdiodev, dev, reg);
207}
208
209int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val)
210{
211 return mdiodev_c45_write(xpcs->mdiodev, dev, reg, val);
212}
213
214static int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg,
215 u16 mask, u16 set)
216{
217 return mdiodev_c45_modify_changed(xpcs->mdiodev, dev, reg, mask, set);
218}
219
220static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg)
221{
222 return xpcs_read(xpcs, dev, DW_VENDOR | reg);
223}
224
225static int xpcs_write_vendor(struct dw_xpcs *xpcs, int dev, int reg,
226 u16 val)
227{
228 return xpcs_write(xpcs, dev, DW_VENDOR | reg, val);
229}
230
231int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg)
232{
233 return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg);
234}
235
236int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val)
237{
238 return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val);
239}
240
241static int xpcs_dev_flag(struct dw_xpcs *xpcs)
242{
243 int ret, oui;
244
245 ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID1);
246 if (ret < 0)
247 return ret;
248
249 oui = ret;
250
251 ret = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_DEVID2);
252 if (ret < 0)
253 return ret;
254
255 ret = (ret >> 10) & 0x3F;
256 oui |= ret << 16;
257
258 if (oui == DW_OUI_WX)
259 xpcs->dev_flag = DW_DEV_TXGBE;
260
261 return 0;
262}
263
264static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev)
265{
266 /* Poll until the reset bit clears (50ms per retry == 0.6 sec) */
267 unsigned int retries = 12;
268 int ret;
269
270 do {
271 msleep(50);
272 ret = xpcs_read(xpcs, dev, MDIO_CTRL1);
273 if (ret < 0)
274 return ret;
275 } while (ret & MDIO_CTRL1_RESET && --retries);
276
277 return (ret & MDIO_CTRL1_RESET) ? -ETIMEDOUT : 0;
278}
279
280static int xpcs_soft_reset(struct dw_xpcs *xpcs,
281 const struct xpcs_compat *compat)
282{
283 int ret, dev;
284
285 switch (compat->an_mode) {
286 case DW_AN_C73:
287 case DW_10GBASER:
288 dev = MDIO_MMD_PCS;
289 break;
290 case DW_AN_C37_SGMII:
291 case DW_2500BASEX:
292 case DW_AN_C37_1000BASEX:
293 dev = MDIO_MMD_VEND2;
294 break;
295 default:
296 return -1;
297 }
298
299 ret = xpcs_write(xpcs, dev, MDIO_CTRL1, MDIO_CTRL1_RESET);
300 if (ret < 0)
301 return ret;
302
303 return xpcs_poll_reset(xpcs, dev);
304}
305
306#define xpcs_warn(__xpcs, __state, __args...) \
307({ \
308 if ((__state)->link) \
309 dev_warn(&(__xpcs)->mdiodev->dev, ##__args); \
310})
311
312static int xpcs_read_fault_c73(struct dw_xpcs *xpcs,
313 struct phylink_link_state *state,
314 u16 pcs_stat1)
315{
316 int ret;
317
318 if (pcs_stat1 & MDIO_STAT1_FAULT) {
319 xpcs_warn(xpcs, state, "Link fault condition detected!\n");
320 return -EFAULT;
321 }
322
323 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2);
324 if (ret < 0)
325 return ret;
326
327 if (ret & MDIO_STAT2_RXFAULT)
328 xpcs_warn(xpcs, state, "Receiver fault detected!\n");
329 if (ret & MDIO_STAT2_TXFAULT)
330 xpcs_warn(xpcs, state, "Transmitter fault detected!\n");
331
332 ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS);
333 if (ret < 0)
334 return ret;
335
336 if (ret & DW_RXFIFO_ERR) {
337 xpcs_warn(xpcs, state, "FIFO fault condition detected!\n");
338 return -EFAULT;
339 }
340
341 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1);
342 if (ret < 0)
343 return ret;
344
345 if (!(ret & MDIO_PCS_10GBRT_STAT1_BLKLK))
346 xpcs_warn(xpcs, state, "Link is not locked!\n");
347
348 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2);
349 if (ret < 0)
350 return ret;
351
352 if (ret & MDIO_PCS_10GBRT_STAT2_ERR) {
353 xpcs_warn(xpcs, state, "Link has errors!\n");
354 return -EFAULT;
355 }
356
357 return 0;
358}
359
360static void xpcs_config_usxgmii(struct dw_xpcs *xpcs, int speed)
361{
362 int ret, speed_sel;
363
364 switch (speed) {
365 case SPEED_10:
366 speed_sel = DW_USXGMII_10;
367 break;
368 case SPEED_100:
369 speed_sel = DW_USXGMII_100;
370 break;
371 case SPEED_1000:
372 speed_sel = DW_USXGMII_1000;
373 break;
374 case SPEED_2500:
375 speed_sel = DW_USXGMII_2500;
376 break;
377 case SPEED_5000:
378 speed_sel = DW_USXGMII_5000;
379 break;
380 case SPEED_10000:
381 speed_sel = DW_USXGMII_10000;
382 break;
383 default:
384 /* Nothing to do here */
385 return;
386 }
387
388 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1);
389 if (ret < 0)
390 goto out;
391
392 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_EN);
393 if (ret < 0)
394 goto out;
395
396 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
397 if (ret < 0)
398 goto out;
399
400 ret &= ~DW_USXGMII_SS_MASK;
401 ret |= speed_sel | DW_USXGMII_FULL;
402
403 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret);
404 if (ret < 0)
405 goto out;
406
407 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1);
408 if (ret < 0)
409 goto out;
410
411 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_RST);
412 if (ret < 0)
413 goto out;
414
415 return;
416
417out:
418 pr_err("%s: XPCS access returned %pe\n", __func__, ERR_PTR(ret));
419}
420
421static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
422 const struct xpcs_compat *compat)
423{
424 int ret, adv;
425
426 /* By default, in USXGMII mode XPCS operates at 10G baud and
427 * replicates data to achieve lower speeds. Hereby, in this
428 * default configuration we need to advertise all supported
429 * modes and not only the ones we want to use.
430 */
431
432 /* SR_AN_ADV3 */
433 adv = 0;
434 if (xpcs_linkmode_supported(compat, 2500baseX_Full))
435 adv |= DW_C73_2500KX;
436
437 /* TODO: 5000baseKR */
438
439 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv);
440 if (ret < 0)
441 return ret;
442
443 /* SR_AN_ADV2 */
444 adv = 0;
445 if (xpcs_linkmode_supported(compat, 1000baseKX_Full))
446 adv |= DW_C73_1000KX;
447 if (xpcs_linkmode_supported(compat, 10000baseKX4_Full))
448 adv |= DW_C73_10000KX4;
449 if (xpcs_linkmode_supported(compat, 10000baseKR_Full))
450 adv |= DW_C73_10000KR;
451
452 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv);
453 if (ret < 0)
454 return ret;
455
456 /* SR_AN_ADV1 */
457 adv = DW_C73_AN_ADV_SF;
458 if (xpcs_linkmode_supported(compat, Pause))
459 adv |= DW_C73_PAUSE;
460 if (xpcs_linkmode_supported(compat, Asym_Pause))
461 adv |= DW_C73_ASYM_PAUSE;
462
463 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv);
464}
465
466static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
467 const struct xpcs_compat *compat)
468{
469 int ret;
470
471 ret = _xpcs_config_aneg_c73(xpcs, compat);
472 if (ret < 0)
473 return ret;
474
475 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_CTRL1);
476 if (ret < 0)
477 return ret;
478
479 ret |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART;
480
481 return xpcs_write(xpcs, MDIO_MMD_AN, MDIO_CTRL1, ret);
482}
483
484static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs,
485 struct phylink_link_state *state,
486 const struct xpcs_compat *compat, u16 an_stat1)
487{
488 int ret;
489
490 if (an_stat1 & MDIO_AN_STAT1_COMPLETE) {
491 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA);
492 if (ret < 0)
493 return ret;
494
495 /* Check if Aneg outcome is valid */
496 if (!(ret & DW_C73_AN_ADV_SF)) {
497 xpcs_config_aneg_c73(xpcs, compat);
498 return 0;
499 }
500
501 return 1;
502 }
503
504 return 0;
505}
506
507static int xpcs_read_lpa_c73(struct dw_xpcs *xpcs,
508 struct phylink_link_state *state, u16 an_stat1)
509{
510 u16 lpa[3];
511 int i, ret;
512
513 if (!(an_stat1 & MDIO_AN_STAT1_LPABLE)) {
514 phylink_clear(state->lp_advertising, Autoneg);
515 return 0;
516 }
517
518 phylink_set(state->lp_advertising, Autoneg);
519
520 /* Read Clause 73 link partner advertisement */
521 for (i = ARRAY_SIZE(lpa); --i >= 0; ) {
522 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA + i);
523 if (ret < 0)
524 return ret;
525
526 lpa[i] = ret;
527 }
528
529 mii_c73_mod_linkmode(state->lp_advertising, lpa);
530
531 return 0;
532}
533
534static int xpcs_get_max_xlgmii_speed(struct dw_xpcs *xpcs,
535 struct phylink_link_state *state)
536{
537 unsigned long *adv = state->advertising;
538 int speed = SPEED_UNKNOWN;
539 int bit;
540
541 for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) {
542 int new_speed = SPEED_UNKNOWN;
543
544 switch (bit) {
545 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT:
546 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT:
547 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT:
548 new_speed = SPEED_25000;
549 break;
550 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT:
551 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT:
552 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT:
553 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT:
554 new_speed = SPEED_40000;
555 break;
556 case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT:
557 case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT:
558 case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT:
559 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT:
560 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT:
561 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT:
562 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT:
563 case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT:
564 new_speed = SPEED_50000;
565 break;
566 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT:
567 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT:
568 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT:
569 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT:
570 case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT:
571 case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT:
572 case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT:
573 case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT:
574 case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT:
575 new_speed = SPEED_100000;
576 break;
577 default:
578 continue;
579 }
580
581 if (new_speed > speed)
582 speed = new_speed;
583 }
584
585 return speed;
586}
587
588static void xpcs_resolve_pma(struct dw_xpcs *xpcs,
589 struct phylink_link_state *state)
590{
591 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX;
592 state->duplex = DUPLEX_FULL;
593
594 switch (state->interface) {
595 case PHY_INTERFACE_MODE_10GKR:
596 state->speed = SPEED_10000;
597 break;
598 case PHY_INTERFACE_MODE_XLGMII:
599 state->speed = xpcs_get_max_xlgmii_speed(xpcs, state);
600 break;
601 default:
602 state->speed = SPEED_UNKNOWN;
603 break;
604 }
605}
606
607static int xpcs_validate(struct phylink_pcs *pcs, unsigned long *supported,
608 const struct phylink_link_state *state)
609{
610 __ETHTOOL_DECLARE_LINK_MODE_MASK(xpcs_supported) = { 0, };
611 const struct xpcs_compat *compat;
612 struct dw_xpcs *xpcs;
613 int i;
614
615 xpcs = phylink_pcs_to_xpcs(pcs);
616 compat = xpcs_find_compat(xpcs->id, state->interface);
617
618 /* Populate the supported link modes for this PHY interface type.
619 * FIXME: what about the port modes and autoneg bit? This masks
620 * all those away.
621 */
622 if (compat)
623 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++)
624 set_bit(compat->supported[i], xpcs_supported);
625
626 linkmode_and(supported, supported, xpcs_supported);
627
628 return 0;
629}
630
631void xpcs_get_interfaces(struct dw_xpcs *xpcs, unsigned long *interfaces)
632{
633 int i, j;
634
635 for (i = 0; i < DW_XPCS_INTERFACE_MAX; i++) {
636 const struct xpcs_compat *compat = &xpcs->id->compat[i];
637
638 for (j = 0; j < compat->num_interfaces; j++)
639 if (compat->interface[j] < PHY_INTERFACE_MODE_MAX)
640 __set_bit(compat->interface[j], interfaces);
641 }
642}
643EXPORT_SYMBOL_GPL(xpcs_get_interfaces);
644
645int xpcs_config_eee(struct dw_xpcs *xpcs, int mult_fact_100ns, int enable)
646{
647 int ret;
648
649 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0);
650 if (ret < 0)
651 return ret;
652
653 if (enable) {
654 /* Enable EEE */
655 ret = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
656 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
657 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
658 mult_fact_100ns << DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT;
659 } else {
660 ret &= ~(DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
661 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
662 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
663 DW_VR_MII_EEE_MULT_FACT_100NS);
664 }
665
666 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, ret);
667 if (ret < 0)
668 return ret;
669
670 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1);
671 if (ret < 0)
672 return ret;
673
674 if (enable)
675 ret |= DW_VR_MII_EEE_TRN_LPI;
676 else
677 ret &= ~DW_VR_MII_EEE_TRN_LPI;
678
679 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, ret);
680}
681EXPORT_SYMBOL_GPL(xpcs_config_eee);
682
683static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs,
684 unsigned int neg_mode)
685{
686 int ret, mdio_ctrl, tx_conf;
687
688 if (xpcs->dev_flag == DW_DEV_TXGBE)
689 xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, DW_CL37_BP | DW_EN_VSMMD1);
690
691 /* For AN for C37 SGMII mode, the settings are :-
692 * 1) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 0b (Disable SGMII AN in case
693 it is already enabled)
694 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 10b (SGMII AN)
695 * 3) VR_MII_AN_CTRL Bit(3) [TX_CONFIG] = 0b (MAC side SGMII)
696 * DW xPCS used with DW EQoS MAC is always MAC side SGMII.
697 * 4) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] = 1b (Automatic
698 * speed/duplex mode change by HW after SGMII AN complete)
699 * 5) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN)
700 *
701 * Note: Since it is MAC side SGMII, there is no need to set
702 * SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from
703 * PHY about the link state change after C28 AN is completed
704 * between PHY and Link Partner. There is also no need to
705 * trigger AN restart for MAC-side SGMII.
706 */
707 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
708 if (mdio_ctrl < 0)
709 return mdio_ctrl;
710
711 if (mdio_ctrl & AN_CL37_EN) {
712 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
713 mdio_ctrl & ~AN_CL37_EN);
714 if (ret < 0)
715 return ret;
716 }
717
718 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL);
719 if (ret < 0)
720 return ret;
721
722 ret &= ~(DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK);
723 ret |= (DW_VR_MII_PCS_MODE_C37_SGMII <<
724 DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT &
725 DW_VR_MII_PCS_MODE_MASK);
726 if (xpcs->dev_flag == DW_DEV_TXGBE) {
727 ret |= DW_VR_MII_AN_CTRL_8BIT;
728 /* Hardware requires it to be PHY side SGMII */
729 tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII;
730 } else {
731 tx_conf = DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII;
732 }
733 ret |= tx_conf << DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT &
734 DW_VR_MII_TX_CONFIG_MASK;
735 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret);
736 if (ret < 0)
737 return ret;
738
739 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
740 if (ret < 0)
741 return ret;
742
743 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
744 ret |= DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
745 else
746 ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
747
748 if (xpcs->dev_flag == DW_DEV_TXGBE)
749 ret |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL;
750
751 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
752 if (ret < 0)
753 return ret;
754
755 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
756 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
757 mdio_ctrl | AN_CL37_EN);
758
759 return ret;
760}
761
762static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs,
763 unsigned int neg_mode,
764 const unsigned long *advertising)
765{
766 phy_interface_t interface = PHY_INTERFACE_MODE_1000BASEX;
767 int ret, mdio_ctrl, adv;
768 bool changed = 0;
769
770 if (xpcs->dev_flag == DW_DEV_TXGBE)
771 xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, DW_CL37_BP | DW_EN_VSMMD1);
772
773 /* According to Chap 7.12, to set 1000BASE-X C37 AN, AN must
774 * be disabled first:-
775 * 1) VR_MII_MMD_CTRL Bit(12)[AN_ENABLE] = 0b
776 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 00b (1000BASE-X C37)
777 */
778 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
779 if (mdio_ctrl < 0)
780 return mdio_ctrl;
781
782 if (mdio_ctrl & AN_CL37_EN) {
783 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
784 mdio_ctrl & ~AN_CL37_EN);
785 if (ret < 0)
786 return ret;
787 }
788
789 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL);
790 if (ret < 0)
791 return ret;
792
793 ret &= ~DW_VR_MII_PCS_MODE_MASK;
794 if (!xpcs->pcs.poll)
795 ret |= DW_VR_MII_AN_INTR_EN;
796 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret);
797 if (ret < 0)
798 return ret;
799
800 /* Check for advertising changes and update the C45 MII ADV
801 * register accordingly.
802 */
803 adv = phylink_mii_c22_pcs_encode_advertisement(interface,
804 advertising);
805 if (adv >= 0) {
806 ret = xpcs_modify_changed(xpcs, MDIO_MMD_VEND2,
807 MII_ADVERTISE, 0xffff, adv);
808 if (ret < 0)
809 return ret;
810
811 changed = ret;
812 }
813
814 /* Clear CL37 AN complete status */
815 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
816 if (ret < 0)
817 return ret;
818
819 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
820 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
821 mdio_ctrl | AN_CL37_EN);
822 if (ret < 0)
823 return ret;
824 }
825
826 return changed;
827}
828
829static int xpcs_config_2500basex(struct dw_xpcs *xpcs)
830{
831 int ret;
832
833 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
834 if (ret < 0)
835 return ret;
836 ret |= DW_VR_MII_DIG_CTRL1_2G5_EN;
837 ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
838 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
839 if (ret < 0)
840 return ret;
841
842 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
843 if (ret < 0)
844 return ret;
845 ret &= ~AN_CL37_EN;
846 ret |= SGMII_SPEED_SS6;
847 ret &= ~SGMII_SPEED_SS13;
848 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, ret);
849}
850
851int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface,
852 const unsigned long *advertising, unsigned int neg_mode)
853{
854 const struct xpcs_compat *compat;
855 int ret;
856
857 compat = xpcs_find_compat(xpcs->id, interface);
858 if (!compat)
859 return -ENODEV;
860
861 if (xpcs->dev_flag == DW_DEV_TXGBE) {
862 ret = txgbe_xpcs_switch_mode(xpcs, interface);
863 if (ret)
864 return ret;
865 }
866
867 switch (compat->an_mode) {
868 case DW_10GBASER:
869 break;
870 case DW_AN_C73:
871 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
872 ret = xpcs_config_aneg_c73(xpcs, compat);
873 if (ret)
874 return ret;
875 }
876 break;
877 case DW_AN_C37_SGMII:
878 ret = xpcs_config_aneg_c37_sgmii(xpcs, neg_mode);
879 if (ret)
880 return ret;
881 break;
882 case DW_AN_C37_1000BASEX:
883 ret = xpcs_config_aneg_c37_1000basex(xpcs, neg_mode,
884 advertising);
885 if (ret)
886 return ret;
887 break;
888 case DW_2500BASEX:
889 ret = xpcs_config_2500basex(xpcs);
890 if (ret)
891 return ret;
892 break;
893 default:
894 return -1;
895 }
896
897 if (compat->pma_config) {
898 ret = compat->pma_config(xpcs);
899 if (ret)
900 return ret;
901 }
902
903 return 0;
904}
905EXPORT_SYMBOL_GPL(xpcs_do_config);
906
907static int xpcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
908 phy_interface_t interface,
909 const unsigned long *advertising,
910 bool permit_pause_to_mac)
911{
912 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
913
914 return xpcs_do_config(xpcs, interface, advertising, neg_mode);
915}
916
917static int xpcs_get_state_c73(struct dw_xpcs *xpcs,
918 struct phylink_link_state *state,
919 const struct xpcs_compat *compat)
920{
921 bool an_enabled;
922 int pcs_stat1;
923 int an_stat1;
924 int ret;
925
926 /* The link status bit is latching-low, so it is important to
927 * avoid unnecessary re-reads of this register to avoid missing
928 * a link-down event.
929 */
930 pcs_stat1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1);
931 if (pcs_stat1 < 0) {
932 state->link = false;
933 return pcs_stat1;
934 }
935
936 /* Link needs to be read first ... */
937 state->link = !!(pcs_stat1 & MDIO_STAT1_LSTATUS);
938
939 /* ... and then we check the faults. */
940 ret = xpcs_read_fault_c73(xpcs, state, pcs_stat1);
941 if (ret) {
942 ret = xpcs_soft_reset(xpcs, compat);
943 if (ret)
944 return ret;
945
946 state->link = 0;
947
948 return xpcs_do_config(xpcs, state->interface, NULL,
949 PHYLINK_PCS_NEG_INBAND_ENABLED);
950 }
951
952 /* There is no point doing anything else if the link is down. */
953 if (!state->link)
954 return 0;
955
956 an_enabled = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
957 state->advertising);
958 if (an_enabled) {
959 /* The link status bit is latching-low, so it is important to
960 * avoid unnecessary re-reads of this register to avoid missing
961 * a link-down event.
962 */
963 an_stat1 = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
964 if (an_stat1 < 0) {
965 state->link = false;
966 return an_stat1;
967 }
968
969 state->an_complete = xpcs_aneg_done_c73(xpcs, state, compat,
970 an_stat1);
971 if (!state->an_complete) {
972 state->link = false;
973 return 0;
974 }
975
976 ret = xpcs_read_lpa_c73(xpcs, state, an_stat1);
977 if (ret < 0) {
978 state->link = false;
979 return ret;
980 }
981
982 phylink_resolve_c73(state);
983 } else {
984 xpcs_resolve_pma(xpcs, state);
985 }
986
987 return 0;
988}
989
990static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs,
991 struct phylink_link_state *state)
992{
993 int ret;
994
995 /* Reset link_state */
996 state->link = false;
997 state->speed = SPEED_UNKNOWN;
998 state->duplex = DUPLEX_UNKNOWN;
999 state->pause = 0;
1000
1001 /* For C37 SGMII mode, we check DW_VR_MII_AN_INTR_STS for link
1002 * status, speed and duplex.
1003 */
1004 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS);
1005 if (ret < 0)
1006 return ret;
1007
1008 if (ret & DW_VR_MII_C37_ANSGM_SP_LNKSTS) {
1009 int speed_value;
1010
1011 state->link = true;
1012
1013 speed_value = (ret & DW_VR_MII_AN_STS_C37_ANSGM_SP) >>
1014 DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT;
1015 if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000)
1016 state->speed = SPEED_1000;
1017 else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100)
1018 state->speed = SPEED_100;
1019 else
1020 state->speed = SPEED_10;
1021
1022 if (ret & DW_VR_MII_AN_STS_C37_ANSGM_FD)
1023 state->duplex = DUPLEX_FULL;
1024 else
1025 state->duplex = DUPLEX_HALF;
1026 } else if (ret == DW_VR_MII_AN_STS_C37_ANCMPLT_INTR) {
1027 int speed, duplex;
1028
1029 state->link = true;
1030
1031 speed = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
1032 if (speed < 0)
1033 return speed;
1034
1035 speed &= SGMII_SPEED_SS13 | SGMII_SPEED_SS6;
1036 if (speed == SGMII_SPEED_SS6)
1037 state->speed = SPEED_1000;
1038 else if (speed == SGMII_SPEED_SS13)
1039 state->speed = SPEED_100;
1040 else if (speed == 0)
1041 state->speed = SPEED_10;
1042
1043 duplex = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_ADVERTISE);
1044 if (duplex < 0)
1045 return duplex;
1046
1047 if (duplex & DW_FULL_DUPLEX)
1048 state->duplex = DUPLEX_FULL;
1049 else if (duplex & DW_HALF_DUPLEX)
1050 state->duplex = DUPLEX_HALF;
1051
1052 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
1053 }
1054
1055 return 0;
1056}
1057
1058static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs,
1059 struct phylink_link_state *state)
1060{
1061 int lpa, bmsr;
1062
1063 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
1064 state->advertising)) {
1065 /* Reset link state */
1066 state->link = false;
1067
1068 lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA);
1069 if (lpa < 0 || lpa & LPA_RFAULT)
1070 return lpa;
1071
1072 bmsr = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR);
1073 if (bmsr < 0)
1074 return bmsr;
1075
1076 /* Clear AN complete interrupt */
1077 if (!xpcs->pcs.poll) {
1078 int an_intr;
1079
1080 an_intr = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS);
1081 if (an_intr & DW_VR_MII_AN_STS_C37_ANCMPLT_INTR) {
1082 an_intr &= ~DW_VR_MII_AN_STS_C37_ANCMPLT_INTR;
1083 xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, an_intr);
1084 }
1085 }
1086
1087 phylink_mii_c22_pcs_decode_state(state, bmsr, lpa);
1088 }
1089
1090 return 0;
1091}
1092
1093static int xpcs_get_state_2500basex(struct dw_xpcs *xpcs,
1094 struct phylink_link_state *state)
1095{
1096 int ret;
1097
1098 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_STS);
1099 if (ret < 0) {
1100 state->link = 0;
1101 return ret;
1102 }
1103
1104 state->link = !!(ret & DW_VR_MII_MMD_STS_LINK_STS);
1105 if (!state->link)
1106 return 0;
1107
1108 state->speed = SPEED_2500;
1109 state->pause |= MLO_PAUSE_TX | MLO_PAUSE_RX;
1110 state->duplex = DUPLEX_FULL;
1111
1112 return 0;
1113}
1114
1115static void xpcs_get_state(struct phylink_pcs *pcs,
1116 struct phylink_link_state *state)
1117{
1118 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
1119 const struct xpcs_compat *compat;
1120 int ret;
1121
1122 compat = xpcs_find_compat(xpcs->id, state->interface);
1123 if (!compat)
1124 return;
1125
1126 switch (compat->an_mode) {
1127 case DW_10GBASER:
1128 phylink_mii_c45_pcs_get_state(xpcs->mdiodev, state);
1129 break;
1130 case DW_AN_C73:
1131 ret = xpcs_get_state_c73(xpcs, state, compat);
1132 if (ret) {
1133 pr_err("xpcs_get_state_c73 returned %pe\n",
1134 ERR_PTR(ret));
1135 return;
1136 }
1137 break;
1138 case DW_AN_C37_SGMII:
1139 ret = xpcs_get_state_c37_sgmii(xpcs, state);
1140 if (ret) {
1141 pr_err("xpcs_get_state_c37_sgmii returned %pe\n",
1142 ERR_PTR(ret));
1143 }
1144 break;
1145 case DW_AN_C37_1000BASEX:
1146 ret = xpcs_get_state_c37_1000basex(xpcs, state);
1147 if (ret) {
1148 pr_err("xpcs_get_state_c37_1000basex returned %pe\n",
1149 ERR_PTR(ret));
1150 }
1151 break;
1152 case DW_2500BASEX:
1153 ret = xpcs_get_state_2500basex(xpcs, state);
1154 if (ret) {
1155 pr_err("xpcs_get_state_2500basex returned %pe\n",
1156 ERR_PTR(ret));
1157 }
1158 break;
1159 default:
1160 return;
1161 }
1162}
1163
1164static void xpcs_link_up_sgmii(struct dw_xpcs *xpcs, unsigned int neg_mode,
1165 int speed, int duplex)
1166{
1167 int val, ret;
1168
1169 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
1170 return;
1171
1172 val = mii_bmcr_encode_fixed(speed, duplex);
1173 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
1174 if (ret)
1175 pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret));
1176}
1177
1178static void xpcs_link_up_1000basex(struct dw_xpcs *xpcs, unsigned int neg_mode,
1179 int speed, int duplex)
1180{
1181 int val, ret;
1182
1183 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
1184 return;
1185
1186 switch (speed) {
1187 case SPEED_1000:
1188 val = BMCR_SPEED1000;
1189 break;
1190 case SPEED_100:
1191 case SPEED_10:
1192 default:
1193 pr_err("%s: speed = %d\n", __func__, speed);
1194 return;
1195 }
1196
1197 if (duplex == DUPLEX_FULL)
1198 val |= BMCR_FULLDPLX;
1199 else
1200 pr_err("%s: half duplex not supported\n", __func__);
1201
1202 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
1203 if (ret)
1204 pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret));
1205}
1206
1207void xpcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
1208 phy_interface_t interface, int speed, int duplex)
1209{
1210 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
1211
1212 if (interface == PHY_INTERFACE_MODE_USXGMII)
1213 return xpcs_config_usxgmii(xpcs, speed);
1214 if (interface == PHY_INTERFACE_MODE_SGMII)
1215 return xpcs_link_up_sgmii(xpcs, neg_mode, speed, duplex);
1216 if (interface == PHY_INTERFACE_MODE_1000BASEX)
1217 return xpcs_link_up_1000basex(xpcs, neg_mode, speed, duplex);
1218}
1219EXPORT_SYMBOL_GPL(xpcs_link_up);
1220
1221static void xpcs_an_restart(struct phylink_pcs *pcs)
1222{
1223 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
1224 int ret;
1225
1226 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
1227 if (ret >= 0) {
1228 ret |= BMCR_ANRESTART;
1229 xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret);
1230 }
1231}
1232
1233static u32 xpcs_get_id(struct dw_xpcs *xpcs)
1234{
1235 int ret;
1236 u32 id;
1237
1238 /* First, search C73 PCS using PCS MMD */
1239 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1);
1240 if (ret < 0)
1241 return 0xffffffff;
1242
1243 id = ret << 16;
1244
1245 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2);
1246 if (ret < 0)
1247 return 0xffffffff;
1248
1249 /* If Device IDs are not all zeros or all ones,
1250 * we found C73 AN-type device
1251 */
1252 if ((id | ret) && (id | ret) != 0xffffffff)
1253 return id | ret;
1254
1255 /* Next, search C37 PCS using Vendor-Specific MII MMD */
1256 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1);
1257 if (ret < 0)
1258 return 0xffffffff;
1259
1260 id = ret << 16;
1261
1262 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2);
1263 if (ret < 0)
1264 return 0xffffffff;
1265
1266 /* If Device IDs are not all zeros, we found C37 AN-type device */
1267 if (id | ret)
1268 return id | ret;
1269
1270 return 0xffffffff;
1271}
1272
1273static const struct xpcs_compat synopsys_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1274 [DW_XPCS_USXGMII] = {
1275 .supported = xpcs_usxgmii_features,
1276 .interface = xpcs_usxgmii_interfaces,
1277 .num_interfaces = ARRAY_SIZE(xpcs_usxgmii_interfaces),
1278 .an_mode = DW_AN_C73,
1279 },
1280 [DW_XPCS_10GKR] = {
1281 .supported = xpcs_10gkr_features,
1282 .interface = xpcs_10gkr_interfaces,
1283 .num_interfaces = ARRAY_SIZE(xpcs_10gkr_interfaces),
1284 .an_mode = DW_AN_C73,
1285 },
1286 [DW_XPCS_XLGMII] = {
1287 .supported = xpcs_xlgmii_features,
1288 .interface = xpcs_xlgmii_interfaces,
1289 .num_interfaces = ARRAY_SIZE(xpcs_xlgmii_interfaces),
1290 .an_mode = DW_AN_C73,
1291 },
1292 [DW_XPCS_10GBASER] = {
1293 .supported = xpcs_10gbaser_features,
1294 .interface = xpcs_10gbaser_interfaces,
1295 .num_interfaces = ARRAY_SIZE(xpcs_10gbaser_interfaces),
1296 .an_mode = DW_10GBASER,
1297 },
1298 [DW_XPCS_SGMII] = {
1299 .supported = xpcs_sgmii_features,
1300 .interface = xpcs_sgmii_interfaces,
1301 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1302 .an_mode = DW_AN_C37_SGMII,
1303 },
1304 [DW_XPCS_1000BASEX] = {
1305 .supported = xpcs_1000basex_features,
1306 .interface = xpcs_1000basex_interfaces,
1307 .num_interfaces = ARRAY_SIZE(xpcs_1000basex_interfaces),
1308 .an_mode = DW_AN_C37_1000BASEX,
1309 },
1310 [DW_XPCS_2500BASEX] = {
1311 .supported = xpcs_2500basex_features,
1312 .interface = xpcs_2500basex_interfaces,
1313 .num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces),
1314 .an_mode = DW_2500BASEX,
1315 },
1316};
1317
1318static const struct xpcs_compat nxp_sja1105_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1319 [DW_XPCS_SGMII] = {
1320 .supported = xpcs_sgmii_features,
1321 .interface = xpcs_sgmii_interfaces,
1322 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1323 .an_mode = DW_AN_C37_SGMII,
1324 .pma_config = nxp_sja1105_sgmii_pma_config,
1325 },
1326};
1327
1328static const struct xpcs_compat nxp_sja1110_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1329 [DW_XPCS_SGMII] = {
1330 .supported = xpcs_sgmii_features,
1331 .interface = xpcs_sgmii_interfaces,
1332 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1333 .an_mode = DW_AN_C37_SGMII,
1334 .pma_config = nxp_sja1110_sgmii_pma_config,
1335 },
1336 [DW_XPCS_2500BASEX] = {
1337 .supported = xpcs_2500basex_features,
1338 .interface = xpcs_2500basex_interfaces,
1339 .num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces),
1340 .an_mode = DW_2500BASEX,
1341 .pma_config = nxp_sja1110_2500basex_pma_config,
1342 },
1343};
1344
1345static const struct xpcs_id xpcs_id_list[] = {
1346 {
1347 .id = SYNOPSYS_XPCS_ID,
1348 .mask = SYNOPSYS_XPCS_MASK,
1349 .compat = synopsys_xpcs_compat,
1350 }, {
1351 .id = NXP_SJA1105_XPCS_ID,
1352 .mask = SYNOPSYS_XPCS_MASK,
1353 .compat = nxp_sja1105_xpcs_compat,
1354 }, {
1355 .id = NXP_SJA1110_XPCS_ID,
1356 .mask = SYNOPSYS_XPCS_MASK,
1357 .compat = nxp_sja1110_xpcs_compat,
1358 },
1359};
1360
1361static const struct phylink_pcs_ops xpcs_phylink_ops = {
1362 .pcs_validate = xpcs_validate,
1363 .pcs_config = xpcs_config,
1364 .pcs_get_state = xpcs_get_state,
1365 .pcs_an_restart = xpcs_an_restart,
1366 .pcs_link_up = xpcs_link_up,
1367};
1368
1369static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev,
1370 phy_interface_t interface)
1371{
1372 struct dw_xpcs *xpcs;
1373 u32 xpcs_id;
1374 int i, ret;
1375
1376 xpcs = kzalloc(sizeof(*xpcs), GFP_KERNEL);
1377 if (!xpcs)
1378 return ERR_PTR(-ENOMEM);
1379
1380 mdio_device_get(mdiodev);
1381 xpcs->mdiodev = mdiodev;
1382
1383 xpcs_id = xpcs_get_id(xpcs);
1384
1385 for (i = 0; i < ARRAY_SIZE(xpcs_id_list); i++) {
1386 const struct xpcs_id *entry = &xpcs_id_list[i];
1387 const struct xpcs_compat *compat;
1388
1389 if ((xpcs_id & entry->mask) != entry->id)
1390 continue;
1391
1392 xpcs->id = entry;
1393
1394 compat = xpcs_find_compat(entry, interface);
1395 if (!compat) {
1396 ret = -ENODEV;
1397 goto out;
1398 }
1399
1400 ret = xpcs_dev_flag(xpcs);
1401 if (ret)
1402 goto out;
1403
1404 xpcs->pcs.ops = &xpcs_phylink_ops;
1405 xpcs->pcs.neg_mode = true;
1406
1407 if (xpcs->dev_flag != DW_DEV_TXGBE) {
1408 xpcs->pcs.poll = true;
1409
1410 ret = xpcs_soft_reset(xpcs, compat);
1411 if (ret)
1412 goto out;
1413 }
1414
1415 return xpcs;
1416 }
1417
1418 ret = -ENODEV;
1419
1420out:
1421 mdio_device_put(mdiodev);
1422 kfree(xpcs);
1423
1424 return ERR_PTR(ret);
1425}
1426
1427void xpcs_destroy(struct dw_xpcs *xpcs)
1428{
1429 if (xpcs)
1430 mdio_device_put(xpcs->mdiodev);
1431 kfree(xpcs);
1432}
1433EXPORT_SYMBOL_GPL(xpcs_destroy);
1434
1435struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr,
1436 phy_interface_t interface)
1437{
1438 struct mdio_device *mdiodev;
1439 struct dw_xpcs *xpcs;
1440
1441 mdiodev = mdio_device_create(bus, addr);
1442 if (IS_ERR(mdiodev))
1443 return ERR_CAST(mdiodev);
1444
1445 xpcs = xpcs_create(mdiodev, interface);
1446
1447 /* xpcs_create() has taken a refcount on the mdiodev if it was
1448 * successful. If xpcs_create() fails, this will free the mdio
1449 * device here. In any case, we don't need to hold our reference
1450 * anymore, and putting it here will allow mdio_device_put() in
1451 * xpcs_destroy() to automatically free the mdio device.
1452 */
1453 mdio_device_put(mdiodev);
1454
1455 return xpcs;
1456}
1457EXPORT_SYMBOL_GPL(xpcs_create_mdiodev);
1458
1459MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare XPCS helpers
5 *
6 * Author: Jose Abreu <Jose.Abreu@synopsys.com>
7 */
8
9#include <linux/delay.h>
10#include <linux/pcs/pcs-xpcs.h>
11#include <linux/mdio.h>
12#include <linux/phylink.h>
13#include <linux/workqueue.h>
14#include "pcs-xpcs.h"
15
16#define phylink_pcs_to_xpcs(pl_pcs) \
17 container_of((pl_pcs), struct dw_xpcs, pcs)
18
19static const int xpcs_usxgmii_features[] = {
20 ETHTOOL_LINK_MODE_Pause_BIT,
21 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
22 ETHTOOL_LINK_MODE_Autoneg_BIT,
23 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
24 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
25 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
26 ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
27 __ETHTOOL_LINK_MODE_MASK_NBITS,
28};
29
30static const int xpcs_10gkr_features[] = {
31 ETHTOOL_LINK_MODE_Pause_BIT,
32 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
33 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
34 __ETHTOOL_LINK_MODE_MASK_NBITS,
35};
36
37static const int xpcs_xlgmii_features[] = {
38 ETHTOOL_LINK_MODE_Pause_BIT,
39 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
40 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
41 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
42 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
43 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
44 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
45 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
46 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
47 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
48 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
49 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
50 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
51 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
52 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
53 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
54 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
55 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
56 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
57 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
58 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
59 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
60 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
61 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
62 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
63 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
64 __ETHTOOL_LINK_MODE_MASK_NBITS,
65};
66
67static const int xpcs_sgmii_features[] = {
68 ETHTOOL_LINK_MODE_10baseT_Half_BIT,
69 ETHTOOL_LINK_MODE_10baseT_Full_BIT,
70 ETHTOOL_LINK_MODE_100baseT_Half_BIT,
71 ETHTOOL_LINK_MODE_100baseT_Full_BIT,
72 ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
73 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
74 __ETHTOOL_LINK_MODE_MASK_NBITS,
75};
76
77static const int xpcs_2500basex_features[] = {
78 ETHTOOL_LINK_MODE_Asym_Pause_BIT,
79 ETHTOOL_LINK_MODE_Autoneg_BIT,
80 ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
81 ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
82 __ETHTOOL_LINK_MODE_MASK_NBITS,
83};
84
85static const phy_interface_t xpcs_usxgmii_interfaces[] = {
86 PHY_INTERFACE_MODE_USXGMII,
87};
88
89static const phy_interface_t xpcs_10gkr_interfaces[] = {
90 PHY_INTERFACE_MODE_10GKR,
91};
92
93static const phy_interface_t xpcs_xlgmii_interfaces[] = {
94 PHY_INTERFACE_MODE_XLGMII,
95};
96
97static const phy_interface_t xpcs_sgmii_interfaces[] = {
98 PHY_INTERFACE_MODE_SGMII,
99};
100
101static const phy_interface_t xpcs_2500basex_interfaces[] = {
102 PHY_INTERFACE_MODE_2500BASEX,
103 PHY_INTERFACE_MODE_MAX,
104};
105
106enum {
107 DW_XPCS_USXGMII,
108 DW_XPCS_10GKR,
109 DW_XPCS_XLGMII,
110 DW_XPCS_SGMII,
111 DW_XPCS_2500BASEX,
112 DW_XPCS_INTERFACE_MAX,
113};
114
115struct xpcs_compat {
116 const int *supported;
117 const phy_interface_t *interface;
118 int num_interfaces;
119 int an_mode;
120 int (*pma_config)(struct dw_xpcs *xpcs);
121};
122
123struct xpcs_id {
124 u32 id;
125 u32 mask;
126 const struct xpcs_compat *compat;
127};
128
129static const struct xpcs_compat *xpcs_find_compat(const struct xpcs_id *id,
130 phy_interface_t interface)
131{
132 int i, j;
133
134 for (i = 0; i < DW_XPCS_INTERFACE_MAX; i++) {
135 const struct xpcs_compat *compat = &id->compat[i];
136
137 for (j = 0; j < compat->num_interfaces; j++)
138 if (compat->interface[j] == interface)
139 return compat;
140 }
141
142 return NULL;
143}
144
145int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface)
146{
147 const struct xpcs_compat *compat;
148
149 compat = xpcs_find_compat(xpcs->id, interface);
150 if (!compat)
151 return -ENODEV;
152
153 return compat->an_mode;
154}
155EXPORT_SYMBOL_GPL(xpcs_get_an_mode);
156
157static bool __xpcs_linkmode_supported(const struct xpcs_compat *compat,
158 enum ethtool_link_mode_bit_indices linkmode)
159{
160 int i;
161
162 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++)
163 if (compat->supported[i] == linkmode)
164 return true;
165
166 return false;
167}
168
169#define xpcs_linkmode_supported(compat, mode) \
170 __xpcs_linkmode_supported(compat, ETHTOOL_LINK_MODE_ ## mode ## _BIT)
171
172int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg)
173{
174 u32 reg_addr = mdiobus_c45_addr(dev, reg);
175 struct mii_bus *bus = xpcs->mdiodev->bus;
176 int addr = xpcs->mdiodev->addr;
177
178 return mdiobus_read(bus, addr, reg_addr);
179}
180
181int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val)
182{
183 u32 reg_addr = mdiobus_c45_addr(dev, reg);
184 struct mii_bus *bus = xpcs->mdiodev->bus;
185 int addr = xpcs->mdiodev->addr;
186
187 return mdiobus_write(bus, addr, reg_addr, val);
188}
189
190static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg)
191{
192 return xpcs_read(xpcs, dev, DW_VENDOR | reg);
193}
194
195static int xpcs_write_vendor(struct dw_xpcs *xpcs, int dev, int reg,
196 u16 val)
197{
198 return xpcs_write(xpcs, dev, DW_VENDOR | reg, val);
199}
200
201static int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg)
202{
203 return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg);
204}
205
206static int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val)
207{
208 return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val);
209}
210
211static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev)
212{
213 /* Poll until the reset bit clears (50ms per retry == 0.6 sec) */
214 unsigned int retries = 12;
215 int ret;
216
217 do {
218 msleep(50);
219 ret = xpcs_read(xpcs, dev, MDIO_CTRL1);
220 if (ret < 0)
221 return ret;
222 } while (ret & MDIO_CTRL1_RESET && --retries);
223
224 return (ret & MDIO_CTRL1_RESET) ? -ETIMEDOUT : 0;
225}
226
227static int xpcs_soft_reset(struct dw_xpcs *xpcs,
228 const struct xpcs_compat *compat)
229{
230 int ret, dev;
231
232 switch (compat->an_mode) {
233 case DW_AN_C73:
234 dev = MDIO_MMD_PCS;
235 break;
236 case DW_AN_C37_SGMII:
237 case DW_2500BASEX:
238 dev = MDIO_MMD_VEND2;
239 break;
240 default:
241 return -1;
242 }
243
244 ret = xpcs_write(xpcs, dev, MDIO_CTRL1, MDIO_CTRL1_RESET);
245 if (ret < 0)
246 return ret;
247
248 return xpcs_poll_reset(xpcs, dev);
249}
250
251#define xpcs_warn(__xpcs, __state, __args...) \
252({ \
253 if ((__state)->link) \
254 dev_warn(&(__xpcs)->mdiodev->dev, ##__args); \
255})
256
257static int xpcs_read_fault_c73(struct dw_xpcs *xpcs,
258 struct phylink_link_state *state)
259{
260 int ret;
261
262 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1);
263 if (ret < 0)
264 return ret;
265
266 if (ret & MDIO_STAT1_FAULT) {
267 xpcs_warn(xpcs, state, "Link fault condition detected!\n");
268 return -EFAULT;
269 }
270
271 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2);
272 if (ret < 0)
273 return ret;
274
275 if (ret & MDIO_STAT2_RXFAULT)
276 xpcs_warn(xpcs, state, "Receiver fault detected!\n");
277 if (ret & MDIO_STAT2_TXFAULT)
278 xpcs_warn(xpcs, state, "Transmitter fault detected!\n");
279
280 ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS);
281 if (ret < 0)
282 return ret;
283
284 if (ret & DW_RXFIFO_ERR) {
285 xpcs_warn(xpcs, state, "FIFO fault condition detected!\n");
286 return -EFAULT;
287 }
288
289 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1);
290 if (ret < 0)
291 return ret;
292
293 if (!(ret & MDIO_PCS_10GBRT_STAT1_BLKLK))
294 xpcs_warn(xpcs, state, "Link is not locked!\n");
295
296 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2);
297 if (ret < 0)
298 return ret;
299
300 if (ret & MDIO_PCS_10GBRT_STAT2_ERR) {
301 xpcs_warn(xpcs, state, "Link has errors!\n");
302 return -EFAULT;
303 }
304
305 return 0;
306}
307
308static int xpcs_read_link_c73(struct dw_xpcs *xpcs, bool an)
309{
310 bool link = true;
311 int ret;
312
313 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1);
314 if (ret < 0)
315 return ret;
316
317 if (!(ret & MDIO_STAT1_LSTATUS))
318 link = false;
319
320 if (an) {
321 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
322 if (ret < 0)
323 return ret;
324
325 if (!(ret & MDIO_STAT1_LSTATUS))
326 link = false;
327 }
328
329 return link;
330}
331
332static int xpcs_get_max_usxgmii_speed(const unsigned long *supported)
333{
334 int max = SPEED_UNKNOWN;
335
336 if (phylink_test(supported, 1000baseKX_Full))
337 max = SPEED_1000;
338 if (phylink_test(supported, 2500baseX_Full))
339 max = SPEED_2500;
340 if (phylink_test(supported, 10000baseKX4_Full))
341 max = SPEED_10000;
342 if (phylink_test(supported, 10000baseKR_Full))
343 max = SPEED_10000;
344
345 return max;
346}
347
348static void xpcs_config_usxgmii(struct dw_xpcs *xpcs, int speed)
349{
350 int ret, speed_sel;
351
352 switch (speed) {
353 case SPEED_10:
354 speed_sel = DW_USXGMII_10;
355 break;
356 case SPEED_100:
357 speed_sel = DW_USXGMII_100;
358 break;
359 case SPEED_1000:
360 speed_sel = DW_USXGMII_1000;
361 break;
362 case SPEED_2500:
363 speed_sel = DW_USXGMII_2500;
364 break;
365 case SPEED_5000:
366 speed_sel = DW_USXGMII_5000;
367 break;
368 case SPEED_10000:
369 speed_sel = DW_USXGMII_10000;
370 break;
371 default:
372 /* Nothing to do here */
373 return;
374 }
375
376 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1);
377 if (ret < 0)
378 goto out;
379
380 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_EN);
381 if (ret < 0)
382 goto out;
383
384 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
385 if (ret < 0)
386 goto out;
387
388 ret &= ~DW_USXGMII_SS_MASK;
389 ret |= speed_sel | DW_USXGMII_FULL;
390
391 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret);
392 if (ret < 0)
393 goto out;
394
395 ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1);
396 if (ret < 0)
397 goto out;
398
399 ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_RST);
400 if (ret < 0)
401 goto out;
402
403 return;
404
405out:
406 pr_err("%s: XPCS access returned %pe\n", __func__, ERR_PTR(ret));
407}
408
409static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
410 const struct xpcs_compat *compat)
411{
412 int ret, adv;
413
414 /* By default, in USXGMII mode XPCS operates at 10G baud and
415 * replicates data to achieve lower speeds. Hereby, in this
416 * default configuration we need to advertise all supported
417 * modes and not only the ones we want to use.
418 */
419
420 /* SR_AN_ADV3 */
421 adv = 0;
422 if (xpcs_linkmode_supported(compat, 2500baseX_Full))
423 adv |= DW_C73_2500KX;
424
425 /* TODO: 5000baseKR */
426
427 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv);
428 if (ret < 0)
429 return ret;
430
431 /* SR_AN_ADV2 */
432 adv = 0;
433 if (xpcs_linkmode_supported(compat, 1000baseKX_Full))
434 adv |= DW_C73_1000KX;
435 if (xpcs_linkmode_supported(compat, 10000baseKX4_Full))
436 adv |= DW_C73_10000KX4;
437 if (xpcs_linkmode_supported(compat, 10000baseKR_Full))
438 adv |= DW_C73_10000KR;
439
440 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv);
441 if (ret < 0)
442 return ret;
443
444 /* SR_AN_ADV1 */
445 adv = DW_C73_AN_ADV_SF;
446 if (xpcs_linkmode_supported(compat, Pause))
447 adv |= DW_C73_PAUSE;
448 if (xpcs_linkmode_supported(compat, Asym_Pause))
449 adv |= DW_C73_ASYM_PAUSE;
450
451 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv);
452}
453
454static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
455 const struct xpcs_compat *compat)
456{
457 int ret;
458
459 ret = _xpcs_config_aneg_c73(xpcs, compat);
460 if (ret < 0)
461 return ret;
462
463 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_CTRL1);
464 if (ret < 0)
465 return ret;
466
467 ret |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART;
468
469 return xpcs_write(xpcs, MDIO_MMD_AN, MDIO_CTRL1, ret);
470}
471
472static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs,
473 struct phylink_link_state *state,
474 const struct xpcs_compat *compat)
475{
476 int ret;
477
478 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
479 if (ret < 0)
480 return ret;
481
482 if (ret & MDIO_AN_STAT1_COMPLETE) {
483 ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL1);
484 if (ret < 0)
485 return ret;
486
487 /* Check if Aneg outcome is valid */
488 if (!(ret & DW_C73_AN_ADV_SF)) {
489 xpcs_config_aneg_c73(xpcs, compat);
490 return 0;
491 }
492
493 return 1;
494 }
495
496 return 0;
497}
498
499static int xpcs_read_lpa_c73(struct dw_xpcs *xpcs,
500 struct phylink_link_state *state)
501{
502 int ret;
503
504 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
505 if (ret < 0)
506 return ret;
507
508 if (!(ret & MDIO_AN_STAT1_LPABLE)) {
509 phylink_clear(state->lp_advertising, Autoneg);
510 return 0;
511 }
512
513 phylink_set(state->lp_advertising, Autoneg);
514
515 /* Clause 73 outcome */
516 ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL3);
517 if (ret < 0)
518 return ret;
519
520 if (ret & DW_C73_2500KX)
521 phylink_set(state->lp_advertising, 2500baseX_Full);
522
523 ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL2);
524 if (ret < 0)
525 return ret;
526
527 if (ret & DW_C73_1000KX)
528 phylink_set(state->lp_advertising, 1000baseKX_Full);
529 if (ret & DW_C73_10000KX4)
530 phylink_set(state->lp_advertising, 10000baseKX4_Full);
531 if (ret & DW_C73_10000KR)
532 phylink_set(state->lp_advertising, 10000baseKR_Full);
533
534 ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL1);
535 if (ret < 0)
536 return ret;
537
538 if (ret & DW_C73_PAUSE)
539 phylink_set(state->lp_advertising, Pause);
540 if (ret & DW_C73_ASYM_PAUSE)
541 phylink_set(state->lp_advertising, Asym_Pause);
542
543 linkmode_and(state->lp_advertising, state->lp_advertising,
544 state->advertising);
545 return 0;
546}
547
548static void xpcs_resolve_lpa_c73(struct dw_xpcs *xpcs,
549 struct phylink_link_state *state)
550{
551 int max_speed = xpcs_get_max_usxgmii_speed(state->lp_advertising);
552
553 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX;
554 state->speed = max_speed;
555 state->duplex = DUPLEX_FULL;
556}
557
558static int xpcs_get_max_xlgmii_speed(struct dw_xpcs *xpcs,
559 struct phylink_link_state *state)
560{
561 unsigned long *adv = state->advertising;
562 int speed = SPEED_UNKNOWN;
563 int bit;
564
565 for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) {
566 int new_speed = SPEED_UNKNOWN;
567
568 switch (bit) {
569 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT:
570 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT:
571 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT:
572 new_speed = SPEED_25000;
573 break;
574 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT:
575 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT:
576 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT:
577 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT:
578 new_speed = SPEED_40000;
579 break;
580 case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT:
581 case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT:
582 case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT:
583 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT:
584 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT:
585 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT:
586 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT:
587 case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT:
588 new_speed = SPEED_50000;
589 break;
590 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT:
591 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT:
592 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT:
593 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT:
594 case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT:
595 case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT:
596 case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT:
597 case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT:
598 case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT:
599 new_speed = SPEED_100000;
600 break;
601 default:
602 continue;
603 }
604
605 if (new_speed > speed)
606 speed = new_speed;
607 }
608
609 return speed;
610}
611
612static void xpcs_resolve_pma(struct dw_xpcs *xpcs,
613 struct phylink_link_state *state)
614{
615 state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX;
616 state->duplex = DUPLEX_FULL;
617
618 switch (state->interface) {
619 case PHY_INTERFACE_MODE_10GKR:
620 state->speed = SPEED_10000;
621 break;
622 case PHY_INTERFACE_MODE_XLGMII:
623 state->speed = xpcs_get_max_xlgmii_speed(xpcs, state);
624 break;
625 default:
626 state->speed = SPEED_UNKNOWN;
627 break;
628 }
629}
630
631void xpcs_validate(struct dw_xpcs *xpcs, unsigned long *supported,
632 struct phylink_link_state *state)
633{
634 __ETHTOOL_DECLARE_LINK_MODE_MASK(xpcs_supported);
635 const struct xpcs_compat *compat;
636 int i;
637
638 /* phylink expects us to report all supported modes with
639 * PHY_INTERFACE_MODE_NA, just don't limit the supported and
640 * advertising masks and exit.
641 */
642 if (state->interface == PHY_INTERFACE_MODE_NA)
643 return;
644
645 bitmap_zero(xpcs_supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
646
647 compat = xpcs_find_compat(xpcs->id, state->interface);
648
649 /* Populate the supported link modes for this
650 * PHY interface type
651 */
652 if (compat)
653 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++)
654 set_bit(compat->supported[i], xpcs_supported);
655
656 linkmode_and(supported, supported, xpcs_supported);
657 linkmode_and(state->advertising, state->advertising, xpcs_supported);
658}
659EXPORT_SYMBOL_GPL(xpcs_validate);
660
661int xpcs_config_eee(struct dw_xpcs *xpcs, int mult_fact_100ns, int enable)
662{
663 int ret;
664
665 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0);
666 if (ret < 0)
667 return ret;
668
669 if (enable) {
670 /* Enable EEE */
671 ret = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
672 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
673 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
674 mult_fact_100ns << DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT;
675 } else {
676 ret &= ~(DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
677 DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
678 DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
679 DW_VR_MII_EEE_MULT_FACT_100NS);
680 }
681
682 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, ret);
683 if (ret < 0)
684 return ret;
685
686 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1);
687 if (ret < 0)
688 return ret;
689
690 if (enable)
691 ret |= DW_VR_MII_EEE_TRN_LPI;
692 else
693 ret &= ~DW_VR_MII_EEE_TRN_LPI;
694
695 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, ret);
696}
697EXPORT_SYMBOL_GPL(xpcs_config_eee);
698
699static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, unsigned int mode)
700{
701 int ret, mdio_ctrl;
702
703 /* For AN for C37 SGMII mode, the settings are :-
704 * 1) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 0b (Disable SGMII AN in case
705 it is already enabled)
706 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 10b (SGMII AN)
707 * 3) VR_MII_AN_CTRL Bit(3) [TX_CONFIG] = 0b (MAC side SGMII)
708 * DW xPCS used with DW EQoS MAC is always MAC side SGMII.
709 * 4) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] = 1b (Automatic
710 * speed/duplex mode change by HW after SGMII AN complete)
711 * 5) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN)
712 *
713 * Note: Since it is MAC side SGMII, there is no need to set
714 * SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from
715 * PHY about the link state change after C28 AN is completed
716 * between PHY and Link Partner. There is also no need to
717 * trigger AN restart for MAC-side SGMII.
718 */
719 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
720 if (mdio_ctrl < 0)
721 return mdio_ctrl;
722
723 if (mdio_ctrl & AN_CL37_EN) {
724 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
725 mdio_ctrl & ~AN_CL37_EN);
726 if (ret < 0)
727 return ret;
728 }
729
730 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL);
731 if (ret < 0)
732 return ret;
733
734 ret &= ~(DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK);
735 ret |= (DW_VR_MII_PCS_MODE_C37_SGMII <<
736 DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT &
737 DW_VR_MII_PCS_MODE_MASK);
738 ret |= (DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII <<
739 DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT &
740 DW_VR_MII_TX_CONFIG_MASK);
741 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret);
742 if (ret < 0)
743 return ret;
744
745 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
746 if (ret < 0)
747 return ret;
748
749 if (phylink_autoneg_inband(mode))
750 ret |= DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
751 else
752 ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
753
754 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
755 if (ret < 0)
756 return ret;
757
758 if (phylink_autoneg_inband(mode))
759 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
760 mdio_ctrl | AN_CL37_EN);
761
762 return ret;
763}
764
765static int xpcs_config_2500basex(struct dw_xpcs *xpcs)
766{
767 int ret;
768
769 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
770 if (ret < 0)
771 return ret;
772 ret |= DW_VR_MII_DIG_CTRL1_2G5_EN;
773 ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
774 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
775 if (ret < 0)
776 return ret;
777
778 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
779 if (ret < 0)
780 return ret;
781 ret &= ~AN_CL37_EN;
782 ret |= SGMII_SPEED_SS6;
783 ret &= ~SGMII_SPEED_SS13;
784 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, ret);
785}
786
787int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface,
788 unsigned int mode)
789{
790 const struct xpcs_compat *compat;
791 int ret;
792
793 compat = xpcs_find_compat(xpcs->id, interface);
794 if (!compat)
795 return -ENODEV;
796
797 switch (compat->an_mode) {
798 case DW_AN_C73:
799 if (phylink_autoneg_inband(mode)) {
800 ret = xpcs_config_aneg_c73(xpcs, compat);
801 if (ret)
802 return ret;
803 }
804 break;
805 case DW_AN_C37_SGMII:
806 ret = xpcs_config_aneg_c37_sgmii(xpcs, mode);
807 if (ret)
808 return ret;
809 break;
810 case DW_2500BASEX:
811 ret = xpcs_config_2500basex(xpcs);
812 if (ret)
813 return ret;
814 break;
815 default:
816 return -1;
817 }
818
819 if (compat->pma_config) {
820 ret = compat->pma_config(xpcs);
821 if (ret)
822 return ret;
823 }
824
825 return 0;
826}
827EXPORT_SYMBOL_GPL(xpcs_do_config);
828
829static int xpcs_config(struct phylink_pcs *pcs, unsigned int mode,
830 phy_interface_t interface,
831 const unsigned long *advertising,
832 bool permit_pause_to_mac)
833{
834 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
835
836 return xpcs_do_config(xpcs, interface, mode);
837}
838
839static int xpcs_get_state_c73(struct dw_xpcs *xpcs,
840 struct phylink_link_state *state,
841 const struct xpcs_compat *compat)
842{
843 int ret;
844
845 /* Link needs to be read first ... */
846 state->link = xpcs_read_link_c73(xpcs, state->an_enabled) > 0 ? 1 : 0;
847
848 /* ... and then we check the faults. */
849 ret = xpcs_read_fault_c73(xpcs, state);
850 if (ret) {
851 ret = xpcs_soft_reset(xpcs, compat);
852 if (ret)
853 return ret;
854
855 state->link = 0;
856
857 return xpcs_do_config(xpcs, state->interface, MLO_AN_INBAND);
858 }
859
860 if (state->an_enabled && xpcs_aneg_done_c73(xpcs, state, compat)) {
861 state->an_complete = true;
862 xpcs_read_lpa_c73(xpcs, state);
863 xpcs_resolve_lpa_c73(xpcs, state);
864 } else if (state->an_enabled) {
865 state->link = 0;
866 } else if (state->link) {
867 xpcs_resolve_pma(xpcs, state);
868 }
869
870 return 0;
871}
872
873static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs,
874 struct phylink_link_state *state)
875{
876 int ret;
877
878 /* Reset link_state */
879 state->link = false;
880 state->speed = SPEED_UNKNOWN;
881 state->duplex = DUPLEX_UNKNOWN;
882 state->pause = 0;
883
884 /* For C37 SGMII mode, we check DW_VR_MII_AN_INTR_STS for link
885 * status, speed and duplex.
886 */
887 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS);
888 if (ret < 0)
889 return false;
890
891 if (ret & DW_VR_MII_C37_ANSGM_SP_LNKSTS) {
892 int speed_value;
893
894 state->link = true;
895
896 speed_value = (ret & DW_VR_MII_AN_STS_C37_ANSGM_SP) >>
897 DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT;
898 if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000)
899 state->speed = SPEED_1000;
900 else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100)
901 state->speed = SPEED_100;
902 else
903 state->speed = SPEED_10;
904
905 if (ret & DW_VR_MII_AN_STS_C37_ANSGM_FD)
906 state->duplex = DUPLEX_FULL;
907 else
908 state->duplex = DUPLEX_HALF;
909 }
910
911 return 0;
912}
913
914static void xpcs_get_state(struct phylink_pcs *pcs,
915 struct phylink_link_state *state)
916{
917 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
918 const struct xpcs_compat *compat;
919 int ret;
920
921 compat = xpcs_find_compat(xpcs->id, state->interface);
922 if (!compat)
923 return;
924
925 switch (compat->an_mode) {
926 case DW_AN_C73:
927 ret = xpcs_get_state_c73(xpcs, state, compat);
928 if (ret) {
929 pr_err("xpcs_get_state_c73 returned %pe\n",
930 ERR_PTR(ret));
931 return;
932 }
933 break;
934 case DW_AN_C37_SGMII:
935 ret = xpcs_get_state_c37_sgmii(xpcs, state);
936 if (ret) {
937 pr_err("xpcs_get_state_c37_sgmii returned %pe\n",
938 ERR_PTR(ret));
939 }
940 break;
941 default:
942 return;
943 }
944}
945
946static void xpcs_link_up_sgmii(struct dw_xpcs *xpcs, unsigned int mode,
947 int speed, int duplex)
948{
949 int val, ret;
950
951 if (phylink_autoneg_inband(mode))
952 return;
953
954 switch (speed) {
955 case SPEED_1000:
956 val = BMCR_SPEED1000;
957 break;
958 case SPEED_100:
959 val = BMCR_SPEED100;
960 break;
961 case SPEED_10:
962 val = BMCR_SPEED10;
963 break;
964 default:
965 return;
966 }
967
968 if (duplex == DUPLEX_FULL)
969 val |= BMCR_FULLDPLX;
970
971 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
972 if (ret)
973 pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret));
974}
975
976void xpcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
977 phy_interface_t interface, int speed, int duplex)
978{
979 struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
980
981 if (interface == PHY_INTERFACE_MODE_USXGMII)
982 return xpcs_config_usxgmii(xpcs, speed);
983 if (interface == PHY_INTERFACE_MODE_SGMII)
984 return xpcs_link_up_sgmii(xpcs, mode, speed, duplex);
985}
986EXPORT_SYMBOL_GPL(xpcs_link_up);
987
988static u32 xpcs_get_id(struct dw_xpcs *xpcs)
989{
990 int ret;
991 u32 id;
992
993 /* First, search C73 PCS using PCS MMD */
994 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1);
995 if (ret < 0)
996 return 0xffffffff;
997
998 id = ret << 16;
999
1000 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2);
1001 if (ret < 0)
1002 return 0xffffffff;
1003
1004 /* If Device IDs are not all zeros or all ones,
1005 * we found C73 AN-type device
1006 */
1007 if ((id | ret) && (id | ret) != 0xffffffff)
1008 return id | ret;
1009
1010 /* Next, search C37 PCS using Vendor-Specific MII MMD */
1011 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1);
1012 if (ret < 0)
1013 return 0xffffffff;
1014
1015 id = ret << 16;
1016
1017 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2);
1018 if (ret < 0)
1019 return 0xffffffff;
1020
1021 /* If Device IDs are not all zeros, we found C37 AN-type device */
1022 if (id | ret)
1023 return id | ret;
1024
1025 return 0xffffffff;
1026}
1027
1028static const struct xpcs_compat synopsys_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1029 [DW_XPCS_USXGMII] = {
1030 .supported = xpcs_usxgmii_features,
1031 .interface = xpcs_usxgmii_interfaces,
1032 .num_interfaces = ARRAY_SIZE(xpcs_usxgmii_interfaces),
1033 .an_mode = DW_AN_C73,
1034 },
1035 [DW_XPCS_10GKR] = {
1036 .supported = xpcs_10gkr_features,
1037 .interface = xpcs_10gkr_interfaces,
1038 .num_interfaces = ARRAY_SIZE(xpcs_10gkr_interfaces),
1039 .an_mode = DW_AN_C73,
1040 },
1041 [DW_XPCS_XLGMII] = {
1042 .supported = xpcs_xlgmii_features,
1043 .interface = xpcs_xlgmii_interfaces,
1044 .num_interfaces = ARRAY_SIZE(xpcs_xlgmii_interfaces),
1045 .an_mode = DW_AN_C73,
1046 },
1047 [DW_XPCS_SGMII] = {
1048 .supported = xpcs_sgmii_features,
1049 .interface = xpcs_sgmii_interfaces,
1050 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1051 .an_mode = DW_AN_C37_SGMII,
1052 },
1053 [DW_XPCS_2500BASEX] = {
1054 .supported = xpcs_2500basex_features,
1055 .interface = xpcs_2500basex_interfaces,
1056 .num_interfaces = ARRAY_SIZE(xpcs_2500basex_features),
1057 .an_mode = DW_2500BASEX,
1058 },
1059};
1060
1061static const struct xpcs_compat nxp_sja1105_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1062 [DW_XPCS_SGMII] = {
1063 .supported = xpcs_sgmii_features,
1064 .interface = xpcs_sgmii_interfaces,
1065 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1066 .an_mode = DW_AN_C37_SGMII,
1067 .pma_config = nxp_sja1105_sgmii_pma_config,
1068 },
1069};
1070
1071static const struct xpcs_compat nxp_sja1110_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1072 [DW_XPCS_SGMII] = {
1073 .supported = xpcs_sgmii_features,
1074 .interface = xpcs_sgmii_interfaces,
1075 .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1076 .an_mode = DW_AN_C37_SGMII,
1077 .pma_config = nxp_sja1110_sgmii_pma_config,
1078 },
1079 [DW_XPCS_2500BASEX] = {
1080 .supported = xpcs_2500basex_features,
1081 .interface = xpcs_2500basex_interfaces,
1082 .num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces),
1083 .an_mode = DW_2500BASEX,
1084 .pma_config = nxp_sja1110_2500basex_pma_config,
1085 },
1086};
1087
1088static const struct xpcs_id xpcs_id_list[] = {
1089 {
1090 .id = SYNOPSYS_XPCS_ID,
1091 .mask = SYNOPSYS_XPCS_MASK,
1092 .compat = synopsys_xpcs_compat,
1093 }, {
1094 .id = NXP_SJA1105_XPCS_ID,
1095 .mask = SYNOPSYS_XPCS_MASK,
1096 .compat = nxp_sja1105_xpcs_compat,
1097 }, {
1098 .id = NXP_SJA1110_XPCS_ID,
1099 .mask = SYNOPSYS_XPCS_MASK,
1100 .compat = nxp_sja1110_xpcs_compat,
1101 },
1102};
1103
1104static const struct phylink_pcs_ops xpcs_phylink_ops = {
1105 .pcs_config = xpcs_config,
1106 .pcs_get_state = xpcs_get_state,
1107 .pcs_link_up = xpcs_link_up,
1108};
1109
1110struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev,
1111 phy_interface_t interface)
1112{
1113 struct dw_xpcs *xpcs;
1114 u32 xpcs_id;
1115 int i, ret;
1116
1117 xpcs = kzalloc(sizeof(*xpcs), GFP_KERNEL);
1118 if (!xpcs)
1119 return ERR_PTR(-ENOMEM);
1120
1121 xpcs->mdiodev = mdiodev;
1122
1123 xpcs_id = xpcs_get_id(xpcs);
1124
1125 for (i = 0; i < ARRAY_SIZE(xpcs_id_list); i++) {
1126 const struct xpcs_id *entry = &xpcs_id_list[i];
1127 const struct xpcs_compat *compat;
1128
1129 if ((xpcs_id & entry->mask) != entry->id)
1130 continue;
1131
1132 xpcs->id = entry;
1133
1134 compat = xpcs_find_compat(entry, interface);
1135 if (!compat) {
1136 ret = -ENODEV;
1137 goto out;
1138 }
1139
1140 xpcs->pcs.ops = &xpcs_phylink_ops;
1141 xpcs->pcs.poll = true;
1142
1143 ret = xpcs_soft_reset(xpcs, compat);
1144 if (ret)
1145 goto out;
1146
1147 return xpcs;
1148 }
1149
1150 ret = -ENODEV;
1151
1152out:
1153 kfree(xpcs);
1154
1155 return ERR_PTR(ret);
1156}
1157EXPORT_SYMBOL_GPL(xpcs_create);
1158
1159void xpcs_destroy(struct dw_xpcs *xpcs)
1160{
1161 kfree(xpcs);
1162}
1163EXPORT_SYMBOL_GPL(xpcs_destroy);
1164
1165MODULE_LICENSE("GPL v2");