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1// SPDX-License-Identifier: GPL-2.0
2// IOMapped CAN bus driver for Bosch M_CAN controller
3// Copyright (C) 2014 Freescale Semiconductor, Inc.
4// Dong Aisheng <b29396@freescale.com>
5//
6// Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
7
8#include <linux/hrtimer.h>
9#include <linux/phy/phy.h>
10#include <linux/platform_device.h>
11
12#include "m_can.h"
13
14struct m_can_plat_priv {
15 struct m_can_classdev cdev;
16
17 void __iomem *base;
18 void __iomem *mram_base;
19};
20
21static inline struct m_can_plat_priv *cdev_to_priv(struct m_can_classdev *cdev)
22{
23 return container_of(cdev, struct m_can_plat_priv, cdev);
24}
25
26static u32 iomap_read_reg(struct m_can_classdev *cdev, int reg)
27{
28 struct m_can_plat_priv *priv = cdev_to_priv(cdev);
29
30 return readl(priv->base + reg);
31}
32
33static int iomap_read_fifo(struct m_can_classdev *cdev, int offset, void *val, size_t val_count)
34{
35 struct m_can_plat_priv *priv = cdev_to_priv(cdev);
36 void __iomem *src = priv->mram_base + offset;
37
38 while (val_count--) {
39 *(unsigned int *)val = ioread32(src);
40 val += 4;
41 src += 4;
42 }
43
44 return 0;
45}
46
47static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val)
48{
49 struct m_can_plat_priv *priv = cdev_to_priv(cdev);
50
51 writel(val, priv->base + reg);
52
53 return 0;
54}
55
56static int iomap_write_fifo(struct m_can_classdev *cdev, int offset,
57 const void *val, size_t val_count)
58{
59 struct m_can_plat_priv *priv = cdev_to_priv(cdev);
60 void __iomem *dst = priv->mram_base + offset;
61
62 while (val_count--) {
63 iowrite32(*(unsigned int *)val, dst);
64 val += 4;
65 dst += 4;
66 }
67
68 return 0;
69}
70
71static struct m_can_ops m_can_plat_ops = {
72 .read_reg = iomap_read_reg,
73 .write_reg = iomap_write_reg,
74 .write_fifo = iomap_write_fifo,
75 .read_fifo = iomap_read_fifo,
76};
77
78static int m_can_plat_probe(struct platform_device *pdev)
79{
80 struct m_can_classdev *mcan_class;
81 struct m_can_plat_priv *priv;
82 struct resource *res;
83 void __iomem *addr;
84 void __iomem *mram_addr;
85 struct phy *transceiver;
86 int irq = 0, ret = 0;
87
88 mcan_class = m_can_class_allocate_dev(&pdev->dev,
89 sizeof(struct m_can_plat_priv));
90 if (!mcan_class)
91 return -ENOMEM;
92
93 priv = cdev_to_priv(mcan_class);
94
95 ret = m_can_class_get_clocks(mcan_class);
96 if (ret)
97 goto probe_fail;
98
99 addr = devm_platform_ioremap_resource_byname(pdev, "m_can");
100 if (IS_ERR(addr)) {
101 ret = PTR_ERR(addr);
102 goto probe_fail;
103 }
104
105 if (device_property_present(mcan_class->dev, "interrupts") ||
106 device_property_present(mcan_class->dev, "interrupt-names")) {
107 irq = platform_get_irq_byname(pdev, "int0");
108 if (irq < 0) {
109 ret = irq;
110 goto probe_fail;
111 }
112 } else {
113 dev_dbg(mcan_class->dev, "Polling enabled, initialize hrtimer");
114 hrtimer_init(&mcan_class->hrtimer, CLOCK_MONOTONIC,
115 HRTIMER_MODE_REL_PINNED);
116 }
117
118 /* message ram could be shared */
119 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram");
120 if (!res) {
121 ret = -ENODEV;
122 goto probe_fail;
123 }
124
125 mram_addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
126 if (!mram_addr) {
127 ret = -ENOMEM;
128 goto probe_fail;
129 }
130
131 transceiver = devm_phy_optional_get(&pdev->dev, NULL);
132 if (IS_ERR(transceiver)) {
133 ret = PTR_ERR(transceiver);
134 dev_err_probe(&pdev->dev, ret, "failed to get phy\n");
135 goto probe_fail;
136 }
137
138 if (transceiver)
139 mcan_class->can.bitrate_max = transceiver->attrs.max_link_rate;
140
141 priv->base = addr;
142 priv->mram_base = mram_addr;
143
144 mcan_class->net->irq = irq;
145 mcan_class->pm_clock_support = 1;
146 mcan_class->can.clock.freq = clk_get_rate(mcan_class->cclk);
147 mcan_class->dev = &pdev->dev;
148 mcan_class->transceiver = transceiver;
149
150 mcan_class->ops = &m_can_plat_ops;
151
152 mcan_class->is_peripheral = false;
153
154 platform_set_drvdata(pdev, mcan_class);
155
156 pm_runtime_enable(mcan_class->dev);
157 ret = m_can_class_register(mcan_class);
158 if (ret)
159 goto out_runtime_disable;
160
161 return ret;
162
163out_runtime_disable:
164 pm_runtime_disable(mcan_class->dev);
165probe_fail:
166 m_can_class_free_dev(mcan_class->net);
167 return ret;
168}
169
170static __maybe_unused int m_can_suspend(struct device *dev)
171{
172 return m_can_class_suspend(dev);
173}
174
175static __maybe_unused int m_can_resume(struct device *dev)
176{
177 return m_can_class_resume(dev);
178}
179
180static void m_can_plat_remove(struct platform_device *pdev)
181{
182 struct m_can_plat_priv *priv = platform_get_drvdata(pdev);
183 struct m_can_classdev *mcan_class = &priv->cdev;
184
185 m_can_class_unregister(mcan_class);
186
187 m_can_class_free_dev(mcan_class->net);
188}
189
190static int __maybe_unused m_can_runtime_suspend(struct device *dev)
191{
192 struct m_can_plat_priv *priv = dev_get_drvdata(dev);
193 struct m_can_classdev *mcan_class = &priv->cdev;
194
195 clk_disable_unprepare(mcan_class->cclk);
196 clk_disable_unprepare(mcan_class->hclk);
197
198 return 0;
199}
200
201static int __maybe_unused m_can_runtime_resume(struct device *dev)
202{
203 struct m_can_plat_priv *priv = dev_get_drvdata(dev);
204 struct m_can_classdev *mcan_class = &priv->cdev;
205 int err;
206
207 err = clk_prepare_enable(mcan_class->hclk);
208 if (err)
209 return err;
210
211 err = clk_prepare_enable(mcan_class->cclk);
212 if (err)
213 clk_disable_unprepare(mcan_class->hclk);
214
215 return err;
216}
217
218static const struct dev_pm_ops m_can_pmops = {
219 SET_RUNTIME_PM_OPS(m_can_runtime_suspend,
220 m_can_runtime_resume, NULL)
221 SET_SYSTEM_SLEEP_PM_OPS(m_can_suspend, m_can_resume)
222};
223
224static const struct of_device_id m_can_of_table[] = {
225 { .compatible = "bosch,m_can", .data = NULL },
226 { /* sentinel */ },
227};
228MODULE_DEVICE_TABLE(of, m_can_of_table);
229
230static struct platform_driver m_can_plat_driver = {
231 .driver = {
232 .name = KBUILD_MODNAME,
233 .of_match_table = m_can_of_table,
234 .pm = &m_can_pmops,
235 },
236 .probe = m_can_plat_probe,
237 .remove_new = m_can_plat_remove,
238};
239
240module_platform_driver(m_can_plat_driver);
241
242MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>");
243MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
244MODULE_LICENSE("GPL v2");
245MODULE_DESCRIPTION("M_CAN driver for IO Mapped Bosch controllers");
1// SPDX-License-Identifier: GPL-2.0
2// IOMapped CAN bus driver for Bosch M_CAN controller
3// Copyright (C) 2014 Freescale Semiconductor, Inc.
4// Dong Aisheng <b29396@freescale.com>
5//
6// Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
7
8#include <linux/platform_device.h>
9
10#include "m_can.h"
11
12struct m_can_plat_priv {
13 struct m_can_classdev cdev;
14
15 void __iomem *base;
16 void __iomem *mram_base;
17};
18
19static inline struct m_can_plat_priv *cdev_to_priv(struct m_can_classdev *cdev)
20{
21 return container_of(cdev, struct m_can_plat_priv, cdev);
22}
23
24static u32 iomap_read_reg(struct m_can_classdev *cdev, int reg)
25{
26 struct m_can_plat_priv *priv = cdev_to_priv(cdev);
27
28 return readl(priv->base + reg);
29}
30
31static u32 iomap_read_fifo(struct m_can_classdev *cdev, int offset)
32{
33 struct m_can_plat_priv *priv = cdev_to_priv(cdev);
34
35 return readl(priv->mram_base + offset);
36}
37
38static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val)
39{
40 struct m_can_plat_priv *priv = cdev_to_priv(cdev);
41
42 writel(val, priv->base + reg);
43
44 return 0;
45}
46
47static int iomap_write_fifo(struct m_can_classdev *cdev, int offset, int val)
48{
49 struct m_can_plat_priv *priv = cdev_to_priv(cdev);
50
51 writel(val, priv->mram_base + offset);
52
53 return 0;
54}
55
56static struct m_can_ops m_can_plat_ops = {
57 .read_reg = iomap_read_reg,
58 .write_reg = iomap_write_reg,
59 .write_fifo = iomap_write_fifo,
60 .read_fifo = iomap_read_fifo,
61};
62
63static int m_can_plat_probe(struct platform_device *pdev)
64{
65 struct m_can_classdev *mcan_class;
66 struct m_can_plat_priv *priv;
67 struct resource *res;
68 void __iomem *addr;
69 void __iomem *mram_addr;
70 int irq, ret = 0;
71
72 mcan_class = m_can_class_allocate_dev(&pdev->dev,
73 sizeof(struct m_can_plat_priv));
74 if (!mcan_class)
75 return -ENOMEM;
76
77 priv = cdev_to_priv(mcan_class);
78
79 ret = m_can_class_get_clocks(mcan_class);
80 if (ret)
81 goto probe_fail;
82
83 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m_can");
84 addr = devm_ioremap_resource(&pdev->dev, res);
85 irq = platform_get_irq_byname(pdev, "int0");
86 if (IS_ERR(addr) || irq < 0) {
87 ret = -EINVAL;
88 goto probe_fail;
89 }
90
91 /* message ram could be shared */
92 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram");
93 if (!res) {
94 ret = -ENODEV;
95 goto probe_fail;
96 }
97
98 mram_addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
99 if (!mram_addr) {
100 ret = -ENOMEM;
101 goto probe_fail;
102 }
103
104 priv->base = addr;
105 priv->mram_base = mram_addr;
106
107 mcan_class->net->irq = irq;
108 mcan_class->pm_clock_support = 1;
109 mcan_class->can.clock.freq = clk_get_rate(mcan_class->cclk);
110 mcan_class->dev = &pdev->dev;
111
112 mcan_class->ops = &m_can_plat_ops;
113
114 mcan_class->is_peripheral = false;
115
116 platform_set_drvdata(pdev, mcan_class);
117
118 m_can_init_ram(mcan_class);
119
120 pm_runtime_enable(mcan_class->dev);
121 ret = m_can_class_register(mcan_class);
122 if (ret)
123 goto out_runtime_disable;
124
125 return ret;
126
127out_runtime_disable:
128 pm_runtime_disable(mcan_class->dev);
129probe_fail:
130 m_can_class_free_dev(mcan_class->net);
131 return ret;
132}
133
134static __maybe_unused int m_can_suspend(struct device *dev)
135{
136 return m_can_class_suspend(dev);
137}
138
139static __maybe_unused int m_can_resume(struct device *dev)
140{
141 return m_can_class_resume(dev);
142}
143
144static int m_can_plat_remove(struct platform_device *pdev)
145{
146 struct m_can_plat_priv *priv = platform_get_drvdata(pdev);
147 struct m_can_classdev *mcan_class = &priv->cdev;
148
149 m_can_class_unregister(mcan_class);
150
151 m_can_class_free_dev(mcan_class->net);
152
153 return 0;
154}
155
156static int __maybe_unused m_can_runtime_suspend(struct device *dev)
157{
158 struct m_can_plat_priv *priv = dev_get_drvdata(dev);
159 struct m_can_classdev *mcan_class = &priv->cdev;
160
161 clk_disable_unprepare(mcan_class->cclk);
162 clk_disable_unprepare(mcan_class->hclk);
163
164 return 0;
165}
166
167static int __maybe_unused m_can_runtime_resume(struct device *dev)
168{
169 struct m_can_plat_priv *priv = dev_get_drvdata(dev);
170 struct m_can_classdev *mcan_class = &priv->cdev;
171 int err;
172
173 err = clk_prepare_enable(mcan_class->hclk);
174 if (err)
175 return err;
176
177 err = clk_prepare_enable(mcan_class->cclk);
178 if (err)
179 clk_disable_unprepare(mcan_class->hclk);
180
181 return err;
182}
183
184static const struct dev_pm_ops m_can_pmops = {
185 SET_RUNTIME_PM_OPS(m_can_runtime_suspend,
186 m_can_runtime_resume, NULL)
187 SET_SYSTEM_SLEEP_PM_OPS(m_can_suspend, m_can_resume)
188};
189
190static const struct of_device_id m_can_of_table[] = {
191 { .compatible = "bosch,m_can", .data = NULL },
192 { /* sentinel */ },
193};
194MODULE_DEVICE_TABLE(of, m_can_of_table);
195
196static struct platform_driver m_can_plat_driver = {
197 .driver = {
198 .name = KBUILD_MODNAME,
199 .of_match_table = m_can_of_table,
200 .pm = &m_can_pmops,
201 },
202 .probe = m_can_plat_probe,
203 .remove = m_can_plat_remove,
204};
205
206module_platform_driver(m_can_plat_driver);
207
208MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>");
209MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
210MODULE_LICENSE("GPL v2");
211MODULE_DESCRIPTION("M_CAN driver for IO Mapped Bosch controllers");