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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI Specific M_CAN Glue
4 *
5 * Copyright (C) 2018-2020 Intel Corporation
6 * Author: Felipe Balbi (Intel)
7 * Author: Jarkko Nikula <jarkko.nikula@linux.intel.com>
8 * Author: Raymond Tan <raymond.tan@intel.com>
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/netdevice.h>
14#include <linux/pci.h>
15#include <linux/pm_runtime.h>
16
17#include "m_can.h"
18
19#define M_CAN_PCI_MMIO_BAR 0
20
21#define M_CAN_CLOCK_FREQ_EHL 200000000
22#define CTL_CSR_INT_CTL_OFFSET 0x508
23
24struct m_can_pci_priv {
25 struct m_can_classdev cdev;
26
27 void __iomem *base;
28};
29
30static inline struct m_can_pci_priv *cdev_to_priv(struct m_can_classdev *cdev)
31{
32 return container_of(cdev, struct m_can_pci_priv, cdev);
33}
34
35static u32 iomap_read_reg(struct m_can_classdev *cdev, int reg)
36{
37 struct m_can_pci_priv *priv = cdev_to_priv(cdev);
38
39 return readl(priv->base + reg);
40}
41
42static int iomap_read_fifo(struct m_can_classdev *cdev, int offset, void *val, size_t val_count)
43{
44 struct m_can_pci_priv *priv = cdev_to_priv(cdev);
45 void __iomem *src = priv->base + offset;
46
47 while (val_count--) {
48 *(unsigned int *)val = ioread32(src);
49 val += 4;
50 src += 4;
51 }
52
53 return 0;
54}
55
56static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val)
57{
58 struct m_can_pci_priv *priv = cdev_to_priv(cdev);
59
60 writel(val, priv->base + reg);
61
62 return 0;
63}
64
65static int iomap_write_fifo(struct m_can_classdev *cdev, int offset,
66 const void *val, size_t val_count)
67{
68 struct m_can_pci_priv *priv = cdev_to_priv(cdev);
69 void __iomem *dst = priv->base + offset;
70
71 while (val_count--) {
72 iowrite32(*(unsigned int *)val, dst);
73 val += 4;
74 dst += 4;
75 }
76
77 return 0;
78}
79
80static struct m_can_ops m_can_pci_ops = {
81 .read_reg = iomap_read_reg,
82 .write_reg = iomap_write_reg,
83 .write_fifo = iomap_write_fifo,
84 .read_fifo = iomap_read_fifo,
85};
86
87static int m_can_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
88{
89 struct device *dev = &pci->dev;
90 struct m_can_classdev *mcan_class;
91 struct m_can_pci_priv *priv;
92 void __iomem *base;
93 int ret;
94
95 ret = pcim_enable_device(pci);
96 if (ret)
97 return ret;
98
99 pci_set_master(pci);
100
101 ret = pcim_iomap_regions(pci, BIT(M_CAN_PCI_MMIO_BAR), pci_name(pci));
102 if (ret)
103 return ret;
104
105 base = pcim_iomap_table(pci)[M_CAN_PCI_MMIO_BAR];
106
107 if (!base) {
108 dev_err(dev, "failed to map BARs\n");
109 return -ENOMEM;
110 }
111
112 mcan_class = m_can_class_allocate_dev(&pci->dev,
113 sizeof(struct m_can_pci_priv));
114 if (!mcan_class)
115 return -ENOMEM;
116
117 priv = cdev_to_priv(mcan_class);
118
119 priv->base = base;
120
121 ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_ALL_TYPES);
122 if (ret < 0)
123 goto err_free_dev;
124
125 mcan_class->dev = &pci->dev;
126 mcan_class->net->irq = pci_irq_vector(pci, 0);
127 mcan_class->pm_clock_support = 1;
128 mcan_class->can.clock.freq = id->driver_data;
129 mcan_class->ops = &m_can_pci_ops;
130
131 pci_set_drvdata(pci, mcan_class);
132
133 ret = m_can_class_register(mcan_class);
134 if (ret)
135 goto err_free_irq;
136
137 /* Enable interrupt control at CAN wrapper IP */
138 writel(0x1, base + CTL_CSR_INT_CTL_OFFSET);
139
140 pm_runtime_set_autosuspend_delay(dev, 1000);
141 pm_runtime_use_autosuspend(dev);
142 pm_runtime_put_noidle(dev);
143 pm_runtime_allow(dev);
144
145 return 0;
146
147err_free_irq:
148 pci_free_irq_vectors(pci);
149err_free_dev:
150 m_can_class_free_dev(mcan_class->net);
151 return ret;
152}
153
154static void m_can_pci_remove(struct pci_dev *pci)
155{
156 struct m_can_classdev *mcan_class = pci_get_drvdata(pci);
157 struct m_can_pci_priv *priv = cdev_to_priv(mcan_class);
158
159 pm_runtime_forbid(&pci->dev);
160 pm_runtime_get_noresume(&pci->dev);
161
162 /* Disable interrupt control at CAN wrapper IP */
163 writel(0x0, priv->base + CTL_CSR_INT_CTL_OFFSET);
164
165 m_can_class_unregister(mcan_class);
166 m_can_class_free_dev(mcan_class->net);
167 pci_free_irq_vectors(pci);
168}
169
170static __maybe_unused int m_can_pci_suspend(struct device *dev)
171{
172 return m_can_class_suspend(dev);
173}
174
175static __maybe_unused int m_can_pci_resume(struct device *dev)
176{
177 return m_can_class_resume(dev);
178}
179
180static SIMPLE_DEV_PM_OPS(m_can_pci_pm_ops,
181 m_can_pci_suspend, m_can_pci_resume);
182
183static const struct pci_device_id m_can_pci_id_table[] = {
184 { PCI_VDEVICE(INTEL, 0x4bc1), M_CAN_CLOCK_FREQ_EHL, },
185 { PCI_VDEVICE(INTEL, 0x4bc2), M_CAN_CLOCK_FREQ_EHL, },
186 { } /* Terminating Entry */
187};
188MODULE_DEVICE_TABLE(pci, m_can_pci_id_table);
189
190static struct pci_driver m_can_pci_driver = {
191 .name = "m_can_pci",
192 .probe = m_can_pci_probe,
193 .remove = m_can_pci_remove,
194 .id_table = m_can_pci_id_table,
195 .driver = {
196 .pm = &m_can_pci_pm_ops,
197 },
198};
199
200module_pci_driver(m_can_pci_driver);
201
202MODULE_AUTHOR("Felipe Balbi (Intel)");
203MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
204MODULE_AUTHOR("Raymond Tan <raymond.tan@intel.com>");
205MODULE_LICENSE("GPL");
206MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller on PCI bus");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI Specific M_CAN Glue
4 *
5 * Copyright (C) 2018-2020 Intel Corporation
6 * Author: Felipe Balbi (Intel)
7 * Author: Jarkko Nikula <jarkko.nikula@linux.intel.com>
8 * Author: Raymond Tan <raymond.tan@intel.com>
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/netdevice.h>
14#include <linux/pci.h>
15#include <linux/pm_runtime.h>
16
17#include "m_can.h"
18
19#define M_CAN_PCI_MMIO_BAR 0
20
21#define M_CAN_CLOCK_FREQ_EHL 100000000
22#define CTL_CSR_INT_CTL_OFFSET 0x508
23
24struct m_can_pci_priv {
25 struct m_can_classdev cdev;
26
27 void __iomem *base;
28};
29
30static inline struct m_can_pci_priv *cdev_to_priv(struct m_can_classdev *cdev)
31{
32 return container_of(cdev, struct m_can_pci_priv, cdev);
33}
34
35static u32 iomap_read_reg(struct m_can_classdev *cdev, int reg)
36{
37 struct m_can_pci_priv *priv = cdev_to_priv(cdev);
38
39 return readl(priv->base + reg);
40}
41
42static u32 iomap_read_fifo(struct m_can_classdev *cdev, int offset)
43{
44 struct m_can_pci_priv *priv = cdev_to_priv(cdev);
45
46 return readl(priv->base + offset);
47}
48
49static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val)
50{
51 struct m_can_pci_priv *priv = cdev_to_priv(cdev);
52
53 writel(val, priv->base + reg);
54
55 return 0;
56}
57
58static int iomap_write_fifo(struct m_can_classdev *cdev, int offset, int val)
59{
60 struct m_can_pci_priv *priv = cdev_to_priv(cdev);
61
62 writel(val, priv->base + offset);
63
64 return 0;
65}
66
67static struct m_can_ops m_can_pci_ops = {
68 .read_reg = iomap_read_reg,
69 .write_reg = iomap_write_reg,
70 .write_fifo = iomap_write_fifo,
71 .read_fifo = iomap_read_fifo,
72};
73
74static int m_can_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
75{
76 struct device *dev = &pci->dev;
77 struct m_can_classdev *mcan_class;
78 struct m_can_pci_priv *priv;
79 void __iomem *base;
80 int ret;
81
82 ret = pcim_enable_device(pci);
83 if (ret)
84 return ret;
85
86 pci_set_master(pci);
87
88 ret = pcim_iomap_regions(pci, BIT(M_CAN_PCI_MMIO_BAR), pci_name(pci));
89 if (ret)
90 return ret;
91
92 base = pcim_iomap_table(pci)[M_CAN_PCI_MMIO_BAR];
93
94 if (!base) {
95 dev_err(dev, "failed to map BARs\n");
96 return -ENOMEM;
97 }
98
99 mcan_class = m_can_class_allocate_dev(&pci->dev,
100 sizeof(struct m_can_pci_priv));
101 if (!mcan_class)
102 return -ENOMEM;
103
104 priv = cdev_to_priv(mcan_class);
105
106 priv->base = base;
107
108 ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_ALL_TYPES);
109 if (ret < 0)
110 return ret;
111
112 mcan_class->dev = &pci->dev;
113 mcan_class->net->irq = pci_irq_vector(pci, 0);
114 mcan_class->pm_clock_support = 1;
115 mcan_class->can.clock.freq = id->driver_data;
116 mcan_class->ops = &m_can_pci_ops;
117
118 pci_set_drvdata(pci, mcan_class);
119
120 ret = m_can_class_register(mcan_class);
121 if (ret)
122 goto err;
123
124 /* Enable interrupt control at CAN wrapper IP */
125 writel(0x1, base + CTL_CSR_INT_CTL_OFFSET);
126
127 pm_runtime_set_autosuspend_delay(dev, 1000);
128 pm_runtime_use_autosuspend(dev);
129 pm_runtime_put_noidle(dev);
130 pm_runtime_allow(dev);
131
132 return 0;
133
134err:
135 pci_free_irq_vectors(pci);
136 return ret;
137}
138
139static void m_can_pci_remove(struct pci_dev *pci)
140{
141 struct m_can_classdev *mcan_class = pci_get_drvdata(pci);
142 struct m_can_pci_priv *priv = cdev_to_priv(mcan_class);
143
144 pm_runtime_forbid(&pci->dev);
145 pm_runtime_get_noresume(&pci->dev);
146
147 /* Disable interrupt control at CAN wrapper IP */
148 writel(0x0, priv->base + CTL_CSR_INT_CTL_OFFSET);
149
150 m_can_class_unregister(mcan_class);
151 pci_free_irq_vectors(pci);
152}
153
154static __maybe_unused int m_can_pci_suspend(struct device *dev)
155{
156 return m_can_class_suspend(dev);
157}
158
159static __maybe_unused int m_can_pci_resume(struct device *dev)
160{
161 return m_can_class_resume(dev);
162}
163
164static SIMPLE_DEV_PM_OPS(m_can_pci_pm_ops,
165 m_can_pci_suspend, m_can_pci_resume);
166
167static const struct pci_device_id m_can_pci_id_table[] = {
168 { PCI_VDEVICE(INTEL, 0x4bc1), M_CAN_CLOCK_FREQ_EHL, },
169 { PCI_VDEVICE(INTEL, 0x4bc2), M_CAN_CLOCK_FREQ_EHL, },
170 { } /* Terminating Entry */
171};
172MODULE_DEVICE_TABLE(pci, m_can_pci_id_table);
173
174static struct pci_driver m_can_pci_driver = {
175 .name = "m_can_pci",
176 .probe = m_can_pci_probe,
177 .remove = m_can_pci_remove,
178 .id_table = m_can_pci_id_table,
179 .driver = {
180 .pm = &m_can_pci_pm_ops,
181 },
182};
183
184module_pci_driver(m_can_pci_driver);
185
186MODULE_AUTHOR("Felipe Balbi (Intel)");
187MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
188MODULE_AUTHOR("Raymond Tan <raymond.tan@intel.com>");
189MODULE_LICENSE("GPL");
190MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller on PCI bus");