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v6.8
   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Renesas SDHI
   4 *
   5 * Copyright (C) 2015-19 Renesas Electronics Corporation
   6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
   7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
   8 * Copyright (C) 2009 Magnus Damm
   9 *
  10 * Based on "Compaq ASIC3 support":
  11 *
  12 * Copyright 2001 Compaq Computer Corporation.
  13 * Copyright 2004-2005 Phil Blundell
  14 * Copyright 2007-2008 OpenedHand Ltd.
  15 *
  16 * Authors: Phil Blundell <pb@handhelds.org>,
  17 *	    Samuel Ortiz <sameo@openedhand.com>
  18 *
  19 */
  20
  21#include <linux/clk.h>
  22#include <linux/delay.h>
  23#include <linux/iopoll.h>
  24#include <linux/kernel.h>
  25#include <linux/mfd/tmio.h>
  26#include <linux/mmc/host.h>
  27#include <linux/mmc/mmc.h>
  28#include <linux/mmc/slot-gpio.h>
  29#include <linux/module.h>
 
  30#include <linux/pinctrl/consumer.h>
  31#include <linux/pinctrl/pinctrl-state.h>
  32#include <linux/platform_device.h>
  33#include <linux/pm_domain.h>
  34#include <linux/regulator/consumer.h>
  35#include <linux/reset.h>
  36#include <linux/sh_dma.h>
  37#include <linux/slab.h>
 
  38
  39#include "renesas_sdhi.h"
  40#include "tmio_mmc.h"
  41
  42#define CTL_HOST_MODE	0xe4
  43#define HOST_MODE_GEN2_SDR50_WMODE	BIT(0)
  44#define HOST_MODE_GEN2_SDR104_WMODE	BIT(0)
  45#define HOST_MODE_GEN3_WMODE		BIT(0)
  46#define HOST_MODE_GEN3_BUSWIDTH		BIT(8)
  47
  48#define HOST_MODE_GEN3_16BIT	HOST_MODE_GEN3_WMODE
  49#define HOST_MODE_GEN3_32BIT	(HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH)
  50#define HOST_MODE_GEN3_64BIT	0
  51
 
 
 
  52#define SDHI_VER_GEN2_SDR50	0x490c
  53#define SDHI_VER_RZ_A1		0x820b
  54/* very old datasheets said 0x490c for SDR104, too. They are wrong! */
  55#define SDHI_VER_GEN2_SDR104	0xcb0d
  56#define SDHI_VER_GEN3_SD	0xcc10
  57#define SDHI_VER_GEN3_SDMMC	0xcd10
  58
  59#define SDHI_GEN3_MMC0_ADDR	0xee140000
  60
  61static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
  62{
  63	u32 val;
  64
  65	/*
  66	 * see also
  67	 *	renesas_sdhi_of_data :: dma_buswidth
  68	 */
  69	switch (sd_ctrl_read16(host, CTL_VERSION)) {
  70	case SDHI_VER_GEN2_SDR50:
  71		val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0;
  72		break;
  73	case SDHI_VER_GEN2_SDR104:
  74		val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE;
  75		break;
  76	case SDHI_VER_GEN3_SD:
  77	case SDHI_VER_GEN3_SDMMC:
  78		if (width == 64)
  79			val = HOST_MODE_GEN3_64BIT;
  80		else if (width == 32)
  81			val = HOST_MODE_GEN3_32BIT;
  82		else
  83			val = HOST_MODE_GEN3_16BIT;
  84		break;
  85	default:
  86		/* nothing to do */
  87		return;
  88	}
  89
  90	sd_ctrl_write16(host, CTL_HOST_MODE, val);
  91}
  92
  93static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
  94{
  95	struct mmc_host *mmc = host->mmc;
  96	struct renesas_sdhi *priv = host_to_priv(host);
  97	int ret;
  98
  99	ret = clk_prepare_enable(priv->clk_cd);
 100	if (ret < 0)
 101		return ret;
 102
 103	/*
 104	 * The clock driver may not know what maximum frequency
 105	 * actually works, so it should be set with the max-frequency
 106	 * property which will already have been read to f_max.  If it
 107	 * was missing, assume the current frequency is the maximum.
 108	 */
 109	if (!mmc->f_max)
 110		mmc->f_max = clk_get_rate(priv->clk);
 111
 112	/*
 113	 * Minimum frequency is the minimum input clock frequency
 114	 * divided by our maximum divider.
 115	 */
 116	mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
 117
 118	/* enable 16bit data access on SDBUF as default */
 119	renesas_sdhi_sdbuf_width(host, 16);
 120
 121	return 0;
 122}
 123
 124static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
 125					    unsigned int wanted_clock)
 126{
 127	struct renesas_sdhi *priv = host_to_priv(host);
 128	struct clk *ref_clk = priv->clk;
 129	unsigned int freq, diff, best_freq = 0, diff_min = ~0;
 130	unsigned int new_clock, clkh_shift = 0;
 131	unsigned int new_upper_limit;
 132	int i;
 133
 134	/*
 135	 * We simply return the current rate if a) we are not on a R-Car Gen2+
 136	 * SoC (may work for others, but untested) or b) if the SCC needs its
 137	 * clock during tuning, so we don't change the external clock setup.
 138	 */
 139	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc))
 140		return clk_get_rate(priv->clk);
 141
 142	if (priv->clkh) {
 143		/* HS400 with 4TAP needs different clock settings */
 144		bool use_4tap = sdhi_has_quirk(priv, hs400_4taps);
 145		bool need_slow_clkh = host->mmc->ios.timing == MMC_TIMING_MMC_HS400;
 146		clkh_shift = use_4tap && need_slow_clkh ? 1 : 2;
 147		ref_clk = priv->clkh;
 148	}
 149
 150	new_clock = wanted_clock << clkh_shift;
 151
 152	/*
 153	 * We want the bus clock to be as close as possible to, but no
 154	 * greater than, new_clock.  As we can divide by 1 << i for
 155	 * any i in [0, 9] we want the input clock to be as close as
 156	 * possible, but no greater than, new_clock << i.
 157	 *
 158	 * Add an upper limit of 1/1024 rate higher to the clock rate to fix
 159	 * clk rate jumping to lower rate due to rounding error (eg: RZ/G2L has
 160	 * 3 clk sources 533.333333 MHz, 400 MHz and 266.666666 MHz. The request
 161	 * for 533.333333 MHz will selects a slower 400 MHz due to rounding
 162	 * error (533333333 Hz / 4 * 4 = 533333332 Hz < 533333333 Hz)).
 163	 */
 164	for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
 165		freq = clk_round_rate(ref_clk, new_clock << i);
 166		new_upper_limit = (new_clock << i) + ((new_clock << i) >> 10);
 167		if (freq > new_upper_limit) {
 168			/* Too fast; look for a slightly slower option */
 169			freq = clk_round_rate(ref_clk, (new_clock << i) / 4 * 3);
 170			if (freq > new_upper_limit)
 
 171				continue;
 172		}
 173
 174		diff = new_clock - (freq >> i);
 175		if (diff <= diff_min) {
 176			best_freq = freq;
 177			diff_min = diff;
 178		}
 179	}
 180
 181	clk_set_rate(ref_clk, best_freq);
 182
 183	if (priv->clkh)
 184		clk_set_rate(priv->clk, best_freq >> clkh_shift);
 185
 186	return clk_get_rate(priv->clk);
 187}
 188
 189static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
 190				   unsigned int new_clock)
 191{
 192	unsigned int clk_margin;
 193	u32 clk = 0, clock;
 194
 195	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 196		sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 197
 198	if (new_clock == 0) {
 199		host->mmc->actual_clock = 0;
 200		goto out;
 201	}
 202
 203	host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);
 204	clock = host->mmc->actual_clock / 512;
 205
 206	/*
 207	 * Add a margin of 1/1024 rate higher to the clock rate in order
 208	 * to avoid clk variable setting a value of 0 due to the margin
 209	 * provided for actual_clock in renesas_sdhi_clk_update().
 210	 */
 211	clk_margin = new_clock >> 10;
 212	for (clk = 0x80000080; new_clock + clk_margin >= (clock << 1); clk >>= 1)
 213		clock <<= 1;
 214
 215	/* 1/1 clock is option */
 216	if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
 217		if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
 218			clk |= 0xff;
 219		else
 220			clk &= ~0xff;
 221	}
 222
 223	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
 224	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 225		usleep_range(10000, 11000);
 226
 227	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 228		sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 229
 230out:
 231	/* HW engineers overrode docs: no sleep needed on R-Car2+ */
 232	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 233		usleep_range(10000, 11000);
 234}
 235
 236static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
 237{
 238	struct renesas_sdhi *priv = host_to_priv(host);
 239
 240	clk_disable_unprepare(priv->clk_cd);
 241}
 242
 243static int renesas_sdhi_card_busy(struct mmc_host *mmc)
 244{
 245	struct tmio_mmc_host *host = mmc_priv(mmc);
 246
 247	return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
 248		 TMIO_STAT_DAT0);
 249}
 250
 251static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
 252						    struct mmc_ios *ios)
 253{
 254	struct tmio_mmc_host *host = mmc_priv(mmc);
 255	struct renesas_sdhi *priv = host_to_priv(host);
 256	struct pinctrl_state *pin_state;
 257	int ret;
 258
 259	switch (ios->signal_voltage) {
 260	case MMC_SIGNAL_VOLTAGE_330:
 261		pin_state = priv->pins_default;
 262		break;
 263	case MMC_SIGNAL_VOLTAGE_180:
 264		pin_state = priv->pins_uhs;
 265		break;
 266	default:
 267		return -EINVAL;
 268	}
 269
 270	/*
 271	 * If anything is missing, assume signal voltage is fixed at
 272	 * 3.3V and succeed/fail accordingly.
 273	 */
 274	if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
 275		return ios->signal_voltage ==
 276			MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
 277
 278	ret = mmc_regulator_set_vqmmc(host->mmc, ios);
 279	if (ret < 0)
 280		return ret;
 281
 282	return pinctrl_select_state(priv->pinctrl, pin_state);
 283}
 284
 285/* SCC registers */
 286#define SH_MOBILE_SDHI_SCC_DTCNTL	0x000
 287#define SH_MOBILE_SDHI_SCC_TAPSET	0x002
 288#define SH_MOBILE_SDHI_SCC_DT2FF	0x004
 289#define SH_MOBILE_SDHI_SCC_CKSEL	0x006
 290#define SH_MOBILE_SDHI_SCC_RVSCNTL	0x008
 291#define SH_MOBILE_SDHI_SCC_RVSREQ	0x00A
 292#define SH_MOBILE_SDHI_SCC_SMPCMP       0x00C
 293#define SH_MOBILE_SDHI_SCC_TMPPORT2	0x00E
 294#define SH_MOBILE_SDHI_SCC_TMPPORT3	0x014
 295#define SH_MOBILE_SDHI_SCC_TMPPORT4	0x016
 296#define SH_MOBILE_SDHI_SCC_TMPPORT5	0x018
 297#define SH_MOBILE_SDHI_SCC_TMPPORT6	0x01A
 298#define SH_MOBILE_SDHI_SCC_TMPPORT7	0x01C
 299
 300#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN		BIT(0)
 301#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT	16
 302#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK	0xff
 303
 304#define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL		BIT(0)
 305
 306#define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN	BIT(0)
 307
 308#define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN	BIT(0)
 309#define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP	BIT(1)
 310#define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR	BIT(2)
 311
 312#define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN	BIT(8)
 313#define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP	BIT(24)
 314#define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR	(BIT(8) | BIT(24))
 315
 316#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL	BIT(4)
 317#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN	BIT(31)
 318
 319/* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */
 320#define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START	BIT(0)
 321
 322/* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */
 323#define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R	BIT(8)
 324#define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W	(0 << 8)
 325#define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK	0x3F
 326
 327/* Definitions for values the SH_MOBILE_SDHI_SCC register */
 328#define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE	0xa5000000
 329#define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK	0x1f
 330#define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE		BIT(7)
 331
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 332static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
 333				struct renesas_sdhi *priv, int addr)
 334{
 335	return readl(priv->scc_ctl + (addr << host->bus_shift));
 336}
 337
 338static inline void sd_scc_write32(struct tmio_mmc_host *host,
 339				  struct renesas_sdhi *priv,
 340				  int addr, u32 val)
 341{
 342	writel(val, priv->scc_ctl + (addr << host->bus_shift));
 343}
 344
 345static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
 346{
 347	struct renesas_sdhi *priv;
 348
 349	priv = host_to_priv(host);
 350
 351	/* Initialize SCC */
 352	sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
 353
 354	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 355			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 356
 357	/* set sampling clock selection range */
 358	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 359		       SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
 360		       0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
 361
 362	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 363		       SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
 364		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 365
 366	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 367		       ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 368		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 369
 370	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
 371
 372	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 373			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 374
 375	/* Read TAPNUM */
 376	return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
 377		SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
 378		SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
 379}
 380
 381static void renesas_sdhi_hs400_complete(struct mmc_host *mmc)
 382{
 383	struct tmio_mmc_host *host = mmc_priv(mmc);
 384	struct renesas_sdhi *priv = host_to_priv(host);
 385	u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
 386	bool use_4tap = sdhi_has_quirk(priv, hs400_4taps);
 387
 388	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 389		sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 390
 391	/* Set HS400 mode */
 392	sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 |
 393			sd_ctrl_read16(host, CTL_SDIF_MODE));
 394
 395	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF,
 396		       priv->scc_tappos_hs400);
 397
 398	if (sdhi_has_quirk(priv, manual_tap_correction))
 
 399		sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 400			       ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 401			       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 402
 403	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
 404		       (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
 405			SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
 406			sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
 407
 
 408	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 409		       SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
 410		       sd_scc_read32(host, priv,
 411				     SH_MOBILE_SDHI_SCC_DTCNTL));
 412
 413	/* Avoid bad TAP */
 414	if (bad_taps & BIT(priv->tap_set)) {
 415		u32 new_tap = (priv->tap_set + 1) % priv->tap_num;
 416
 417		if (bad_taps & BIT(new_tap))
 418			new_tap = (priv->tap_set - 1) % priv->tap_num;
 419
 420		if (bad_taps & BIT(new_tap)) {
 421			new_tap = priv->tap_set;
 422			dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n");
 423		}
 424
 425		priv->tap_set = new_tap;
 426	}
 427
 428	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
 429		       priv->tap_set / (use_4tap ? 2 : 1));
 430
 431	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 432		       SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
 433		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 434
 435	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 436			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 437
 438	if (priv->adjust_hs400_calib_table)
 439		priv->needs_adjust_hs400 = true;
 440}
 441
 442static void renesas_sdhi_disable_scc(struct mmc_host *mmc)
 443{
 444	struct tmio_mmc_host *host = mmc_priv(mmc);
 445	struct renesas_sdhi *priv = host_to_priv(host);
 446
 447	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 448			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 449
 450	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 451		       ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
 452		       sd_scc_read32(host, priv,
 453				     SH_MOBILE_SDHI_SCC_CKSEL));
 454
 455	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 456		       ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
 457		       sd_scc_read32(host, priv,
 458				     SH_MOBILE_SDHI_SCC_DTCNTL));
 459
 460	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 461			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 462}
 463
 464static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host,
 465				 struct renesas_sdhi *priv, u32 addr)
 466{
 467	/* read mode */
 468	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
 469		       SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
 470		       (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
 471
 472	/* access start and stop */
 473	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
 474		       SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
 475	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
 476
 477	return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7);
 478}
 479
 480static void sd_scc_tmpport_write32(struct tmio_mmc_host *host,
 481				   struct renesas_sdhi *priv, u32 addr, u32 val)
 482{
 483	/* write mode */
 484	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
 485		       SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
 486		       (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
 487
 488	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val);
 489
 490	/* access start and stop */
 491	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
 492		       SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
 493	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
 494}
 495
 496static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host)
 497{
 498	struct renesas_sdhi *priv = host_to_priv(host);
 499	u32 calib_code;
 500
 501	/* disable write protect */
 502	sd_scc_tmpport_write32(host, priv, 0x00,
 503			       SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
 504	/* read calibration code and adjust */
 505	calib_code = sd_scc_tmpport_read32(host, priv, 0x26);
 506	calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
 507
 508	sd_scc_tmpport_write32(host, priv, 0x22,
 509			       SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE |
 510			       priv->adjust_hs400_calib_table[calib_code]);
 511
 512	/* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */
 513	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3);
 514
 515	/* adjustment done, clear flag */
 516	priv->needs_adjust_hs400 = false;
 517}
 518
 519static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host)
 520{
 521	struct renesas_sdhi *priv = host_to_priv(host);
 522
 523	/* disable write protect */
 524	sd_scc_tmpport_write32(host, priv, 0x00,
 525			       SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
 526	/* disable manual calibration */
 527	sd_scc_tmpport_write32(host, priv, 0x22, 0);
 528	/* clear offset value of TMPPORT3 */
 529	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0);
 530}
 531
 532static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
 533					  struct renesas_sdhi *priv)
 534{
 535	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 536			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 537
 538	/* Reset HS400 mode */
 539	sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 &
 540			sd_ctrl_read16(host, CTL_SDIF_MODE));
 541
 542	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
 543
 544	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
 545		       ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
 546			 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
 547			sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
 548
 549	if (sdhi_has_quirk(priv, hs400_calib_table) || sdhi_has_quirk(priv, hs400_bad_taps))
 550		renesas_sdhi_adjust_hs400_mode_disable(host);
 551
 552	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 553			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 554}
 555
 556static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
 557{
 558	struct tmio_mmc_host *host = mmc_priv(mmc);
 559
 560	renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
 561	return 0;
 562}
 563
 564static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv)
 565{
 566	renesas_sdhi_disable_scc(host->mmc);
 567	renesas_sdhi_reset_hs400_mode(host, priv);
 568	priv->needs_adjust_hs400 = false;
 569
 570	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 571		       ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 572		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 573}
 574
 575/* only populated for TMIO_MMC_MIN_RCAR2 */
 576static void renesas_sdhi_reset(struct tmio_mmc_host *host, bool preserve)
 577{
 578	struct renesas_sdhi *priv = host_to_priv(host);
 579	int ret;
 580	u16 val;
 581
 582	if (!preserve) {
 583		if (priv->rstc) {
 584			reset_control_reset(priv->rstc);
 585			/* Unknown why but without polling reset status, it will hang */
 586			read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100,
 587					  false, priv->rstc);
 588			/* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */
 589			sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
 590			priv->needs_adjust_hs400 = false;
 591			renesas_sdhi_set_clock(host, host->clk_cache);
 592		} else if (priv->scc_ctl) {
 593			renesas_sdhi_scc_reset(host, priv);
 594		}
 595	}
 596
 597	if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) {
 598		val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT);
 599		val |= CARD_OPT_EXTOP;
 600		sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val);
 601	}
 602}
 603
 604static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host)
 605{
 606	u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT);
 607
 608	num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT;
 609	return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num);
 610
 611}
 612
 613#define SH_MOBILE_SDHI_MIN_TAP_ROW 3
 614
 615static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
 616{
 617	struct renesas_sdhi *priv = host_to_priv(host);
 618	unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i;
 619	unsigned int taps_size = priv->tap_num * 2, min_tap_row;
 620	unsigned long *bitmap;
 621
 622	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 623
 624	/*
 625	 * When tuning CMD19 is issued twice for each tap, merge the
 626	 * result requiring the tap to be good in both runs before
 627	 * considering it for tuning selection.
 628	 */
 629	for (i = 0; i < taps_size; i++) {
 630		int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1);
 631
 632		if (!test_bit(i, priv->taps))
 633			clear_bit(i + offset, priv->taps);
 634
 635		if (!test_bit(i, priv->smpcmp))
 636			clear_bit(i + offset, priv->smpcmp);
 637	}
 638
 639	/*
 640	 * If all TAP are OK, the sampling clock position is selected by
 641	 * identifying the change point of data.
 642	 */
 643	if (bitmap_full(priv->taps, taps_size)) {
 644		bitmap = priv->smpcmp;
 645		min_tap_row = 1;
 646	} else {
 647		bitmap = priv->taps;
 648		min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW;
 649	}
 650
 651	/*
 652	 * Find the longest consecutive run of successful probes. If that
 653	 * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the
 654	 * center index as the tap, otherwise bail out.
 655	 */
 656	for_each_set_bitrange(rs, re, bitmap, taps_size) {
 657		if (re - rs > tap_cnt) {
 658			tap_end = re;
 659			tap_start = rs;
 660			tap_cnt = tap_end - tap_start;
 661		}
 662	}
 663
 664	if (tap_cnt >= min_tap_row)
 665		priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num;
 666	else
 667		return -EIO;
 668
 669	/* Set SCC */
 670	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set);
 671
 672	/* Enable auto re-tuning */
 673	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 674		       SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
 675		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 676
 677	return 0;
 678}
 679
 680static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode)
 681{
 682	struct tmio_mmc_host *host = mmc_priv(mmc);
 683	struct renesas_sdhi *priv = host_to_priv(host);
 684	int i, ret;
 685
 686	priv->tap_num = renesas_sdhi_init_tuning(host);
 687	if (!priv->tap_num)
 688		return 0; /* Tuning is not supported */
 689
 690	if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) {
 691		dev_err(&host->pdev->dev,
 692			"Too many taps, please update 'taps' in tmio_mmc_host!\n");
 693		return -EINVAL;
 694	}
 695
 696	bitmap_zero(priv->taps, priv->tap_num * 2);
 697	bitmap_zero(priv->smpcmp, priv->tap_num * 2);
 698
 699	/* Issue CMD19 twice for each tap */
 700	for (i = 0; i < 2 * priv->tap_num; i++) {
 701		int cmd_error = 0;
 702
 703		/* Set sampling clock position */
 704		sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num);
 705
 706		if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0)
 707			set_bit(i, priv->taps);
 708
 709		if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0)
 710			set_bit(i, priv->smpcmp);
 711
 712		if (cmd_error)
 713			mmc_send_abort_tuning(mmc, opcode);
 714	}
 715
 716	ret = renesas_sdhi_select_tuning(host);
 717	if (ret < 0)
 718		renesas_sdhi_scc_reset(host, priv);
 719	return ret;
 720}
 721
 722static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap)
 723{
 724	struct renesas_sdhi *priv = host_to_priv(host);
 725	unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set;
 726	u32 val;
 727
 728	val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ);
 729	if (!val)
 730		return false;
 731
 732	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 733
 734	/* Change TAP position according to correction status */
 735	if (sdhi_has_quirk(priv, manual_tap_correction) &&
 736	    host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
 737		u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
 738		/*
 739		 * With HS400, the DAT signal is based on DS, not CLK.
 740		 * Therefore, use only CMD status.
 741		 */
 742		u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) &
 743					   SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR;
 744		if (!smpcmp) {
 745			return false;	/* no error in CMD signal */
 746		} else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) {
 747			new_tap++;
 748			error_tap--;
 749		} else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) {
 750			new_tap--;
 751			error_tap++;
 752		} else {
 753			return true;	/* need retune */
 754		}
 755
 756		/*
 757		 * When new_tap is a bad tap, we cannot change. Then, we compare
 758		 * with the HS200 tuning result. When smpcmp[error_tap] is OK,
 759		 * we can at least retune.
 760		 */
 761		if (bad_taps & BIT(new_tap % priv->tap_num))
 762			return test_bit(error_tap % priv->tap_num, priv->smpcmp);
 763	} else {
 764		if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)
 765			return true;    /* need retune */
 766		else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP)
 767			new_tap++;
 768		else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN)
 769			new_tap--;
 770		else
 771			return false;
 772	}
 773
 774	priv->tap_set = (new_tap % priv->tap_num);
 775	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
 776		       priv->tap_set / (use_4tap ? 2 : 1));
 777
 778	return false;
 779}
 780
 781static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host)
 782{
 783	struct renesas_sdhi *priv = host_to_priv(host);
 784
 785	/* Check SCC error */
 786	if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
 787	    SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
 788		sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 789		return true;
 790	}
 791
 792	return false;
 793}
 794
 795static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host,
 796					 struct mmc_request *mrq)
 797{
 798	struct renesas_sdhi *priv = host_to_priv(host);
 799	bool use_4tap = sdhi_has_quirk(priv, hs400_4taps);
 800	bool ret = false;
 801
 802	/*
 803	 * Skip checking SCC errors when running on 4 taps in HS400 mode as
 804	 * any retuning would still result in the same 4 taps being used.
 805	 */
 806	if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
 807	    !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
 808	    !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
 809		return false;
 810
 811	if (mmc_doing_tune(host->mmc))
 812		return false;
 813
 814	if (((mrq->cmd->error == -ETIMEDOUT) ||
 815	     (mrq->data && mrq->data->error == -ETIMEDOUT)) &&
 816	    ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
 817	     (host->ops.get_cd && host->ops.get_cd(host->mmc))))
 818		ret |= true;
 819
 820	if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
 821	    SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN)
 822		ret |= renesas_sdhi_auto_correction(host);
 823	else
 824		ret |= renesas_sdhi_manual_correction(host, use_4tap);
 825
 826	return ret;
 827}
 828
 829static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
 830{
 831	int timeout = 1000;
 832	/* CBSY is set when busy, SCLKDIVEN is cleared when busy */
 833	u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
 834
 835	while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
 836			      & bit) == wait_state)
 837		udelay(1);
 838
 839	if (!timeout) {
 840		dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
 841		return -EBUSY;
 842	}
 843
 844	return 0;
 845}
 846
 847static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
 848{
 849	u32 bit = TMIO_STAT_SCLKDIVEN;
 850
 851	switch (addr) {
 852	case CTL_SD_CMD:
 853	case CTL_STOP_INTERNAL_ACTION:
 854	case CTL_XFER_BLK_COUNT:
 855	case CTL_SD_XFER_LEN:
 856	case CTL_SD_MEM_CARD_OPT:
 857	case CTL_TRANSACTION_CTL:
 858	case CTL_DMA_ENABLE:
 859	case CTL_HOST_MODE:
 860		if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
 861			bit = TMIO_STAT_CMD_BUSY;
 862		fallthrough;
 863	case CTL_SD_CARD_CLK_CTL:
 864		return renesas_sdhi_wait_idle(host, bit);
 865	}
 866
 867	return 0;
 868}
 869
 870static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
 871				       unsigned int direction, int blk_size)
 872{
 873	/*
 874	 * In Renesas controllers, when performing a
 875	 * multiple block read of one or two blocks,
 876	 * depending on the timing with which the
 877	 * response register is read, the response
 878	 * value may not be read properly.
 879	 * Use single block read for this HW bug
 880	 */
 881	if ((direction == MMC_DATA_READ) &&
 882	    blk_size == 2)
 883		return 1;
 884
 885	return blk_size;
 886}
 887
 888static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq)
 889{
 890	struct renesas_sdhi *priv = host_to_priv(host);
 891
 892	if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS)
 893		renesas_sdhi_adjust_hs400_mode_enable(host);
 894}
 895static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
 896{
 897	/* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
 898	int width = (host->bus_shift == 2) ? 64 : 32;
 899
 900	sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
 901	renesas_sdhi_sdbuf_width(host, enable ? width : 16);
 902}
 903
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 904int renesas_sdhi_probe(struct platform_device *pdev,
 905		       const struct tmio_mmc_dma_ops *dma_ops,
 906		       const struct renesas_sdhi_of_data *of_data,
 907		       const struct renesas_sdhi_quirks *quirks)
 908{
 909	struct tmio_mmc_data *mmd = pdev->dev.platform_data;
 
 
 
 910	struct tmio_mmc_data *mmc_data;
 911	struct renesas_sdhi_dma *dma_priv;
 912	struct tmio_mmc_host *host;
 913	struct renesas_sdhi *priv;
 914	int num_irqs, irq, ret, i;
 915	struct resource *res;
 916	u16 ver;
 917
 
 
 
 
 
 
 918	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 919	if (!res)
 920		return -EINVAL;
 921
 922	priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
 923			    GFP_KERNEL);
 924	if (!priv)
 925		return -ENOMEM;
 926
 927	priv->quirks = quirks;
 928	mmc_data = &priv->mmc_data;
 929	dma_priv = &priv->dma_priv;
 930
 931	priv->clk = devm_clk_get(&pdev->dev, NULL);
 932	if (IS_ERR(priv->clk))
 933		return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), "cannot get clock");
 934
 935	priv->clkh = devm_clk_get_optional(&pdev->dev, "clkh");
 936	if (IS_ERR(priv->clkh))
 937		return dev_err_probe(&pdev->dev, PTR_ERR(priv->clkh), "cannot get clkh");
 938
 939	/*
 940	 * Some controllers provide a 2nd clock just to run the internal card
 941	 * detection logic. Unfortunately, the existing driver architecture does
 942	 * not support a separation of clocks for runtime PM usage. When
 943	 * native hotplug is used, the tmio driver assumes that the core
 944	 * must continue to run for card detect to stay active, so we cannot
 945	 * disable it.
 946	 * Additionally, it is prohibited to supply a clock to the core but not
 947	 * to the card detect circuit. That leaves us with if separate clocks
 948	 * are presented, we must treat them both as virtually 1 clock.
 949	 */
 950	priv->clk_cd = devm_clk_get_optional(&pdev->dev, "cd");
 951	if (IS_ERR(priv->clk_cd))
 952		return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk_cd), "cannot get cd clock");
 953
 954	priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
 955	if (IS_ERR(priv->rstc))
 956		return PTR_ERR(priv->rstc);
 957
 958	priv->pinctrl = devm_pinctrl_get(&pdev->dev);
 959	if (!IS_ERR(priv->pinctrl)) {
 960		priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
 961						PINCTRL_STATE_DEFAULT);
 962		priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
 963						"state_uhs");
 964	}
 965
 966	host = tmio_mmc_host_alloc(pdev, mmc_data);
 967	if (IS_ERR(host))
 968		return PTR_ERR(host);
 969
 970	if (of_data) {
 971		mmc_data->flags |= of_data->tmio_flags;
 972		mmc_data->ocr_mask = of_data->tmio_ocr_mask;
 973		mmc_data->capabilities |= of_data->capabilities;
 974		mmc_data->capabilities2 |= of_data->capabilities2;
 975		mmc_data->dma_rx_offset = of_data->dma_rx_offset;
 976		mmc_data->max_blk_count = of_data->max_blk_count;
 977		mmc_data->max_segs = of_data->max_segs;
 978		dma_priv->dma_buswidth = of_data->dma_buswidth;
 979		host->bus_shift = of_data->bus_shift;
 980		/* Fallback for old DTs */
 981		if (!priv->clkh && of_data->sdhi_flags & SDHI_FLAG_NEED_CLKH_FALLBACK)
 982			priv->clkh = clk_get_parent(clk_get_parent(priv->clk));
 983
 984	}
 985
 986	host->write16_hook = renesas_sdhi_write16_hook;
 987	host->clk_enable = renesas_sdhi_clk_enable;
 988	host->clk_disable = renesas_sdhi_clk_disable;
 989	host->set_clock = renesas_sdhi_set_clock;
 990	host->multi_io_quirk = renesas_sdhi_multi_io_quirk;
 991	host->dma_ops = dma_ops;
 992
 993	if (sdhi_has_quirk(priv, hs400_disabled))
 994		host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
 995
 996	/* For some SoC, we disable internal WP. GPIO may override this */
 997	if (mmc_can_gpio_ro(host->mmc))
 998		mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
 999
1000	/* SDR speeds are only available on Gen2+ */
1001	if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
1002		/* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
1003		host->ops.card_busy = renesas_sdhi_card_busy;
1004		host->ops.start_signal_voltage_switch =
1005			renesas_sdhi_start_signal_voltage_switch;
1006		host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27;
1007		host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2;
1008		host->reset = renesas_sdhi_reset;
1009	} else {
1010		host->sdcard_irq_mask_all = TMIO_MASK_ALL;
1011	}
1012
1013	/* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
1014	if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
1015		host->bus_shift = 1;
1016
1017	if (mmd)
1018		*mmc_data = *mmd;
1019
1020	dma_priv->filter = shdma_chan_filter;
1021	dma_priv->enable = renesas_sdhi_enable_dma;
1022
 
1023	mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
1024
1025	/*
1026	 * All SDHI blocks support 2-byte and larger block sizes in 4-bit
1027	 * bus width mode.
1028	 */
1029	mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
1030
1031	/*
1032	 * All SDHI blocks support SDIO IRQ signalling.
1033	 */
1034	mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
1035
1036	/* All SDHI have CMD12 control bit */
1037	mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
1038
1039	/* All SDHI have SDIO status bits which must be 1 */
1040	mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
1041
1042	/* All SDHI support HW busy detection */
1043	mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT;
1044
1045	dev_pm_domain_start(&pdev->dev);
1046
1047	ret = renesas_sdhi_clk_enable(host);
1048	if (ret)
1049		goto efree;
1050
 
 
 
 
1051	ver = sd_ctrl_read16(host, CTL_VERSION);
1052	/* GEN2_SDR104 is first known SDHI to use 32bit block count */
1053	if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)
1054		mmc_data->max_blk_count = U16_MAX;
1055
1056	/* One Gen2 SDHI incarnation does NOT have a CBSY bit */
1057	if (ver == SDHI_VER_GEN2_SDR50)
1058		mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
1059
1060	if (ver == SDHI_VER_GEN3_SDMMC && sdhi_has_quirk(priv, hs400_calib_table)) {
1061		host->fixup_request = renesas_sdhi_fixup_request;
1062		priv->adjust_hs400_calib_table = *(
1063			res->start == SDHI_GEN3_MMC0_ADDR ?
1064			quirks->hs400_calib_table :
1065			quirks->hs400_calib_table + 1);
1066	}
1067
1068	/* these have an EXTOP bit */
1069	if (ver >= SDHI_VER_GEN3_SD)
1070		host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles;
1071
1072	/* Check for SCC so we can reset it if needed */
1073	if (of_data && of_data->scc_offset && ver >= SDHI_VER_GEN2_SDR104)
1074		priv->scc_ctl = host->ctl + of_data->scc_offset;
1075
1076	/* Enable tuning iff we have an SCC and a supported mode */
1077	if (priv->scc_ctl && (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
1078	    host->mmc->caps2 & MMC_CAP2_HSX00_1_8V)) {
 
 
1079		const struct renesas_sdhi_scc *taps = of_data->taps;
1080		bool use_4tap = sdhi_has_quirk(priv, hs400_4taps);
1081		bool hit = false;
1082
1083		for (i = 0; i < of_data->taps_num; i++) {
1084			if (taps[i].clk_rate == 0 ||
1085			    taps[i].clk_rate == host->mmc->f_max) {
1086				priv->scc_tappos = taps->tap;
1087				priv->scc_tappos_hs400 = use_4tap ?
1088							 taps->tap_hs400_4tap :
1089							 taps->tap;
1090				hit = true;
1091				break;
1092			}
1093		}
1094
1095		if (!hit)
1096			dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n");
1097
 
1098		host->check_retune = renesas_sdhi_check_scc_error;
1099		host->ops.execute_tuning = renesas_sdhi_execute_tuning;
1100		host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning;
1101		host->ops.hs400_downgrade = renesas_sdhi_disable_scc;
1102		host->ops.hs400_complete = renesas_sdhi_hs400_complete;
1103	}
1104
1105	sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask_all);
 
 
1106
1107	num_irqs = platform_irq_count(pdev);
1108	if (num_irqs < 0) {
1109		ret = num_irqs;
1110		goto eirq;
1111	}
1112
1113	/* There must be at least one IRQ source */
1114	if (!num_irqs) {
1115		ret = -ENXIO;
1116		goto eirq;
1117	}
1118
1119	for (i = 0; i < num_irqs; i++) {
1120		irq = platform_get_irq(pdev, i);
1121		if (irq < 0) {
1122			ret = irq;
1123			goto eirq;
1124		}
1125
1126		ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
1127				       dev_name(&pdev->dev), host);
1128		if (ret)
1129			goto eirq;
1130	}
1131
1132	ret = tmio_mmc_host_probe(host);
1133	if (ret < 0)
1134		goto edisclk;
1135
1136	dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n",
1137		 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000);
1138
1139	return ret;
1140
1141eirq:
1142	tmio_mmc_host_remove(host);
1143edisclk:
1144	renesas_sdhi_clk_disable(host);
1145efree:
1146	tmio_mmc_host_free(host);
1147
1148	return ret;
1149}
1150EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
1151
1152void renesas_sdhi_remove(struct platform_device *pdev)
1153{
1154	struct tmio_mmc_host *host = platform_get_drvdata(pdev);
1155
1156	tmio_mmc_host_remove(host);
1157	renesas_sdhi_clk_disable(host);
1158	tmio_mmc_host_free(host);
 
 
1159}
1160EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
1161
1162MODULE_LICENSE("GPL v2");
v5.14.15
   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Renesas SDHI
   4 *
   5 * Copyright (C) 2015-19 Renesas Electronics Corporation
   6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
   7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
   8 * Copyright (C) 2009 Magnus Damm
   9 *
  10 * Based on "Compaq ASIC3 support":
  11 *
  12 * Copyright 2001 Compaq Computer Corporation.
  13 * Copyright 2004-2005 Phil Blundell
  14 * Copyright 2007-2008 OpenedHand Ltd.
  15 *
  16 * Authors: Phil Blundell <pb@handhelds.org>,
  17 *	    Samuel Ortiz <sameo@openedhand.com>
  18 *
  19 */
  20
  21#include <linux/clk.h>
  22#include <linux/delay.h>
  23#include <linux/iopoll.h>
  24#include <linux/kernel.h>
  25#include <linux/mfd/tmio.h>
  26#include <linux/mmc/host.h>
  27#include <linux/mmc/mmc.h>
  28#include <linux/mmc/slot-gpio.h>
  29#include <linux/module.h>
  30#include <linux/of_device.h>
  31#include <linux/pinctrl/consumer.h>
  32#include <linux/pinctrl/pinctrl-state.h>
  33#include <linux/platform_device.h>
  34#include <linux/pm_domain.h>
  35#include <linux/regulator/consumer.h>
  36#include <linux/reset.h>
  37#include <linux/sh_dma.h>
  38#include <linux/slab.h>
  39#include <linux/sys_soc.h>
  40
  41#include "renesas_sdhi.h"
  42#include "tmio_mmc.h"
  43
  44#define CTL_HOST_MODE	0xe4
  45#define HOST_MODE_GEN2_SDR50_WMODE	BIT(0)
  46#define HOST_MODE_GEN2_SDR104_WMODE	BIT(0)
  47#define HOST_MODE_GEN3_WMODE		BIT(0)
  48#define HOST_MODE_GEN3_BUSWIDTH		BIT(8)
  49
  50#define HOST_MODE_GEN3_16BIT	HOST_MODE_GEN3_WMODE
  51#define HOST_MODE_GEN3_32BIT	(HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH)
  52#define HOST_MODE_GEN3_64BIT	0
  53
  54#define CTL_SDIF_MODE	0xe6
  55#define SDIF_MODE_HS400		BIT(0)
  56
  57#define SDHI_VER_GEN2_SDR50	0x490c
  58#define SDHI_VER_RZ_A1		0x820b
  59/* very old datasheets said 0x490c for SDR104, too. They are wrong! */
  60#define SDHI_VER_GEN2_SDR104	0xcb0d
  61#define SDHI_VER_GEN3_SD	0xcc10
  62#define SDHI_VER_GEN3_SDMMC	0xcd10
  63
  64#define SDHI_GEN3_MMC0_ADDR	0xee140000
  65
  66static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
  67{
  68	u32 val;
  69
  70	/*
  71	 * see also
  72	 *	renesas_sdhi_of_data :: dma_buswidth
  73	 */
  74	switch (sd_ctrl_read16(host, CTL_VERSION)) {
  75	case SDHI_VER_GEN2_SDR50:
  76		val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0;
  77		break;
  78	case SDHI_VER_GEN2_SDR104:
  79		val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE;
  80		break;
  81	case SDHI_VER_GEN3_SD:
  82	case SDHI_VER_GEN3_SDMMC:
  83		if (width == 64)
  84			val = HOST_MODE_GEN3_64BIT;
  85		else if (width == 32)
  86			val = HOST_MODE_GEN3_32BIT;
  87		else
  88			val = HOST_MODE_GEN3_16BIT;
  89		break;
  90	default:
  91		/* nothing to do */
  92		return;
  93	}
  94
  95	sd_ctrl_write16(host, CTL_HOST_MODE, val);
  96}
  97
  98static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
  99{
 100	struct mmc_host *mmc = host->mmc;
 101	struct renesas_sdhi *priv = host_to_priv(host);
 102	int ret;
 103
 104	ret = clk_prepare_enable(priv->clk_cd);
 105	if (ret < 0)
 106		return ret;
 107
 108	/*
 109	 * The clock driver may not know what maximum frequency
 110	 * actually works, so it should be set with the max-frequency
 111	 * property which will already have been read to f_max.  If it
 112	 * was missing, assume the current frequency is the maximum.
 113	 */
 114	if (!mmc->f_max)
 115		mmc->f_max = clk_get_rate(priv->clk);
 116
 117	/*
 118	 * Minimum frequency is the minimum input clock frequency
 119	 * divided by our maximum divider.
 120	 */
 121	mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
 122
 123	/* enable 16bit data access on SDBUF as default */
 124	renesas_sdhi_sdbuf_width(host, 16);
 125
 126	return 0;
 127}
 128
 129static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
 130					    unsigned int new_clock)
 131{
 132	struct renesas_sdhi *priv = host_to_priv(host);
 
 133	unsigned int freq, diff, best_freq = 0, diff_min = ~0;
 
 
 134	int i;
 135
 136	/*
 137	 * We simply return the current rate if a) we are not on a R-Car Gen2+
 138	 * SoC (may work for others, but untested) or b) if the SCC needs its
 139	 * clock during tuning, so we don't change the external clock setup.
 140	 */
 141	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc))
 142		return clk_get_rate(priv->clk);
 143
 
 
 
 
 
 
 
 
 
 
 144	/*
 145	 * We want the bus clock to be as close as possible to, but no
 146	 * greater than, new_clock.  As we can divide by 1 << i for
 147	 * any i in [0, 9] we want the input clock to be as close as
 148	 * possible, but no greater than, new_clock << i.
 
 
 
 
 
 
 149	 */
 150	for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
 151		freq = clk_round_rate(priv->clk, new_clock << i);
 152		if (freq > (new_clock << i)) {
 
 153			/* Too fast; look for a slightly slower option */
 154			freq = clk_round_rate(priv->clk,
 155					      (new_clock << i) / 4 * 3);
 156			if (freq > (new_clock << i))
 157				continue;
 158		}
 159
 160		diff = new_clock - (freq >> i);
 161		if (diff <= diff_min) {
 162			best_freq = freq;
 163			diff_min = diff;
 164		}
 165	}
 166
 167	clk_set_rate(priv->clk, best_freq);
 
 
 
 168
 169	return clk_get_rate(priv->clk);
 170}
 171
 172static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
 173				   unsigned int new_clock)
 174{
 
 175	u32 clk = 0, clock;
 176
 177	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 178		sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 179
 180	if (new_clock == 0) {
 181		host->mmc->actual_clock = 0;
 182		goto out;
 183	}
 184
 185	host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);
 186	clock = host->mmc->actual_clock / 512;
 187
 188	for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
 
 
 
 
 
 
 189		clock <<= 1;
 190
 191	/* 1/1 clock is option */
 192	if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
 193		if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
 194			clk |= 0xff;
 195		else
 196			clk &= ~0xff;
 197	}
 198
 199	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
 200	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 201		usleep_range(10000, 11000);
 202
 203	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 204		sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 205
 206out:
 207	/* HW engineers overrode docs: no sleep needed on R-Car2+ */
 208	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 209		usleep_range(10000, 11000);
 210}
 211
 212static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
 213{
 214	struct renesas_sdhi *priv = host_to_priv(host);
 215
 216	clk_disable_unprepare(priv->clk_cd);
 217}
 218
 219static int renesas_sdhi_card_busy(struct mmc_host *mmc)
 220{
 221	struct tmio_mmc_host *host = mmc_priv(mmc);
 222
 223	return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
 224		 TMIO_STAT_DAT0);
 225}
 226
 227static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
 228						    struct mmc_ios *ios)
 229{
 230	struct tmio_mmc_host *host = mmc_priv(mmc);
 231	struct renesas_sdhi *priv = host_to_priv(host);
 232	struct pinctrl_state *pin_state;
 233	int ret;
 234
 235	switch (ios->signal_voltage) {
 236	case MMC_SIGNAL_VOLTAGE_330:
 237		pin_state = priv->pins_default;
 238		break;
 239	case MMC_SIGNAL_VOLTAGE_180:
 240		pin_state = priv->pins_uhs;
 241		break;
 242	default:
 243		return -EINVAL;
 244	}
 245
 246	/*
 247	 * If anything is missing, assume signal voltage is fixed at
 248	 * 3.3V and succeed/fail accordingly.
 249	 */
 250	if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
 251		return ios->signal_voltage ==
 252			MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
 253
 254	ret = mmc_regulator_set_vqmmc(host->mmc, ios);
 255	if (ret < 0)
 256		return ret;
 257
 258	return pinctrl_select_state(priv->pinctrl, pin_state);
 259}
 260
 261/* SCC registers */
 262#define SH_MOBILE_SDHI_SCC_DTCNTL	0x000
 263#define SH_MOBILE_SDHI_SCC_TAPSET	0x002
 264#define SH_MOBILE_SDHI_SCC_DT2FF	0x004
 265#define SH_MOBILE_SDHI_SCC_CKSEL	0x006
 266#define SH_MOBILE_SDHI_SCC_RVSCNTL	0x008
 267#define SH_MOBILE_SDHI_SCC_RVSREQ	0x00A
 268#define SH_MOBILE_SDHI_SCC_SMPCMP       0x00C
 269#define SH_MOBILE_SDHI_SCC_TMPPORT2	0x00E
 270#define SH_MOBILE_SDHI_SCC_TMPPORT3	0x014
 271#define SH_MOBILE_SDHI_SCC_TMPPORT4	0x016
 272#define SH_MOBILE_SDHI_SCC_TMPPORT5	0x018
 273#define SH_MOBILE_SDHI_SCC_TMPPORT6	0x01A
 274#define SH_MOBILE_SDHI_SCC_TMPPORT7	0x01C
 275
 276#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN		BIT(0)
 277#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT	16
 278#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK	0xff
 279
 280#define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL		BIT(0)
 281
 282#define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN	BIT(0)
 283
 284#define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN	BIT(0)
 285#define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP	BIT(1)
 286#define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR	BIT(2)
 287
 288#define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN	BIT(8)
 289#define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP	BIT(24)
 290#define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR	(BIT(8) | BIT(24))
 291
 292#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL	BIT(4)
 293#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN	BIT(31)
 294
 295/* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */
 296#define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START	BIT(0)
 297
 298/* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */
 299#define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R	BIT(8)
 300#define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W	(0 << 8)
 301#define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK	0x3F
 302
 303/* Definitions for values the SH_MOBILE_SDHI_SCC register */
 304#define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE	0xa5000000
 305#define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK	0x1f
 306#define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE		BIT(7)
 307
 308static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
 309	{ 3,  3,  3,  3,  3,  3,  3,  4,  4,  5,  6,  7,  8,  9, 10, 15,
 310	 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 },
 311	{ 5,  5,  5,  5,  5,  5,  5,  5,  5,  5,  5,  5,  6,  7,  8, 11,
 312	 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 }
 313};
 314
 315static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
 316	{ 1,  2,  6,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15, 15, 15, 16,
 317	 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 },
 318	{ 2,  3,  4,  4,  5,  6,  7,  9, 10, 11, 12, 13, 14, 15, 16, 17,
 319	 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 }
 320};
 321
 322static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
 323	{ 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
 324	  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },
 325	{ 0,  0,  0,  1,  2,  3,  3,  4,  4,  4,  5,  5,  6,  8,  9, 10,
 326	 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 }
 327};
 328
 329static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
 330				struct renesas_sdhi *priv, int addr)
 331{
 332	return readl(priv->scc_ctl + (addr << host->bus_shift));
 333}
 334
 335static inline void sd_scc_write32(struct tmio_mmc_host *host,
 336				  struct renesas_sdhi *priv,
 337				  int addr, u32 val)
 338{
 339	writel(val, priv->scc_ctl + (addr << host->bus_shift));
 340}
 341
 342static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
 343{
 344	struct renesas_sdhi *priv;
 345
 346	priv = host_to_priv(host);
 347
 348	/* Initialize SCC */
 349	sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
 350
 351	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 352			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 353
 354	/* set sampling clock selection range */
 355	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 356		       SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
 357		       0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
 358
 359	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 360		       SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
 361		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 362
 363	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 364		       ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 365		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 366
 367	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
 368
 369	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 370			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 371
 372	/* Read TAPNUM */
 373	return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
 374		SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
 375		SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
 376}
 377
 378static void renesas_sdhi_hs400_complete(struct mmc_host *mmc)
 379{
 380	struct tmio_mmc_host *host = mmc_priv(mmc);
 381	struct renesas_sdhi *priv = host_to_priv(host);
 382	u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
 383	bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
 384
 385	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 386		sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 387
 388	/* Set HS400 mode */
 389	sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 |
 390			sd_ctrl_read16(host, CTL_SDIF_MODE));
 391
 392	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF,
 393		       priv->scc_tappos_hs400);
 394
 395	/* Gen3 can't do automatic tap correction with HS400, so disable it */
 396	if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC)
 397		sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 398			       ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 399			       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 400
 401	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
 402		       (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
 403			SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
 404			sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
 405
 406	/* Set the sampling clock selection range of HS400 mode */
 407	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 408		       SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
 409		       0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
 
 410
 411	/* Avoid bad TAP */
 412	if (bad_taps & BIT(priv->tap_set)) {
 413		u32 new_tap = (priv->tap_set + 1) % priv->tap_num;
 414
 415		if (bad_taps & BIT(new_tap))
 416			new_tap = (priv->tap_set - 1) % priv->tap_num;
 417
 418		if (bad_taps & BIT(new_tap)) {
 419			new_tap = priv->tap_set;
 420			dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n");
 421		}
 422
 423		priv->tap_set = new_tap;
 424	}
 425
 426	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
 427		       priv->tap_set / (use_4tap ? 2 : 1));
 428
 429	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 430		       SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
 431		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 432
 433	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 434			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 435
 436	if (priv->adjust_hs400_calib_table)
 437		priv->needs_adjust_hs400 = true;
 438}
 439
 440static void renesas_sdhi_disable_scc(struct mmc_host *mmc)
 441{
 442	struct tmio_mmc_host *host = mmc_priv(mmc);
 443	struct renesas_sdhi *priv = host_to_priv(host);
 444
 445	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 446			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 447
 448	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 449		       ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
 450		       sd_scc_read32(host, priv,
 451				     SH_MOBILE_SDHI_SCC_CKSEL));
 452
 453	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 454		       ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
 455		       sd_scc_read32(host, priv,
 456				     SH_MOBILE_SDHI_SCC_DTCNTL));
 457
 458	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 459			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 460}
 461
 462static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host,
 463				 struct renesas_sdhi *priv, u32 addr)
 464{
 465	/* read mode */
 466	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
 467		       SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
 468		       (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
 469
 470	/* access start and stop */
 471	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
 472		       SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
 473	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
 474
 475	return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7);
 476}
 477
 478static void sd_scc_tmpport_write32(struct tmio_mmc_host *host,
 479				   struct renesas_sdhi *priv, u32 addr, u32 val)
 480{
 481	/* write mode */
 482	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
 483		       SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
 484		       (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
 485
 486	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val);
 487
 488	/* access start and stop */
 489	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
 490		       SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
 491	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
 492}
 493
 494static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host)
 495{
 496	struct renesas_sdhi *priv = host_to_priv(host);
 497	u32 calib_code;
 498
 499	/* disable write protect */
 500	sd_scc_tmpport_write32(host, priv, 0x00,
 501			       SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
 502	/* read calibration code and adjust */
 503	calib_code = sd_scc_tmpport_read32(host, priv, 0x26);
 504	calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
 505
 506	sd_scc_tmpport_write32(host, priv, 0x22,
 507			       SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE |
 508			       priv->adjust_hs400_calib_table[calib_code]);
 509
 510	/* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */
 511	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3);
 512
 513	/* adjustment done, clear flag */
 514	priv->needs_adjust_hs400 = false;
 515}
 516
 517static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host)
 518{
 519	struct renesas_sdhi *priv = host_to_priv(host);
 520
 521	/* disable write protect */
 522	sd_scc_tmpport_write32(host, priv, 0x00,
 523			       SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
 524	/* disable manual calibration */
 525	sd_scc_tmpport_write32(host, priv, 0x22, 0);
 526	/* clear offset value of TMPPORT3 */
 527	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0);
 528}
 529
 530static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
 531					  struct renesas_sdhi *priv)
 532{
 533	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 534			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 535
 536	/* Reset HS400 mode */
 537	sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 &
 538			sd_ctrl_read16(host, CTL_SDIF_MODE));
 539
 540	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
 541
 542	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
 543		       ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
 544			 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
 545			sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
 546
 547	if (priv->adjust_hs400_calib_table)
 548		renesas_sdhi_adjust_hs400_mode_disable(host);
 549
 550	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 551			sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 552}
 553
 554static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
 555{
 556	struct tmio_mmc_host *host = mmc_priv(mmc);
 557
 558	renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
 559	return 0;
 560}
 561
 562static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv)
 563{
 564	renesas_sdhi_disable_scc(host->mmc);
 565	renesas_sdhi_reset_hs400_mode(host, priv);
 566	priv->needs_adjust_hs400 = false;
 567
 568	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 569		       ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 570		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 571}
 572
 573/* only populated for TMIO_MMC_MIN_RCAR2 */
 574static void renesas_sdhi_reset(struct tmio_mmc_host *host)
 575{
 576	struct renesas_sdhi *priv = host_to_priv(host);
 577	int ret;
 578	u16 val;
 579
 580	if (priv->rstc) {
 581		reset_control_reset(priv->rstc);
 582		/* Unknown why but without polling reset status, it will hang */
 583		read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100,
 584				  false, priv->rstc);
 585		/* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */
 586		sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
 587		priv->needs_adjust_hs400 = false;
 588		renesas_sdhi_set_clock(host, host->clk_cache);
 589	} else if (priv->scc_ctl) {
 590		renesas_sdhi_scc_reset(host, priv);
 
 
 591	}
 592
 593	if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) {
 594		val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT);
 595		val |= CARD_OPT_EXTOP;
 596		sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val);
 597	}
 598}
 599
 600static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host)
 601{
 602	u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT);
 603
 604	num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT;
 605	return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num);
 606
 607}
 608
 609#define SH_MOBILE_SDHI_MIN_TAP_ROW 3
 610
 611static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
 612{
 613	struct renesas_sdhi *priv = host_to_priv(host);
 614	unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i;
 615	unsigned int taps_size = priv->tap_num * 2, min_tap_row;
 616	unsigned long *bitmap;
 617
 618	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 619
 620	/*
 621	 * When tuning CMD19 is issued twice for each tap, merge the
 622	 * result requiring the tap to be good in both runs before
 623	 * considering it for tuning selection.
 624	 */
 625	for (i = 0; i < taps_size; i++) {
 626		int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1);
 627
 628		if (!test_bit(i, priv->taps))
 629			clear_bit(i + offset, priv->taps);
 630
 631		if (!test_bit(i, priv->smpcmp))
 632			clear_bit(i + offset, priv->smpcmp);
 633	}
 634
 635	/*
 636	 * If all TAP are OK, the sampling clock position is selected by
 637	 * identifying the change point of data.
 638	 */
 639	if (bitmap_full(priv->taps, taps_size)) {
 640		bitmap = priv->smpcmp;
 641		min_tap_row = 1;
 642	} else {
 643		bitmap = priv->taps;
 644		min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW;
 645	}
 646
 647	/*
 648	 * Find the longest consecutive run of successful probes. If that
 649	 * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the
 650	 * center index as the tap, otherwise bail out.
 651	 */
 652	bitmap_for_each_set_region(bitmap, rs, re, 0, taps_size) {
 653		if (re - rs > tap_cnt) {
 654			tap_end = re;
 655			tap_start = rs;
 656			tap_cnt = tap_end - tap_start;
 657		}
 658	}
 659
 660	if (tap_cnt >= min_tap_row)
 661		priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num;
 662	else
 663		return -EIO;
 664
 665	/* Set SCC */
 666	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set);
 667
 668	/* Enable auto re-tuning */
 669	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 670		       SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
 671		       sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 672
 673	return 0;
 674}
 675
 676static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode)
 677{
 678	struct tmio_mmc_host *host = mmc_priv(mmc);
 679	struct renesas_sdhi *priv = host_to_priv(host);
 680	int i, ret;
 681
 682	priv->tap_num = renesas_sdhi_init_tuning(host);
 683	if (!priv->tap_num)
 684		return 0; /* Tuning is not supported */
 685
 686	if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) {
 687		dev_err(&host->pdev->dev,
 688			"Too many taps, please update 'taps' in tmio_mmc_host!\n");
 689		return -EINVAL;
 690	}
 691
 692	bitmap_zero(priv->taps, priv->tap_num * 2);
 693	bitmap_zero(priv->smpcmp, priv->tap_num * 2);
 694
 695	/* Issue CMD19 twice for each tap */
 696	for (i = 0; i < 2 * priv->tap_num; i++) {
 697		int cmd_error;
 698
 699		/* Set sampling clock position */
 700		sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num);
 701
 702		if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0)
 703			set_bit(i, priv->taps);
 704
 705		if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0)
 706			set_bit(i, priv->smpcmp);
 707
 708		if (cmd_error)
 709			mmc_send_abort_tuning(mmc, opcode);
 710	}
 711
 712	ret = renesas_sdhi_select_tuning(host);
 713	if (ret < 0)
 714		renesas_sdhi_scc_reset(host, priv);
 715	return ret;
 716}
 717
 718static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap)
 719{
 720	struct renesas_sdhi *priv = host_to_priv(host);
 721	unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set;
 722	u32 val;
 723
 724	val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ);
 725	if (!val)
 726		return false;
 727
 728	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 729
 730	/* Change TAP position according to correction status */
 731	if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC &&
 732	    host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
 733		u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
 734		/*
 735		 * With HS400, the DAT signal is based on DS, not CLK.
 736		 * Therefore, use only CMD status.
 737		 */
 738		u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) &
 739					   SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR;
 740		if (!smpcmp) {
 741			return false;	/* no error in CMD signal */
 742		} else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) {
 743			new_tap++;
 744			error_tap--;
 745		} else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) {
 746			new_tap--;
 747			error_tap++;
 748		} else {
 749			return true;	/* need retune */
 750		}
 751
 752		/*
 753		 * When new_tap is a bad tap, we cannot change. Then, we compare
 754		 * with the HS200 tuning result. When smpcmp[error_tap] is OK,
 755		 * we can at least retune.
 756		 */
 757		if (bad_taps & BIT(new_tap % priv->tap_num))
 758			return test_bit(error_tap % priv->tap_num, priv->smpcmp);
 759	} else {
 760		if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)
 761			return true;    /* need retune */
 762		else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP)
 763			new_tap++;
 764		else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN)
 765			new_tap--;
 766		else
 767			return false;
 768	}
 769
 770	priv->tap_set = (new_tap % priv->tap_num);
 771	sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
 772		       priv->tap_set / (use_4tap ? 2 : 1));
 773
 774	return false;
 775}
 776
 777static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host)
 778{
 779	struct renesas_sdhi *priv = host_to_priv(host);
 780
 781	/* Check SCC error */
 782	if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
 783	    SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
 784		sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 785		return true;
 786	}
 787
 788	return false;
 789}
 790
 791static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host,
 792					 struct mmc_request *mrq)
 793{
 794	struct renesas_sdhi *priv = host_to_priv(host);
 795	bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
 796	bool ret = false;
 797
 798	/*
 799	 * Skip checking SCC errors when running on 4 taps in HS400 mode as
 800	 * any retuning would still result in the same 4 taps being used.
 801	 */
 802	if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
 803	    !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
 804	    !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
 805		return false;
 806
 807	if (mmc_doing_tune(host->mmc))
 808		return false;
 809
 810	if (((mrq->cmd->error == -ETIMEDOUT) ||
 811	     (mrq->data && mrq->data->error == -ETIMEDOUT)) &&
 812	    ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
 813	     (host->ops.get_cd && host->ops.get_cd(host->mmc))))
 814		ret |= true;
 815
 816	if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
 817	    SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN)
 818		ret |= renesas_sdhi_auto_correction(host);
 819	else
 820		ret |= renesas_sdhi_manual_correction(host, use_4tap);
 821
 822	return ret;
 823}
 824
 825static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
 826{
 827	int timeout = 1000;
 828	/* CBSY is set when busy, SCLKDIVEN is cleared when busy */
 829	u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
 830
 831	while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
 832			      & bit) == wait_state)
 833		udelay(1);
 834
 835	if (!timeout) {
 836		dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
 837		return -EBUSY;
 838	}
 839
 840	return 0;
 841}
 842
 843static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
 844{
 845	u32 bit = TMIO_STAT_SCLKDIVEN;
 846
 847	switch (addr) {
 848	case CTL_SD_CMD:
 849	case CTL_STOP_INTERNAL_ACTION:
 850	case CTL_XFER_BLK_COUNT:
 851	case CTL_SD_XFER_LEN:
 852	case CTL_SD_MEM_CARD_OPT:
 853	case CTL_TRANSACTION_CTL:
 854	case CTL_DMA_ENABLE:
 855	case CTL_HOST_MODE:
 856		if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
 857			bit = TMIO_STAT_CMD_BUSY;
 858		fallthrough;
 859	case CTL_SD_CARD_CLK_CTL:
 860		return renesas_sdhi_wait_idle(host, bit);
 861	}
 862
 863	return 0;
 864}
 865
 866static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
 867				       unsigned int direction, int blk_size)
 868{
 869	/*
 870	 * In Renesas controllers, when performing a
 871	 * multiple block read of one or two blocks,
 872	 * depending on the timing with which the
 873	 * response register is read, the response
 874	 * value may not be read properly.
 875	 * Use single block read for this HW bug
 876	 */
 877	if ((direction == MMC_DATA_READ) &&
 878	    blk_size == 2)
 879		return 1;
 880
 881	return blk_size;
 882}
 883
 884static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq)
 885{
 886	struct renesas_sdhi *priv = host_to_priv(host);
 887
 888	if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS)
 889		renesas_sdhi_adjust_hs400_mode_enable(host);
 890}
 891static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
 892{
 893	/* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
 894	int width = (host->bus_shift == 2) ? 64 : 32;
 895
 896	sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
 897	renesas_sdhi_sdbuf_width(host, enable ? width : 16);
 898}
 899
 900static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
 901	.hs400_disabled = true,
 902	.hs400_4taps = true,
 903};
 904
 905static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
 906	.hs400_4taps = true,
 907	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
 908};
 909
 910static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = {
 911	.hs400_disabled = true,
 912};
 913
 914static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = {
 915	.hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
 916};
 917
 918static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = {
 919	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
 920};
 921
 922static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
 923	.hs400_4taps = true,
 924	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
 925	.hs400_calib_table = r8a7796_es13_calib_table,
 926};
 927
 928static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
 929	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
 930	.hs400_calib_table = r8a77965_calib_table,
 931};
 932
 933static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = {
 934	.hs400_calib_table = r8a77990_calib_table,
 935};
 936
 937/*
 938 * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
 939 * So, we want to treat them equally and only have a match for ES1.2 to enforce
 940 * this if there ever will be a way to distinguish ES1.2.
 941 */
 942static const struct soc_device_attribute sdhi_quirks_match[]  = {
 943	{ .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
 944	{ .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 },
 945	{ .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap },
 946	{ .soc_id = "r8a7795", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps2367 },
 947	{ .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
 948	{ .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 },
 949	{ .soc_id = "r8a77961", .data = &sdhi_quirks_bad_taps1357 },
 950	{ .soc_id = "r8a77965", .data = &sdhi_quirks_r8a77965 },
 951	{ .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 },
 952	{ .soc_id = "r8a77990", .data = &sdhi_quirks_r8a77990 },
 953	{ /* Sentinel. */ },
 954};
 955
 956int renesas_sdhi_probe(struct platform_device *pdev,
 957		       const struct tmio_mmc_dma_ops *dma_ops)
 
 
 958{
 959	struct tmio_mmc_data *mmd = pdev->dev.platform_data;
 960	const struct renesas_sdhi_quirks *quirks = NULL;
 961	const struct renesas_sdhi_of_data *of_data;
 962	const struct soc_device_attribute *attr;
 963	struct tmio_mmc_data *mmc_data;
 964	struct tmio_mmc_dma *dma_priv;
 965	struct tmio_mmc_host *host;
 966	struct renesas_sdhi *priv;
 967	int num_irqs, irq, ret, i;
 968	struct resource *res;
 969	u16 ver;
 970
 971	of_data = of_device_get_match_data(&pdev->dev);
 972
 973	attr = soc_device_match(sdhi_quirks_match);
 974	if (attr)
 975		quirks = attr->data;
 976
 977	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 978	if (!res)
 979		return -EINVAL;
 980
 981	priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
 982			    GFP_KERNEL);
 983	if (!priv)
 984		return -ENOMEM;
 985
 986	priv->quirks = quirks;
 987	mmc_data = &priv->mmc_data;
 988	dma_priv = &priv->dma_priv;
 989
 990	priv->clk = devm_clk_get(&pdev->dev, NULL);
 991	if (IS_ERR(priv->clk)) {
 992		ret = PTR_ERR(priv->clk);
 993		dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
 994		return ret;
 995	}
 
 996
 997	/*
 998	 * Some controllers provide a 2nd clock just to run the internal card
 999	 * detection logic. Unfortunately, the existing driver architecture does
1000	 * not support a separation of clocks for runtime PM usage. When
1001	 * native hotplug is used, the tmio driver assumes that the core
1002	 * must continue to run for card detect to stay active, so we cannot
1003	 * disable it.
1004	 * Additionally, it is prohibited to supply a clock to the core but not
1005	 * to the card detect circuit. That leaves us with if separate clocks
1006	 * are presented, we must treat them both as virtually 1 clock.
1007	 */
1008	priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
1009	if (IS_ERR(priv->clk_cd))
1010		priv->clk_cd = NULL;
 
 
 
 
1011
1012	priv->pinctrl = devm_pinctrl_get(&pdev->dev);
1013	if (!IS_ERR(priv->pinctrl)) {
1014		priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
1015						PINCTRL_STATE_DEFAULT);
1016		priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
1017						"state_uhs");
1018	}
1019
1020	host = tmio_mmc_host_alloc(pdev, mmc_data);
1021	if (IS_ERR(host))
1022		return PTR_ERR(host);
1023
1024	if (of_data) {
1025		mmc_data->flags |= of_data->tmio_flags;
1026		mmc_data->ocr_mask = of_data->tmio_ocr_mask;
1027		mmc_data->capabilities |= of_data->capabilities;
1028		mmc_data->capabilities2 |= of_data->capabilities2;
1029		mmc_data->dma_rx_offset = of_data->dma_rx_offset;
1030		mmc_data->max_blk_count = of_data->max_blk_count;
1031		mmc_data->max_segs = of_data->max_segs;
1032		dma_priv->dma_buswidth = of_data->dma_buswidth;
1033		host->bus_shift = of_data->bus_shift;
 
 
 
 
1034	}
1035
1036	host->write16_hook	= renesas_sdhi_write16_hook;
1037	host->clk_enable	= renesas_sdhi_clk_enable;
1038	host->clk_disable	= renesas_sdhi_clk_disable;
1039	host->set_clock		= renesas_sdhi_set_clock;
1040	host->multi_io_quirk	= renesas_sdhi_multi_io_quirk;
1041	host->dma_ops		= dma_ops;
1042
1043	if (quirks && quirks->hs400_disabled)
1044		host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
1045
1046	/* For some SoC, we disable internal WP. GPIO may override this */
1047	if (mmc_can_gpio_ro(host->mmc))
1048		mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
1049
1050	/* SDR speeds are only available on Gen2+ */
1051	if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
1052		/* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
1053		host->ops.card_busy = renesas_sdhi_card_busy;
1054		host->ops.start_signal_voltage_switch =
1055			renesas_sdhi_start_signal_voltage_switch;
1056		host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27;
1057		host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2;
1058		host->reset = renesas_sdhi_reset;
 
 
1059	}
1060
1061	/* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
1062	if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
1063		host->bus_shift = 1;
1064
1065	if (mmd)
1066		*mmc_data = *mmd;
1067
1068	dma_priv->filter = shdma_chan_filter;
1069	dma_priv->enable = renesas_sdhi_enable_dma;
1070
1071	mmc_data->alignment_shift = 1; /* 2-byte alignment */
1072	mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
1073
1074	/*
1075	 * All SDHI blocks support 2-byte and larger block sizes in 4-bit
1076	 * bus width mode.
1077	 */
1078	mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
1079
1080	/*
1081	 * All SDHI blocks support SDIO IRQ signalling.
1082	 */
1083	mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
1084
1085	/* All SDHI have CMD12 control bit */
1086	mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
1087
1088	/* All SDHI have SDIO status bits which must be 1 */
1089	mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
1090
1091	/* All SDHI support HW busy detection */
1092	mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT;
1093
1094	dev_pm_domain_start(&pdev->dev);
1095
1096	ret = renesas_sdhi_clk_enable(host);
1097	if (ret)
1098		goto efree;
1099
1100	priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1101	if (IS_ERR(priv->rstc))
1102		return PTR_ERR(priv->rstc);
1103
1104	ver = sd_ctrl_read16(host, CTL_VERSION);
1105	/* GEN2_SDR104 is first known SDHI to use 32bit block count */
1106	if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)
1107		mmc_data->max_blk_count = U16_MAX;
1108
1109	/* One Gen2 SDHI incarnation does NOT have a CBSY bit */
1110	if (ver == SDHI_VER_GEN2_SDR50)
1111		mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
1112
1113	if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) {
1114		host->fixup_request = renesas_sdhi_fixup_request;
1115		priv->adjust_hs400_calib_table = *(
1116			res->start == SDHI_GEN3_MMC0_ADDR ?
1117			quirks->hs400_calib_table :
1118			quirks->hs400_calib_table + 1);
1119	}
1120
1121	/* these have an EXTOP bit */
1122	if (ver >= SDHI_VER_GEN3_SD)
1123		host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles;
1124
 
 
 
 
1125	/* Enable tuning iff we have an SCC and a supported mode */
1126	if (of_data && of_data->scc_offset &&
1127	    (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
1128	     host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR |
1129				 MMC_CAP2_HS400_1_8V))) {
1130		const struct renesas_sdhi_scc *taps = of_data->taps;
1131		bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
1132		bool hit = false;
1133
1134		for (i = 0; i < of_data->taps_num; i++) {
1135			if (taps[i].clk_rate == 0 ||
1136			    taps[i].clk_rate == host->mmc->f_max) {
1137				priv->scc_tappos = taps->tap;
1138				priv->scc_tappos_hs400 = use_4tap ?
1139							 taps->tap_hs400_4tap :
1140							 taps->tap;
1141				hit = true;
1142				break;
1143			}
1144		}
1145
1146		if (!hit)
1147			dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n");
1148
1149		priv->scc_ctl = host->ctl + of_data->scc_offset;
1150		host->check_retune = renesas_sdhi_check_scc_error;
1151		host->ops.execute_tuning = renesas_sdhi_execute_tuning;
1152		host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning;
1153		host->ops.hs400_downgrade = renesas_sdhi_disable_scc;
1154		host->ops.hs400_complete = renesas_sdhi_hs400_complete;
1155	}
1156
1157	ret = tmio_mmc_host_probe(host);
1158	if (ret < 0)
1159		goto edisclk;
1160
1161	num_irqs = platform_irq_count(pdev);
1162	if (num_irqs < 0) {
1163		ret = num_irqs;
1164		goto eirq;
1165	}
1166
1167	/* There must be at least one IRQ source */
1168	if (!num_irqs) {
1169		ret = -ENXIO;
1170		goto eirq;
1171	}
1172
1173	for (i = 0; i < num_irqs; i++) {
1174		irq = platform_get_irq(pdev, i);
1175		if (irq < 0) {
1176			ret = irq;
1177			goto eirq;
1178		}
1179
1180		ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
1181				       dev_name(&pdev->dev), host);
1182		if (ret)
1183			goto eirq;
1184	}
1185
 
 
 
 
1186	dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n",
1187		 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000);
1188
1189	return ret;
1190
1191eirq:
1192	tmio_mmc_host_remove(host);
1193edisclk:
1194	renesas_sdhi_clk_disable(host);
1195efree:
1196	tmio_mmc_host_free(host);
1197
1198	return ret;
1199}
1200EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
1201
1202int renesas_sdhi_remove(struct platform_device *pdev)
1203{
1204	struct tmio_mmc_host *host = platform_get_drvdata(pdev);
1205
1206	tmio_mmc_host_remove(host);
1207	renesas_sdhi_clk_disable(host);
1208	tmio_mmc_host_free(host);
1209
1210	return 0;
1211}
1212EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
1213
1214MODULE_LICENSE("GPL v2");