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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Memory controller driver for ARM PrimeCell PL172
4 * PrimeCell MultiPort Memory Controller (PL172)
5 *
6 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
7 *
8 * Based on:
9 * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
10 */
11
12#include <linux/amba/bus.h>
13#include <linux/clk.h>
14#include <linux/device.h>
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_platform.h>
22#include <linux/time.h>
23
24#define MPMC_STATIC_CFG(n) (0x200 + 0x20 * (n))
25#define MPMC_STATIC_CFG_MW_8BIT 0x0
26#define MPMC_STATIC_CFG_MW_16BIT 0x1
27#define MPMC_STATIC_CFG_MW_32BIT 0x2
28#define MPMC_STATIC_CFG_PM BIT(3)
29#define MPMC_STATIC_CFG_PC BIT(6)
30#define MPMC_STATIC_CFG_PB BIT(7)
31#define MPMC_STATIC_CFG_EW BIT(8)
32#define MPMC_STATIC_CFG_B BIT(19)
33#define MPMC_STATIC_CFG_P BIT(20)
34#define MPMC_STATIC_WAIT_WEN(n) (0x204 + 0x20 * (n))
35#define MPMC_STATIC_WAIT_WEN_MAX 0x0f
36#define MPMC_STATIC_WAIT_OEN(n) (0x208 + 0x20 * (n))
37#define MPMC_STATIC_WAIT_OEN_MAX 0x0f
38#define MPMC_STATIC_WAIT_RD(n) (0x20c + 0x20 * (n))
39#define MPMC_STATIC_WAIT_RD_MAX 0x1f
40#define MPMC_STATIC_WAIT_PAGE(n) (0x210 + 0x20 * (n))
41#define MPMC_STATIC_WAIT_PAGE_MAX 0x1f
42#define MPMC_STATIC_WAIT_WR(n) (0x214 + 0x20 * (n))
43#define MPMC_STATIC_WAIT_WR_MAX 0x1f
44#define MPMC_STATIC_WAIT_TURN(n) (0x218 + 0x20 * (n))
45#define MPMC_STATIC_WAIT_TURN_MAX 0x0f
46
47/* Maximum number of static chip selects */
48#define PL172_MAX_CS 4
49
50struct pl172_data {
51 void __iomem *base;
52 unsigned long rate;
53 struct clk *clk;
54};
55
56static int pl172_timing_prop(struct amba_device *adev,
57 const struct device_node *np, const char *name,
58 u32 reg_offset, u32 max, int start)
59{
60 struct pl172_data *pl172 = amba_get_drvdata(adev);
61 int cycles;
62 u32 val;
63
64 if (!of_property_read_u32(np, name, &val)) {
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start;
66 if (cycles < 0) {
67 cycles = 0;
68 } else if (cycles > max) {
69 dev_err(&adev->dev, "%s timing too tight\n", name);
70 return -EINVAL;
71 }
72
73 writel(cycles, pl172->base + reg_offset);
74 }
75
76 dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start +
77 readl(pl172->base + reg_offset));
78
79 return 0;
80}
81
82static int pl172_setup_static(struct amba_device *adev,
83 struct device_node *np, u32 cs)
84{
85 struct pl172_data *pl172 = amba_get_drvdata(adev);
86 u32 cfg;
87 int ret;
88
89 /* MPMC static memory configuration */
90 if (!of_property_read_u32(np, "mpmc,memory-width", &cfg)) {
91 if (cfg == 8) {
92 cfg = MPMC_STATIC_CFG_MW_8BIT;
93 } else if (cfg == 16) {
94 cfg = MPMC_STATIC_CFG_MW_16BIT;
95 } else if (cfg == 32) {
96 cfg = MPMC_STATIC_CFG_MW_32BIT;
97 } else {
98 dev_err(&adev->dev, "invalid memory width cs%u\n", cs);
99 return -EINVAL;
100 }
101 } else {
102 dev_err(&adev->dev, "memory-width property required\n");
103 return -EINVAL;
104 }
105
106 if (of_property_read_bool(np, "mpmc,async-page-mode"))
107 cfg |= MPMC_STATIC_CFG_PM;
108
109 if (of_property_read_bool(np, "mpmc,cs-active-high"))
110 cfg |= MPMC_STATIC_CFG_PC;
111
112 if (of_property_read_bool(np, "mpmc,byte-lane-low"))
113 cfg |= MPMC_STATIC_CFG_PB;
114
115 if (of_property_read_bool(np, "mpmc,extended-wait"))
116 cfg |= MPMC_STATIC_CFG_EW;
117
118 if (amba_part(adev) == 0x172 &&
119 of_property_read_bool(np, "mpmc,buffer-enable"))
120 cfg |= MPMC_STATIC_CFG_B;
121
122 if (of_property_read_bool(np, "mpmc,write-protect"))
123 cfg |= MPMC_STATIC_CFG_P;
124
125 writel(cfg, pl172->base + MPMC_STATIC_CFG(cs));
126 dev_dbg(&adev->dev, "mpmc static config cs%u: 0x%08x\n", cs, cfg);
127
128 /* MPMC static memory timing */
129 ret = pl172_timing_prop(adev, np, "mpmc,write-enable-delay",
130 MPMC_STATIC_WAIT_WEN(cs),
131 MPMC_STATIC_WAIT_WEN_MAX, 1);
132 if (ret)
133 goto fail;
134
135 ret = pl172_timing_prop(adev, np, "mpmc,output-enable-delay",
136 MPMC_STATIC_WAIT_OEN(cs),
137 MPMC_STATIC_WAIT_OEN_MAX, 0);
138 if (ret)
139 goto fail;
140
141 ret = pl172_timing_prop(adev, np, "mpmc,read-access-delay",
142 MPMC_STATIC_WAIT_RD(cs),
143 MPMC_STATIC_WAIT_RD_MAX, 1);
144 if (ret)
145 goto fail;
146
147 ret = pl172_timing_prop(adev, np, "mpmc,page-mode-read-delay",
148 MPMC_STATIC_WAIT_PAGE(cs),
149 MPMC_STATIC_WAIT_PAGE_MAX, 1);
150 if (ret)
151 goto fail;
152
153 ret = pl172_timing_prop(adev, np, "mpmc,write-access-delay",
154 MPMC_STATIC_WAIT_WR(cs),
155 MPMC_STATIC_WAIT_WR_MAX, 2);
156 if (ret)
157 goto fail;
158
159 ret = pl172_timing_prop(adev, np, "mpmc,turn-round-delay",
160 MPMC_STATIC_WAIT_TURN(cs),
161 MPMC_STATIC_WAIT_TURN_MAX, 1);
162 if (ret)
163 goto fail;
164
165 return 0;
166fail:
167 dev_err(&adev->dev, "failed to configure cs%u\n", cs);
168 return ret;
169}
170
171static int pl172_parse_cs_config(struct amba_device *adev,
172 struct device_node *np)
173{
174 u32 cs;
175
176 if (!of_property_read_u32(np, "mpmc,cs", &cs)) {
177 if (cs >= PL172_MAX_CS) {
178 dev_err(&adev->dev, "cs%u invalid\n", cs);
179 return -EINVAL;
180 }
181
182 return pl172_setup_static(adev, np, cs);
183 }
184
185 dev_err(&adev->dev, "cs property required\n");
186
187 return -EINVAL;
188}
189
190static const char * const pl172_revisions[] = {"r1", "r2", "r2p3", "r2p4"};
191static const char * const pl175_revisions[] = {"r1"};
192static const char * const pl176_revisions[] = {"r0"};
193
194static int pl172_probe(struct amba_device *adev, const struct amba_id *id)
195{
196 struct device_node *child_np, *np = adev->dev.of_node;
197 struct device *dev = &adev->dev;
198 static const char *rev = "?";
199 struct pl172_data *pl172;
200 int ret;
201
202 if (amba_part(adev) == 0x172) {
203 if (amba_rev(adev) < ARRAY_SIZE(pl172_revisions))
204 rev = pl172_revisions[amba_rev(adev)];
205 } else if (amba_part(adev) == 0x175) {
206 if (amba_rev(adev) < ARRAY_SIZE(pl175_revisions))
207 rev = pl175_revisions[amba_rev(adev)];
208 } else if (amba_part(adev) == 0x176) {
209 if (amba_rev(adev) < ARRAY_SIZE(pl176_revisions))
210 rev = pl176_revisions[amba_rev(adev)];
211 }
212
213 dev_info(dev, "ARM PL%x revision %s\n", amba_part(adev), rev);
214
215 pl172 = devm_kzalloc(dev, sizeof(*pl172), GFP_KERNEL);
216 if (!pl172)
217 return -ENOMEM;
218
219 pl172->clk = devm_clk_get(dev, "mpmcclk");
220 if (IS_ERR(pl172->clk)) {
221 dev_err(dev, "no mpmcclk provided clock\n");
222 return PTR_ERR(pl172->clk);
223 }
224
225 ret = clk_prepare_enable(pl172->clk);
226 if (ret) {
227 dev_err(dev, "unable to mpmcclk enable clock\n");
228 return ret;
229 }
230
231 pl172->rate = clk_get_rate(pl172->clk) / MSEC_PER_SEC;
232 if (!pl172->rate) {
233 dev_err(dev, "unable to get mpmcclk clock rate\n");
234 ret = -EINVAL;
235 goto err_clk_enable;
236 }
237
238 ret = amba_request_regions(adev, NULL);
239 if (ret) {
240 dev_err(dev, "unable to request AMBA regions\n");
241 goto err_clk_enable;
242 }
243
244 pl172->base = devm_ioremap(dev, adev->res.start,
245 resource_size(&adev->res));
246 if (!pl172->base) {
247 dev_err(dev, "ioremap failed\n");
248 ret = -ENOMEM;
249 goto err_no_ioremap;
250 }
251
252 amba_set_drvdata(adev, pl172);
253
254 /*
255 * Loop through each child node, which represent a chip select, and
256 * configure parameters and timing. If successful; populate devices
257 * under that node.
258 */
259 for_each_available_child_of_node(np, child_np) {
260 ret = pl172_parse_cs_config(adev, child_np);
261 if (ret)
262 continue;
263
264 of_platform_populate(child_np, NULL, NULL, dev);
265 }
266
267 return 0;
268
269err_no_ioremap:
270 amba_release_regions(adev);
271err_clk_enable:
272 clk_disable_unprepare(pl172->clk);
273 return ret;
274}
275
276static void pl172_remove(struct amba_device *adev)
277{
278 struct pl172_data *pl172 = amba_get_drvdata(adev);
279
280 clk_disable_unprepare(pl172->clk);
281 amba_release_regions(adev);
282}
283
284static const struct amba_id pl172_ids[] = {
285 /* PrimeCell MPMC PL172, EMC found on NXP LPC18xx and LPC43xx */
286 {
287 .id = 0x07041172,
288 .mask = 0x3f0fffff,
289 },
290 /* PrimeCell MPMC PL175, EMC found on NXP LPC32xx */
291 {
292 .id = 0x07041175,
293 .mask = 0x3f0fffff,
294 },
295 /* PrimeCell MPMC PL176 */
296 {
297 .id = 0x89041176,
298 .mask = 0xff0fffff,
299 },
300 { 0, 0 },
301};
302MODULE_DEVICE_TABLE(amba, pl172_ids);
303
304static struct amba_driver pl172_driver = {
305 .drv = {
306 .name = "memory-pl172",
307 },
308 .probe = pl172_probe,
309 .remove = pl172_remove,
310 .id_table = pl172_ids,
311};
312module_amba_driver(pl172_driver);
313
314MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
315MODULE_DESCRIPTION("PL172 Memory Controller Driver");
316MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Memory controller driver for ARM PrimeCell PL172
4 * PrimeCell MultiPort Memory Controller (PL172)
5 *
6 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
7 *
8 * Based on:
9 * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
10 */
11
12#include <linux/amba/bus.h>
13#include <linux/clk.h>
14#include <linux/device.h>
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_platform.h>
22#include <linux/time.h>
23
24#define MPMC_STATIC_CFG(n) (0x200 + 0x20 * (n))
25#define MPMC_STATIC_CFG_MW_8BIT 0x0
26#define MPMC_STATIC_CFG_MW_16BIT 0x1
27#define MPMC_STATIC_CFG_MW_32BIT 0x2
28#define MPMC_STATIC_CFG_PM BIT(3)
29#define MPMC_STATIC_CFG_PC BIT(6)
30#define MPMC_STATIC_CFG_PB BIT(7)
31#define MPMC_STATIC_CFG_EW BIT(8)
32#define MPMC_STATIC_CFG_B BIT(19)
33#define MPMC_STATIC_CFG_P BIT(20)
34#define MPMC_STATIC_WAIT_WEN(n) (0x204 + 0x20 * (n))
35#define MPMC_STATIC_WAIT_WEN_MAX 0x0f
36#define MPMC_STATIC_WAIT_OEN(n) (0x208 + 0x20 * (n))
37#define MPMC_STATIC_WAIT_OEN_MAX 0x0f
38#define MPMC_STATIC_WAIT_RD(n) (0x20c + 0x20 * (n))
39#define MPMC_STATIC_WAIT_RD_MAX 0x1f
40#define MPMC_STATIC_WAIT_PAGE(n) (0x210 + 0x20 * (n))
41#define MPMC_STATIC_WAIT_PAGE_MAX 0x1f
42#define MPMC_STATIC_WAIT_WR(n) (0x214 + 0x20 * (n))
43#define MPMC_STATIC_WAIT_WR_MAX 0x1f
44#define MPMC_STATIC_WAIT_TURN(n) (0x218 + 0x20 * (n))
45#define MPMC_STATIC_WAIT_TURN_MAX 0x0f
46
47/* Maximum number of static chip selects */
48#define PL172_MAX_CS 4
49
50struct pl172_data {
51 void __iomem *base;
52 unsigned long rate;
53 struct clk *clk;
54};
55
56static int pl172_timing_prop(struct amba_device *adev,
57 const struct device_node *np, const char *name,
58 u32 reg_offset, u32 max, int start)
59{
60 struct pl172_data *pl172 = amba_get_drvdata(adev);
61 int cycles;
62 u32 val;
63
64 if (!of_property_read_u32(np, name, &val)) {
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start;
66 if (cycles < 0) {
67 cycles = 0;
68 } else if (cycles > max) {
69 dev_err(&adev->dev, "%s timing too tight\n", name);
70 return -EINVAL;
71 }
72
73 writel(cycles, pl172->base + reg_offset);
74 }
75
76 dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start +
77 readl(pl172->base + reg_offset));
78
79 return 0;
80}
81
82static int pl172_setup_static(struct amba_device *adev,
83 struct device_node *np, u32 cs)
84{
85 struct pl172_data *pl172 = amba_get_drvdata(adev);
86 u32 cfg;
87 int ret;
88
89 /* MPMC static memory configuration */
90 if (!of_property_read_u32(np, "mpmc,memory-width", &cfg)) {
91 if (cfg == 8) {
92 cfg = MPMC_STATIC_CFG_MW_8BIT;
93 } else if (cfg == 16) {
94 cfg = MPMC_STATIC_CFG_MW_16BIT;
95 } else if (cfg == 32) {
96 cfg = MPMC_STATIC_CFG_MW_32BIT;
97 } else {
98 dev_err(&adev->dev, "invalid memory width cs%u\n", cs);
99 return -EINVAL;
100 }
101 } else {
102 dev_err(&adev->dev, "memory-width property required\n");
103 return -EINVAL;
104 }
105
106 if (of_property_read_bool(np, "mpmc,async-page-mode"))
107 cfg |= MPMC_STATIC_CFG_PM;
108
109 if (of_property_read_bool(np, "mpmc,cs-active-high"))
110 cfg |= MPMC_STATIC_CFG_PC;
111
112 if (of_property_read_bool(np, "mpmc,byte-lane-low"))
113 cfg |= MPMC_STATIC_CFG_PB;
114
115 if (of_property_read_bool(np, "mpmc,extended-wait"))
116 cfg |= MPMC_STATIC_CFG_EW;
117
118 if (amba_part(adev) == 0x172 &&
119 of_property_read_bool(np, "mpmc,buffer-enable"))
120 cfg |= MPMC_STATIC_CFG_B;
121
122 if (of_property_read_bool(np, "mpmc,write-protect"))
123 cfg |= MPMC_STATIC_CFG_P;
124
125 writel(cfg, pl172->base + MPMC_STATIC_CFG(cs));
126 dev_dbg(&adev->dev, "mpmc static config cs%u: 0x%08x\n", cs, cfg);
127
128 /* MPMC static memory timing */
129 ret = pl172_timing_prop(adev, np, "mpmc,write-enable-delay",
130 MPMC_STATIC_WAIT_WEN(cs),
131 MPMC_STATIC_WAIT_WEN_MAX, 1);
132 if (ret)
133 goto fail;
134
135 ret = pl172_timing_prop(adev, np, "mpmc,output-enable-delay",
136 MPMC_STATIC_WAIT_OEN(cs),
137 MPMC_STATIC_WAIT_OEN_MAX, 0);
138 if (ret)
139 goto fail;
140
141 ret = pl172_timing_prop(adev, np, "mpmc,read-access-delay",
142 MPMC_STATIC_WAIT_RD(cs),
143 MPMC_STATIC_WAIT_RD_MAX, 1);
144 if (ret)
145 goto fail;
146
147 ret = pl172_timing_prop(adev, np, "mpmc,page-mode-read-delay",
148 MPMC_STATIC_WAIT_PAGE(cs),
149 MPMC_STATIC_WAIT_PAGE_MAX, 1);
150 if (ret)
151 goto fail;
152
153 ret = pl172_timing_prop(adev, np, "mpmc,write-access-delay",
154 MPMC_STATIC_WAIT_WR(cs),
155 MPMC_STATIC_WAIT_WR_MAX, 2);
156 if (ret)
157 goto fail;
158
159 ret = pl172_timing_prop(adev, np, "mpmc,turn-round-delay",
160 MPMC_STATIC_WAIT_TURN(cs),
161 MPMC_STATIC_WAIT_TURN_MAX, 1);
162 if (ret)
163 goto fail;
164
165 return 0;
166fail:
167 dev_err(&adev->dev, "failed to configure cs%u\n", cs);
168 return ret;
169}
170
171static int pl172_parse_cs_config(struct amba_device *adev,
172 struct device_node *np)
173{
174 u32 cs;
175
176 if (!of_property_read_u32(np, "mpmc,cs", &cs)) {
177 if (cs >= PL172_MAX_CS) {
178 dev_err(&adev->dev, "cs%u invalid\n", cs);
179 return -EINVAL;
180 }
181
182 return pl172_setup_static(adev, np, cs);
183 }
184
185 dev_err(&adev->dev, "cs property required\n");
186
187 return -EINVAL;
188}
189
190static const char * const pl172_revisions[] = {"r1", "r2", "r2p3", "r2p4"};
191static const char * const pl175_revisions[] = {"r1"};
192static const char * const pl176_revisions[] = {"r0"};
193
194static int pl172_probe(struct amba_device *adev, const struct amba_id *id)
195{
196 struct device_node *child_np, *np = adev->dev.of_node;
197 struct device *dev = &adev->dev;
198 static const char *rev = "?";
199 struct pl172_data *pl172;
200 int ret;
201
202 if (amba_part(adev) == 0x172) {
203 if (amba_rev(adev) < ARRAY_SIZE(pl172_revisions))
204 rev = pl172_revisions[amba_rev(adev)];
205 } else if (amba_part(adev) == 0x175) {
206 if (amba_rev(adev) < ARRAY_SIZE(pl175_revisions))
207 rev = pl175_revisions[amba_rev(adev)];
208 } else if (amba_part(adev) == 0x176) {
209 if (amba_rev(adev) < ARRAY_SIZE(pl176_revisions))
210 rev = pl176_revisions[amba_rev(adev)];
211 }
212
213 dev_info(dev, "ARM PL%x revision %s\n", amba_part(adev), rev);
214
215 pl172 = devm_kzalloc(dev, sizeof(*pl172), GFP_KERNEL);
216 if (!pl172)
217 return -ENOMEM;
218
219 pl172->clk = devm_clk_get(dev, "mpmcclk");
220 if (IS_ERR(pl172->clk)) {
221 dev_err(dev, "no mpmcclk provided clock\n");
222 return PTR_ERR(pl172->clk);
223 }
224
225 ret = clk_prepare_enable(pl172->clk);
226 if (ret) {
227 dev_err(dev, "unable to mpmcclk enable clock\n");
228 return ret;
229 }
230
231 pl172->rate = clk_get_rate(pl172->clk) / MSEC_PER_SEC;
232 if (!pl172->rate) {
233 dev_err(dev, "unable to get mpmcclk clock rate\n");
234 ret = -EINVAL;
235 goto err_clk_enable;
236 }
237
238 ret = amba_request_regions(adev, NULL);
239 if (ret) {
240 dev_err(dev, "unable to request AMBA regions\n");
241 goto err_clk_enable;
242 }
243
244 pl172->base = devm_ioremap(dev, adev->res.start,
245 resource_size(&adev->res));
246 if (!pl172->base) {
247 dev_err(dev, "ioremap failed\n");
248 ret = -ENOMEM;
249 goto err_no_ioremap;
250 }
251
252 amba_set_drvdata(adev, pl172);
253
254 /*
255 * Loop through each child node, which represent a chip select, and
256 * configure parameters and timing. If successful; populate devices
257 * under that node.
258 */
259 for_each_available_child_of_node(np, child_np) {
260 ret = pl172_parse_cs_config(adev, child_np);
261 if (ret)
262 continue;
263
264 of_platform_populate(child_np, NULL, NULL, dev);
265 }
266
267 return 0;
268
269err_no_ioremap:
270 amba_release_regions(adev);
271err_clk_enable:
272 clk_disable_unprepare(pl172->clk);
273 return ret;
274}
275
276static void pl172_remove(struct amba_device *adev)
277{
278 struct pl172_data *pl172 = amba_get_drvdata(adev);
279
280 clk_disable_unprepare(pl172->clk);
281 amba_release_regions(adev);
282}
283
284static const struct amba_id pl172_ids[] = {
285 /* PrimeCell MPMC PL172, EMC found on NXP LPC18xx and LPC43xx */
286 {
287 .id = 0x07041172,
288 .mask = 0x3f0fffff,
289 },
290 /* PrimeCell MPMC PL175, EMC found on NXP LPC32xx */
291 {
292 .id = 0x07041175,
293 .mask = 0x3f0fffff,
294 },
295 /* PrimeCell MPMC PL176 */
296 {
297 .id = 0x89041176,
298 .mask = 0xff0fffff,
299 },
300 { 0, 0 },
301};
302MODULE_DEVICE_TABLE(amba, pl172_ids);
303
304static struct amba_driver pl172_driver = {
305 .drv = {
306 .name = "memory-pl172",
307 },
308 .probe = pl172_probe,
309 .remove = pl172_remove,
310 .id_table = pl172_ids,
311};
312module_amba_driver(pl172_driver);
313
314MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
315MODULE_DESCRIPTION("PL172 Memory Controller Driver");
316MODULE_LICENSE("GPL v2");